AD AD8003ACPZ-REEL7 Triple, 1.5 ghz op amp Datasheet

Triple, 1.5 GHz Op Amp
AD8003
POWER DOWN 2
+IN 2
–IN 2
FEEDBACK 2
+VS2
CONNECTION DIAGRAM
24
23
22
21
20
19
2
17
FEEDBACK 3
–IN 1
3
16
–IN 3
4
15
POWER DOWN 1
5
14
POWER DOWN 3
–VS1
6
13
–VS3
7
8
9
10
11
12
+IN 3
05721-001
+IN 1
OUT 3
FEEDBACK 1
NC
+VS3
OUT 2
18
NC
1
OUT 1
+VS1
NC
High speed
1650 MHz (G = +1)
730 MHz (G = +2, VO = 2 V p-p)
4300 V/μs (G = +2, 4 V step)
Settling time 12 ns to 0.1%, 2 V step
Excellent for QXGA resolution video
Gain flatness 0.1 dB to 190 MHz
0.05% differential gain error, RL = 150 Ω
0.01° differential phase error, RL = 150 Ω
Low voltage offset: 0.7 mV (typical)
Low input bias current: 7 μA (typical)
Low noise: 1.8 nV/√Hz
Low distortion over wide bandwidth: SFDR −73 dBc @ 20 MHz
High output drive: 100 mA output load drive
Supply operation: +5 V to ±5 V voltage supply
Supply current: 9.5 mA/amplifier
–VS2
FEATURES
Figure 1. 24-Lead, 4 mm × 4 mm LFCSP_VQ (CP-24)
APPLICATIONS
High resolution video graphics
Professional video
Consumer video
High speed instrumentation
The AD8003 has excellent video specifications with a frequency
response that remains flat out to 190 MHz and 0.1% settling within
12 ns to ensure that even the most demanding video systems
maintain excellent fidelity. For applications that use NTSC video,
as well as high speed video, the amplifier provides a differential
gain of 0.05% and a differential gain of 0.01°.
The AD8003 has very low spurious-free dynamic range (SFDR)
(−73 dBc @ 20 MHz) and noise (1.8 nV/√Hz). With a supply
range between 5 V and 11 V and ability to source 100 mA of
output current, the AD8003 is ideal for a variety of applications.
The AD8003 amplifier is available in a compact 4 mm × 4 mm,
24-lead LFCSP_VQ. The AD8003 is rated to work over the
industrial temperature range of −40°C to +85°C.
3
VS = ±5V
2 G = +1, RF = 432Ω
G = +2, +5, RF = 464Ω
RL = 150Ω
1
VOUT = 2V p-p
G = +1
G = +2
0
–1
–2
G = +5
–3
–4
–5
05721-009
The AD8003 is a triple ultrahigh speed current feedback
amplifier. Using ADI’s proprietary eXtra Fast Complementary
Bipolar (XFCB) process, the AD8003 achieves a bandwidth of
1.5 GHz and a slew rate of 4300 V/μs. Additionally, the
amplifier provides excellent dc precision with an input bias
current of 50 μA maximum and a dc input voltage of 0.7 mV.
The AD8003 operates on only 9.5 mA of supply current per
amplifier. The independent power-down function of the
AD8003 reduces the quiescent current even further to 1.6 mA.
NORMALIZED CLOSED-LOOP GAIN (dB)
GENERAL DESCRIPTION
–6
–7
1
10
100
1000
FREQUENCY (MHz)
Figure 2. Large Signal Frequency Response for Various Gains
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8003
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Configurations .................................................................. 12
Applications....................................................................................... 1
RGB Video Driver ...................................................................... 12
Connection Diagram ....................................................................... 1
Printed Circuit Board Layout ....................................................... 13
General Description ......................................................................... 1
Low Distortion Pinout............................................................... 13
Revision History ............................................................................... 2
Signal Routing............................................................................. 13
Specifications with ±5 V Supply ..................................................... 3
Exposed Paddle........................................................................... 13
Specifications with +5 V Supply ..................................................... 4
Power Supply Bypassing ............................................................ 13
Absolute Maximum Ratings............................................................ 5
Grounding ................................................................................... 14
Thermal Resistance ...................................................................... 5
Outline Dimensions ....................................................................... 15
ESD Caution.................................................................................. 5
Ordering Guide .......................................................................... 15
Typical Performance Characteristics ............................................. 6
Applications..................................................................................... 12
REVISION HISTORY
2/06—Rev. 0 to Rev. A
Changes to Figure 34...................................................................... 11
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
AD8003
SPECIFICATIONS WITH ±5 V SUPPLY
TA = 25°C, VS = ±5 V, RL = 150 Ω, Gain = +2, RF = 464 Ω, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Conditions
Min
Typ
Max
Unit
G = +1, Vo = 0.2 V p-p, RF = 432 Ω
G = +2, Vo = 2 V p-p
1650
MHz
730
MHz
G = +10, Vo = 0.2 V p-p
G = +5, Vo = 2 V p-p
290
MHz
330
MHz
Bandwidth for 0.1 dB Flatness
Vo = 2 V p-p
190
MHz
Slew Rate
G = +2, Vo = 2 V step, RL = 150 Ω
3800
V/μs
Settling Time to 0.1%
G = +2, Vo = 2 V step
12
ns
30/40
ns
G = +1, Vo = 2 V p-p
76/97
dBc
G = +1, Vo = 2 V p-p
f = 1 MHz
f = 1 MHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
79/73
dBc
1.8
36/3
0.05
0.01
nV/√Hz
pA/√Hz
%
Degree
Overload Recovery Input/Output
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic @ 5 MHz
Second/Third Harmonic @ 20 MHz
Input Voltage Noise
Input Current Noise (I−/I+)
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
−9.3
+IB/−IB
TMIN − TMAX (+IB/−IB)
−19/−40
Vo = ±2.5 V
400
+0.7
1.08
7.4
−7/−7
−3.8/+29.5
±14.2
600
VCM = ±2.5 V
−51
1.6/3
±3.6
−48
RL = 150 Ω
VO = 2 V p-p, second harmonic < −50 dBc
40% over shoot
±3.85
TMIN − TMAX
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Transimpedance
INPUT CHARACTERISTICS
Noninverting Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Capacitive Load Drive
POWER DOWN PINS
Power-Down Input Voltage
Turn-Off Time
Turn-On Time
Input Current
Enabled
Power-Down
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Quiescent Current per Amplifier
Power Supply Rejection Ratio (+PSRR/−PSRR)
Power down
Enable
50% of power-down voltage to
10% of VOUT final, VIN = 0.5 V p-p
50% of power-down voltage to
90% of VOUT final, VIN = 0.5 V p-p
Enabled
Power down
Rev. A | Page 3 of 16
±3.9
100
27
+9.3
1100
mV
mV
μV/°C
μA
μA
μA
kΩ
−46
MΩ/pF
V
dB
+4/+50
±3.92
V
mA
pF
<VS − 2.5
>VS − 2.5
40
V
V
ns
130
ns
−365
0.1
−235
−85
μA
μA
4.5
8.1
1.2
−59/−57
9.5
1.4
−57/−53
10
10.2
1.6
−55/−50
V
mA
mA
dB
AD8003
SPECIFICATIONS WITH +5 V SUPPLY
TA = 25°C, VS = 5 V, RL = 150 Ω, Gain = +2, RF = 464 Ω, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Conditions
Min
Typ
Max
Unit
G = +1, Vo = 0.2 V p-p, RF = 432 Ω
G = +2, Vo = 2 V p-p
1050
MHz
590
MHz
G = +10, Vo = 0.2 V p-p
G = +5, Vo = 2 V p-p
290
MHz
310
MHz
Bandwidth for 0.1 dB Flatness
Vo = 2 V p-p
83
MHz
Slew Rate
G = +2, Vo = 2 V step, RL = 150 Ω
2860
V/μs
Settling Time to 0.1%
G = +2, Vo = 2 V step
12
ns
40/60
ns
75/78
dBc
Overload Recovery Input/Output
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic @ 5 MHz
Second/Third Harmonic @ 20 MHz
Input Voltage Noise
Input Current Noise (I−/I+)
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
G = +1, Vo = 2 V p-p
G = +1, Vo = 2 V p-p
66/61
dBc
f = 1 MHz
f = 1 MHz
NTSC, G = +2, RL = 150 Ω
NTSC, G = +2, RL = 150 Ω
1.8
36/3
0.04
0.01
nV/√Hz
pA/√Hz
%
Degree
−6.5
300
+2.7
2.06
14.2
−7.7/−2.3
−4/−27.8
±5.4
530
−50
1.6/3
1.3 to 3.7
−48
TMIN − TMAX
Input Offset Voltage Drift
Input Bias Current (+IB/−IB)
−21/−50
TMIN − TMAX (+IB/−IB)
Input Offset Current
Transimpedance
INPUT CHARACTERISTICS
Noninverting Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Capacitive Load Drive
POWER DOWN PINS
Power-Down Input Voltage
Turn-Off Time
Turn-On Time
Input Current
Enabled
Power-Down
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Quiescent Current per Amplifier
Power Supply Rejection Ratio (+PSRR/−PSRR)
RL = 150 Ω
VO = 2 V p-p, second harmonic < −50 dBc
45% over shoot
±1.52
Power down
Enable
50% of power-down voltage to
10% of VOUT final, VIN = 0.5 V p-p
50% of power-down voltage to
90% of VOUT final, VIN = 0.5 V p-p
Enabled
Power down
Rev. A | Page 4 of 16
±1.57
70
27
+11
1500
mV
mV
μV/°C
μA
μA
μA
kΩ
−45
MΩ/pF
V
dB
+5/+48
±1.62
V
mA
pF
<VS − 2.5
>VS − 2.5
125
V
V
ns
80
ns
−160
0.1
−43
+80
μA
μA
4.5
6.3
0.8
−59/−56
7.9
0.9
−57/−53
10
9.4
1.1
−55/−50
V
mA
mA
dB
AD8003
ABSOLUTE MAXIMUM RATINGS
Rating
11 V
See Figure 3
−VS − 0.7 V to +VS + 0.7 V
±VS
−VS
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
24-Lead LFCSP_VQ
θJA
70
Unit
°C/W
Maximum Power Dissipation
The maximum safe power dissipation for the AD8003 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the AD8003. Exceeding a junction temperature of 175°C for
an extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the AD8003 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
PD = Quiescent Power + (Total Drive Power – Load Power)
⎛V V
PD = (VS × I S ) + ⎜⎜ S × OUT
RL
⎝ 2
⎞ VOUT 2
⎟–
⎟
RL
⎠
RMS output voltages should be considered. If RL is referenced to
−VS, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
PD = (VS × I S ) +
(VS / 4 )2
RL
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads and exposed paddle from metal traces, through holes,
ground, and power planes reduce θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle,
4 mm × 4 mm LFCSP_VQ (70°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
3.0
2.5
2.0
1.5
1.0
0.5
0
05721-037
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
MAXIMUM POWER DISSIPATION (W)
Table 3.
–55
–35
–15
5
25
45
65
85
AMBIENT TEMPERATURE (°C)
105
125
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation and loss of functionality.
Rev. A | Page 5 of 16
AD8003
TYPICAL PERFORMANCE CHARACTERISTICS
3
0
–1
–2
–3
G = –1
–4
–5
G = –2
–6
–7
1
10
100
1
–1
–2
G = +10
–3
–4
–5
–6
1
10
NORMALIZED CLOSED-LOOP GAIN (dB)
0
VS = ±5V
–1
–2
–3
–4
VS = +5V
–5
05721-004
NORMALIZED CLOSED-LOOP GAIN (dB)
3
G = +2
RL = 150Ω
VOUT = 200mV p-p
1
–6
–7
1
10
100
1
0
–2
–3
–4
T = +25°C
–5
T = –40°C
–6
1
10
3
RF = 357Ω
0
RF = 432Ω
–1
–2
RF = 464Ω
–3
–4
–5
–6
–7
1
10
100
1
RF = 392Ω
RF = 357Ω
0
–1
RF = 432Ω
–2
RF = 464Ω
–3
–4
–5
–6
–7
1000
G = +2
VS = ±5V
RL = 150Ω
VOUT = 2V p-p
2
05721-008
RF = 392Ω
NORMALIZED CLOSED-LOOP GAIN (dB)
1
1000
Figure 8. Small Signal Frequency Response for Various Temperatures
05721-007
NORMALIZED CLOSED-LOOP GAIN (dB)
2
100
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response for Various Supplies
G = +2
VS = ±5V
RL = 150Ω
VOUT = 200mV p-p
T = +105°C
–1
–7
1000
G = +2
VS = ±5V
RL = 150Ω
VOUT = 200mV p-p
2
FREQUENCY (MHz)
3
1000
Figure 7. Small Signal Frequency Response for Various Gains
Figure 4. Small Signal Frequency Response for Various Gains
2
100
FREQUENCY (MHz)
FREQUENCY (MHz)
3
G = +1
0
–7
1000
G = +2
05721-003
1
VS = ±5V
G = +1, RF = 432Ω
G = +2, +10, RF = 464Ω
RL = 150Ω
VOUT = 200mV p-p
2
05721-005
2
NORMALIZED CLOSED-LOOP GAIN (dB)
VS = ±5V
RF = 464Ω
RL = 150Ω
VOUT = 200mV p-p
05721-002
NORMALIZED CLOSED-LOOP GAIN (dB)
3
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Large Signal Feedback Resistor (RF) Optimization
Figure 6. Small Signal Feedback Resistor (RF) Optimization
Rev. A | Page 6 of 16
AD8003
0.3
NORMALIZED CLOSED-LOOP GAIN (dB)
RS = 0Ω
RS = 25Ω
0
RS = 50Ω
–3
–6
–9
1
10
100
FREQUENCY (MHz)
1000
0
VS = ±5V
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
10000
1
G = +1
G = +2
0
–1
–2
G = +5
–4
–5
–6
–7
1
10
100
1
T = +105°C
T = –40°C
0
T = +25°C
–1
–2
–3
–4
–5
–6
–7
1000
VS = ±5V
G = +2
RL = 150Ω
VOUT = 2V p-p
2
1
10
FREQUENCY (MHz)
G = +1
R = 100Ω
–40 V L = 2V p-p
OUT
–30
G = +2
R = 150Ω
–40 V L = 2V p-p
OUT
VS = ±5V
VS = +5V
DISTORTION (dBc)
DISTORTION (dBc)
VS = ±5V
VS = +5V
–50
–60
SECOND
–70
–80
THIRD
–60
–70
–90
–110
–110
05721-017
–100
1
10
FREQUENCY (MHz)
–120
0.1
100
Figure 12. Harmonic Distortion vs. Frequency for Various Supplies
SECOND
–80
–100
–120
0.1
1000
Figure 14. Large Signal Frequency Response for Various Temperatures
–50
–90
100
FREQUENCY (MHz)
Figure 11. Large Signal Frequency Response for Various Gains
–30
1000
05721-010
NORMALIZED CLOSED-LOOP GAIN (dB)
3
05721-009
NORMALIZED CLOSED-LOOP GAIN (dB)
3
–3
10
100
FREQUENCY (MHz)
Figure 13. 0.1 dB Flatness Response
Figure 10. G = +1 Series Resistor (RS) Optimization
VS = ±5V
2 G = +1, RF = 432Ω
G = +2, +5, RF = 464Ω
RL = 150Ω
1
VOUT = 2V p-p
VS = +5V
THIRD
05721-018
–12
G = +2
0.2 RL = 150Ω
VOUT = 2V p-p
0.1
05721-016
G = +1
VS = ±5V
RL = 150Ω
3 VOUT = 200mV p-p
05721-006
NORMALIZED CLOSED-LOOP GAIN (dB)
6
1
10
FREQUENCY (MHz)
100
Figure 15. Harmonic Distortion vs. Frequency for Various Supplies
Rev. A | Page 7 of 16
AD8003
0.20
VS = ±5V
VS = +5V
0.15
OUTPUT VOLTAGE (V)
SECOND
–40
–50
–60
THIRD
–70
–90
05721-019
–80
10
12
14
16
18
20
RL (Ω)
22
24
26
28
2.60
VS = ±5V
0.05
2.55
0
2.50
–0.05
2.45
–0.10
2.40
–0.15
2.35
0
Figure 16. Harmonic Distortion vs. RL
1.5
–1.5
1.0
–2.0
0.5
10 11 12 13 14 15
4
5
6
7 8 9
TIME (ns)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
–1.0
6
7 8 9
TIME (ns)
10 11 12 13 14 15
2.30
0.1
CL = 15pF
0
CL = 0pF
–0.1
G = +2
RL = 150Ω
VS = ±5V
VOUT = 200mV p-p
–0.2
05721-012
2.0
–0.3
0
5
10
CL = 27pF
15
20
TIME (ns)
25
30
35
Figure 17. Large Signal Pulse Response for Various Supplies
Figure 20. Small Signal Pulse Response for Various Capacitive Loads
2.8
1.5
2.7
1.0
G = +2
VS = ±5V
RL = 150Ω
0.3
VOUT
0.2
VIN
2.5
CL = 0pF
2.4
G = +2
RL = 150Ω
VS = 5V
VOUT = 200mV p-p
2.3
2.2
0
5
10
CL = 27pF
15
20
TIME (ns)
25
30
35
0.5
0.1
0
0
VSETTLE
–0.5
–0.1
–1.0
–1.5
Figure 18. Small Signal Pulse Response for Various Capacitive Loads
–0.2
–5
0
5
10
15
20
25
TIME (ns)
30
35
40
Figure 21. Short-Term 0.1% Settling Time
Rev. A | Page 8 of 16
45
–0.3
05721-021
CL = 15pF
SETTLING (%)
AMPLITUDE (V)
2.6
05721-022
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.0
–0.5
3
5
0.2
3.5
2.5
2
4
0.3
0
1
3
4.0
VS = ±5V
0
2
4.5
VS = +5V
0.5
1
Figure 19. Small Signal Pulse Response for Various Supplies
2.0 G = +2
RL = 150Ω
1.5 VOUT = 2V p-p
1.0
2.65
0.10
–0.20
30
VS = +5V
05721-020
DISTORTION (dBc)
–30
2.70
G = +2
RL = 150Ω
VOUT = 200mV p-p
OUTPUT VOLTAGE (V)
G = +2
VOUT = 2V p-p
–20 f = 5MHz
C
05721-011
–10
AD8003
6000
G = +2
RL = 150Ω
5
RISE
FALL
VS = ±5V
G = +1
VS = ±5V
RL = 150Ω
INPUT
4
5000
3
AMPLITUDE (V)
3000
VS = +5V
2000
1
0
–1
–2
–3
1000
–4
05721-013
0
1
0
2
3
4
VOUT p-p (V)
5
6
05721-023
SLEW RATE (V/µs)
OUTPUT
2
4000
–5
7
0
0.1
1000
G = +2
VS = ±5V
RL = 150Ω
INPUT × 2
4
0.3
0.4
0.5
0.6
TIME (µs)
0.7
0.8
0.9
1.0
Figure 25. Input Overdrive Recovery
Figure 22. Slew Rate vs. Output Voltage
5
0.2
3
G = +1/+2
VS = ±5V
100
OUTPUT
IMPEDANCE (Ω)
AMPLITUDE (V)
2
1
0
–1
–2
10
1
–5
0
0.1
0.2
0.3
0.4
0.5
0.6
TIME (µs)
0.7
0.8
0.9
0.1
0.1
1.0
0
POWER SUPPLY REJECTION (dB)
G=0
VS = ±5V
RL = 150Ω
–20
–30
–40
–50
–60
0.1
05721-026
COMMON-MODE REJECTION (dB)
–10
1
10
FREQUENCY (MHz)
10
FREQUENCY (MHz)
100
1000
Figure 26. Output Impedance vs. Frequency
Figure 23. Output Overdrive Recovery
0
1
–10
G = +2
VS = ±5V
RL = 150Ω
–20
–30
PSR–
–40
–50
PSR+
–60
–70
0.1
100
Figure 24. Common-Mode Rejection vs. Frequency
05721-025
–4
05721-027
05721-024
–3
1
10
FREQUENCY (MHz)
100
Figure 27. Power Supply Rejection vs. Frequency
Rev. A | Page 9 of 16
1000
AD8003
80
20
15
60
VS = ±5V
VS = +5V
40
VS = +5V
VS = ±5V
10
IB (µA)
VOS (mV)
5
20
0
0
–5
–20
–10
–60
–5
–4
–3
–2
–1
0
1
2
3
4
–20
–5
5
05721-032
–15
05721-031
–40
–4
–3
–2
–1
VCM (V)
0
1
2
3
4
5
VCM (V)
Figure 31. Noninverting Input Bias Current vs. Common-Mode Range
Figure 28. Offset Voltage vs. Input Common-Mode Range
10
6
VS = +5V
8
6
5
VS = ±5V
4
AMPLITUDE (V)
0
–2
–4
VDIS (VS = +5V)
3
VOUT (VS = +5V)
2
VOUT (VS = ±5V)
–6
–4
–3
–2
–1
0
1
2
3
4
VOUT (VS = ±5V)
5
0
VOUT (V)
Figure 29. Inverting Input Bias Current Linearity
10
150
9
50
0
IDIS
5
–50
4
–100
3
–150
ICC
2
–200
POSITIVE SUPPLY CURRENT (mA)
100
7
POWER DOWN PIN CURRENT (µA)
0.7
0.8
1.0
0.9
Figure 30. POWER DOWN Pin Current and Supply Current vs.
POWER DOWN Pin Voltage
30
20
ICC
10
IDIS
–10
4
–20
3
–30
2
–40
–50
0
5
40
0
1
4
0.4
0.5
0.6
TIME (µs)
5
–300
–3
–2
–1
0
1
2
3
POWER DOWN PIN VOLTAGE (VDIS (V))
0.3
6
0
–4
0.2
G = +2
RL = 150Ω
VS = 5V
7
–250
–5
0.1
8
1
05721-028
POSITIVE SUPPLY CURRENT (mA)
200
8
6
0
Figure 32. Disable Switching Time for Various Supplies
G = +2
RL = 150Ω
VS = ±5V
9
05721-014
–10
–5
VOUT (VS = +5V)
1
05721-033
–8
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
POWER DOWN PIN VOLTAGE (VDIS (V))
4.5
5.0
–60
Figure 33. POWER DOWN Pin Current and Supply Current vs.
POWER DOWN Pin Voltage
Rev. A | Page 10 of 16
POWER DOWN PIN CURRENT (µA)
IB (μA)
2
05721-029
4
10
G = +2
RL = 150Ω
VIN = 0.5V dc
VDIS (VS = ±5V)
AD8003
10000
100
100
I–
10
I+
100
1k
10k
100k
1M
1
10
10M
100
1k
100k
1M
10M
Figure 36. Input Current Noise vs. Frequency
Figure 34. Input Voltage Noise vs. Frequency
200
1M
0
G = +2
RL = 150Ω
–10
DRIVING: CH1 AND CH3
RECEIVING: CH2
–20
180
VS = ±5V
160
100k
MAGNITUDE (Ω)
VS = +5V
–40
–50
–60
120
10k
100
80
60
–70
1k
40
–80
–90
–100
0.1
PHASE (Degrees)
140
–30
20
05721-015
NORMALIZED CLOSED-LOOP GAIN (dB)
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
1
10
FREQUENCY (MHz)
100
100
1k
1000
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 35. Worst-Case Crosstalk
Figure 37. Transimpedance
Rev. A | Page 11 of 16
100M
1G
0
05721-030
1
10
1000
05721-034
10
VS = ±5V
05721-035
VS = ±5V
RF = 1kΩ
INPUT CURRENT NOISE (pA/√Hz)
INPUT VOLTAGE NOISE (nV/√Hz)
1000
AD8003
APPLICATIONS
GAIN CONFIGURATIONS
RGB VIDEO DRIVER
Unlike conventional voltage feedback amplifiers, the feedback
resistor has a direct impact on the closed-loop bandwidth and
stability of the current feedback op amp circuit. Reducing the
resistance below the recommended value can make the amplifier
response peak and can even become unstable. Increasing the
size of the feedback resistor reduces the closed-loop bandwidth.
Figure 40 shows a typical RGB driver application using
bipolar supplies. The gain of the amplifier is set at +2 , where
RF = RG = 464 Ω. The amplifier inputs are terminated with
shunt 75 Ω resistors, and the outputs have series 75 Ω resistors
for proper video matching. In Figure 40, the POWER DOWN
pins are not shown connected to any signal source for simplicity. If
the power-down function is not used, it is recommended that
the POWER DOWN pins be tied to the positive supply and not
be left floating (not connected).
Table 5 provides a convenient reference for quickly determining
the feedback and gain set resistor values, and the small and
large signal bandwidths for common gain configurations. The
feedback resistors in Table 5 have been optimized for 0.1 dB
flatness frequency response.
Table 5. Recommended Values and Frequency Response1
RF (Ω)
300
432
464
300
300
RG (Ω)
300
N/A
464
75
33.2
RS (Ω)
0
24.9
0
0
0
Large
Signal
−3 dB
BW
668
822
730
558
422
Large
Signal
0.1 dB
BW
--190
165
170
PD3
PD2
PD1
5
23
+VS
14
10µF
1
0.1µF
RIN
4
RG
75Ω
464Ω
RF
464Ω
1
Conditions: VS = ±5 V, TA = 25°C, RL = 150 Ω.
Figure 38 and Figure 39 show the typical noninverting and inverting
configurations and recommended bypass capacitor values.
75Ω
–VS
3
6
0.1µF
2
+VS
+VS
10µF
10µF
AD8003
RF
RG
VIN
RS
0.1µF
FB
0.1µF
75Ω
75Ω
AD8003
VO
+
–V
19
22
GIN
+V
–
ROUT
10µF
RG
VO
RL
464Ω
RF
464Ω
0.1µF
10µF
–VS
21
GOUT
10µF
24
0.1µF
20
+VS
10µF
18
05721-038
–VS
0.1µF
Figure 38. Noninverting Gain
RG
10µF
464Ω
RF
464Ω
RF
0.1µF
FB
AD8003
+
VO
16
10µF
Figure 39. Inverting Gain
Rev. A | Page 12 of 16
BOUT
10µF
13
0.1µF
Figure 40. RGB Video Driver
VO
RL
–V 0.1µF
–VS
–VS
17
+V
–
05721-039
RG
75Ω
75Ω
+VS
VIN
15
BIN
05721-036
Gain
−1
+1
+2
+5
+10
−3 dB
SS BW
(MHz)
734
1650
761
567
446
In applications that require a fixed gain of +2, as previously
mentioned, the designer may consider the ADA4862-3.
The ADA4862-3 is another high performance triple current
feedback amplifier. The ADA4862-3 has integrated feedback
and gain set resistors that reduce board area and simplify designs.
AD8003
PRINTED CIRCUIT BOARD LAYOUT
Printed circuit board (PCB) layout is usually one of the last
steps in the design process and often proves to be one of the
most critical. A high performance design can be rendered
mediocre due to poor or sloppy layout. Because the AD8003
can operate into the RF frequency spectrum, high frequency
board layout considerations must be taken into account. The
PCB layout, signal routing, power supply bypassing, and
grounding must all be addressed to ensure optimal
performance.
LOW DISTORTION PINOUT
The AD8003 LFCSP features ADI’s low distortion pinout. The
pinout lowers the second harmonic distortion and simplifies the
circuit layout. The close proximity of the noninverting input
and the negative supply pin creates a source of second harmonic
distortion. Physical separation of the noninverting input pin
and the negative power supply pin reduces this distortion.
By providing an additional output pin, the feedback resistor
can be connected directly between the feedback pin and the
inverting input. This greatly simplifies the routing of the
feedback resistor and allows a more compact circuit layout,
which reduces its size and helps to minimize parasitics and
increase stability.
SIGNAL ROUTING
To minimize parasitic inductances, ground planes should be
used under high frequency signal traces. However, the ground
plane should be removed from under the input and output pins
to minimize the formation of parasitic capacitors, which
degrades phase margin. Signals that are susceptible to noise
pickup should be run on the internal layers of the PCB, which
can provide maximum shielding.
EXPOSED PADDLE
The AD8003 features an exposed paddle, which lowers the
thermal resistance by approximately 40% compared to a
standard SOIC plastic package. The paddle can be soldered
directly to the ground plane of the board. Thermal vias or heat
pipes can also be incorporated into the design of the mounting
pad for the exposed paddle. These additional vias improve the
thermal transfer from the package to the PCB. Using a heavier
weight copper also reduces the overall thermal resistance path
to ground.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, the AD8003 power supply pins
need to be properly bypassed.
Each amplifier has its own supply pins brought out for the
utmost flexibility. Supply pins can be commoned together or
routed to a dedicated power plane. Commoned supply connections
can also reduce the need for bypass capacitors on each supply
line. The exact number and values of the bypass capacitors are
dictated by the design specifications of the actual circuit.
A parallel combination of different value capacitors from each
of the power supply pins to ground tends to work the best.
Paralleling different values and sizes of capacitors helps to
ensure that the power supply pins see a low ac impedance across
a wide band of frequencies. This is important for minimizing
the coupling of noise into the amplifier. Starting directly at the
power supply pins, the smallest value and physical-sized
component should be placed on the same side of the board as
the amplifier, and as close as possible to the amplifier, and
connected to the ground plane. This process should be repeated
for the next largest capacitor value. It is recommended that a
0.1 μF ceramic 0508 case be used for the AD8003. The 0508
offers low series inductance and excellent high frequency
performance. The 0.1 μF case provides low impedance at high
frequencies. A 10 μF electrolytic capacitor should be placed in
parallel with the 0.1 μF. The 10 μF capacitor provides low ac
impedance at low frequencies. Smaller values of electrolytic
capacitors can be used depending on the circuit requirements.
Additional smaller value capacitors help provide a low impedance
path for unwanted noise out to higher frequencies but are not
always necessary.
Placement of the capacitor returns (grounds), where the
capacitors enter into the ground plane, is also important.
Returning the capacitor grounds close to the amplifier load is
critical for distortion performance. Keeping the capacitors
distance short, but equal from the load, is optimal for
performance.
In some cases, bypassing between the two supplies can help
improve PSRR and maintain distortion performance in
crowded or difficult layouts. Designers should note this as
another option for improving performance.
Rev. A | Page 13 of 16
AD8003
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduces the trace inductance. A
series inductance with the parallel capacitance can form a tank
circuit, which can introduce high frequency ringing at the
output. This additional inductance can also contribute to
increased distortion due to high frequency compression at the
output. The use of vias should be minimized in the direct path
to the amplifier power supply pins because vias can introduce
parasitic inductance, which can lead to instability. When
required, use multiple large diameter vias because this lowers
the equivalent parasitic inductance.
GROUNDING
The use of ground and power planes is encouraged as a method
of proving low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce
stray trace inductance and provide a low thermal path for the
amplifier. Ground and power planes should not be used under
any of the pins of the AD8003. The mounting pads and the
ground or power planes can form a parasitic capacitance at the
amplifiers input. Stray capacitance on the inverting input and
the feedback resistor form a pole, which degrades the phase
margin, leading to instability. Excessive stray capacitance on the
output also forms a pole, which degrades phase margin.
Rev. A | Page 14 of 16
AD8003
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
PIN 1
INDICATOR
0.60 MAX
TOP
VIEW
0.50
BSC
3.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
0.80 MAX
0.65 TYP
12° MAX
0.30
0.23
0.18
SEATING
PLANE
PIN 1
INDICATOR
24 1
19
18
2.25
2.10 SQ
1.95
EXPOSED
PAD
(BOTTOM VIEW)
13
12
7
6
0.25 MIN
2.50 REF
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8003ACPZ-R2 1
AD8003ACPZ-REEL1
AD8003ACPZ-REEL71
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Z = Pb-free part.
Rev. A | Page 15 of 16
Package Option
CP-24-1
CP-24-1
CP-24-1
Ordering Quantity
250
5,000
1,500
AD8003
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05721-0-2/06(A)
Rev. A | Page 16 of 16