19-2851; Rev 3; 2/10 KIT ATION EVALU E L B AVAILA 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Features The MAX1227/MAX1229/MAX1231 are serial 12-bit analog-to-digital converters (ADCs) with an internal reference and an internal temperature sensor. These devices feature an on-chip FIFO, scan mode, internal clock mode, internal averaging, and AutoShutdown™. The maximum sampling rate is 300ksps using an external clock. The MAX1231 has 16 input channels, the MAX1229 has 12 input channels, and the MAX1227 has 8 input channels. All input channels are configurable for single-ended or differential inputs in unipolar or bipolar mode. All three devices operate from a +3V supply and contain a 10MHz SPI™-/QSPI™-/MICROWIRE™-compatible serial port. The MAX1231 is available in 28-pin 5mm x 5mm TQFN with exposed pad and 24-pin QSOP packages. The MAX1227/MAX1229 are only available in QSOP packages. All three devices are specified over the extended -40°C to +85°C temperature range. ♦ Internal Temperature Sensor (±1°C Accuracy) ♦ 16-Entry First-In/First-Out (FIFO) ♦ Analog Multiplexer with True Differential Track/Hold 16-, 12-, 8-Channel Single Ended 8-, 6-, 4-Channel True Differential (Unipolar or Bipolar) ♦ Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing Codes Overtemperature ♦ Scan Mode, Internal Averaging, and Internal Clock ♦ Low-Power Single +3V Operation 0.62mA at 300ksps ♦ Internal 2.5V Reference or External Differential Reference ♦ 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible Interface ♦ Space-Saving 28-Pin 5mm x 5mm TQFN Package ________________________Applications Ordering Information System Supervision Data-Acquisition Systems PART TEMP RANGE PIN-PACKAGE Industrial Control Systems MAX1227BCEE-T 0°C to +70°C 16 QSOP Patient Monitoring MAX1227BEEE-T -40°C to +85°C 16 QSOP Data Logging MAX1229BCEP-T 0°C to +70°C 20 QSOP Instrumentation MAX1229BEEP-T -40°C to +85°C 20 QSOP Ordering Information continued at end of data sheet. AutoShutdown is a trademark of Maxim Integrated Products, Inc. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Pin Configurations TOP VIEW AIN0 1 16 EOC AIN1 2 15 DOUT AIN2 3 AIN3 4 AIN0 1 20 EOC AIN1 2 19 DOUT AIN2 3 18 DIN AIN3 4 17 CS 14 DIN MAX1227 AIN4 5 AIN4 5 MAX1229 AIN5 6 15 VDD AIN6 7 14 GND AIN7 8 13 REF+ AIN8 9 12 CNVST/AIN11 AIN9 10 11 REF-/AIN10 12 SCLK AIN5 6 11 VDD REF-/AIN6 7 10 GND CNVST/AIN7 8 16 SCLK 13 CS 9 REF+ QSOP Pin Configurations continued at end of data sheet. QSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1227/MAX1229/MAX1231 General Description MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (VDD + 0.3V) AIN0–AIN13, REF-/AIN_, CNVST/AIN_, REF+ to GND.........................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW 20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW 24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW 28-Pin TQFN 5mm x 5mm (derate 20.8mW/°C above +70°C) ........................1667mW Operating Temperature Ranges MAX12__C__.......................................................0°C to +70°C MAX12__E__ ....................................................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +3.6V, fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1.0 LSB ±1.0 LSB ±0.5 ±4.0 LSB ±0.5 ±4.0 LSB DC ACCURACY (NOTE 1) Resolution RES Integral Nonlinearity INL Differential Nonlinearity DNL 12 No missing codes over temperature Offset Error Gain Error Bits (Note 2) Offset Error Temperature Coefficient ±2 ppm/°C FSR Gain Temperature Coefficient ±0.8 ppm/°C Channel-to-Channel Offset Matching ±0.1 LSB 70 dB DYNAMIC SPECIFICATIONS (10kHz sine wave input, 2.5VP-P, 300ksps, fSCLK = 4.8MHz) Signal-to-Noise Plus Distortion SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion -82 dBc 80 dBc fin1 = 9.9kHz, fin2 = 10.2kHz 76 dBc Full-Power Bandwidth -3dB point 1 MHz Full-Linear Bandwidth S / (N + D) > 68dB 25 kHz 2 IMD Up to the 5th harmonic _______________________________________________________________________________________ 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference (VDD = +2.7V to +3.6V, fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVERSION RATE Power-Up Time tPU Acquisition Time tACQ Conversion Time tCONV External Clock Frequency fSCLK External reference 0.8 Internal reference (Note 3) 65 µs 0.6 Internally clocked 3.5 Externally clocked (Note 4) 2.7 Externally clocked conversion 0.1 µs 4.8 Data I/O SCLK Duty Cycle µs 10 40 60 MHz % Aperture Delay 30 ns Aperture Jitter <50 ps ANALOG INPUT Unipolar Input Voltage Range Bipolar (Note 5) Input Leakage Current VIN = VDD Input Capacitance During acquisition time (Note 6) 0 VREF -VREF / 2 VREF / 2 ±0.01 ±1 24 V µA pF INTERNAL TEMPERATURE SENSOR Measurement Error (Note 7) Grade B, TA = +25°C ±0.7 Grade B, TA = TMIN to TMAX ±1.2 ±2.5 °C Temperature Measurement Noise 0.4 Temperature Resolution 1/8 °CRMS °C Power-Supply Rejection 0.3 °C/V INTERNAL REFERENCE REF Output Voltage 2.48 REF Temperature Coefficient TCREF Grade B 2.50 2.52 ±30 V ppm/°C Output Resistance 6.5 kΩ REF Output Noise 200 µVRMS -70 dB REF Power-Supply Rejection PSRR EXTERNAL REFERENCE INPUT REF- Input Voltage Range VREF- 0 REF+ Input Voltage Range VREF+ 1.0 REF+ Input Current IREF+ VREF+ = 2.5V, fSAMPLE = 300ksps VREF+ = 2.5V, fSAMPLE = 0 500 VDD + 50mV 40 100 ±0.1 ±5 mV V µA _______________________________________________________________________________________ 3 MAX1227/MAX1229/MAX1231 ELECTRICAL CHARACTERISTICS (continued) MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V, fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, CNVST) Input Voltage Low Input Voltage High Input Hysteresis VIL VDD x 0.3 VIH VDD x 0.7 VHYST Input Leakage Current IIN Input Capacitance CIN V 200 VIN = 0 or VDD V ±0.01 mV ±1.0 15 µA pF DIGITAL OUTPUTS (DOUT, EOC) Output Voltage Low VOL Output Voltage High VOH Tri-State Leakage Current Tri-State Output Capacitance ISINK = 2mA 0.4 ISINK = 4mA 0.8 ISOURCE = 1.5mA VDD - 0.5 V V IL CS = VDD ±0.05 COUT CS = VDD 15 ±1 µA pF POWER REQUIREMENTS Supply Voltage VDD 2.7 Internal reference Supply Current (Note 8) IDD Power-Supply Rejection PSR During temp sense 2200 2700 fSAMPLE = 300ksps 1550 1800 fSAMPLE = 0, REF on 1000 1200 Shutdown External reference 3.6 0.2 5 During temp sense 1550 2000 fSAMPLE = 300ksps 880 1100 Shutdown 0.2 5 ±0.2 ±1 VDD = 2.7V to 3.6V; full-scale input V µA mV Tested at VDD = +2.7V, unipolar input mode. Offset nulled. Time for reference to power up and settle to within 1 LSB. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. The operational input voltage range for each individual input of a differentially configured pair is from GND to VDD. The operational input voltage difference is from -VREF/2 to +VREF/2. Note 6: See Figure 3 (Input Equivalent Circuit) and the Typical Operating Curve in the Sampling Error vs. Source Impedance section. Note 7: Fast automated test, excludes self-heating effects. Note 8: Supply current is specified depending on whether an internal or external reference is used for voltage conversions. Temperature measurements always use the internal reference. Note 1: Note 2: Note 3: Note 4: Note 5: 4 _______________________________________________________________________________________ 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference PARAMETER SYMBOL SCLK Clock Period tCP SCLK Duty Cycle tCH CONDITIONS MIN Externally clocked conversion 208 Data I/O 100 TYP MAX UNITS ns 40 60 % SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 40 ns CS Rise to DOUT Disable tDOD CLOAD = 30pF 40 ns CS Fall to DOUT Enable tDOE CLOAD = 30pF 40 ns 40 ns 40 ns DIN to SCLK Rise Setup tDS SCLK Rise to DIN Hold tDH CS to SCLK Rise Setup tCSS SCLK Rise to CS Hold tCSH CNVST Pulse Width tCSW 0 0 tTS CS or CNVST Rise to EOC Low (Note 9) ns ns CKSEL = 00, CKSEL = 01 (temp sense) 40 ns CKSEL = 01 (voltage conversion) 1.4 µs Temp sense 55 Voltage conversion 7 Reference power-up 65 µs Note 9: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal reference needs to be powered up, the total time is additive. The internal reference is always used for temperature measurements. Typical Operating Characteristics (VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 OUTPUT CODE 3072 4096 0.8 0.6 0.4 90 80 AMPLITUDE (dB) 0.6 SINAD vs. FREQUENCY 100 MAX1227/29/31 toc02 INTEGRAL NONLINEARITY (LSB) 0.8 1.0 DIFFERENTIAL NONLINEARITY (LSB) MAX1227/29/31 toc01 1.0 DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.2 0 -0.2 70 60 50 40 -0.4 30 -0.6 20 -0.8 10 -1.0 MAX1227/29/31 toc03 INTEGRAL NONLINEARITY vs. OUTPUT CODE 0 0 1024 2048 OUTPUT CODE 3072 4096 0.1 1 10 100 1000 FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX1227/MAX1229/MAX1231 TIMING CHARACTERISTICS (Figure 1) Typical Operating Characteristics (continued) (VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT (μA) 600 80 60 40 500 400 700 0 1000 100 1 10 FREQUENCY (kHz) SUPPLY CURRENT vs. TEMPERATURE fS = 300ksps SUPPLY CURRENT (μA) 0.4 3.3 625 MAX1227/29/31 toc07 0.5 SHUTDOWN SUPPLY CURRENT (μA) 3.0 SUPPLY VOLTAGE (V) SAMPLING RATE (ksps) SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.3 0.2 620 615 610 0.1 0 605 2.7 3.0 3.3 3.6 -40 -15 10 35 60 SUPPLY VOLTAGE (V) TEMPERATURE (°C) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE 0.4 0.3 0.2 0.1 0 2.4990 INTERNAL REFERENCE VOLTAGE (V) MAX1227/29/31 toc09 0.5 SHUTDOWN SUPPLY CURRENT (μA) 2.7 1000 100 MAX1227/29/31 toc08 10 85 MAX1227/29/31 toc10 1 600 500 200 0.1 650 550 300 20 MAX1227/29/31 toc06 MAX1227/29/31 toc05 MAX1227/29/31 toc04 100 2.4986 2.4982 2.4978 2.4974 2.4970 -40 -15 10 35 TEMPERATURE (°C) 6 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SAMPLING RATE 700 SUPPLY CURRENT (μA) SFDR vs. FREQUENCY 120 AMPLITUDE (dB) MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference 60 85 2.7 3.0 3.3 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.6 3.6 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.502 2.498 2.494 0.1 0 -0.1 -0.2 2.490 -15 10 35 60 85 3.0 3.3 -0.1 -40 3.6 -15 35 60 85 GAIN ERROR vs. TEMPERATURE 1.5 GAIN ERROR (LSB) 1.0 MAX1227/29/31 toc15 2.0 MAX1227/29/31 toc14 1.5 10 TEMPERATURE (°C) GAIN ERROR vs. SUPPLY VOLTAGE 1.0 0.5 0.5 0 2.7 3.0 -40 -15 10 35 60 SUPPLY VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE SENSOR ERROR vs. TEMPERATURE SAMPLING ERROR vs. SOURCE IMPEDANCE 0.75 0.50 GRADE A 0.25 0 -0.25 GRADE B 1 0 SAMPLING ERROR (LSB) MAX1227/29/31 toc16 1.00 -0.50 0 3.6 3.3 85 MAX1227/29/31 toc17 GAIN ERROR (LSB) 0 SUPPLY VOLTAGE (V) 2.0 TEMPERATURE SENSOR ERROR (°C) 0.1 -0.3 2.7 TEMPERATURE (°C) -1 -2 -3 -4 -0.75 -1.00 0.2 -0.2 -0.3 -40 MAX1227/29/31 toc13 0.3 OFFSET ERROR (LSB) 0.2 OFFSET ERROR (LSB) 2.506 0.4 MAX1227/29/31 toc12 0.3 MAX1227/29/31 toc11 2.510 INTERNAL REFERENCE VOLTAGE (V) OFFSET ERROR vs. TEMPERATURE OFFSET ERROR vs. SUPPLY VOLTAGE -5 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 2 4 6 8 10 SOURCE IMPEDANCE (kΩ) _______________________________________________________________________________________ 7 MAX1227/MAX1229/MAX1231 Typical Operating Characteristics (continued) (VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Pin Description MAX1231 TQFN-EP MAX1231 QSOP MAX1229 MAX1227 NAME 2–12, 26, 27, 28, 1–14 — — AIN0–13 Analog Inputs — — 1–10 — AIN0–9 Analog Inputs — — — 1–6 AIN0–5 Analog Inputs 13 15 — — REF-/AIN14 Negative Input for External Differential Reference/Analog Input 14. See Table 3 for details on programming the setup register. — — 11 — REF-/AIN10 Negative Input for External Differential Reference/Analog Input 10. See Table 3 for details on programming the setup register. — — — 7 REF-/AIN6 Negative Input for External Differential Reference/Analog Input 6. See Table 3 for details on programming the setup register. 14 16 — — CNVST/ AIN15 Active-Low Conversion Start Input/Analog Input 15. See Table 3 for details on programming the setup register. — — 12 — CNVST/ AIN11 Active-Low Conversion Start Input/Analog Input 11. See Table 3 for details on programming the setup register. — — — 8 CNVST/ AIN7 Active-Low Conversion Start Input/Analog Input 7. See Table 3 for details on programming the setup register. Positive Reference Input. Bypass to GND with a 0.1μF capacitor. 15 17 13 9 REF+ 16 18 14 10 GND Ground 18 19 15 11 VDD Power Input. Bypass to GND with a 0.1μF capacitor. 20 20 16 12 SCLK 21 21 17 13 CS Active-Low Chip Select Input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high impedance. 22 22 18 14 DIN Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK. 23 23 19 15 DOUT Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is connected to VDD. 24 24 20 16 EOC End of Conversion Output. Data is valid after EOC pulls low. — — — N.C. No Connection. Not internally connected. — — — EP 1, 17, 19, 25 — 8 FUNCTION Serial Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be 40% to 60%.) See Table 3 for details on programming the clock mode. Exposed Pad (TQFN Only). Connect to GND. _______________________________________________________________________________________ 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference MAX1227/MAX1229/MAX1231 CS tCP tCH tCSS tCSH tCSH tCSS SCLK tDH tDS DIN tDOT tDOD tDOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK SERIAL INTERFACE OSCILLATOR CONTROL DOUT EOC CNVST AIN1 AIN2 T/H AIN15 12-BIT SAR ADC FIFO AND ACCUMULATOR TEMP SENSE REFREF+ INTERNAL REFERENCE MAX1227 MAX1229 MAX1231 Figure 2. Functional Diagram Detailed Description The MAX1227/MAX1229/MAX1231 are low-power, serial-output, multichannel ADCs with temperature-sensing capability for temperature-control, process-control, and monitoring applications. These 12-bit ADCs have internal track and hold (T/H) circuitry that supports singleended and fully differential inputs. Data is converted from an internal temperature sensor or analog voltage sources in a variety of channel and data-acquisition configurations. Microprocessor (µP) control is made easy through a 3-wire SPI-/QSPI/ MICROWIRE-compatible serial interface. Figure 2 shows a simplified functional diagram of the MAX1227/MAX1229/MAX1231 internal architecture. The MAX1227 has eight single-ended analog input channels or four differential channels. The MAX1229 has 12 single-ended analog input channels or six differential channels. The MAX1231 has 16 single-ended analog input channels or eight differential channels. _______________________________________________________________________________________ 9 MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Converter Operation The MAX1227/MAX1229/MAX1231 ADCs use a fully differential, successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert temperature and voltage signals into a 12-bit digital result. Both single-ended and differential configurations are supported, with a unipolar signal range for singleended mode and bipolar or unipolar ranges for differential mode. Input Bandwidth The ADC’s input-tracking circuitry has a 1MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest. Analog Input Protection Internal ESD protection diodes clamp all pins to VDD and GND, allowing the inputs to swing from (GND 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than GND by 50mV. If an off-channel analog input voltage exceeds the supplies, limit the input current to 2mA. Tables 1–7 detail the register descriptions. Bits 5 and 4, CKSEL1 and CKSEL0, respectively, control the clock modes in the setup register (see Table 3). Choose between four different clock modes for various ways to start a conversion and determine whether the acquisitions are internally or externally timed. Select clock mode 00 to configure CNVST/AIN_ to act as a conversion start and use it to request the programmed, internally timed conversions without tying up the serial bus. In clock mode 01, use CNVST to request conversions one channel at a time, controlling the sampling speed without tying up the serial bus. Request and start internally timed conversions through the serial interface by writing to the conversion register in the default clock mode 10. Use clock mode 11 with SCLK up to 4.8MHz for externally timed acquisitions to achieve sampling rates up to 300ksps. Clock mode 11 disables scanning and averaging. See Figures 4–7 for timing specifications and how to begin a conversion. These devices feature an active-low, end-of-conversion output. EOC goes low when the ADC completes the lastrequested operation and is waiting for the next input data byte (for clock modes 00 and 10). In clock mode 01, EOC goes low after the ADC completes each requested operation. EOC goes high when CS or CNVST goes low. EOC is always high in clock mode 11. 3-Wire Serial Interface Single-Ended/Differential Input The MAX1227/MAX1229/MAX1231 feature a serial interface compatible with SPI/QSPI and MICROWIRE devices. For SPI/QSPI, ensure the CPU serial interface runs in master mode so it generates the serial clock signal. Select the SCLK frequency of 10MHz or less, and set clock polarity (CPOL) and phase (CPHA) in the µP control registers to the same value. The MAX1227/ MAX1229/MAX1231 operate with SCLK idling high or low, and thus operate with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch input data at DIN on the rising edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK. Bipolar true differential results and temperature sensor results are available in two’s complement format, while all others are in binary. The MAX1227/MAX1229/MAX1231 use a fully differential ADC for all conversions. The analog inputs can be configured for either differential or single-ended conversions by writing to the setup register (see Table 3). Single-ended conversions are internally referenced to GND (see Figure 3). In differential mode, the T/H samples the difference between two analog inputs, eliminating common-mode DC offsets and noise. IN+ and IN- are selected from the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13, and AIN14/AIN15. AIN0–AIN7 are available on the MAX1227, MAX1229, and MAX1231. AIN8–AIN11 are only available on the MAX1229 and MAX1231. AIN12–AIN15 are only available on the MAX1231. See Tables 2–5 for more details on configuring the inputs. For the inputs that can be configured as CNVST or an analog input, only one can be used at a time. For the inputs that can be configured as REF- or an analog input, the REF- configuration excludes the analog input. Serial communication always begins with an 8-bit input data byte (MSB first) loaded from DIN. Use a second byte, immediately following the setup byte, to write to the unipolar mode or bipolar mode registers (see Tables 1, 3, 4, and 5). A high-to-low transition on CS initiates the data input operation. The input data byte and the subsequent data bytes are clocked from DIN into the serial interface on the rising edge of SCLK. 10 ______________________________________________________________________________________ 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference CIN+ DAC COMPARATOR + HOLD GND (SINGLE ENDED); AIN1, AIN3, AIN5…AIN15 (DIFFERENTIAL) CIN- HOLD HOLD VDD/2 Figure 3. Equivalent Input Circuit Unipolar/Bipolar Address the unipolar and bipolar registers through the setup register (bits 1 and 0). Program a pair of analog channels for differential operation by writing a 1 to the appropriate bit of the bipolar or unipolar register. Unipolar mode sets the differential input range from 0 to VREF. A negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to ±VREF/2. The digital output code is binary in unipolar mode and two’s complement in bipolar mode (Figures 8 and 9). In single-ended mode, the MAX1227/MAX1229/ MAX1231 always operate in unipolar mode. The analog inputs are internally referenced to GND with a full-scale input range from 0 to VREF. True Differential Analog Input T/H The equivalent circuit of Figure 3 shows the MAX1227/ MAX1229/MAX1231s’ input architecture. In track mode, a positive input capacitor is connected to AIN0–AIN15 in single-ended mode (and AIN0, AIN2, AIN4…AIN14 in differential mode). A negative input capacitor is connected to GND in single-ended mode (or AIN1, AIN3, AIN5…AIN15 in differential mode). For external T/H timing, use clock mode 01. After the T/H enters hold mode, the difference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. If the input signal’s source impedance is high, the required acquisition time lengthens. The acquisition ⎛ THD = 20 x log ⎜ ⎝ (V 2 2 ) ⎞ + V32 + V42 + V52 / V1⎟ ⎠ where RIN = 1.5kΩ, RS is the source impedance of the input signal, and tPWR = 1µs, the power-up time of the device. The varying power-up times are detailed in the explanation of the clock mode conversions. tACQ is never less than 1.4µs, and any source impedance below 300Ω does not significantly affect the ADC’s AC performance. A high-impedance source can be accommodated either by lengthening tACQ or by placing a 1µF capacitor between the positive and negative analog inputs. Internal FIFO The MAX1227/MAX1229/MAX1231 contain a FIFO buffer that can hold up to 16 ADC results plus one temperature result. This allows the ADC to handle multiple internally clocked conversions and a temperature measurement, without tying up the serial bus. If the FIFO is filled and further conversions are requested without reading from the FIFO, the oldest ADC results are overwritten by the new ADC results. Each result contains 2 bytes, with the MSB preceded by four leading zeros. After each falling edge of CS, the oldest available byte of data is available at DOUT, MSB first. When the FIFO is empty, DOUT is zero. The first 2 bytes of data read out after a temperature measurement always contain the temperature result preceded by four leading zeros, MSB first. If another temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result. Temperature results are in degrees Celsius (two’s complement) at a resolution of 1/8 of a degree. See the Temperature Measurements section for details on converting the digital code to a temperature. Internal Clock The MAX1227/MAX1229/MAX1231 operate from an internal oscillator, which is accurate within 10% of the 4.4MHz nominal clock rate. The internal oscillator is active in clock modes 00, 01, and 10. Read out the data at clock speeds up to 10MHz. See Figures 4–7 for details on timing specifications and starting a conversion. ______________________________________________________________________________________ 11 MAX1227/MAX1229/MAX1231 REF GND AIN0-AIN15 (SINGLE ENDED); AIN0, AIN2, AIN4…AIN14 (DIFFERENTIAL) time, tACQ, is the maximum time needed for a signal to be acquired, plus the power-up time. It is calculated by the following equation: MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Applications Information Register Descriptions The MAX1227/MAX1229/MAX1231 communicate between the internal registers and the external circuitry through the SPI-/QSPI-compatible serial interface. Table 1 details the registers and the bit names. Tables 2–7 show the various functions within the conversion register, setup register, averaging register, reset register, unipolar register, and bipolar register. Conversion Time Calculations The conversion time for each scan is based on a number of different factors: conversion time per sample, samples per result, results per scan, if a temperature measurement is requested, and if the external reference is in use. Use the following formula to calculate the total conversion time for an internally timed conversion in clock modes 00 and 10 (see the Electrical Characteristics section as applicable): total conversion time = tcnv x navg x nresult + tTS + tRP where: tcnv = tacq(max) + tconv(max) navg = samples per result (amount of averaging) nresult = number of FIFO results requested; determined by number of channels being scanned or by NSCAN1, NSCAN0 tTS = time required for temperature measurement; set to zero if temp measurement is not requested tRP = internal reference wake up; set to zero if internal reference is already powered up or external reference is being used In clock mode 01, the total conversion time depends on how long CNVST is held low or high, including any time required to turn on the internal reference. Conversion time in externally clocked mode (CKSEL1, CKSEL0 = 11) depends on the SCLK period and how long CS is held high between each set of eight SCLK cycles. In clock mode 01, the total conversion time does not include the time required to turn on the internal reference. Conversion Register Select active analog input channels, scan modes, and a single temperature measurement per scan by writing to the conversion register. Table 2 details channel selection, the four scan modes, and how to request a temperature measurement. Request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the CNVST pin when in clock mode 00 or 01. A conversion is not performed if it is requested on a channel that has been configured as CNVST or REF-. Do not request conversions on channels 8–15 on the MAX1227 and channels 12–15 on the MAX1229. Set CHSEL3:CHSELO to the lower channel’s binary value. If the last two channels are configured as a differential pair and one of them has been reconfigured as CNVST or REF-, the pair is ignored. Select scan mode 00 or 01 to return one result per single-ended channel and one result per differential pair within the requested range, plus one temperature result if selected. Select scan mode 10 to scan a single input channel numerous times, depending on NSCAN1 and NSCAN0 in the averaging register (Table 6). Select scan mode 11 to return only one result from a single channel. Setup Register Write a byte to the setup register to configure the clock, reference, and power-down modes. Table 3 details the Table 1. Input Data Byte (MSB First) REGISTER NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Conversion 1 CHSEL3 CHSEL2 CHSEL1 CHSEL0 SCAN1 SCAN0 TEMP Setup 0 1 CKSEL1 CKSEL0 REFSEL1 REFSEL0 DIFFSEL1 DIFFSEL0 Averaging 0 0 1 AVGON NAVG1 NAVG0 NSCAN1 NSCAN0 X X X 0 0 0 1 RESET Unipolar mode (setup) UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9* Bipolar mode (setup) BCH0/1 BCH1/2 BCH4/5 BCH6/7 BCH8/9* Reset BIT 2 BIT 1 UCH10/11 UCH12/138** UCH14/15** BCH10/11 BCH12/13** BCH14/15** *Unipolar/bipolar channels 8–15 are only valid on the MAX1229 and MAX1231. *Unipolar/bipolar channels 12–15 are only valid on the MAX1231. X = Don’t care. 12 BIT 0 ______________________________________________________________________________________ 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference BIT NAME — BIT FUNCTION 7 (MSB) Set to 1 to select conversion register. CHSEL3 6 Analog input channel select. CHSEL2 5 Analog input channel select. CHSEL1 4 Analog input channel select. CHSEL0 3 Analog input channel select. SCAN1 2 Scan mode select. SCAN0 1 Scan mode select. TEMP Set to 1 to take a single temperature 0 (LSB) measurement. The first conversion result of a scan contains temperature information. * See below for bit details. CHSEL3 CHSEL2 CHSEL1 CHSEL0 SELECTED CHANNEL (N) 0 0 0 0 AIN0 0 0 0 1 AIN1 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AIN8 1 0 0 1 AIN9 1 0 1 0 AIN10 1 0 1 1 AIN11 1 1 0 0 AIN12 1 1 0 1 AIN13 1 1 1 0 AIN14 1 1 1 1 AIN15 SCAN1 SCAN0 SCAN MODE (CHANNEL N IS SELECTED BY BITS CHSEL3–CHSEL0) 0 0 Scans channels 0 through N. 0 1 Scans channels N through the highest numbered channel. 1 0 Scans channel N repeatedly. The averaging register sets the number of results. 1 1 No scan. Converts channel N once only. bits in the setup register. Bits 5 and 4 (CKSEL1 and CKSEL0) control the clock mode, acquisition and sampling, and the conversion start. Bits 3 and 2 (REFSEL1 and REFSEL0) control internal or external reference use. Bits 1 and 0 (DIFFSEL1 and DIFFSEL0) address the unipolar mode and bipolar mode registers and configure the analog input channels for differential operation. Unipolar/Bipolar Registers The final 2 bits (LSBs) of the setup register control the unipolar/bipolar mode address registers. Set bits 1 and 0 (DIFFSEL1 and DIFFSEL0) to 10 to write to the unipolar mode register. Set bits 1 and 0 to 11 to write to the bipolar mode register. In both cases, the setup byte must be followed immediately by 1 byte of data written to the unipolar register or bipolar register. Hold CS low and run 16 SCLK cycles before pulling CS high. If the last 2 bits of the setup register are 00 or 01, neither the unipolar mode register nor the bipolar mode register is written. Any subsequent byte is recognized as a new input data byte. See Tables 4 and 5 to program the unipolar and bipolar mode registers. If a channel is configured as both unipolar and bipolar, the unipolar setting takes precedence. In unipolar mode, AIN+ can exceed AIN- by up to VREF. The output format in unipolar mode is binary. In bipolar mode, either input can exceed the other by up to VREF/2. The output format in bipolar mode is two's complement. Averaging Register Write to the averaging register to configure the ADC to average up to 32 samples for each requested result, and to independently control the number of results requested for single-channel scans. Table 2 details the four scan modes available in the conversion register. All four scan modes allow averaging as long as the AVGON bit, bit 4 in the averaging register, is set to 1. Select scan mode 10 to scan the same channel multiple times. Clock mode 11 disables averaging. Reset Register Write to the reset register (as shown in Table 7) to clear the FIFO or to reset all registers to their default states. Set the RESET bit to 1 to reset the FIFO. Set the reset bit to zero to return the MAX1227/MAX1229/MAX1231 to the default power-up state. Power-Up Default State The MAX1227/MAX1229/MAX1231 power up with all blocks in shutdown, including the reference. All registers power up in state 00000000, except for the setup register, which powers up in clock mode 10 (CKSEL1 = 1). ______________________________________________________________________________________ 13 MAX1227/MAX1229/MAX1231 Table 2. Conversion Register MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Table 3. Setup Register BIT NAME BIT — 7 (MSB) FUNCTION Set to zero to select setup register. — 6 Set to 1 to select setup register. CKSEL1 5 Clock mode and CNVST configuration. Resets to 1 at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference mode configuration. REFSEL0 2 Reference mode configuration. DIFFSEL1 1 Unipolar/bipolar mode register configuration for differential mode. DIFFSEL0 0 (LSB) Unipolar/bipolar mode register configuration for differential mode. * See below for bit details. CKSEL1 CKSEL0 CONVERSION CLOCK ACQUISITION/SAMPLING CNVST CONFIGURATION 0 0 Internal Internally timed CNVST 0 1 Internal Externally timed through CNVST CNVST 1 0 Internal Internally timed AIN15/11/7 1 1 External (4.8MHz max) Externally timed through SCLK AIN15/11/7 REFSEL1 REFSEL0 VOLTAGE REFERENCE 0 0 Internal 0 1 1 AutoShutdown REF- CONFIGURATION Reference off after scan; need wake-up delay. AIN14/10/6 External single ended Reference off; no wake-up delay. AIN14/10/6 0 Internal Reference always on; no wake-up delay. AIN14/10/6 1 1 External differential Reference off; no wake-up delay. REF- DIFFSEL1 DIFFSEL0 0 0 No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged. 0 1 No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged. 1 0 One byte of data follows the setup byte and is written to the unipolar mode register. 1 1 One byte of data follows the setup byte and is written to the bipolar mode register. 14 FUNCTION ______________________________________________________________________________________ 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Output Data Format Figures 4–7 illustrate the conversion timing for the MAX1227/MAX1229/MAX1231. The 12-bit conversion result is output in MSB-first format with four leading zeros. DIN data is latched into the serial interface on the rising edge of SCLK. Data on DOUT transitions on the falling edge of SCLK. Conversions in clock modes 00 and 01 are initiated by CNVST. Conversions in clock modes 10 and 11 are initiated by writing an input data byte to the conversion register. Data is binary for unipolar mode and two’s complement for bipolar mode. Table 4. Unipolar Mode Register (Addressed Through Setup Register) BIT NAME BIT FUNCTION UCH0/1 7 (MSB) Set to 1 to configure AIN0 and AIN1 for unipolar differential conversion. UCH2/3 6 Set to 1 to configure AIN2 and AIN3 for unipolar differential conversion. UCH4/5 5 Set to 1 to configure AIN4 and AIN5 for unipolar differential conversion. UCH6/7 4 Set to 1 to configure AIN6 and AIN7 for unipolar differential conversion. UCH8/9 3 Set to 1 to configure AIN8 and AIN9 for unipolar differential conversion (MAX1229/MAX1231 only). UCH10/11 2 Set to 1 to configure AIN10 and AIN11 for unipolar differential conversion (MAX1229/MAX1231 only). UCH12/13 1 Set to 1 to configure AIN12 and AIN13 for unipolar differential conversion (MAX1231 only). UCH14/15 0 (LSB) Set to 1 to configure AIN14 and AIN15 for unipolar differential conversion (MAX1231 only). Table 5. Bipolar Mode Register (Addressed Through Setup Register) BIT NAME BIT BCH0/1 7 (MSB) Set to 1 to configure AIN0 and AIN1 for bipolar differential conversion. FUNCTION BCH2/3 6 Set to 1 to configure AIN2 and AIN3 for bipolar differential conversion. BCH4/5 5 Set to 1 to configure AIN4 and AIN5 for bipolar differential conversion. BCH6/7 4 Set to 1 to configure AIN6 and AIN7 for bipolar differential conversion. BCH8/9 3 Set to 1 to configure AIN8 and AIN9 for bipolar differential conversion (MAX1229/MAX1231 only). BCH10/11 2 Set to 1 to configure AIN10 and AIN11 for bipolar differential conversion (MAX1229/MAX1231 only). BCH12/13 1 Set to 1 to configure AIN12 and AIN13 for bipolar differential conversion (MAX1231 only). BCH14/15 0 (LSB) Set to 1 to configure AIN14 and AIN15 for bipolar differential conversion (MAX1231only). ______________________________________________________________________________________ 15 MAX1227/MAX1229/MAX1231 Temperature Measurements The MAX1227/MAX1229/MAX1231 perform temperature measurements with an internal diode-connected transistor. The diode bias current changes from 68µA to 4µA to produce a temperature-dependent bias voltage difference. The second conversion result at 4µA is subtracted from the first at 68µA to calculate a digital value that is proportional to absolute temperature. The output data appearing at DOUT is the above digital code minus an offset to adjust from Kelvin to Celsius. The reference voltage used for the temperature measurements is derived from the internal reference source to ensure that 1 LSB corresponds to 1/8 of a degree. MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Table 6. Averaging Register BIT NAME BIT FUNCTION — 7 (MSB) Set to zero to select averaging register. — 6 Set to zero to select averaging register. — 5 Set to 1 to select averaging register. AVGON 4 Set to 1 to turn averaging on. Set to zero to turn averaging off. NAVG1 3 Configures the number of conversions for single-channel scans. NAVG0 2 Configures the number of conversions for single-channel scans. NSCAN1 1 Single-channel scan count. (Scan mode 10 only.) NSCAN0 0 (LSB) Single-channel scan count. (Scan mode 10 only.) * See below for bit details. AVGON NAVG1 NAVG0 0 x x Performs 1 conversion for each requested result. FUNCTION 1 0 0 Performs 4 conversions and returns the average for each requested result. 1 0 1 Performs 8 conversions and returns the average for each requested result. 1 1 0 Performs 16 conversions and returns the average for each requested result. 1 1 1 Performs 32 conversions and returns the average for each requested result. NSCAN1 NSCAN0 0 0 Scans channel N and returns 4 results. 0 1 Scans channel N and returns 8 results. 1 0 Scans channel N and returns 12 results. 1 1 Scans channel N and returns 16 results. FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED) Table 7. Reset Register BIT NAME BIT — 7 (MSB) Set to zero to select reset register. — 6 Set to zero to select reset register. — 5 Set to zero to select reset register. — 4 Set to 1 to select reset register. RESET 3 Set to zero to reset all registers. Set to 1 to clear the FIFO only. x 2 Reserved. Don’t care. x 1 Reserved. Don’t care. x 0 (LSB) Reserved. Don’t care. 16 FUNCTION ______________________________________________________________________________________ 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Performing Conversions in Clock Mode 00 In clock mode 00, the wake-up, acquisition, conversion, and shutdown sequences are initiated through CNVST and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read out later. See Figure 4 for clock mode 00 timing. Initiate a scan by setting CNVST low for at least 40ns before pulling it high again. The MAX1227/MAX1229/ MAX1231 then wake up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. Wait until EOC goes low before pulling CS low to communicate with the serial interface. EOC stays low until CS or CNVST is pulled low again. A temperature measurement result, if requested, precedes all other FIFO results. Do not initiate a second CNVST before EOC goes low; otherwise, the FIFO can become corrupted. Externally Timed Acquisitions and Internally Timed Conversions with CNVST Performing Conversions in Clock Mode 01 In clock mode 01, conversions are requested one at a time using CNVST and performed automatically using the internal oscillator. See Figure 5 for clock mode 01 timing. Setting CNVST low begins an acquisition, wakes up the ADC, and places it in track mode. Hold CNVST low for at least 1.4µs to complete the acquisition. If internal reference needs to wake up, an additional 65µs is required for the internal reference to power up. If a temperature measurement is being requested, reference power-up and temperature measurement are internally timed. In this case, hold CNVST low for at least 40ns. Set CNVST high to begin a conversion. After the conversion is complete, the ADC shuts down and pulls EOC low. EOC stays low until CS or CNVST is pulled low again. Wait until EOC goes low before pulling CS or CNVST low. If averaging is turned on, multiple CNVST pulses need to be performed before a result is written to the FIFO. Once the proper number of conversions has been performed to generate an averaged FIFO result, as specified by the averaging register, the scan logic automatically switches the analog input multiplexer to the next-requested channel. If a temperature measurement is programmed, it is performed after the first rising edge of CNVST following the input data byte written to the conversion register. The result is available on DOUT once EOC has been pulled low. CNVST (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION. Figure 4. Clock Mode 00 ______________________________________________________________________________________ 17 MAX1227/MAX1229/MAX1231 Internally Timed Acquisitions and Conversions Using CNVST MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference CNVST (CONVERSION2) (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT LSB1 MSB1 MSB2 EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 (CONVERSION BYTE) DIN (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. Figure 6. Clock Mode 10 Internally Timed Acquisitions and Conversions Using the Serial Interface Performing Conversions in Clock Mode 10 In clock mode 10, the wake-up, acquisition, conversion, and shutdown sequences are initiated by writing an input data byte to the conversion register, and are performed automatically using the internal oscillator. This is the default clock mode upon power-up. See Figure 6 for clock mode 10 timing. 18 Initiate a scan by writing a byte to the conversion register. The MAX1227/MAX1229/MAX1231 then power up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. If a temperature measurement is requested, the temperature result precedes all other FIFO results. EOC stays low until CS is pulled low again. ______________________________________________________________________________________ 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference (ACQUISITION1) (CONVERSION1) (ACQUISITION2) CS SCLK DOUT MSB1 LSB1 MSB2 EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Externally Clocked Acquisitions and Conversions Using the Serial Interface Performing Conversions in Clock Mode 11 In clock mode 11, acquisitions and conversions are initiated by writing to the conversion register and are performed one at a time using the SCLK as the conversion clock. Scanning and averaging are disabled, and the conversion result is available at DOUT during the conversion. See Figure 7 for clock mode 11 timing. Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles. If CS is pulsed high between the eighth and ninth cycles, the pulse width must be less than 100µs. To continuously convert at 16 cycles per conversion, alternate 1 byte of zeros between each conversion byte. If reference mode 00 is requested, or if an external reference is selected but a temperature measurement is being requested, wait 65µs with CS high after writing the conversion byte to extend the acquisition and allow the internal reference to power up. To perform a temperature measurement, write 24 bytes (192 cycles) of zeros after the conversion byte. The temperature result appears on DOUT during the last 2 bytes of the 192 cycles. Partial Reads and Partial Writes If the first byte of an entry in the FIFO is partially read (CS is pulled high after fewer than eight SCLK cycles), the second byte of data that is read out contains the next 8 bits (not b7–b0). The remaining bits are lost for that entry. If the first byte of an entry in the FIFO is read out fully, but the second byte is read out partially, the rest of the entry is lost. The remaining data in the FIFO is uncorrupted and can be read out normally after taking CS low again, as long as the 4 leading bits (normally zeros) are ignored. Internal registers that are written partially through the SPI contain new values, starting at the MSB up to the point that the partial write is stopped. The part of the register that is not written contains previously written values. If CS is pulled low before EOC goes low, a conversion cannot be completed and the FIFO is corrupted. Transfer Function Figure 8 shows the unipolar transfer function for singleended or differential inputs. Figure 9 shows the bipolar transfer function for differential inputs. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1 LSB = VREF / 2.5V for unipolar and bipolar operation, and 1 LSB = 0.125°C for temperature measurements. Layout, Grounding, and Bypassing For best performance, use PC boards. Do not use wirewrap boards. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) signals parallel to one another or run digital lines underneath the MAX1227/MAX1229/MAX1231 package. High-frequency noise in the VDD power supply can affect performance. Bypass the VDD supply with a 0.1µF capacitor to GND, close to the VDD pin. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, connect a 10Ω resistor in series with the supply to improve power-supply filtering. For the TQFN package, connect its exposed pad to ground. ______________________________________________________________________________________ 19 MAX1227/MAX1229/MAX1231 (CONVERSION BYTE) DIN MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference OUTPUT CODE OUTPUT CODE FULL-SCALE TRANSITION 11 . . . 111 11 . . . 110 11 . . . 101 011 . . . 111 V FS = REF + VCOM 2 011 . . . 110 ZS = COM 000 . . . 010 000 . . . 001 FS = VREF + VCOM ZS = VCOM V 1 LSB = REF 4096 00 . . . 011 00 . . . 010 -VREF + VCOM 2 V 1 LSB = REF 4096 -FS = 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 00 . . . 001 100 . . . 000 00 . . . 000 0 1 (COM) 2 3 FS INPUT VOLTAGE (LSB) FS - 3/2 LSB *VCOM ≥ VREF / 2 Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1227/MAX1229/MAX1231 is measured using the end-point method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture Delay Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quanti20 - FS COM* +FS - 1 LSB INPUT VOLTAGE (LSB) Figure 9. Bipolar Transfer Function, Full Scale (±FS) = ±VREF / 2 zation error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD (dB) = 20 x log (SignalRMS / NoiseRMS) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02 ______________________________________________________________________________________ 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference AIN9 10 15 REF-/AIN14 AIN10 11 14 AIN13 AIN11 12 13 AIN12 AIN0 N.C. EOC DOUT DIN 26 25 24 23 22 18 VDD AIN5 4 AIN6 5 17 N.C. AIN7 6 16 GND AIN8 7 15 REF+ 14 16 CNVST/AIN15 N.C. MAX1231 CNVST/AIN15 AIN8 9 SCLK 19 13 17 REF+ 20 3 REF-/AIN14 AIN7 8 2 AIN4 12 18 GND AIN3 AIN13 AIN6 7 CS 11 19 VDD 21 AIN12 AIN5 6 1 10 20 SCLK N.C. AIN11 MAX1231 AIN4 5 AIN1 21 CS AIN2 AIN3 4 27 22 DIN 9 23 DOUT AIN2 3 8 AIN1 2 AIN9 24 EOC AIN10 AIN0 1 28 TOP VIEW TQFN QSOP Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: ⎛ THD = 20 x log ⎜ ⎝ (V 2 2 + V32 + V42 + V52 ) ⎞ / V1⎟ ⎠ Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE MAX1231BCEG-T 0°C to +70°C 24 QSOP MAX1231BEEG-T -40°C to +85°C MAX1231BCTI-T 0°C to +70°C 28 TQFN-EP* MAX1231BETI-T -40°C to +85°C 28 TQFN-EP* 24 QSOP *EP = Exposed paddle. (Connect to GND.) where V1 is the fundamental amplitude, and V2–V5 are the amplitudes of the first five harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. Chip Information TRANSISTOR COUNT: 30,889 PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE 16 QSOP E16-1 20 QSOP E20-1 24 QSOP E24-1 28 TQFN-EP T2855-6 DOCUMENT NO. 21-0055 21-0140 ______________________________________________________________________________________ 21 MAX1227/MAX1229/MAX1231 Pin Configurations (continued) MAX1227/MAX1229/MAX1231 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference Revision History REVISION NUMBER REVISION DATE 3 2/10 DESCRIPTION Removed the A grade products from the Ordering Information table and Electrical Characteristics table. PAGES CHANGED 1, 3, 21 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.