ASM5P23S04A September 2005 rev 1.3 3.3V ‘SpreadTrak’ Zero Delay Buffer Features the REF pin. The PLL feedback is required to be driven to Zero input - output propagation delay, adjustable FBK pin, and can be obtained from one of the outputs. The by capacitive load on FBK input. input-to-output propagation delay is guaranteed to be less Multiple configurations - Refer “ASM5P23S04A than 250pS, and the output-to-output skew is guaranteed to Configurations Table”. be less than 200pS. Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. The ASM5P23S04A has two banks of two outputs each. Output-output skew less than 200pS. Multiple ASM5P23S04A devices can accept the same input Device-device skew less than 500pS. clock and distribute it. In this case the skew between the Two banks of two outputs each. outputs of the two devices is guaranteed to be less than Less than 200pS Cycle-to-cycle jitter 500pS. Available in space saving, 8 pin 150-mil SOIC The (-1, -1H, -2, -2H). ASM5P23S04A (Refer is available in “ASM5P23S04A two different package. configurations 3.3V operation. Table). The ASM5P23S04A-1 is the base part, where the Configurations Advanced 0.35µ CMOS technology. output frequencies equal the reference if there is no Industrial temperature available. counter in the feedback path. The ASM5P23S04A-1H is ‘SpreadTrak’. the high-drive version of the -1 and the rise and fall times on this device are much faster. Functional Description ASM5P23S04A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in a 8 pin package. The part has The ASM5P23S04A-2 allows the user to obtain REF and 1/2X or 2X frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. an on-chip PLL, which locks to an input clock, presented on Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 Alliance Semiconductor 2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. ASM5P23S04A September 2005 rev 1.3 ASM5P23S04A Configurations Device Feedback From Bank A Frequency ASM5P23S04A-1 Bank A or Bank B Reference Reference ASM5P23S04A-1H Bank A or Bank B Reference Reference ASM5P23S04A-2 Bank A Reference Reference /2 ASM5P23S04A-2 Bank B 2 X Reference Reference ASM5P23S04A-2H Bank A Reference Reference/2 ASM5P23S04A-2H Bank B 2 X Reference Reference ‘SpreadTrak’ Bank B Frequency assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature through, Many systems being designed now utilize a technology the result is a significant amount of tracking skew which called Spread Spectrum Frequency Timing Generation. may ASM5P23S04A is designed so as not to filter off the cause problems in the systems requiring synchronization. Spread Spectrum feature of the Reference Input, 1500 REF-Input to CLKA/CLKB Delay (ps) 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 15 ASM5P23S04A September 2005 rev 1.3 Zero Delay and Skew Control output delay. This is shown in the above graph. For For applications requiring zero input-output delay, all outputs must be equally loaded. To close the feedback loop of ASM5P23S04A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. respect to the remaining outputs) can adjust the input Pin Configuration 8 FBK REF 1 CLKA1 2 ASM5P23S04A 7 VDD CLKA2 3 6 CLKB2 GND 4 5 CLKB1 Pin Description for ASM5P23S04A Pin # Pin Name Description 1 REF1 2 CLKA12 Buffered clock output, bank A 3 CLKA22 Buffered clock output, bank A 4 GND 5 CLKB12 Buffered clock output, bank B 6 CLKB2 2 Buffered clock output, bank B 7 VDD 3.3V supply 8 FBK PLL feedback input Input reference frequency, 5V tolerant input Ground Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 15 ASM5P23S04A September 2005 rev 1.3 Absolute Maximum Ratings Parameter Min Max Unit Supply Voltage to Ground Potential -0.5 +7.0 V DC Input Voltage (Except REF) -0.5 VDD + 0.5 V DC Input Voltage (REF) -0.5 7 V Storage Temperature -65 +150 °C Max. Soldering Temperature (10 sec) 260 °C Junction Temperature 150 °C >2000 V Static Discharge Voltage (As per JEDEC STD22- A114-B) Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P23S04A Commercial Temperature Devices Parameter Description Min Max Unit 3.0 3.6 V 0 70 °C VDD Supply Voltage TA Operating Temperature (Ambient Temperature) CL Load Capacitance, below 100MHz 30 pF CL Load Capacitance, from 100MHz to 133MHz 15 pF CIN Input Capacitance3 7 pF Note: 3. Applies to both Ref Clock and FBK. 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 15 ASM5P23S04A September 2005 rev 1.3 Electrical Characteristics for ASM5P23S04A Commercial Temperature Devices Parameter Description Test Conditions Min Max Unit 0.8 V VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50.0 µA IIH Input HIGH Current VIN = VDD 100.0 µA 0.4 V 2.0 VOL Output LOW Voltage 4 VOH Output HIGH Voltage 4 IOL = 8mA (-1, -2) IOH = 12mA (-1H, -2H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -2H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) V 2.4 V 45.0 32.0 mA 18.0 Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 15 ASM5P23S04A September 2005 rev 1.3 Switching Characteristics for ASM5P23S04A Commercial Temperature Devices Parameter Description Test Conditions Min Typ Max Unit 1/t1 Output Frequency 30pF load, All devices 15 100 MHz 1/t1 Output Frequency 15pF load, -1H, -2H devices 15 133 MHz 1/t1 Output Frequency 15pF load, -1, -2 devices 15 133 MHz 5 Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -2H) Measured at 1.4V, FOUT = 66.66MHz 30pF load 40.0 50.0 60.0 % Duty Cycle 5 = (t2 / t1) * 100 (-1, -2,-1H, -2H) Measured at 1.4V, FOUT = <50MHz 15 pF load 45.0 50.0 55.0 % t3 Output Rise Time 5 (-1, -2) Measured between 0.8V and 2.0V 30pF load 2.20 nS t3 Output Rise Time 5 (-1, -2) Measured between 0.8V and 2.0V 15pF load 1.50 nS t3 Output Rise Time 5 (-1H, -2H) Measured between 0.8V and 2.0V 30pF load 1.50 nS t4 Output Fall Time 5 (-1, -2) Measured between 2.0V and 0.8V 30pF load 2.20 nS t4 Output Fall Time 5 (-1, -2) Measured between 2.0V and 0.8V 15pF load 1.50 nS t4 Output Fall Time 5 (-1H, -2H) Measured between 2.0V and 0.8V 30pF load 1.25 nS Output-to-output skew on same bank (-1, -2) 5 All outputs equally loaded 200 Output-to-output skew (-1H, -2H) All outputs equally loaded 200 Output bank A -to- output bank B skew (-1, -2H) All outputs equally loaded 200 Output bank A to output bank B skew (-2) All outputs equally loaded 400 t6 Delay, REF Rising Edge to FBK Rising Edge 5 Measured at VDD /2 0 ±250 pS t7 Device-to-Device Skew 5 Measured at VDD/2 on the FBK pins of the device 0 500 pS t8 Output Slew Rate5 Measured between 0.8V and 2.0V using Test Circuit #2 t5 tJ tJ tLOCK Cycle-to-cycle jitter 5 (-1, -1H, -2H) Cycle-to-cycle jitter 5 (-2) PLL Lock Time 5 1 pS V/nS Measured at 66.67MHz, loaded outputs, 15pF load 175 Measured at 66.67MHz, loaded outputs, 30pF load 200 Measured at 133MHz, loaded outputs, 15pF load 100 Measured at 66.67MHz, loaded outputs, 30pF load 400 pS pS Measured at 66.67MHz, loaded outputs, 15pF load 375 Stable power supply, valid clock presented on REF and FBK pins 1.0 Note: 5. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 15 mS ASM5P23S04A September 2005 rev 1.3 Operating Conditions for ASM5I23S04A Industrial Temperature Devices Parameter Description Min Max Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) -40 85 °C CL Load Capacitance, below 100MHz 30 pF CL Load Capacitance, from 100MHz to 133MHz 15 pF CIN Input Capacitance 7 pF 6 Note: 6. Applies to both Ref Clock and FBK. Electrical Characteristics for ASM5I23S04A Industrial Temperature Devices Parameter Description Test Conditions Min Max Unit 0.8 V VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50.0 µA IIH Input HIGH Current VIN = VDD 100.0 µA 0.4 V VOL Output LOW Voltage VOH Output HIGH Voltage 2.0 7 IOL = 8mA (-1, -2) IOH = 12mA (-1H, -2H) 7 IOL = -8mA (-1, -2) IOH = -12mA (-1H, -2H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND IDD V 2.4 V 45.0 Supply Current mA Unloaded outputs, 66MHz REF (-1, -2) 35.0 Unloaded outputs, 33MHz REF (-1, -2) 20.0 Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 15 ASM5P23S04A September 2005 rev 1.3 Switching Characteristics for ASM5I23S04A Industrial Temperature Devices Parameter Description Test Conditions Min Typ Max Unit t1 Output Frequency 30pF load, All devices 15 100 MHz t1 Output Frequency 15pF load, -1H, -2H devices 15 133 MHz t1 Output Frequency 15pF load, -1 and -2 devices 15 133 MHz Duty Cycle 8 = (t2 / t1) * 100 (-1, -2, -1H, -2H) Measured at 1.4V, FOUT = <66.66MHz 30pF load 40.0 50.0 60.0 % Duty Cycle 8= (t2 / t1) * 100 (-1, -2, -1H, -2H) Measured at 1.4V, FOUT = <50MHz 15pF load 45.0 50.0 55.0 % t3 Output Rise Time 8 (-1, -2) Measured between 0.8V and 2.0V 30pF load 2.50 nS t3 Output Rise Time 8 (-1, -2) Measured between 0.8V and 2.0V 15pF load 1.50 nS t3 Output Rise Time 8 (-1H, -2H) Measured between 0.8V and 2.0V 30pF load 1.50 nS t4 Output Fall Time 8 (-1, -2) Measured between 2.0V and 0.8V 30pF load 2.50 nS t4 Output Fall Time 8 (-1, -2) Measured between 2.0V and 0.8V 15pF load 1.50 nS t4 Output Fall Time 8 (-1H, -2H) Measured between 2.0V and 0.8V 30pF load 1.25 nS Output-to-output skew on same bank (-1, -2) 8 All outputs equally loaded 200 Output-to-output skew (-1H, -2H) All outputs equally loaded 200 Output bank A -to- output bank B skew (-1, -2H) All outputs equally loaded 200 Output bank A -to- output bank B skew (-2) All outputs equally loaded 400 t6 Delay, REF Rising Edge to FBK Rising Edge 8 Measured at VDD /2 0 ±250 pS t7 Device-to-Device Skew 8 Measured at VDD/2 on the FBK pins of the device 0 500 pS t8 Output Slew Rate8 Measured between 0.8V and 2.0V using Test Circuit #2 t5 tJ tJ tLOCK Cycle-to-cycle jitter 8 (-1, -1H, -2H) Cycle-to-cycle jitter 8 (-2) PLL Lock Time 8 1 pS V/nS Measured at 66.67MHz, loaded outputs, 15pF load 180 Measured at 66.67MHz, loaded outputs, 30pF load 200 Measured at 133MHz, loaded outputs, 15pF load 100 Measured at 66.67MHz, loaded outputs, 30pF load 400 Measured at 66.67 MHz, loaded outputs, 15pF load 380 Stable power supply, valid clock presented on REF and FBK pins 1.0 pS pS Note: 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 15 mS ASM5P23S04A September 2005 rev 1.3 Switching Waveforms Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time OUTPUT 2.0 V 0.8 V 2.0 V 0.8 V 3.3 V 0V t4 t3 Output - Output Skew 1.4 V OUTPUT1 1.4 V OUTPUT2 t 5 Input - Output Propagation Delay VDD /2 INPUT VDD /2 OUTPUT t6 Device - Device Skew VDD /2 CLKOUT, Device 1 VDD /2 CLKOUT, Device 2 t 7 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 15 ASM5P23S04A September 2005 rev 1.3 Test Circuits TEST CIRCUIT # 2 TEST CIRCUIT # 1 VDD VDD CLKOUT 0.1uF CLOAD VDD 0.1uF 0.1uF OUTPUT GND GND 1KΩ OUTPUT 1KΩ VDD 0.1uF GND GND For parameter t8 (output skew rate) 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 15 10pF ASM5P23S04A September 2005 rev 1.3 Package Information 8-lead (150-mil) SOIC Package H E D A2 A C A1 D θ e L B Dimensions Symbol Inches Min Max Millimeters Min Max A1 0.004 0.010 0.10 0.25 A 0.053 0.069 1.35 1.75 A2 0.049 0.059 1.25 1.50 B 0.012 0.020 0.31 0.51 C 0.007 0.010 0.18 0.25 D 0.193 BSC 4.90 BSC E 0.154 BSC 3.91 BSC e 0.050 BSC 1.27 BSC H 0.236 BSC 6.00 BSC L 0.016 0.050 0.41 1.27 θ 0° 8° 0° 8° 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 15 ASM5P23S04A September 2005 rev 1.3 Ordering Codes Ordering Code Marking Package Type Operating Range ASM5P23S04A-1-08-SR 5P23S04A-1 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5P23S04A-1-08-ST 5P23S04A-1 8-pin 150-mil SOIC-TUBE Commercial ASM5I23S04A-1-08-SR 5I23S04A-1 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5I23S04A-1-08-ST 5I23S04A-1 8-pin 150-mil SOIC-TUBE Industrial ASM5P23S04A-1H-08-SR 5P23S04A-1H 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5P23S04A-1H-08-ST 5P23S04A-1H 8-pin 150-mil SOIC-TUBE Commercial ASM5I23S04A-1H-08-SR 5I23S04A-1H 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5I23S04A-1H-08-ST 5I23S04A-1H 8-pin 150-mil SOIC-TUBE Industrial ASM5P23S04A-2-08-SR 5P23S04A-2 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5P23S04A-2-08-ST 5P23S04A-2 8-pin 150-mil SOIC-TUBE Commercial ASM5I23S04A-2-08-SR 5I23S04A-2 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5I23S04A-2-08-ST 5I23S04A-2 8-pin 150-mil SOIC-TUBE Industrial ASM5P23S04A-2H-08-SR 5P23S04A-2H 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5P23S04A-2H-08-ST 5P23S04A-2H 8-pin 150-mil SOIC-TUBE Commercial ASM5I23S04A-2H-08-SR 5I23S04A-2H 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5I23S04A-2H-08-ST 5I23S04A-2H 8-pin 150-mil SOIC-TUBE Industrial ASM5P23S04AF-1-08-SR 5P23S04AF-1 8-pin 150-mil SOIC-TAPE & REEL, Pb free Commercial ASM5P23S04AF-1-08-ST 5P23S04AF-1 8-pin 150-mil SOIC-TUBE, Pb free Commercial ASM5I23S04AF-1-08-SR 5I23S04AF-1 8-pin 150-mil SOIC-TAPE & REEL, Pb free Industrial ASM5I23S04AF-1-08-ST 5I23S04AF-1 8-pin 150-mil SOIC-TUBE, Pb free Industrial 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 15 ASM5P23S04A September 2005 rev 1.3 Ordering Codes (cont’d) Ordering Code Marking Package Type Operating Range ASM5P23S04AF-1H-08-SR 5P23S04AF-1H 8-pin 150-mil SOIC-TAPE & REEL, Pb free Commercial ASM5P23S04AF-1H-08-ST 5P23S04AF-1H 8-pin 150-mil SOIC-TUBE, Pb free Commercial ASM5I23S04AF-1H-08-SR 5I23S04AF-1H 8-pin 150-mil SOIC-TAPE & REEL, Pb free Industrial ASM5I23S04AF-1H-08-ST 5I23S04AF-1H 8-pin 150-mil SOIC-TUBE, Pb free Industrial ASM5P23S04AF-2-08-SR 5P23S04AF-2 8-pin 150-mil SOIC-TAPE & REEL, Pb free Commercial ASM5P23S04AF-2-08-ST 5P23S04AF-2 8-pin 150-mil SOIC-TUBE, Pb free Commercial ASM5I23S04AF-2-08-SR 5I23S04AF-2 8-pin 150-mil SOIC-TAPE & REEL, Pb free Industrial ASM5I23S04AF-2-08-ST 5I23S04AF-2 8-pin 150-mil SOIC-TUBE, Pb free Industrial ASM5P23S04AF-2H-08-SR 5P23S04AF-2H 8-pin 150-mil SOIC-TAPE & REEL, Pb free Commercial ASM5P23S04AF-2H-08-ST 5P23S04AF-2H 8-pin 150-mil SOIC-TUBE, Pb free Commercial ASM5I23S04AF-2H-08-SR 5I23S04AF2H 8-pin 150-mil SOIC-TAPE & REEL, Pb free Industrial ASM5I23S04AF-2H-08-ST 5I23S04AFH 8-pin 150-mil SOIC-TUBE, Pb free Industrial ASM5P23S04AG-1-08-SR 5P23S04AG-1 8-pin 150-mil SOIC-TAPE & REEL, Green Commercial ASM5P23S04AG-1-08-ST 5P23S04AG-1 8-pin 150-mil SOIC-TUBE, Green Commercial ASM5I23S04AG-1-08-SR 5I23S04AG-1 8-pin 150-mil SOIC-TAPE & REEL, Green Industrial ASM5I23S04AG-1-08-ST 5I23S04AG-1 8-pin 150-mil SOIC-TUBE, Green Industrial ASM5P23S04AG-1H-08-SR 5P23S04AG-1H 8-pin 150-mil SOIC-TAPE & REEL, Green Commercial ASM5P23S04AG-1H-08-ST 5P23S04AG-1H 8-pin 150-mil SOIC-TUBE, Green Commercial ASM5I23S04AG-1H-08-SR 5I23S04AG-1H 8-pin 150-mil SOIC-TAPE & REEL, Green Industrial ASM5I23S04AG-1H-08-ST 5I23S04AG-1H 8-pin 150-mil SOIC-TUBE, Green Industrial 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 15 ASM5P23S04A September 2005 rev 1.3 Ordering Codes (cont’d) Ordering Code Marking Operating Package Type Range ASM5P23S04AG-2-08-SR 5P23S04AG-2 8-pin 150-mil SOIC-TAPE & REEL, Green Commercial ASM5P23S04AG-2-08-ST 5P23S04AG-2 8-pin 150-mil SOIC-TUBE, Green Commercial ASM5I23S04AG-2-08-SR 5I23S04AG-2 8-pin 150-mil SOIC-TAPE & REEL, Green Industrial ASM5I23S04AG-2-08-ST 5I23S04AG-2 8-pin 150-mil SOIC-TUBE, Green Industrial ASM5P23S04AG-2H-08-SR 5P23S04AG-2H 8-pin 150-mil SOIC-TAPE & REEL, Green Commercial ASM5P23S04AG-2H-08-ST 5P23S04AG-2H 8-pin 150-mil SOIC-TUBE, Green Commercial ASM5I23S04AG-2H-08-SR 5I23S04AG-2H 8-pin 150-mil SOIC-TAPE & REEL, Green Industrial ASM5I23S04AG-2H-08-ST 5I23S04AG-2H 8-pin 150-mil SOIC-TUBE, Green Industrial Device Ordering Information A S M 5 P 2 3 S 0 4 A F - 0 8 - S R R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 15 ASM5P23S04A September 2005 rev 1.3 Alliance Semiconductor Corporation 2575 Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM5P23S04A Document Version: 1.3 Note: This product utilizes US# 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3 Zero ‘SpreadTrak’ Delay Buffer Notice: The information in this document is subject to change without notice. 15 of 15