Mitsubishi M38B79MFH-A055 Single-chip 8-bit cmos microcomputerã ã ã Datasheet

MITSUBISHI MICROCOMPUTERS
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38B7 Group
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DESCRIPTION
The 38B7 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38B7 group has six 8-bit timers, one 16-bit timer, a fluorescent
display automatic display circuit, 16-channel 10-bit A-D converter, a
serial I/O with automatic transfer function, which are available for
controlling musical instruments and household appliances.
The 38B7 group has variations of internal memory type. For details,
refer to the section on part numbering.
For details on availability of microcomputers in the 38B7 group, refer
to the section on group expansion.
Built-in pull-down resistors connected to high-breakdown voltage ports
are available by specifying with the mask option in the mask ROM
version. For the details, refer to the section on the mask option of
pull-down resistor.
FEATURES
<Microcomputer mode>
Basic machine-language instructions ....................................... 71
The minimum instruction execution time .......................... 0.48 µs
(at 4.19 MHz oscillation frequency)
Memory size
ROM ........................................................ 60K bytes
RAM .......................................................2048 bytes
Programmable input/output ports ............................................. 75
High-breakdown-voltage output ports ...................................... 52
Software pull-up resistors . (Ports P64 to P67, P7, P80 to P83, P9,
PA, PB)
Interrupts .................................................. 22 sources, 16 vectors
Timers ........................................................... 8-bit ✕ 6, 16-bit ✕ 1
Serial I/O1 (Clock-synchronized) ................................... 8-bit ✕ 1
(max. 256-byte automatic transfer function)
Serial I/O2 (UART or Clock-synchronized) .................... 8-bit ✕ 1
Serial I/O3 (Clock-synchronized) ................................... 8-bit ✕ 1
PWM ............................................................................ 14-bit ✕ 1
8-bit ✕ 1 (also functions as timer 6)
A-D converter .............................................. 10-bit ✕ 16 channels
D-A converter ................................................................ 1 channel
Fluorescent display function ......................... Total 56 control pins
Interrupt interval determination function ..................................... 1
(Serviceable even in low-speed mode)
Watchdog timer ............................................................ 16-bit ✕ 1
Buzzer output ............................................................................. 1
Two clock generating circuits
Main clock (XIN–XOUT) .......................... Internal feedback resistor
Sub-clock (XCIN–XCOUT) .......... Without internal feedback resistor
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage
In high-speed mode ................................................... 4.0 to 5.5 V
(at 4.19 MHz oscillation frequency and high-speed selected)
In middle-speed mode ........................................... 2.7 to 5.5 V (*)
(at 4.19 MHz oscillation frequency and middle-speed selected)
In low-speed mode ................................................ 2.7 to 5.5 V (*)
(at 32 kHz oscillation frequency)
(*: 4.0 to 5.5 V for Flash memory version)
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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Power dissipation
In high-speed mode .......................................................... 35 mW
(at 4.19 MHz oscillation frequency)
In low-speed mode ............................................................. 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Operating temperature range ................................... –20 to 85 °C
<Flash memory mode>
●Supply voltage ................................................. VCC = 5 V ± 10 %
●Program/Erase voltage ............................... VPP = 11.7 to 12.6 V
●Programming method ...................... Programming in unit of byte
●Erasing method
Batch erasing ........................................ Parallel/Serial I/O mode
Block erasing .................................... CPU reprogramming mode
●Program/Erase control by software command
●Number of times for programming/erasing ............................ 100
●Operating temperature range (at programming/erasing)
..................................................................... Normal temperature
■Notes
1. The flash memory version cannot be used for application embedded in the MCU card.
2. Power source voltage Vcc of the flash memory version is 4.0
to 5.5 V.
APPLICATION
Musical instruments, VCR, household appliances, etc.
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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M38B79MFH-XXXXFP
*P46/FLD38
*P47/FLD39
*P50/FLD40
*P51/FLD41
*P52/FLD42
*P53/FLD43
*P54/FLD44
*P55/FLD45
*P56/FLD46
*P57/FLD47
*P60/FLD48
*P61/FLD49
*P62/FLD50
*P63/FLD51
P64/RxD/FLD52
P65/TxD/FLD53
P66/SCLK21/FLD54
P67/SRDY2/SCLK22/FLD55
P70/INT0
P71/INT1
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
P97/BUZ02/AN15
P96/PWM0/AN14
P95/RTP0/AN13
P94/RTP1/AN12
P93/SRDY3/AN11
P92/SCLK3/AN10
P91/SOUT3/AN9
P90/SIN3/AN8
P83/CNTR0/CNTR2
P82/CNTR1
CNVSS
RESET
P81/XCOUT
P80/XCIN
VS S
XIN
XOUT
VCC
P77/INT4/BUZ01
P76/T3OUT
P75/T1OUT
P74/PWM1
P73/INT3/DIMOUT
P72/INT2
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27
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*P27/FLD7
*P26/FLD6
*P25/FLD5
*P24/FLD4
*P23/FLD3
*P22/FLD2
*P21/FLD1
*P20/FLD0
VE E
PB6/SIN1
PB5/SOUT1
PB4/SCLK11
PB3/SSTB1
PB2/SBUSY1
PB1/SRDY1
PB0/SCLK12/DA
AVSS
VREF
PA7/AN7
PA6/AN6
55
54
53
52
51
80
79
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77
76
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*P00/FLD8
*P01/FLD9
*P02/FLD10
*P03/FLD11
*P04/FLD12
*P05/FLD13
*P06/FLD14
*P07/FLD15
*P10/FLD16
*P11/FLD17
*P12/FLD18
*P13/FLD19
*P14/FLD20
*P15/FLD21
*P16/FLD22
*P17/FLD23
*P30/FLD24
*P31/FLD25
*P32/FLD26
*P33/FLD27
*P34/FLD28
*P35/FLD29
*P36/FLD30
*P37/FLD31
*P40/FLD32
*P41/FLD33
*P42/FLD34
*P43/FLD35
*P44/FLD36
*P45/FLD37
PIN CONFIGURATION (TOP VIEW)
*High-breakdown-voltage output port: Totaling 52
Package type: 100P6S-A
Fig. 1 Pin configuration of M38B79MFH-XXXXFP
2
Port P0(8)
8
Port P1(8)
8
8
Port P6(8)
8
Port P7(8)
(52 high-breakdown
voltage ports)
56 control pins
FLD display function
4
Port P8(4)
Interrupt interval
determination function
Watchdog timer
CPU core
8
8
Port PA(8)
RAM
ROM
Me mo r y
XIN-XOUT
(main-clock)
XCIN-XCOUT
(sub-clock)
Timer X(16-bit)
Timer 1(8-bit)
Timer 2(8-bit)
Timer 3(8-bit)
Timer 4(8-bit)
Timer 5(8-bit)
Timer 6(8-bit)
Port P4(8)
8
System clock generation
Port P9(8)
Port P3(8)
8
Timers
Port P2(8)
8
7
Port PB(7)
Port P5(8)
8
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Buzzer output
PWM0(14-bit)
PWM1(8-bit)
Serial I/O3(Clock-synchronized)
Serial I/O2
(Clock-synchronized or UART)
Serial I/O1(Clock-synchronized)
(256 byte automatic transfer)
Serial I/Os
(10-bit ✕ 12 channel)
A-D converter
Build-in peripheral functions
I/O ports
FUNCTIONAL BLOCK DIAGRAM
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 2 Functional block diagram
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 1 Pin description (1)
Pin
Name
VCC, VSS
CNVSS
Power source
CNVSS
VEE
Pull-down
power source
VREF
AV SS
Reference voltage
Analog power
source
Reset input
Clock input
______
RESET
XIN
XOUT
Clock output
P00/FLD8–
Output port P0
P07/FLD15
P10/FLD16 – I/O port P1
P17/FLD23
Function
Function except a port function
• Apply voltage of 4.0–5.5 V to VCC, and 0 V to V SS.
• Connect to V SS.
• VPP power input pin in flash memory mode.
• Apply voltage supplied to pull-down resistors of ports P0, P1, P2 and P3.
• Reference voltage input pin for A-D converter.
• Analog power source input pin for A-D converter.
• Connect to V SS.
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the X OUT pin open.
• The clock is used as the oscillating source of system clock.
• 8-bit output port.
• FLD automatic display
• High-breakdown-voltage P-channel open-drain output structure.
pins
• A pull-down resistor is built in between port P0 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit I/O port.
• FLD automatic display
• I/O direction register allows each pin to be individually programmed as either pins
input or output.
• At reset, this port is set to input mode.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
P20/FLD0–
P27/FLD7
Output port P2
P30/FLD24 –
P37/FLD31
I/O port P3
P40/FLD32 – I/O port P4
P47/FLD39
P50/FLD40 – I/O port P5
P57/FLD47
P60/FLD48 – I/O port P6
P63/FLD51
4
• A pull-down resistor is built in between port P1 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit output port with the same function as port P0.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is built in between port P2 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit I/O port with the same function as port P1.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is built in between port P3 and the VEE pin.
• At reset, this port is set to VEE level.
• 8-bit I/O port with the same function as port P1.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P4 and the VEE pin.
• FLD automatic display
pins
• FLD automatic display
pins
• FLD automatic display
pins
• 8-bit I/O port with the same function as port P1.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P5 and the VEE pin.
• 4-bit I/O port with the same function as port P1.
• FLD automatic display
pins
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P6 and the VEE pin.
pins
• FLD automatic display
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Pin
P64/RXD/FLD 52,
Name
I/O port P6
Function
• 4-bit I/O port .
Function except a port function
• FLD automatic display
P65/T XD/FLD53,
P66/S CLK21/FLD54,
P67/S RDY2/SCLK22/
FLD55 ,
P70/INT 0,
I/O port P7
P71/INT 1,
• Low-voltage input level for input ports.
• CMOS compatible input level for RxD, SCLK21, SCLK22.
• CMOS 3-state output structure.
pins
• Serial I/O2 function pins
• 8-bit I/O port.
• CMOS compatible input level.
• Interrupt input pins
P72/INT 2,
P73/INT 3/DIMOUT ,
• CMOS 3-state output structure.
• Interrupt input pin
• Dimmer signal output pin
• PWM output pin
• Timer output pins
P74/PWM1
P75/T1 OUT,
P76/T3 OUT,
P77/INT 4/B UZ01
P80/XCIN,
P81/XCOUT
I/O port P8
P82/CNTR1,
P83/CNTR0/CNTR2
P90/S IN3/AN8,
I/O port P9
P91/S OUT3/AN9,
P92/S CLK3/AN10 ,
P93/S RDY3/AN11 ,
P94/RTP 1/AN12 ,
• 4-bit I/O port with the same function as port P7.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 8-bit I/O port with the same function as port P7.
• CMOS compatible input level.
• CMOS 3-state output structure.
P97/B UZ02/AN15
PA0/AN0 –PA7 /AN7 I/O port PA
• 8-bit I/O port with the same function as port P7.
PB 0/SCLK12/DA
• CMOS compatible input level.
• CMOS 3-state output structure.
• 7-bit I/O port with the same function as port P7.
• CMOS compatible input level.
• CMOS 3-state output structure.
PB 1/SRDY1,
circuit (connect a ceramic resonator
or a quarts-crystal oscillator)
• Timer input pin
• Timer I/O pin
• Serial I/O3 function pins
• A-D converter input pins
• Real time port output pins
P95/RTP 0/AN13
P96/PWM0/AN14
I/O port PB
• Interrupt input pin
• Buzzer output pin
• I/O pins for sub-clock generating
• A-D converter input pins
• 14-bit PWM output pin
• A-D converter input pin
• Buzzer output pin
• A-D converter input pin
• A-D converter input pin
• Serial I/O1 function pin
• D-A converter output pin
• Serial I/O1 function pins
PB 2/SBUSY1 ,
PB 3/SSTB1,
PB 4/SCLK11,
PB 5/SOUT1,
PB6/SIN1
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Product M38B7 9 M F H - XXXX FP
Package type
FP : 100P6S-A package
ROM number
Omitted in Flash memory version
High-breakdown voltage pull-down option
Regarding option contents, refer to section
“MASK OPTION OF PULL-DOWN RESISTOR”.
For Flash memory version, there is not the
option specification.
ROM/Flash memory size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used for
users.
Memory type
M : Mask ROM version
F : Flash memory version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3 Part numbering
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 38B7 group as follows.
Memory Type
Support for Mask ROM and Flash memory versions.
Memory Size
Flash memory size ........................................................... 60K bytes
Mask ROM size ................................................................ 60K bytes
RAM size .........................................................................2048 bytes
Package
100P6S-A .................................. 0.65 mm-pitch plastic molded QFP
Under development
ROM size (bytes)
M38B79FF
60 K
M38B79MFH
56 K
Under development
52 K
48 K
44 K
40 K
36 K
32 K
28 K
24 K
20 K
16 K
12 K
8K
4K
256
512
768
1,024
1,536
2,048
RAM size (bytes)
Note : Products under development: the development schedule and specifications may be revised without notice.
Fig. 4 Memory expansion plan
Currently supported products are listed below.
Table 3 List of supported products
ROM size (bytes)
Product
ROM size for User ( )
M38B79MFH-XXXXFP
61440
(61310)
M38B79FFFP
As of Mar. 2000
RAM size (bytes)
Package
2048
100P6S-A
Remarks
Mask ROM version
Flash memory version
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016 ”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116 ”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine
calls.
The 38B7 group uses the standard 740 Family instruction set. Refer to the table of 740 Series addressing modes and machine
instructions or the 740 Series Software Manual for details on the
instruction set.
Machine-resident 740 Series instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PC H and PC L. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
C flag
Set instruction
Clear instruction
10
SEC
CLC
Z flag
_
_
I flag
SEI
CLI
D flag
SED
CLD
B flag
_
_
T flag
SET
CLT
V flag
_
CLV
N flag
_
_
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B 16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit etc.
The CPU mode register is allocated at address 003B 16 .
b7
b0
CPU mode register
(CPUM: address 003B16)
Processor mode bits
b1b0
0 0 : Single-chip mode
0 1:
1 0 : Not available
1 1:
Stack page selection bit
0 : Page 0
1 : Page 1
Not used (return “1” when read)
(Do not write “0” to this bit.)
Port XC switch bit
0 : I/O port function
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN) (high-speed mode)
1 : f(XIN)/4 (middle-speed mode)
Internal system clock selection bit
0 : XIN-XOUT selection (middle-/high-speed mode)
1 : XCIN-XCOUT selection (low-speed mode)
Fig. 7 Structure of CPU mode register
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
The special function register (SFR) area contains control registers
for I/O ports, timers and other functions.
Zero Page
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
Special Page
ROM
The special page addressing mode can be used to specify memory
addresses in the special page area. Access to this area with only 2
bytes is possible in the special page addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing, and the other areas are user areas for storing programs.
RAM area
RAM size
(byte)
Address
XXXX16
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
000016
SFR area 1
RAM
Zero page
004016
010016
XXXX16
044016
ROM area
ROM size
(byte)
Address
YYYY16
Address
ZZZZ16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
ROM
0E0016
0EDF16
0EE016
0EFF16
0F0016
0FFF16
YYYY16
Reserved area
Not used (Note)
RAM area for FLD automatic display
SFR area 2
RAM area for Serial I/O
automatic transfer
Reserved ROM area
(common ROM area,128 bytes)
ZZZZ16
FF0016
Special page
FFDC16
Interrupt vector area
FFFE16
FFFF16
Reserved ROM area
Note: When 1024 bytes or more are used as RAM area, this area can be used.
Fig. 8 Memory map diagram
12
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000016
Port P0 (P0)
000116
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
002016
Timer 1 (T1)
002116
Timer 2 (T2)
000216
Port P1 (P1)
002216
Timer 3 (T3)
000316
Port P1 direction register (P1D)
002316
Timer 4 (T4)
000416
Port P2 (P2)
002416
Timer 5 (T5)
002516
Timer 6 (T6)
000516
000616
Port P3 (P3)
002616
PWM control register (PWMCON)
000716
Port P3 direction register (P3D)
002716
Timer 6 PWM register (T6PWM)
000816
Port P4 (P4)
002816
Timer 12 mode register (T12M)
000916
Port P4 direction register (P4D)
002916
Timer 34 mode register (T34M)
000A16
Port P5 (P5)
002A16
Timer 56 mode register (T56M)
000B16
Port P5 direction register (P5D)
002B16
D-A conversion register (DA)
000C16
Port P6 (P6)
002C16
Timer X (low-order) (TXL)
000D16
Port P6 direction register (P6D)
002D16
Timer X (high-order) (TXH)
000E16
Port P7 (P7)
002E16
Timer X mode register 1 (TXM1)
000F16
Port P7 direction register (P7D)
002F16
Timer X mode register 2 (TXM2)
001016
Port P8 (P8)
003016
Interrupt interval determination register (IID)
001116
Port P8 direction register (P8D)
003116
Interrupt interval determination control register (IIDCON)
001216
Port P9 (P9)
003216
AD/DA control register (ADCON)
001316
Port P9 direction register (P9D)
003316
A-D conversion register (low-order) (ADL)
001416
Port PA (PA)
003416
A-D conversion register (high-order) (ADH)
001516
Port PA direction register (PAD)
003516
PWM register (high-order) (PWMH)
001616
Port PB (PB)
003616
PWM register (low-order) (PWML)
001716
Port PB direction register (PBD)
003716
Baud rate generator (BRG)
001816
Serial I/O1 automatic transfer data pointer (SIO1DP)
003816
UART control register (UARTCON)
001916
Serial I/O1 control register 1 (SIO1CON1)
003916
Interrupt source switch register (IFR)
001A16
Serial I/O1 control register 2 (SIO1CON2)
003A16
Interrupt edge selection register (INTEDGE)
001B16
Serial I/O1 register/Transfer counter (SIO1)
003B16
CPU mode register (CPUM)
001C16
Serial I/O1 control register 3 (SIO1CON3)
003C16
Interrupt request register 1(IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2(IREQ2)
001E16
Serial I/O2 status register (SIO2STS)
003E16
Interrupt control register 1(ICON1)
001F16
Serial I/O2 transmit/receive buffer register (TB/RB)
003F16
Interrupt control register 2(ICON2)
0EEC16
Serial I/O3 control register (SIO3CON)
0EF616
Toff1 time set register (TOFF1)
0EED16
Serial I/O3 register (SIO3)
0EF716
Toff2 time set register (TOFF2)
0EEE16
Watchdog timer control register (WDTCON)
0EF816
FLD data pointer (FLDDP)
0EEF16
Pull-up control register 3 (PULL3)
0EF916
Port P4 FLD/Port switch register (P4FPR)
0EF016
Pull-up control register 1 (PULL1)
0EFA16
Port P5 FLD/Port switch register (P5FPR)
0EF116
Pull-up control register 2 (PULL2)
0EFB16
Port P6 FLD/Port switch register (P6FPR)
0EF216
Port P0 digit output set switch register (P0DOR)
0EFC16 FLD output control register (FLDCON)
0EF316
Port P2 digit output set switch register (P2DOR)
0EFD16 Buzzer output control register (BUZCON)
0EF416
FLDC mode register (FLDM)
0EFE16
Flash memory control register (FCON)
(Note)
0EF516
Tdisp time set register (TDISP)
0EFF16
Flash command register (FCMD)
(Note)
Note: Flash memory version only.
Fig. 9 Memory map of special function register (SFR)
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
[Direction Registers] PiD
[High-Breakdown-Voltage Output Ports]
The 38B7 group has 75 programmable I/O pins arranged in ten individual I/O ports (P1, P3, P4, P5, P6, P7, P8, P9, PA and PB).
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input
port or output port. When “0” is written to the bit corresponding to
a pin, that pin becomes an input pin. When “1” is written to that
pin, that pin becomes an output pin. If data is read from a pin set
to output, the value of the port output latch is read, not the value of
the pin itself. Pins set to input (the bit corresponding to that pin
must be set to “0”) are floating and the value of that pin can be
read. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
b7
The 38B7 group has seven ports with high-breakdown-voltage
pins (por ts P0 to P5 and P60–P6 3). The high-breakdown-voltage
ports have P-channel open-drain output with Vcc – 45 V of breakdown voltage. Each pin in ports P0 to P3 has an internal pull-down
resistor connected to VEE . At reset, the P-channel output transistor of each port latch is turned off, so that it goes to VEE level (“L”)
by the pull-down resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register
(address 0EF4 16) shows the rising transition of the output transistors for reducing transient noise. At reset, bit 7 of the FLDC mode
register is set to “0” (strong drivability).
[Pull-up Control Register] PULL
Ports P64 –P6 7, P7, P8 0–P8 3 , P9, PA and PB have built-in programmable pull-up resistors. The pull-up resistors are valid only in
the case that the each control bit is set to “1” and the corresponding port direction registers are set to input mode.
b7
b0
b0
Pull-up control register 2
(PULL2 : address 0EF116)
Pull-up control register 1
(PULL1 : address 0EF016)
P64, P65 pull-up control bit
P80, P81 pull-up control bit
P66, P67 pull-up control bit
P82, P83 pull-up control bit
P70, P71 pull-up control bit
P72, P73 pull-up control bit
0: No pull-up
1: Pull-up
P74, P75 pull-up control bit
P76, P77 pull-up control bit
Not used (returns “0” when read)
(Do not write “1”.)
Not used (returns “0” when read)
(Do not write “1”.)
P90, P91 pull-up control bit
P92, P93 pull-up control bit
P94, P95 pull-up control bit
P96, P97 pull-up control bit
Not used (returns “0” when read)
(Do not write “1”.)
0: No pull-up
1: Pull-up
b7
b0
Pull-up control register 3
(PULL3 : address 0EEF16)
PA0, PA1 pull-up control bit
PA2, PA3 pull-up control bit
PA4, PA5 pull-up control bit
PA6, PA7 pull-up control bit
PB0, PB1 pull-up control bit
0: No pull-up
1: Pull-up
PB2, PB3 pull-up control bit
PB4, PB5 pull-up control bit
PB6 pull-up control bit
Fig. 10 Structure of pull-up control registers (PULL1, PULL2 and PULL3)
14
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 List of I/O port functions (1)
Pin
P00/FLD8 –
P07/FLD15
Nama
Port P0
Input/Output
Output
P10/FLD16 –
P17/FLD23
Port P1
Input/output,
individual
bits
P20/FLD0 –
P27/FLD7
Port P2
Output
P30/FLD24 –
P37/FLD31
Port P3
Input/output,
individual
bits
P40/FLD32 –
P47/FLD39
Port P4
Input/output,
individual
bits
P50/FLD40 –
P57/FLD47
Port P5
Input/output,
individual
bits
P60/FLD48 –
P63/FLD51
Port P6
Input/output,
individual
bits
P64/RxD/
FLD 52
P65/TxD/
FLD53,
P66/SCLK21/
FLD 54
P67/SRDY2/
SCLK22/
FLD 55
P70/INT0,
P71/INT1
P72/INT2
I/O Format
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
(port input)
CMOS compatible input
level (RxD, S CLK21,
SCLK22)
CMOS 3-state output
Non-Port Function
FLD automatic display
function
FLD automatic display
function
Serial I/O2 function I/O
Ref.No.
(1)
FLDC mode register
(2)
FLDC mode register
P2 digit output set switch
register
(1)
FLDC mode register
(2)
FLDC mode register
Port P4 FLD/Port switch
register
(2)
FLDC mode register
Port P5 FLD/Port switch
register
(2)
FLDC mode register
Port P6 FLD/Port switch
register
(2)
FLDC mode register
Serial I/O2 control
register
UART control register
(3)
(4)
(5)
Port P7
Input/output,
individual
bits
CMOS compatible input
level
CMOS 3-state output
External interrput input
P73/INT3/
DIMOUT
External interrput input
Dimmer signal output
P74/PWM1
P75/T1 OUT
P76/T3 OUT
P77/INT4/
BUZ01
PWM output
Timer output
Timer output
Buzzer output
External interrput input
P80/XCIN
P81/XCOUT
P82/CNTR1
P83/CNTR0/
CNTR2
Related SFRs
FLDC mode register
P0 digit output set switch
register
Port P8
Input/output,
individual
bits
CMOS compatible input
level
CMOS 3-state output
Sub-clock generating
circuit I/O
External count input
Interrupt edge selection
register
Interrupt edge selection
register
Interrupt interval determination control register
Interrupt edge selection
register
FLD output control register
Timer 56 mode register
Timer 12 mode register
Timer 34 mode register
Buzzer output control
register
Interrupt edge selection
register
CPU mode register
Interrupt edge selection
register
(6)
(7)
(8)
(9)
(10)
(11)
(6)
(12)
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Table 7 List of I/O port functions (2)
Pin
Nama
Input/Output
P90/S IN3/
Port P9
Input/output,
AN 8
individual
bits
P91/S OUT3/
AN 9,
P92/S CLK3/
AN 10
P93/S RDY3/
AN11
P94/RTP1/
AN 12,
P95/RTP0/
AN 13
P96/PWM 0/
AN 14
P97/B UZ02/
AN 15
PA0/AN 0–
Port PA
Input/output,
PA7 /AN7
individual
bits
PB 0/S CLK12/
DA
Port PB
Input/output,
individual
bits
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Format
CMOS compatible input
level
CMOS 3-state output
Non-Port Function
Serial I/O3 function I/O
A-D conversion input
Related SFRs
Serial I/O3 control
register
AD/DA control register
(13)
(14)
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
Real time port output
A-D conversion input
Timer X mode register 2
AD/DA control register
(15)
PWM output
A-D conversion input
Buzzer output
A-D conversion input
A-D conversion input
PWM control register
AD/DA control register
Buzzer output control register
AD/DA control register
AD/DA control register
(16)
Serial I/O1 function I/O
D-A conversion output
Serial I/O1 control
registers 1, 2
AD/DA control register
Serial I/O1 control
registers 1, 2
Serial I/O1 function I/O
PB 1/S RDY1
PB 2/SBUSY1
PB 3/S STB1
PB 4/SCLK11
PB 5/S OUT1
PB 6/SIN1
Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections.
2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
16
Ref.No.
(6)
(16)
(17)
(18)
(19)
(18)
(20)
(21)
(6)
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P2
(2) Ports P1, P3, P4, P5, P60 to P63
FLD/Port
switch register
Dimmer signal
(Note 1)
Local data
bus
Data bus
P4, P5, P60 to P63
Dimmer signal
(Note 1)
Output
✽
Port latch
Direction register
Local data
bus
✽
Port latch
Data bus
read
VEE
(Note 2)
VEE
(3) Port P64
(4) Ports P65, P66
Pull-up control
Dimmer signal
(Note 1)
P-channel output disable signal (P65)
Pull-up control
Output OFF control signal
FLD/Port
switch register
Dimmer signal
(Note 1)
FLD/Port
switch register
Direction register
Local data
bus
Serial I/O2 selection signal
Port latch
Data bus
Direction register
Local data
bus
Data bus
Port latch
RxD input
TxD or SCLK21 output
Serial clock input
P66
(5) Port P67
(6) Ports P70 to P72, P82, P90, PB6
Dimmer signal
(Note 1)
Pull-up control
Pull-up control
FLD/Port
switch register
Direction register
Local data
bus
Data bus
Direction register
Data bus
Port latch
Port latch
INT0, INT1, INT2 interrupt input
CNTR1 input
Serial I/O input
Serial ready output
SRDY2 output enable bit
Serial I/O2 enable bit
A-D conversion input
Analog input pin selection bit
Serial clock output
P90
Clock I/O pin selection bit
Synchronous clock
selection bit
Serial clock input
✽ High-breakdown-voltage P-channel transistor
Notes 1: The dimmer signal sets the Toff timing.
2: A pull-down resistor is not built in to ports P4, P5 and P60 to P63.
Fig. 11 Port block diagram (1)
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(7) Port P73
(8) Ports P74 to P76
Timer 1 output selection bit
Timer 3 output selection bit
Timer 6 output selection bit
Pull-up control
Dimmer output
control bit
Direction register
Direction register
Data bus
Pull-up control
Data bus
Port latch
Port latch
Dimmer signal output
Timer 1 output
Timer 3 output
Timer 6 output
INT3 interrupt input
(9) Port P77
(10) Port P80
Pull-up control
Pull-up control
Port Xc switch bit
Buzzer control signal
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
Buzzer signal output
INT4 interrupt input
Sub-clock generating circuit input
(12) Port P83
(11) Port P81
Pull-up control
Port Xc switch bit
Pull-up control
Timer X operating mode bits
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillator
Timer X output
Port P80
CNTR0, CNTR2 input
Port Xc switch bit
(13) Ports P91, P92
(14) Port P93
Pull-up control
P-channel output disable signal (P91)
Output OFF control signal
Pull-up control
SRDY3 output enable bit
Serial I/O3 selection signal
Direction register
Data bus
Direction register
Data bus
Port latch
Port latch
SOUT or SCLK
Serial ready output
Serial clock input
A-D conversion input
Analog input pin selection bits
Fig. 12 Port block diagram (2)
18
A-D conversion input
Analog input pin selection bits
P92
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(16) Ports P96, P97
(15) Ports P94, P95
Pull-up control
Pull-up control
PWM output selection bit
Buzzer control signal
Real time port control bit
Direction register
Data bus
Direction register
Data bus
Port latch
Port latch
PWM output
Buzzer signal output
RTP output
A-D conversion input
A-D conversion input
Analog input pin selection bits
(17) Port PA
Analog input pin selection bits
(18) Ports PB0, PB2
Pull-up control
Pull-up control
Serial I/O1 selection signal
PB1/SRDY1•PB2/SBUSY1 pin
control bit
Direction register
Data bus
Direction register
Port latch
Data bus
Port latch
SCLK12 output
SBUSY1 output
Serial clock input
SBUSY1 input
A-D conversion input
Analog input pin selection bits
D-A converter output
D-A output enable bit
PB0
(20) Port PB3
(19) Port PB1
Pull-up control
Pull-up control
PB1/SRDY1•PB2/SBUSY1 pin
control bit
PB3/SSTB1 pin control bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
SSTB1 output
Serial ready output
Serial ready input
(21) Ports PB4, PB5
Pull-up control
P-channel output disable signal (PB5)
Output OFF control signal
Serial I/O1 selection signal
Direction register
Data bus
Port latch
SOUT or SCLK
Serial clock input
PB4
Fig. 13 Port block diagram (3)
19
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INTERRUPTS
Interrupts occur by twenty two sources: five external, sixteen internal, and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an interrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is
“0.” Interrupt enable bits can be set or cleared by software. Interrupt
request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occur at
the same time, the interrupt with highest priority is accepted first.
Interrupt Operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source Selection
Any of the following interrupt sources can be selected by the interrupt source switch register (address 003916).
1. INT 1 or Serial I/O3
2. INT 3 or Serial I/O2 transmit
3. INT4 or A-D conversion
■Note
When the active edge of an external interrupt (INT0–INT4) is set or
when switching interrupt sources in the same vector address, the
corresponding interrupt request bit may also be set. Therefore, please
take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(3) Clear the set interrupt request bit to “0.”
(4) Enable the external interrupt which is selected.
20
MITSUBISHI MICROCOMPUTERS
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 Interrupt vector addresses and priority
Interrupt Source Priority
Vector Addresses (Note 1)
Reset (Note 2)
INT0
1
2
High
FFFD16
FFFB16
INT1
3
FFF916
FFF816
Serial I/O3
INT2
4
FFF716
FFF616
Remote control/
counter overflow
Serial I/O1
Low
FFFC16
FFFA16
Interrupt Request
At reset
At detection of either rising or falling edge of
Non-maskable
External interrupt
INT0 input
At detection of either rising or falling edge of
INT1 input
(active edge selectable)
External interrupt
(active edge selectable)
Valid when INT1 interrupt is selected
Valid when serial I/O3 is selected
External interrupt
At completion of data transfer
At detection of either rising or falling edge of
INT2 input
At 8-bit counter overflow
5
FFF516
FFF416
At completion of data transfer
Serial I/O automatic transfer
Timer X
Timer 1
Timer 2
6
7
8
FFF316
FFF116
FFEF16
FFF216
FFF016
FFEE16
At timer X underflow
At timer 1 underflow
At timer 2 underflow
Timer 3
Timer 4
Timer 5
Timer 6
Serial I/O2 receive
9
10
11
12
13
FFED16
FFEB16
FFE916
FFE716
FFE516
FFEC16
FFEA16
FFE816
FFE616
FFE416
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At completion of serial I/O2 data receive
INT3
14
FFE316
FFE216
At detection of either rising or falling edge of
INT3 input
Serial I/O2 transmit
INT4
15
FFE116
FFE016
At completion of the last data transfer
At completion of serial I/O2 data transmit
At detection of either rising or falling edge of
INT4 input
A-D conversion
FLD blanking
16
FFDF16
FFDE16
Remarks
Generating Conditions
At completion of A-D conversion
At falling edge of the last timing immediately
before blanking period starts
FLD digit
At rising edge of digit (each timing)
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
(active edge selectable)
Valid when interrupt interval
determination is operating
Valid when serial I/O ordinary
mode is selected
Valid when serial I/O automatic
transfer mode is selected
STP release timer underflow
External interrupt
(active edge selectable)
Valid when INT3 interrupt is selected
External interrupt
(active edge selectable)
Valid when INT4 interrupt is selected
Valid when A-D conversion is selected
Valid when FLD blanking
interrupt is selected
Valid when FLD digit interrupt is selected
Non-maskable software interrupt
21
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 14 Interrupt control
b7
b0 Interrupt source switch register
(IFR : address 003916)
INT3/serial I/O2 transmit interrupt switch bit
0 : INT3 interrupt
1 : Serial I/O2 transmit interrupt
INT4/AD conversion interrupt switch bit
0 : INT4 interrupt
1 : A-D conversion interrupt
INT1/serial I/O3 interrupt switch bit
0 : INT1 interrupt
1 : Serial I/O3 interrupt
Not used (return “0” when read)
(Do not write “1” to these bits.)
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
INT4 interrupt edge selection bit
Not used (return “0” when read)
CNTR0 pin edge switch bit
CNTR1 pin edge switch bit
b7
0 : Falling edge active
1 : Rising edge active
0 : Rising edge count
1 : Falling edge count
b0 Interrupt request register 1
(IREQ1 : address 003C16)
b7
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O3 interrupt request bit
INT2 interrupt request bit
Remote controller/counter overflow interrupt
request bit
Serial I/O1 interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
b0 Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O3 interrupt enable bit
INT2 interrupt enable bit
Remote controller/counter overflow interrupt
enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Fig. 15 Structure of interrupt related registers
22
Interrupt request register 2
(IREQ2 : address 003D16)
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Serial I/O2 receive interrupt request bit
INT3/serial I/O2 transmit interrupt request bit
INT4 interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
Serial I/O automatic transfer interrupt request bit
b7
b0
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 2
(ICON2 : address 003F16)
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
Serial I/O2 receive interrupt enable bit
INT3/serial I/O2 transmit interrupt enable bit
INT4 interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupt disabled
1 : Interrupt enabled
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MITSUBISHI MICROCOMPUTERS
.
TIMERS
8-Bit Timer
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Timer 12 mode register
(T12M: address 002816)
The 38B7 group has six built-in 8-bit timers : Timer 1, Timer 2, Timer
3, Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “00 16”, an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is set
to “1”.
The count can be stopped by setting the stop bit of each timer to “1”.
The internal system clock can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
the timer internal count source is switched to either f(XIN) or f(XCIN).
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 can be output from the P75/T1OUT pin. The
active edge of the external clock CNTR 0 can be switched with the bit
6 of the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0”, timer 1 is set to “FF 16”, and timer 2
is set to “0116”.
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : f(XCIN)
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR0
11 : Not available
Timer 1 output selection bit (P75)
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
Timer 34 mode register
(T34M: address 002916)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR1
11 : Not available
Timer 3 output selection bit (P76)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 can be output from the P76/T3OUT pin. The
active edge of the external clock CNTR 1 can be switched with the bit
7 of the interrupt edge selection register.
●Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P7 4/PWM1 pin.
b7
●Timer 6 PWM1 Mode
Timer 6 can output a PWM rectangular waveform with “H” duty cycle
n/(n+m) from the P74/PWM1 pin by setting the timer 56 mode register (refer to Figure 18). The n is the value set in timer 6 latch (address
0025 16) and m is the value in the timer 6 PWM register (address
0027 16). If n is “0,” the PWM output is “L”, if m is “0”, the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
b0
Timer 56 mode register
(T56M: address 002A16)
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/8 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P74)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Fig. 16 Structure of timer related registers
23
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
XCIN
Timer 1 latch (8)
1/2
Timer 1 count source
“1”
Internal system clock
selection bit
1/8
XI N
“0”
“01” selection bits
Timer 1 (8)
“00”
1/16
FF16
“10”
RESET
STP instruction
Timer 1 interrupt request
Timer 1 count
stop bit
1/64
“11”
P75 latch
P75/T1OUT
1/2
Timer 1 output selection bit
Timer 2 latch (8)
“00”
Timer 2 count source
selection bits
0 11 6
Timer 2 (8)
P75 direction register
“10”
CNTR0
P83/CNTR0/CNTR2
Timer 2 interrupt request
“01”
Timer 2 count
stop bit
Rising/Falling
active edge switch
CNTR2
Timer 3 latch (8)
“01”
“00”
P76/T3OUT
Timer 3 count source
selection bits
Timer 3 (8)
“10”
P76 latch
Timer 3 interrupt request
Timer 3 count
stop bit
“11”
1/2
Timer 3 output selection bit
Timer 4 latch (8)
“01”
P76 direction register
Timer 4 count source
selection bits
Timer 4 (8)
“00”
P82/CNTR1
Timer 4 interrupt request
Timer 4 count
stop bit
“10”
Rising/Falling
active edge switch
Timer 5 latch (8)
“1”
Timer 5 count source
selection bit
Timer 5 (8)
“0”
Timer 5 interrupt request
Timer 5 count
stop bit
Timer 6 latch (8)
“01”
Timer 6 count source
selection bits
Timer 6 (8)
“00”
Timer 6 count
stop bit
“10”
Timer 6 PWM register (8)
P74/PWM1
P74 latch
“1”
“0”
PWM
1/2
Timer 6 output selection bit
Timer 6 operation
mode selection bit
P74 direction register
Fig. 17 Block diagram of timer
24
Timer 6 interrupt request
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.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts
Timer 6
count source
Timer 6 PWM
mode
n ✕ ts
m ✕ ts
(n+m) ✕ ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n + m) and period: (n + m) ✕ ts) is output.
n : setting value of Timer 6
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 18 Timing chart of timer 6 PWM1 mode
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
16-Bit Timer
■ Note
Timer X is a 16-bit timer that can be selected in one of four modes by
the Timer X mode registers 1, 2 and can be controlled for the timer X
write and the real time port by setting the timer X mode registers.
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the loworder byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
•Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch at
the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value in
the latch is loaded in timer X after timer X underflows.
When the value is written in latch only, unexpected value may be set
in the high-order counter if the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Timer X
Timer X is a down-counter. When the timer reaches “000016”, an
underflow occurs with the next count pulse. Then the contents of the
timer latch is reloaded into the timer and the timer continues downcounting. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
(1) Timer mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR2 pin
is inverted. Except for this, the operation in pulse output mode is the
same as in timer mode. When using a timer in this mode, set the port
shared with the CNTR2 pin to output.
(3) Event counter mode
The timer counts signals input through the CNTR2 pin. Except for
this, the operation in event counter mode is the same as in timer
mode. When using a timer in this mode, set the port shared with the
CNTR2 pin to input.
(4) Pulse width measurement mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1. When
CNTR2 active edge switch bit is “0”, the timer counts while the input
signal of the CNTR2 pin is at “H”. When it is “1”, the timer counts
while the input signal of the CNTR2 pin is at “L”. When using a timer
in this mode, set the port shared with the CNTR2 pin to input.
26
•Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P94 and P95 each time the timer X underflows.
(However, if the real time port control bit is changed from “0” to “1”,
data are output independent of the timer X.) When the data for the
real time port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction registers to output mode.
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Real time port
control bit “1”
Data bus
Q D
P94 data for real time port
P94
“0 ”
Latch
P94 direction
register
P94 latch
Real time port
control bit “1”
Q D
Real time port
control bit (P94) “0”
“0 ”
Latch
P95 direction
register
P95 latch
Real time port
control bit (P95) “0”
“1”
Timer X mode register
write signal
P95 data for real time port
P95
1/2
“1 ”
XIN
“0 ”
“1”
Timer X mode register
write signal
Internal system clock
selection bit
1/2
Count source selection bit
1/8
1/64
Timer X stop
control bit
Timer X operating
Divider
XCIN
CNTR2 active
edge switch bit
P83/CNTR0/CNTR2
Timer X write
control bit
mode bits
“0 ”
Timer X latch (low-order) (8) Timer X latch (high-order) (8)
“00”,“01”,“11”
Timer X (low-order) (8)
Timer X (high-order) (8)
“10”
“1 ”
Pulse width
measurement mode
CNTR2 active
edge switch bit “0”
Pulse output mode
Q
P83 direction
register
“1”
Timer X
interrupt request
S
T
Q
P83 latch
Pulse output mode
CNTR0
Fig. 19 Block diagram of timer X
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 1
(TXM1 : address 002E16)
Timer X mode register 2
(TXM2 : address 002F16)
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bits
b2 b1
0 0 : f(XIN)/2 or f(XCIN)/4
0 1 : f(XIN)/8 or f(XCIN)/16
1 0 : f(XIN)/64 or f(XCIN)/128
1 1 : Not available
Not used (returns “0” when read)
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR2 active edge switch bit
0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse width measurement mode ; measures “H” periods
1 : • Event counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse width measurement mode ; measures “L” periods
Timer X stop control bit
0 : Count operating
1 : Count stop
Real time port control bit (P94)
0 : Real time port function is invalid
1 : Real time port function is valid
Real time port control bit (P95)
0 : Real time port function is invalid
1 : Real time port function is valid
P94 data for real time port
P95 data for real time port
Not used (returns “0” when read)
Fig. 20 Structure of timer X related registers
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
Serial I/O1
0F0016 to 0FFF16).
The PB 1 /SRDY1, PB 2/SBUSY1 , and PB3/S STB1 pins each have a
handshake I/O signal function and can select either “H” active or
“L” active for active logic.
Serial I/O1 is used as the clock synchronous serial I/O and has an
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
Main address
bus
Local address
bus
Serial I/O automatic
transfer RAM
(0F0016 to 0FFF16)
Main
Local
data bus data bus
Serial I/O1
automatic transfer
data pointer
Address decoder
Serial I/O1
automatic transfer
controller
XCIN
1/2
Serial I/O1
control register 3
Internal system
clock selection bit
“1 ”
“0”
PB3 latch
“0 ”
Divider
XIN
(PB3/SSTB1 pin control bit)
PB3/SSTB1
“1”
PB1/SRDY1•PB2/SBUSY1 PB2 latch
pin control bit
“0 ”
Internal synchronous
clock selection bits
Serial I/O1
synchronous clock
selection bit
PB2/SBUSY1
“1 ”
PB1/SRDY1•PB2/SBUSY1
PB1 latch
pin control bit
1/4
1/8
1/16
1/32
1/64
1/128
1/256
“0”
Synchronous
circuit
“1”
SCLK1
“0”
PB1/SRDY1
“1 ”
Serial I/O1 clock
pin selection bit
“0 ”
“1”
Serial transfer
status flag
PB4 latch
“0”
PB4/SCLK11
“0 ”
“1 ”
“1 ”
Serial I/O1 counter
“1 ”
PB0/SCLK12
Serial I/O1 clock
pin selection bits
“0 ”
PB0 latch
“0 ”
PB5/SOUT1
PB5 latch
“1” Serial transfer selection bits
PB6/SIN1
Fig. 21 Block diagram of serial I/O1
28
Serial I/O1 register (8)
Serial I/O1
interrupt request
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 1
(SIO1CON1 (SC11):address 001916)
Serial transfer selection bits
b1 b0
0 0 : Serial I/O disabled (pins PB0 to PB6 are I/O ports)
0 1 : 8-bit serial I/O
1 0 : Not available
1 1 : Automatic transfer serial I/O (8-bits)
Serial I/O1 synchronous clock selection bits (PB3/SSTB1 pin control bit)
b3 b2
0 0 : Internal synchronous clock (PB3 pin is an I/O port.)
0 1 : External synchronous clock (PB3 pin is an I/O port.)
1 0 : Internal synchronous clock (PB3 pin is an SSTB1 output.)
1 1 : Internal synchronous clock (PB3 pin is an SSTB1 output.)
Serial I/O initialization bit
0: Serial I/O initialization
1: Serial I/O enabled
Transfer mode selection bit
0: Full duplex (transmit and receive) mode (PB6 pin is an SIN1 input.)
1: Transmit-only mode (PB6 pin is an I/O port.)
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O1 clock pin selection bit
0:SCLK11 (PB0/SCLK12 pin is an I/O port.)
1:SCLK12 (PB4/SCLK11 pin is an I/O port.)
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 2
(SIO1CON2 (SC12): address 001A16)
PB1/SRDY1 • PB2/SBUSY1 pin control bits
b3b2b1b0
0 0 0 0: Pins PB1 and PB2 are I/O ports
0 0 0 1: Not used
0 0 1 0: PB1 pin is an SRDY1 output, PB2 pin is an I/O port.
0 0 1 1: PB1 pin is an SRDY1 output, PB2 pin is an I/O port.
0 1 0 0: PB1 pin is an I/O port, PB2 pin is an SBUSY1 input.
0 1 0 1: PB1 pin is an I/O port, PB2 pin is an SBUSY1 input.
0 1 1 0: PB1 pin is an I/O port, PB2 pin is an SBUSY1 output.
0 1 1 1: PB1 pin is an I/O port, PB2 pin is an SBUSY1 output.
1 0 0 0: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output.
1 0 0 1: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output.
1 0 1 0: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output.
1 0 1 1: PB1 pin is an SRDY1 input, PB2 pin is an SBUSY1 output.
1 1 0 0: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input.
1 1 0 1: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input.
1 1 1 0: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input.
1 1 1 1: PB1 pin is an SRDY1 output, PB2 pin is an SBUSY1 input.
SBUSY1 output • SSTB1 output function selection bit
(Valid in automatic transfer mode)
0: Functions as each 1-byte signal
1: Functions as signal for all transfer data
Serial transfer status flag
0: Serial transfer completion
1: Serial transferring
SOUT1 pin control bit (at no-transfer serial data)
0: Output active
1: Output high-impedance
PB5/SOUT1 P-channel output disable bit
0: CMOS 3-state (P-channel output is valid.)
1: N-channel open-drain (P-channel output is invalid.)
Fig. 22 Structure of serial I/O1 control registers 1, 2
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Serial I/O1 operation
Either the internal synchronous clock or external synchronous
clock can be selected by the serial I/O1 synchronous clock selection bits (b2 and b3 of address 0019 16) of serial I/O1 control
register 1 as synchronous clock for serial transfer.
The internal synchronous clock has a built-in dedicated divider
where 7 different clocks are selected by the internal synchronous
clock selection bits (b5, b6 and b7 of address 001C16) of serial
I/O1 control register 3.
The PB1/S RDY1, PB2/S BUSY1, and PB3 /SSTB1 pins each select either I/O port or handshake I/O signal by the serial I/O1
synchronous clock selection bits (b2 and b3 of address 001916) of
serial I/O1 control register 1 as well as the PB 1/S RDY1 • PB2 /
SBUSY1 pin control bits (b0 to b3 of address 001A 16) of serial
I/O1 control register 2.
For the SOUT 1 being used as an output pin, either CMOS output
or N-channel open-drain output is selected by the PB5/S OUT1 Pchannel output disable bit (b7 of address 001A16) of serial I/O1
control register 2.
Either output active or high-impedance can be selected as a
SOUT1 pin state at serial non-transfer by the SOUT1 pin control bit
(b6 of address 001A16) of serial I/O1 control register 2. However,
when the external synchronous clock is selected, perform the following setup to put the SOUT1 pin into a high-impedance state:
When the SCLK1 input is “H” after completion of transfer, set the
SOUT1 pin control bit to “1”.
b7 b6 b5 b4 b3 b2 b1 b0
When the S CLK1 input goes to “L” after the start of the next serial
transfer, the SOUT1 pin control bit is automatically reset to “0” and
put into an output active state.
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the transmit-only mode are available for serial transfer, one of which is
selected by the transfer mode selection bit (b5 of address 0019 16)
of serial I/O1 control register 1.
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6
of address 0019 16) of serial I/O1 control register 1.
When using serial I/O1, first select either 8-bit serial I/O or automatic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 0019 16 ) of serial I/O1 control register 1, after
completion of the above bit setup. Next, set the serial I/O initialization bit (b4 of address 001916 ) of serial I/O1 control register 1 to
“1” (Serial I/O enable) .
When stopping serial transfer while data is being transferred, regardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to “0”.
Serial I/O1 control register 3
(SIO1CON3 (SC13): address 001C16)
Automatic transfer interval set bits
b4b3b2b1b0
0 0 0 0 0: 2 cycles of transfer clocks
0 0 0 0 1: 3 cycles of transfer clocks
:
1 1 1 1 0: 32 cycles of transfer clocks
1 1 1 1 1: 33 cycles of transfer clocks
Data is written to a latch and read from a decrement counter.
Internal synchronous clock selection bits
b7b6b5
0 0 0: f(XIN)/4 or f(XCIN)/8
0 0 1: f(XIN)/8 or f(XCIN)/16
0 1 0: f(XIN)/16 or f(XCIN)/32
0 1 1: f(XIN)/32 or f(XCIN)/64
1 0 0: f(XIN)/64 or f(XCIN)/128
1 0 1: f(XIN)/128 or f(XCIN)/256
1 1 0: f(XIN)/256 or f(XCIN)/512
Fig. 23 Structure of serial I/O1 control register 3
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MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) 8-bit serial I/O mode
Address 001B 16 is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B 16).
The serial transfer status flag (b5 of address 001A16 ) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by writing into the serial I/O1 register, which becomes a transfer start trigger and reset to “0” after completion of
8-bit transfer. At the same time, a serial I/O1 interrupt request occurs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer
clocks are input to SCLK1. Therefore, the clock needs to be controlled externally.
(3) Automatic transfer serial I/O mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so that the function of
address 001B 16 is used as a transfer counter (1-byte unit).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F0016 to 0FFF16 ), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 001816)
beforehand.
Input the low-order 8 bits of the first data store address to be serially transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer interval for each 1-byte data can be set by the automatic transfer
interval set bits (b0 to b4 of address 001C 16) of serial I/O1 control
register 3 in the following cases:
1. When using no handshake signal
2. When using the S RDY1 output, SBUSY1 output, and S STB1 output
of the handshake signal independently
3. When using a combination of S RDY1 output and SSTB1 output or
a combination of S BUSY1 output and S STB1 output of the handshake signal.
It is possible to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the S BUSY1 output and selecting the SBUSY1 output •
SSTB1 output function selection bit (b4 of address 001A16 ) of serial
b7
I/O1 control register 2 as the signal for all transfer data, provided
that the automatic transfer interval setting is valid, a transfer interval is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For SSTB1 output, regardless of the contents of the SBUSY1 output
• SSTB1 output function selection bit (b4), the transfer interval for
each 1-byte data is longer than the set value by 2 cycles.
Furthermore, when using a combination of SBUSY1 output and
SSTB1 output as a signal for all transfer data, the transfer interval
after the end of transmission/reception of the last data is longer
than the set value by 2 cycles.
When the external synchronous clock is selected, automatic transfer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes – 1” into the transfer counter
(address 001B16 ).
When the external synchronous clock is selected, write the value
of “number of transfer bytes – 1” into the transfer counter and
keep an internal system clock interval of 5 cycles or more. After
that, input transfer clock to SCLK1.
As a transfer interval for each 1-byte data transfer, keep an internal system clock interval of 5 cycles or more from the clock rise
time of the last bit.
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The serial transfer
status flag (b5 of address 001A16) is set to “1” by writing data into
the transfer counter. Writing data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data
is written into the automatic transfer RAM. At the same time, a serial I/O1 interrupt request occurs.
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 001816) and the automatic transfer interval
set bits (b0 to b4 of address 001C 16) are held in the latch.
When data is written into the transfer counter, the values latched
in the automatic transfer data pointer set bits (b0 to b7) and the
automatic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 001816)
Automatic transfer data pointer set bits
Specify the low-order 8 bits of the first data store address on the serial I/O automatic
transfer RAM. Data is written into the latch and read from the decrement counter.
Fig. 24 Structure of serial I/O1 automatic transfer data pointer
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Automatic transfer RAM
FFF16
Automatic transfer
data pointer
5216
F5216
F5116
F5016
F4F16
F4E16
Transfer counter
0416
F0016
SIN1
SOUT1
Serial I/O1 register
Fig. 25 Automatic transfer serial I/O operation
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(4) Handshake signal
1. S STB1 output signal
The S STB1 output is a signal to inform an end of transmission/reception to the serial transfer destination . The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O initialization bit (b4) is reset to “0”, the S STB1 output goes to “L”, or
the S STB1 output goes to “H”.
At the end of transmit/receive operation, when the data of the serial I/O1 register is all output from S OUT1, pulses are output in the
period of 1 cycle of the transfer clock so as to cause the S STB1
output to go “H” or the S STB1 output to go “L”. After that, each
pulse is returned to the initial status in which SSTB1 output goes to
“L” or the SSTB1 output goes to “H”.
Furthermore, after 1 cycle, the serial transfer status flag (b5) is reset to “0”.
In the automatic transfer serial I/O mode, whether the SSTB1 output is to be active at an end of each 1-byte data or after
completion of transfer of all data can be selected by the S BUSY1
output • SSTB1 output function selection bit (b4 of address 001A16)
of serial I/O1 control register 2.
2. S BUSY1 input signal
The S BUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H”
level signal into the S BUSY1 input and an “L” level signal into the
SBUSY1 input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level signal into the SBUSY1 input and an “H” level signal into the SBUSY1
input in the period of 1.5 cycles or more of the transfer clock.
Then, transfer clocks are output from the S CLK1 output.
When an “H” level signal is input into the S BUSY1 input and an “L”
level signal into the SBUSY1 input after a transmit/receive operation is started, this transmit/receive operation are not stopped
immediately and the transfer clocks from the S CLK1 output is not
stopped until the specified number of bits are transmitted and received.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
When the external synchronous clock is selected, input an “H”
level signal into the S BUSY1 input and an “L” level signal into the
S BUSY1 input in the initial status in which transfer is stopped. At
this time, the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 become valid, enabling a transmit/receive operation, while an “L”
level signal is input into the SBUSY1 input and an “H” level signal is
input into the S BUSY1 input.
When changing the input values in the S BUSY1 input and the
SBUSY1 input at these operations, change them when the SCLK1
input is in a high state.
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, enabling serial transfer by inputting a transfer clock to SCLK1, while
an “L” level signal is input into the S BUSY1 input and an “H” level
signal is input into the S BUSY1 input.
SSTB1
Serial transfer
status flag
SCLK1
SOUT1
Fig. 26 SSTB1 output operation
SBUSY1
SCLK1
SOUT1
Fig. 27 SBUSY1 input operation (internal synchronous clock)
SBUSY1
SCLK1
Invalid
SOUT1
(Output high-impedance)
Fig. 28 SBUSY1 input operation (external synchronous clock)
3. SBUSY1 output signal
The SBUSY1 output is a signal which requests a stop of transmission/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external synchronous clock, whether the S BUSY1 output is to be active at
transfer of each 1-byte data or during transfer of all data can be
selected by the S BUSY1 output • SSTB1 output function selection bit
(b4).
In the initial status, the status in which the serial I/O initialization
bit (b4) is reset to “0”, the S BUSY1 output goes to “H” and the
SBUSY1 output goes to “L”.
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When the internal synchronous clock is selected, in the 8-bit serial
I/O mode and the automatic transfer serial I/O mode (SBUSY1 output function outputs in 1-byte units), the SBUSY1 output goes to “L”
and the SBUSY1 output goes to “H” before 0.5 cycle (transfer clock)
of the timing at which the transfer clock from the S CLK1 output
goes to “L” at a start of transmit/receive operation.
In the automatic transfer serial I/O mode (the SBUSY1 output function outputs all transfer data), the SBUSY1 output goes to “L” and
the SBUSY1 output goes to “H” when the first transmit data is written into the serial I/O1 register (address 001B16 ).
When the external synchronous clock is selected, the SBUSY1 output goes to “L” and the SBUSY1 output goes to “H” when transmit
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
data is written into the serial I/O1 register to start a transmit operation, regardless of the serial I/O transfer mode.
At termination of transmit/receive operation, the SBUSY1 output returns to “H” and the SBUSY1 output returns to “L”, the initial status,
when the serial transfer status flag is set to “0”, regardless of
whether the internal or external synchronous clock is selected.
Furthermore, in the automatic transfer serial I/O mode (SBUSY1
output function outputs in 1-byte units), the S BUSY1 output goes to
“H” and the SBUSY1 output goes to “L” each time 1-byte of receive
data is written into the automatic transfer RAM.
SBUSY1
SBUSY1
Serial transfer
status flag
Serial transfer
status flag
SCLK1
SCLK1
Write to Serial
I/O1 register
SOUT1
Fig. 29 SBUSY1 output operation
(internal synchronous clock, 8-bit serial I/O)
Fig. 30 SBUSY1 output operation
(external synchronous clock, 8-bit serial I/O)
Automatic transfer
interval
SCLK1
Serial I/O1 register
→Automatic transfer RAM
Automatic transfer RAM
→Serial I/O1 register
SBUSY1
Serial transfer
status flag
SOUT1
Fig. 31 SBUSY1 output operation in automatic transfer serial I/O mode
(internal synchronous clock, SBUSY1 output function outputs each 1-byte)
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MITSUBISHI MICROCOMPUTERS
.
4. S RDY1 output signal
The SRDY1 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready.
In the initial status, when the serial I/O initialization bit (b4) is reset
to “0”, the SRDY1 output goes to “L” and the SRDY1 output goes to
“H”. After transmitted data is stored in the serial I/O1 register (address 001B 16) and a transmit/receive operation becomes ready,
the SRDY1 output goes to “H” and the SRDY1 output goes to “L”.
When a transmit/receive operation is started and the transfer clock
goes to “L”, the S RDY1 output goes to “L” and the SRDY1 output
goes to “H”.
5. S RDY1 input signal
The SRDY1 input signal becomes valid only when the SRDY1 input
and the S BUSY1 output are used. The SRDY1 input is a signal for
receiving a transmit/receive ready completion signal from the serial transfer destination.
When the internal synchronous clock is selected, input a low level
signal into the S RDY1 input and a high level signal into the SRDY1
input in the initial status in which the transfer is stopped.
When an “H” level signal is input into the S RDY1 input and an “L”
level signal is input into the SRDY1 input for a period of 1.5 cycles
or more of transfer clock, transfer clocks are output from the
SCLK1 output and a transmit/receive operation is started.
After the transmit/receive operation is started and an “L” level signal is input into the S RDY1 input and an “H” level signal into the
SRDY1 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received,
the transfer clocks from the S CLK1 output is stopped. The handshake unit of the 8-bit serial I/O and that of the automatic transfer
serial I/O are of 8 bits.
When the external synchronous clock is selected, the S RDY1 input
becomes one of the triggers to output the SBUSY1 signal.
To start a transmit/receive operation (S BUSY1 output: “L”, S BUSY1
output: “H”), input an “H” level signal into the SRDY1 input and an
“L” level signal into the SRDY1 input, and also write transmit data
into the serial I/O1 register.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SRDY1
SCLK1
Write to serial
I/O1 register
Fig. 32 SRDY1 output operation
SRDY1
SCLK1
SOUT1
Fig. 33 SRDY1 input operation (internal synchronous clock)
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SCLK1
SCLK1
SRDY1
SRDY1
SBUSY1
A:
Write to serial
I/O1 register
SRDY1
SBUSY1
SBUSY1
A:
SCLK1
B:
Internal synchronous
clock selection
External synchronous
clock selection
B:
Write to serial
I/O1 register
Fig. 34 Handshake operation at serial I/O1 mutual connecting (1)
SCLK1
SCLK1
SRDY1
SRDY1
SBUSY1
A:
Write to serial
I/O1 register
SRDY1
SBUSY1
SBUSY1
A:
Internal synchronous
clock selection
SCLK1
B:
External synchronous
clock selection
B:
Fig. 35 Handshake operation at serial I/O1 mutual connecting (2)
36
Write to serial
I/O1 register
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.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
register (address 001D16 ) to “1”. For clock synchronous serial I/O,
the transmitter and the receiver must use the same clock for serial
I/O2 operation. If an internal clock is used, transmit/receive is
started by a write signal to the serial I/O2 transmit/receive buffer
register (TB/RB) (address 001F16).
When P6 7 (SCLK22) is selected as a clock I/O pin, S RDY2 output
function is invalid, and P66 (SCLK21) is used as an I/O port.
Serial I/O2 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 operation.
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control
Data bus
Serial I/O2 control register
Address 001F16
Receive buffer register
Shift clock
“0 ”
P66/SCLK21
P67/SRDY2/SCLK22
XIN
Serial I/O2 clock I/O pin selection bit
P67/SRDY2/SCLK22
P65/TXD
Clock control circuit
“1 ”
“0 ”
Internal system clock selection bit
Serial I/O2 synchronous clock selection bit
“0 ”
“1 ”
XCIN
Receive interrupt request (RI)
Receive shift register
P64/RXD
Address 001D16
Receive buffer full flag (RBF)
“1 ”
1/2
F/F
BRG count source selection bit Division ratio 1/(n+1)
Baud rate generator
BRG clock
Address 003716
1
/
4
switch bit
Falling edge detector
Serial I/O2
clock I/O pin
selection bit
1/4
Clock control circuit
Transmit shift register shift
completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Shift clock
Transmit shift register
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O2 status register
Address 001E16
Address 001F16
Data bus
Fig. 36 Block diagram of clock synchronous serial I/O2
Transmit/Receive shift clock
(1/2 to 1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F16)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Fig. 37 Operation of clock synchronous serial I/O2 function
37
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The transmit and receive shift registers each have a buffer (the
two buffers have the same address in memory). Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be
transmitted, and the receive buffer can receive 2-byte data continuously.
(2) Asynchronous serial I/O (UART) mode
The asynchronous serial I/O (UART) mode can be selected by
clearing the serial I/O2 mode selection bit (b6) of the serial I/O2
control register (address 001D16) to “0”. Eight serial data transfer
formats can be selected and the transfer formats used by the
transmitter and receiver must be identical.
Data bus
Serial I/O2 control register Address 001D16
Address 001F16
P64/RXD
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
OE
Character length selection bit
7 bit
ST detector
Receive shift register
1/16
8 bit
PE FE
P66/SCLK21
P67/SRDY2/SCLK22
XIN
“0 ”
Clock control circuit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 clock I/O pin
selection bit
“1 ”
Internal system clock selection bit
“0 ”
“1 ”
XCIN
UART control register
Address 003816
SP detector
1/2
BRG count source
selection bit
“1 ”
BRG clock
switch bit
1/4
Division ratio 1/(n+1)
Baud rate generator
Address 003716
ST/SP/PA generator
Transmit shift register shift
completion flag (TSC)
1/16
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
P65/TXD
Character length selection bit
Transmit buffer empty flag (TBE)
Address 001E16
Serial I/O2 status register
Transmit buffer register
Address 001F16
Data bus
Fig. 38 Block diagram of UART serial I/O2
Transmit or receive clock
Write-in signal to
transmit buffer register
TBE=0
TSC=0
TBE=1
Serial I/O2 output TXD
TBE=0
TBE=1
ST
D0
D1
SP
TSC=1*
ST
D0
D1
Read-out signal from receive
buffer register
SP
* Generated at 2nd bit in 2-stop
bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
RBF=0
RBF=1
Serial I/O2 input RXD
ST
D0
Fig. 39 Operation of UART serial I/O2 function
38
D1
SP
RBF=1
ST
D0
D1
SP
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O2 Control Register] SIO2CON (001D16)
The serial I/O2 control register contains eight control bits for serial
I/O2 functions.
[UART Control Register] UARTCON (0038 16)
This is a 7 bit register containing four control bits, of which four
bits are valid when UART is selected, and of which three bits are
always valid.
Data format of serial data receive/transfer and the output structure
of the P6 5/TxD pin and others are set by this register.
[Serial I/O2 Status Register] SIO2STS (001E16)
The read-only serial I/O2 status register consists of seven flags
(b0 to b6) which indicate the operating status of the serial I/O2
function and various errors. Three of the flags (b4 to b6) are only
valid in the UART mode. The receive buffer full flag (b1) is cleared
to “0” when the receive buffer is read.
The error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register,
and the receive buffer full flag is set. A writing to the serial I/O2
status register clears error flags OE, PE, FE, and SE (b3 to b6, respectively). Writing “0” to the serial I/O2 enable bit (SIOE : b7 of
the serial I/O2 control register) also clears all the status flags, including the error flags.
All bits of the serial I/O2 status register are initialized to “0” at reset, but if the transmit enable bit (b4) of the serial I/O2 control
register has been set to “1”, the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become “1”.
[Serial I/O2 Transmit Buffer Register/Receive
Buffer Register] TB/RB (001F16)
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored
in the receive buffer is “0”.
[Baud Rate Generator] BRG (0037 16)
The baud rate generator determines the baud rate for serial transfer. With the 8-bit counter having a reload register, the baud rate
generator divides the frequency of the count source by 1/(n+1),
where n is the value written to the baud rate generator.
39
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b7
b0
Serial I/O2 status register
(SIO2STS : address 001E16)
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
b7
b0
UART control register
(UARTCON : address 003816)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P65/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
BRG clock switch bit
0: XIN or XCIN (depends on internal system clock)
1: XCIN
Serial I/O2 clock I/O pin selection bit
0: SCLK21 (P67/SCLK22 pin is used as I/O port or SRDY2 output pin.)
1: SCLK22 (P66/SCLK21 pin is used as I/O port.)
Not used (return “1” when read)
Fig. 40 Structure of serial I/O2 related register
40
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
BRG count source selection bit (CSS)
0: f(XIN) or f(XCIN)/2 or f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
SRDY2 output enable bit (SRDY)
0: P67 pin operates as ordinary I/O pin
1: P67 pin operates as SRDY2 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O2 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
(pins P64 to P67 operate as ordinary I/O pins)
1: Serial I/O2 enabled
(pins P64 to P67 operate as serial I/O pins)
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.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O3
The serial I/O3 function can be used only for 8-bit clock synchronous serial I/O.
All serial I/O pins are shared with port P9, which can be set with
the serial I/O3 control register (address 0EEC 16).
b7
b0
Internal synchronous clock selection bits
b2 b1 b0
0 0 0: f(XIN)/4 (f(XCIN)/8)
0 0 1: f(XIN)/8 (f(XCIN)/16)
0 1 0: f(XIN)/16 (f(XCIN)/32)
0 1 1: f(XIN)/32 (f(XCIN)/64)
1 1 0: f(XIN)/64 (f(XCIN)/128)
1 1 1: f(XIN)/128 (f(XCIN)/256)
[Serial I/O3 Control Register (SIO3CON)] 0EEC16
The serial I/O3 control register contains eight bits which control
various serial I/O functions.
Serial I/O3 port selection bit (P91, P92)
0: I/O port
1: SOUT3, SCLK3 signal output
● Serial I/O3 Operation
Either the internal clock or external clock can be selected as synchronous clock for serial I/O3 transfer.
The internal clock can use a built-in dedicated divider where 6 different clocks are selected. In the case of the internal clock used,
transfer is started by a write signal to the serial I/O3 register (address 0EED 16). When 8-bit data has been transferred, the SOUT3
pin goes to high impedance state.
In the case of the external clock used, the clock must be externally
controlled. It is because the contents of serial I/O3 register is kept
shifted while the clock is being input. Additionally, the function to
put the S OUT3 pin high impedance state at completion of data
transfer is not available.
The serial I/O3 interrupt request bit is set at completion of 8-bit
data transfer, regardless of use of the internal clock or external
clock.
1/2
SRDY3 output selection bit (P93)
0: I/O port
1: SRDY3 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O3 synchronous clock selection bit
0: External clock
1: Internal clock
P91/SOUT3 P-channel output disable bit (P91)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Fig. 42 Structure of serial I/O3 control register
1/4
Internal system clock
selection bit
“1 ”
Internal synchronous
clock selection bits
1/8
Divider
XCIN
Serial I/O3 control register
(SIO3CON : address 0EEC16)
XIN
“0 ”
1/16
Data bus
1/32
1/64
1/128
P93 latch
“0 ”
SRDY3
Synchronization
“1 ”
circuit
SRDY3 output selection bit
SCLK3
P93/SRDY3
Serial I/O3 synchronous
clock selection bit “1”
“0 ”
External clock
P92 latch
“0 ”
P92/SCLK3
“1 ”
Serial I/O3 port selection bit
Serial I/O3 counter (3)
Serial I/O3
interrupt request
P91 latch
“0 ”
P91/SOUT3
“1 ”
Serial I/O3 port selection bit
P90/SIN3
Serial I/O3 shift register (8)
Fig. 41 Block diagram of serial I/O3
41
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Synchronous clock
Transfer clock
Serial I/O3 register
write signal
(Note)
Serial I/O3 output SOUT3
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O3 input SIN3
Receive enable signal SRDY3
Note: When the internal clock is selected as the transfer clock, the SOUT3 pin goes to high
impedance after transfer completion.
Fig. 43 Timing of serial I/O3 (LSB first)
42
Serial I/O3 interrupt request bit set
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD CONTROLLER
The M38B7 group has fluorescent display (FLD) drive and control
circuits.
Table 9 shows the FLD controller specifications.
Table 9 FLD controller specifications
FLD
controller
port
Item
High-breakdownvoltage output port
CMOS port
Display pixel number
Period
Dimmer time
Interrupt
Key-scan
Expanded function
Specifications
• 52 pins (20 pins can be switched to general-purpose ports)
• 4 pins (all 4 pins can be switched to general-purpose ports)
(A driver IC must be installed externally)
• Used FLD output
28 segment ✕ 28 digit (segment number + digit number ≤ 56)
• Used digit output
40 segment ✕ 16 digit (segment number ≤ 40, digit number ≤ 16)
• Connected to M35501
56 segment ✕ (connected number of M35501) digit
(segment number ≤ 56, digit number ≤ number of M35501 ✕ 16)
• Used P6 4 to P67 expansion
52 segment ✕ 16 digit (segment number ≤ 52, digit number ≤ 16)
• 4.0 µs to 1024 µs (count source X IN/16, 4 MHz)
• 16.0 µs to 4096 µs (count source X IN/64, 4 MHz)
• 4.0 µs to 1024 µs (count source X IN/16, 4 MHz)
• 16.0 µs to 4096 µs (count source X IN/64, 4 MHz)
• Digit interrupt
• FLD blanking interrupt
• Key-scan using digit
• Key-scan using segment
• Digit pulse output function
This function automatically outputs digit pulses.
• M35501 connection function
The number of digits can be increased easily by using the output of DIMOUT (P73 ) as CLK for the
M35501.
• Toff section generating/nothing function
This function does not generate Toff1 section when the connected outputs are the same.
• Gradation display function
This function allows each segment to be set for dark or bright display.
• P64 to P67 expansion function
This function provides 16 lines of digit outputs from four ports by attaching the decoder converting
4-bit data to 16-bit data.
43
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Main
data bus
Main address bus
Local
data bus
Digit output set switch register
P20/FLD0 DIG/FLD
P21/FLD1 DIG/FLD
P22/FLD2 DIG/FLD
P23/FLD3 DIG/FLD 8
Local address bus
FLD automatic display RAM
0E0016
P24/FLD4
P25/FLD5
P26/FLD6
P27/FLD7
000416
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
0EF316
P00/FLD8
P01/FLD9
P02/FLD10
P03/FLD11
P04/FLD12
P05/FLD13
P06/FLD14
P07/FLD15
000016
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD 8
DIG/FLD
DIG/FLD
DIG/FLD
DIG/FLD
0EF216
P10/FLD16
P11/FLD17
P12/FLD18
P13/FLD19 8
P14/FLD20
P15/FLD21
P16/FLD22
P17/FLD23
000216
0EDF16
P30/FLD24
P31/FLD25
P32/FLD26
P33/FLD27 8
P34/FLD28
P35/FLD29
P36/FLD30
P37/FLD31
000616
FLDC mode
register
(0EF416)
FLD data pointer
reload register
(0EF816)
Address
decoder
FLD data pointer
(0EF816)
Timing generator
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
0EF916
P40/FLD32
P41/FLD33
P42/FLD34
P43/FLD35 8
P44/FLD36
P45/FLD37
P46/FLD38
P47/FLD39
000816
FLD/P P50/FLD40
FLD/P P51/FLD41
FLD/P P52/FLD42
FLD/P P53/FLD43 8
FLD/P P54/FLD44
FLD/P P55/FLD45
FLD/P P56/FLD46
FLD/P P57/FLD47
000A16
0EFA16
FLD blanking interrupt
FLD digit interrupt
FLD/P P60/FLD48
FLD/P P61/FLD49
FLD/P P62/FLD50
FLD/P P63/FLD51 8
FLD/P P64/FLD52
FLD/P P65/FLD53
FLD/P P66/FLD54
FLD/P P67/FLD55
000C16
0EFB16
FLD/Port switch register
Fig. 44 Block diagram of FLD control circuit
44
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 b6 b5 b4 b3 b2 b1 b0
FLDC mode register
(FLDM: address 0EF416)
Automatic display control bit
0 : General-purpose mode
1 : Automatic display mode
Display start bit
0 : Stop display
1 : Display (start to display by switching “0” to “1”)
Tscan control bits
b3b2
0 0 : FLD digit interrupt (at rising edge of each digit)
0 1 : 1 ✕ Tdisp
1 0 : 2 ✕ Tdisp
FLD blanking interrupt
1 1 : 3 ✕ Tdisp
(at falling edge of the last digit)
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
Gradation display mode selection control bit
0 : Not selecting
1 : Selecting (Note)
Tdisp counter count source selection bit
0 : f(XIN)/16
1 : f(XIN)/64
High-breakdown voltage port drivability selection bit
0 : Drivability strong
1 : Drivability weak
Note: When the gradation display mode is selected, the max. number of timing is 16
timing. (Be sure to set the timing number control bit to “0”.)
b7 b6 b5 b4 b3 b2 b1 b0
FLD output control register
(FLDCON: address 0EFC16)
P64 to P67 output reverse bit
0 : Output normally
1 : Reverse output
Not used (return “0” when read); (Do not write “1”.)
P64 to P67 Toff invalid bit
0 : Operation normally
1 : Toff invalid
Not used (return “0” when read); (Do not write “1”.)
P73 dimmer output control bit
0 : Normal port
1 : Dimmer output
Generating/Not of CMOS port Toff section selection bit
0 : Toff section not generated
1 : Toff section generated
Generating/Not of high-breakdown voltage port Toff section
selection bit
0 : Toff section not generated
1 : Toff section generated
Toff2 SET/RESET switch bit
0 : Toff2 RESET; Toff1 SET
1 : Toff2 SET; Tdisp RESET
Fig. 45 Structure of FLDC related registers (1)
45
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 b6 b5 b4 b3 b2 b1 b0
Port P4 FLD/Port switch register
(P4FPR: address 0EF916)
Port P40 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P41 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P42 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P43 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P44 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P45 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P46 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P47 FLD/Port switch bit
0 : Normal port
1 : FLD output port
b7 b6 b5 b4 b3 b2 b1 b0
Port P5 FLD/Port switch register
(P5FPR: address 0EFA16)
Port P50 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P51 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P52 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P53 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P54 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P55 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P56 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P57 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Fig. 46 Structure of FLDC related registers (2)
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 FLD/Port switch register
(P6FPR: address 0EFB16)
Port P60 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P61 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P62 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P63 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P64 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P65 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Port P66 FLD/Port switch bit
0 : Normal port
1 : FLD output Port
Port P67 FLD/Port switch bit
0 : Normal port
1 : FLD output port
Fig. 47 Structure of FLDC related registers (3)
47
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 digit output set switch register
(P0DOR: address 0EF216)
Port P00 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P01 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P02 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P03 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P04 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P05 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P06 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P07 FLD/Digit switch bit
0 : FLD output
1 : Digit output
b7 b6 b5 b4 b3 b2 b1 b0
Port P2 digit output set switch register
(P2DOR: address 0EF316)
Port P20 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P21 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P22 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P23 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P24 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P25 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P26 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Port P27 FLD/Digit switch bit
0 : FLD output
1 : Digit output
Fig. 48 Structure of FLDC related registers (4)
48
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD Automatic Display Pins
P0 to P6 are the pins capable of automatic display output for the
FLD. The FLD starts operating by setting the automatic display
control bit (bit 0 at address 0EF416 ) to “1”. There is the FLD output
function that outputs the RAM contents from the port every timing
or the digit output function that drives the port high with a digit tim-
ing. The FLD can be displayed using the FLD output for the segments and the digit or FLD output for the digits. When using the
FLD output for the digits, be sure to write digit display patterns to
the RAM in advance. The remaining segment and digit lines can
be used as general-purpose ports. Settings of each port are
shown below.
Table 10 Pins in FLD automatic display mode
Automatic display pin
Setting method
Port
FLD0 to FLD 15
The individual bits of the digit output set switch registers (addresses 0EF216 , 0EF316) can
P0, P2
set each pin to either an FLD port (“0”) or a digit port (“1”).
When the pins are set for the digit port, the digit pulse output function is enabled, so that the
digit pulses can always be output regardless the value of FLD automatic display RAM.
Setting the automatic display control bit (bit 0 of address 0EF416 ) to “1” can set these ports
P1, P3
FLD 16 to FLD 31
to the FLD exclusive use port.
P4, P5,
FLD32 to FLD 51
The individual bits of the FLD/Port switch register (addresses 0EF916 to 0EFB 16 ) can set
P60 to P63
each pin to either an FLD port (“1”) or a general-purpose port (“0”).
P64 to P67
FLD52 to FLD 55
The individual bits of the port P6 FLD/Port switch register (address 0EFB16) can set each
pin to either FLD port (“1”) or general-purpose port (“0”). A variety of output pulses can be
available by setting of the FLD output control register (address 0EFC16 ). The port output
structure is the CMOS output. When using the port as a display pin, a driver IC must be installed externally.
Setting example 1
This is a register setup example where only FLD output is used.
In this case, the digit display output pattern must be set in the FLD automatic
display RAM in advance.
Number of segments
Number of digits
Port P2
Port P0
Port P1
36
16
The contents of digit output set switch registers
(0EF216, 0EF316)
FLD0 (DIG output)
FLD1 (DIG output)
FLD2 (DIG output)
FLD3 (DIG output)
FLD4 (DIG output)
FLD5 (DIG output)
FLD6 (DIG output)
FLD7 (DIG output)
0
0
0
0
0
0
0
0
FLD8 (DIG output)
FLD9 (DIG output)
FLD10 (DIG output)
FLD11 (DIG output)
FLD12 (DIG output)
FLD13 (DIG output)
FLD14 (DIG output)
FLD15 (DIG output)
0
0
0
0
0
0
FLD16 (SEG output)
FLD17 (SEG output)
FLD18 (SEG output)
FLD19 (SEG output)
FLD20 (SEG output)
FLD21 (SEG output)
FLD22 (SEG output)
FLD24 (SEG output)
FLD25 (SEG output)
FLD26 (SEG output)
FLD27 (SEG output)
FLD28 (SEG output)
FLD29 (SEG output)
FLD30 (SEG output)
FLD31 (SEG output)
Number of segments
Number of digits
Port P2
FLD/Port switch registers
(0EF916 to 0EFB16)
Port P4
0
0
Port P5
FLD23 (SEG output)
Port P3
Setting example 2
This is a register setup example where both FLD output and digit waveform output are
used. In this case, because the digit display output is automatically generated, there is
no need to set the display pattern in the FLD automatic display RAM.
Port P6
1
1
1
1
1
1
1
1
FLD32 (SEG output)
FLD33 (SEG output)
FLD34 (SEG output)
FLD35 (SEG output)
FLD36 (SEG output)
FLD37 (SEG output)
FLD38 (SEG output)
Port P0
FLD39(SEG output)
1 FLD40 (SEG output)
1 FLD41 (SEG output)
1 FLD42 (SEG output)
1 FLD43 (SEG output)
1 FLD44 (SEG output)
1 FLD45 (SEG output)
1 FLD46 (SEG output)
1 FLD47 (SEG output)
Port P1
1
1
1
1
0
0
0
0
Port P3
FLD48 (SEG output)
FLD49 (SEG output)
FLD50 (SEG output)
FLD51 (SEG output)
FLD52 (port output)
FLD53 (port output)
FLD54 (port output)
FLD55 (port output)
DIG output : This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is general-purpose port (used by program).
28
12
The contents of digit output set switch registers
(0EF216, 0EF316)
FLD0 (DIG output)
FLD1 (DIG output)
FLD2 (DIG output)
FLD3 (DIG output)
FLD4 (DIG output)
FLD5 (DIG output)
FLD6 (DIG output)
FLD7 (DIG output)
1
1
1
1
1
1
1
1
FLD8 (DIG output)
FLD9 (DIG output)
FLD10 (DIG output)
FLD11 (DIG output)
FLD12 (SEG output)
FLD13 (SEG output)
FLD14 (SEG output)
FLD15 (SEG output)
1
1
1
1
0
0
FLD16 (SEG output)
FLD17 (SEG output)
FLD18 (SEG output)
FLD19 (SEG output)
FLD20 (SEG output)
FLD21 (SEG output)
FLD22 (SEG output)
FLD23 (SEG output)
FLD24 (SEG output)
FLD25 (SEG output)
FLD26 (SEG output)
FLD27 (SEG output)
FLD28 (SEG output)
FLD29 (SEG output)
FLD30 (SEG output)
FLD31 (SEG output)
FLD/Port switch registers
(0EF916 to 0EFB16)
Port P4
0
0
Port P5
Port P6
1
1
1
1
1
1
1
1
FLD32 (SEG output)
1
1
1
1
0
0
0
0
FLD40 (SEG output)
FLD41 (SEG output)
FLD42 (SEG output)
FLD43 (SEG output)
0
0
0
0
0
FLD48 (port output)
FLD49 (port output)
FLD50 (port output)
FLD51 (port output)
FLD52 (port output)
FLD33 (SEG output)
FLD34 (SEG output)
FLD35 (SEG output)
FLD36 (SEG output)
FLD37 (SEG output)
FLD38 (SEG output)
FLD39 (SEG output)
FLD44 (port output)
FLD45 (port output)
FLD46 (port output)
FLD47 (port output)
0 FLD53 (port output)
0 FLD54 (port output)
0 FLD55 (port output)
DIG output : This output is connected to digit of the FLD.
SEG output : This output is connected to segment of the FLD.
Port output : This output is general-purpose port (used by program).
Fig. 49 Segment/Digit setting example
49
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD Automatic Display RAM
(3) 32-timing mode
The FLD automatic display RAM uses the 224 bytes of addresses
0E0016 to 0EDF16. For FLD, the 3 modes of 16-timing•ordinary
mode, 16-timing•gradation display mode and 32-timing mode are
available depending on the number of timings and the use/not use
of gradation display.
The automatic display RAM in each mode is as follows:
This mode is used when the display timing is 16 or greater. This
mode can be used for up to 32-timing.
The 224 bytes of addresses 0E00 16 to 0EDF16 are used as an
FLD display data store area.
(1) 16-timing•ordinary mode
This mode is used when the display timing is 16 or less. The 112
bytes of addresses 0E7016 to 0EDF 16 are used as a FLD display
data store area. Because addresses 0E0016 to 0E6F 16 are not
used as the automatic display RAM, they can be the ordinary
RAM.
The FLD data pointer (address 0EF8 16 ) is a register to count display timings. This pointer has a reload register. When the pointer
underflow occurs, it starts counting over again after being reloaded with the initial value in the reload register. Make sure that
(the timing counts – 1) is set to the FLD data pointer. When writing
data to this address, the data is written to the FLD data pointer reload register; when reading data from this address, the value in
the FLD data pointer is read.
(2) 16-timing•gradation display mode
This mode is used when the display timing is 16 or less, in which
mode each segment can be set for dark or bright display. The 224
bytes of addresses 0E0016 to 0EDF16 are used. The 112 bytes of
addresses 0E70 16 to 0EDF16 are used as an FLD display data
store area, while the 112 bytes of addresses 0E0016 to 0E6F16 are
used as a gradation display control data store area.
16-timing•ordinary mode
16-timing•gradation display mode
0E0016
0E0016
1 to 32 timing display
data stored area
0E7016
1 to 16 timing display
data stored area
0EDF16
Fig. 50 FLD automatic display RAM assignment
50
0E0016
Gradation display
control data stored
area
Not used
0E7016
32-timing mode
1 to 16 timing display
data stored area
0EDF16
0EDF16
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data Setup
(1) 16-timing•ordinary mode
(2) 16-timing•gradation display mode
The area of addresses 0E7016 to 0EDF16 are used as a FLD automatic display RAM.
When data is stored in the FLD automatic display RAM, the last
data of FLD port P6 is stored at address 0E70 16 , the last data of
FLD port P5 is stored at address 0E80 16, the last data of FLD port
P4 is stored at address 0E90 16, the last data of FLD port P3 is
stored at address 0EA016 , the last data of FLD port P1 is stored at
address 0EB016 , the last data of FLD port P0 is stored at address
0EC0 16, and the last data of FLD port P2 is stored at address
0ED016 , to assign in sequence from the last data respectively.
The first data of the FLD port P6, P5, P4, P3, P1, P0, and P2 is
stored at an address which adds the value of (the timing number –
1) to the corresponding addresses 0E7016 , 0E8016, 0E90 16,
0EA016 , 0EB016, 0EC016 and 0ED016.
Set the FLD data pointer reload register to the value given by (the
timing number – 1).
Display data setting is performed in the same way as that of the
16-timing•ordinary mode. Gradation display control data is arranged at an address resulting from subtracting 007016 from the
display data store address of each timing and pin. Bright display is
performed by setting “0”, and dark display is performed by setting
“1” .
(3) 32-timing Mode
The area of addresses 0E0016 to 0EDF16 is used as a FLD automatic display RAM.
When data is stored in the FLD automatic display RAM, the last
data of FLD port P6 is stored at address 0E0016 , the last data of
FLD port P5 is stored at address 0E20 16, the last data of FLD port
P4 is stored at address 0E4016, the last data of FLD port P3 is
stored at address 0E60 16, the last data of FLD port P1 is stored at
address 0E8016 , the last data of FLD port P0 is stored at address
0EA016, and the last data of FLD port P2 is stored at address
0EC016, to assign in sequence from the last data respectively.
The first data of the FLD port P6, P5, P4, P3, P1, P0, and P2 is
stored at an address which adds the value of (the timing number –
1) to the corresponding addresses 0E00 16, 0E20 16, 0E4016 ,
0E6016 , 0E8016, 0EA016 and 0EC016.
Set the FLD data pointer reload register to the value given by (the
timing number – 1).
Number of timing: 8
(FLD data pointer reload register = 7)
B it
Address
0E7016
0E7116
0E7216
0E7316
0E7416
0E7516
0E7616
0E7716
0E7816
0E7916
0E7A16
0E7B16
0E7C16
0E7D16
0E7E16
0E7F16
0E8016
0E8116
0E8216
0E8316
0E8416
0E8516
0E8616
0E8716
0E8816
0E8916
0E8A16
0E8B16
0E8C16
0E8D16
0E8E16
0E8F16
0E9016
0E9116
0E9216
0E9316
0E9416
0E9516
0E9616
0E9716
0E9816
0E9916
0E9A16
0E9B16
0E9C16
0E9D16
0E9E16
0E9F16
0EA016
0EA116
0EA216
0EA316
0EA416
0EA516
0EA616
0EA716
0EA816
0EA916
0EAA16
0EAB16
0EAC16
0EAD16
0EAE16
0EAF16
7
6
5
4
3
2
1
B it
0
Address
The last timing
(The last data of FLDP6)
Timing for start
(The first data of FLDP6)
FLDP6 data area
The last timing
(The last data of FLDP5)
Timing for start
(The first data of FLDP5)
FLDP5 data area
The last timing
(The last data of FLDP4)
Timing for start
(The first data of FLDP4)
FLDP4 data area
0EB016
0EB116
0EB216
0EB316
0EB416
0EB516
0EB616
0EB716
0EB816
0EB916
0EBA16
0EBB16
0EBC16
0EBD16
0EBE16
0EBF16
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
0EDA16
0EDB16
0EDC16
0EDD16
0EDE16
0EDF16
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP1)
Timing for start
(The first data of FLDP1)
FLDP1 data area
The last timing
(The last data of FLDP0)
Timing for start
(The first data of FLDP0)
FLDP0 data area
The last timing
(The last data of FLDP2)
Timing for start
(The first data of FLDP2)
FLDP2 data area
The last timing
(The last data of FLDP3)
Timing for start
(The first data of FLDP3)
FLDP3 data area
Fig. 51 Example of using FLD automatic display RAM in 16-timing•ordinary mode
51
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Number of timing: 15
(FLD data pointer reload register = 14)
B it
Address
0E7016
0E7116
0E7216
0E7316
0E7416
0E7516
0E7616
0E7716
0E7816
0E7916
0E7A16
0E7B16
0E7C16
0E7D16
0E7E16
0E7F16
0E8016
0E8116
0E8216
0E8316
0E8416
0E8516
0E8616
0E8716
0E8816
0E8916
0E8A16
0E8B16
0E8C16
0E8D16
0E8E16
0E8F16
0E9016
0E9116
0E9216
0E9316
0E9416
0E9516
0E9616
0E9716
0E9816
0E9916
0E9A16
0E9B16
0E9C16
0E9D16
0E9E16
0E9F16
0EA016
0EA116
0EA216
0EA316
0EA416
0EA516
0EA616
0EA716
0EA816
0EA916
0EAA16
0EAB16
0EAC16
0EAD16
0EAE16
0EAF16
0EB016
0EB116
0EB216
0EB316
0EB416
0EB516
0EB616
0EB716
0EB816
0EB916
0EBA16
0EBB16
0EBC16
0EBD16
0EBE16
0EBF16
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
0EDA16
0EDB16
0EDC16
0EDD16
0EDE16
0EDF16
7
6
5
4
3
2
1
B it
0
Address
The last timing
(The last data of FLDP6)
FLDP6 data area
Timing for start
(The first data of FLDP6)
The last timing
(The last data of FLDP5)
FLDP5 data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP4)
FLDP4 data area
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
7
6
5
4
3
2
1
0
0E0016
0E0116
0E0216
0E0316
0E0416
0E0516
0E0616
0E0716
0E0816
0E0916
0E0A16
0E0B16
0E0C16
0E0D16
0E0E16
0E0F16
0E1016
0E1116
0E1216
0E1316
0E1416
0E1516
0E1616
0E1716
0E1816
0E1916
0E1A16
0E1B16
0E1C16
0E1D16
0E1E16
0E1F16
0E2016
0E2116
0E2216
0E2316
0E2416
0E2516
0E2616
0E2716
0E2816
0E2916
0E2A16
0E2B16
0E2C16
0E2D16
0E2E16
0E2F16
0E3016
0E3116
0E3216
0E3316
0E3416
0E3516
0E3616
0E3716
0E3816
0E3916
0E3A16
0E3B16
0E3C16
0E3D16
0E3E16
0E3F16
0E4016
0E4116
0E4216
0E4316
0E4416
0E4516
0E4616
0E4716
0E4816
0E4916
0E4A16
0E4B16
0E4C16
0E4D16
0E4E16
0E4F16
0E5016
0E5116
0E5216
0E5316
0E5416
0E5516
0E5616
0E5716
0E5816
0E5916
0E5A16
0E5B16
0E5C16
0E5D16
0E5E16
0E5F16
0E6016
0E6116
0E6216
0E6316
0E6416
0E6516
0E6616
0E6716
0E6816
0E6916
0E6A16
0E6B16
0E6C16
0E6D16
0E6E16
0E6F16
Fig. 52 Example of using FLD automatic display RAM in 16-timing•gradation display mode
52
The last timing
(The last data of FLDP6)
FLDP6 gradation
display data area
Timing for start
(The first data of FLDP6)
The last timing
(The last data of FLDP5)
FLDP5 gradation
display data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP4)
FLDP4 gradation
display data area
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
FLDP3 gradation
display data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP1)
FLDP1 gradation
display data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP0 gradation
display data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP2)
FLDP2 gradation
display data area
Timing for start
(The first data of FLDP2)
MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
B it
Number of timing: 20
(FLD data pointer reload register = 19)
B it
Address
0E7016
0E7116
0E7216
0E7316
0E7416
0E7516
0E7616
0E7716
0E7816
0E7916
0E7A16
0E7B16
0E7C16
0E7D16
0E7E16
0E7F16
0E8016
0E8116
0E8216
0E8316
0E8416
0E8516
0E8616
0E8716
0E8816
0E8916
0E8A16
0E8B16
0E8C16
0E8D16
0E8E16
0E8F16
0E9016
0E9116
0E9216
0E9316
0E9416
0E9516
0E9616
0E9716
0E9816
0E9916
0E9A16
0E9B16
0E9C16
0E9D16
0E9E16
0E9F16
0EA016
0EA116
0EA216
0EA316
0EA416
0EA516
0EA616
0EA716
0EA816
0EA916
0EAA16
0EAB16
0EAC16
0EAD16
0EAE16
0EAF16
0EB016
0EB116
0EB216
0EB316
0EB416
0EB516
0EB616
0EB716
0EB816
0EB916
0EBA16
0EBB16
0EBC16
0EBD16
0EBE16
0EBF16
0EC016
0EC116
0EC216
0EC316
0EC416
0EC516
0EC616
0EC716
0EC816
0EC916
0ECA16
0ECB16
0ECC16
0ECD16
0ECE16
0ECF16
0ED016
0ED116
0ED216
0ED316
0ED416
0ED516
0ED616
0ED716
0ED816
0ED916
0EDA16
0EDB16
0EDC16
0EDD16
0EDE16
0EDF16
7
6
5
4
3
2
Address
1
0
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
0E0016
0E0116
0E0216
0E0316
0E0416
0E0516
0E0616
0E0716
0E0816
0E0916
0E0A16
0E0B16
0E0C16
0E0D16
0E0E16
0E0F16
0E1016
0E1116
0E1216
0E1316
0E1416
0E1516
0E1616
0E1716
0E1816
0E1916
0E1A16
0E1B16
0E1C16
0E1D16
0E1E16
0E1F16
0E2016
0E2116
0E2216
0E2316
0E2416
0E2516
0E2616
0E2716
0E2816
0E2916
0E2A16
0E2B16
0E2C16
0E2D16
0E2E16
0E2F16
0E3016
0E3116
0E3216
0E3316
0E3416
0E3516
0E3616
0E3716
0E3816
0E3916
0E3A16
0E3B16
0E3C16
0E3D16
0E3E16
0E3F16
0E4016
0E4116
0E4216
0E4316
0E4416
0E4516
0E4616
0E4716
0E4816
0E4916
0E4A16
0E4B16
0E4C16
0E4D16
0E4E16
0E4F16
0E5016
0E5116
0E5216
0E5316
0E5416
0E5516
0E5616
0E5716
0E5816
0E5916
0E5A16
0E5B16
0E5C16
0E5D16
0E5E16
0E5F16
0E6016
0E6116
0E6216
0E6316
0E6416
0E6516
0E6616
0E6716
0E6816
0E6916
0E6A16
0E6B16
0E6C16
0E6D16
0E6E16
0E6F16
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP6)
FLDP6 data area
Timing for start
(The first data of FLDP6)
The last timing
(The last data of FLDP5)
FLDP5 data area
Timing for start
(The first data of FLDP5)
The last timing
(The last data of FLDP4)
FLDP4 data area
Timing for start
(The first data of FLDP4)
The last timing
(The last data of FLDP3)
FLDP3 data area
Fig. 53 Example of using FLD automatic display RAM in 32-timing mode
53
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing Setting
(3) Toff2 time setting
Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register.
The Toff2 time is time for dark display. For bright display, the FLD
display output remains effective until the counter that is counting
Tdisp underflows. For dark display, however, “L” (or “off”) signal is
output when the counter that is counting Toff2 underflows. This
Toff2 time setting is valid only for FLD ports which are in the gradation display mode and whose gradation display control RAM
value is “1” .
Set the Toff2 time by the Toff2 time set register. Make sure the
value set to Toff2 is smaller than Tdisp but larger than Toff1. Supposing that the value of the Toff2 time set register is n2, the Toff2
time is represented as Toff2 = n2 ✕ t. When the Tdisp counter
count source selection bit of the FLDC mode register is “0” and
the value of the Toff2 time set register is 180 (B416 ), Toff2 = 180 ✕
4.0 µs (at XIN = 4 MHz) = 720 µs.
When bit 7 of the FLD output control register (address 0EFC 16 ) is
set to “1”, be sure to set the value of 0316 or more to the Toff2 time
set register (address 0EF716 ).
(1) Tdisp time setting
The Tdisp time means the length of display timing. In non-gradation display mode, it consists of the FLD display output term and
the Toff1 time. In gradation display mode, it consists of the display
output term and the Toff1 time plus a low signal output term for
dark display. Set the Tdisp time by the Tdisp counter count source
selection bit of the FLDC mode register and the Tdisp time set
register. Supposing that the value of the Tdisp time set register is
n, the Tdisp time is represented as Tdisp = (n+1) ✕ t (t: count
source). When the Tdisp counter count source selection bit of the
FLDC mode register is “0” and the value of the Tdisp time set register is 200 (C816 ), the Tdisp time is: Tdisp = (200 + 1) ✕ 4.0 µs (at
XIN = 4 MHz) = 804 µs. When reading the Tdisp time set register,
the counting value is read out.
(2) Toff1 time setting
The Toff1 time means a non-output (low signal output) time to prevent blurring of FLD and for dimmer display. Use the Toff1 time set
register to set this Toff1 time. Make sure the value set to Toff1 is
smaller than Tdisp and Toff2. Supposing that the value of the Toff1
time set register is n1, the Toff1 time is represented as Toff1 =
n1 ✕ t. When the Tdisp counter count source selection bit of the
FLDC mode register is “0” and the value of the Toff1 time set register is 30 (1E16 ), Toff1 = 30 ✕ 4.0 µs (at X IN = 4 MHz) = 120 µs.
Be sure to set the value of 0316 or more to the Toff1 time set register (address 0EF616 ).
Low output term for
blurring prevention
Display output term
•Gradation display mode is not selected
(Address 0EF416 bit 5 = “0”)
•Gradation display mode is selected and set for bright display
(Address 0EF416 bit 5 = “1” and the corresponding gradation
display control data = “0”)
Toff1
Tdisp
Low output term for
blurring prevention Display output term
•Gradation display mode is selected and set for dark display
(Address 0EF416 bit 5 = “1” and the corresponding gradation
display control data = “1”)
Toff1
Toff2
Tdisp
Fig. 54 FLD and digit output timing
54
Low output term for
dark display
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.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD Automatic Display Start
Key-scan and Interrupt
Automatic display starts by setting both the automatic display control bit (bit 0 of address 0EF4 16 ) and the display start bit (bit 1 of
address 0EF4 16) to “1”. The RAM contents at a location apart from
the start address of the automatic display RAM for each port by
(FLD data pointer (address 0EF816 ) – 1) are output to each port.
The FLD data pointer (address 0EF8 16) counts down in the Tdisp
interval. When the count results in “FF16 ”, the pointer is reloaded
and starts counting over again. Before setting the display start bit
(bit 1 of address 0EF4 16) to “1”, be sure to set the FLD/port switch
registers, digit output set switch registers, FLDC mode register,
Tdisp time set register, Toff1 time set register, Toff2 time set register, and FLD data pointer.
During FLD automatic display, the display start bit always keeps
“1”, and FLD automatic display can be interrupted by writing “0” to
this bit.
Either the FLD digit interrupt or FLD blanking interrupt can be selected using the Tscan control bits (bits 2, 3 of address 0EF4 16).
The FLD digit interrupt is generated when the Toff1 time in each
timing expires (at rising edge of digit output). Key scanning that
makes use of FLD digits can be achieved using each FLD digit interrupt. To use FLD digit interrupts for key scanning, follow the
procedure described below:
(1) Read the port value each time the interrupt occurs.
(2) The key is fixed on the last digit interrupt.
The output digit positions can be determined by reading the FLD
data pointer (address 0EF816 ).
Repeat cycle
Tdisp
Toff1
Tn
Tn-1 Tn-2
T4
T3
T2
T1
Tn
Tn-1 Tn-2
T4
FLD digit output
FLD digit interrupt generated at the rising edge of digit (each timing)
Fig. 55 Timing using digit interrupt
55
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
■ Note
The FLD blanking interrupt is generated when the FLD data
pointer (address 0EF816 ) reaches “FF16 ”. The FLD automatic display output is turned off for a duration of 1 ✕ Tdisp, 2 ✕ Tdisp, or
3 ✕ Tdisp depending on post-interrupt settings. During this time,
key scanning that makes use of FLD segments can be achieved.
When the key scanning is performed with the segment during
key-scan blanking time Tscan, follow the procedure described
below:
(1) Write “0” to the automatic display control bit (bit 0 of address
0EF416).
(2) Set the port corresponding to the segment for key scanning to
the output port.
(3) Perform key scanning.
(4) Write “1” to the automatic display control bit.
When performing a key-scan according to the above steps 1 to 4,
take the following points into consideration.
1. Do not set the display start bit (bit 1 of address 0EF416 ) to “0”.
2. Do not set “1” in the ports corresponding to digits.
Repeat cycle
Tdisp
Tn
Tscan
Tn-1 Tn-2
T4
T3
T2
T1
Tn
Tn-1 Tn-2
FLD digit output
Segment setting by software
FLD blanking interrupt generated at the
falling of edge of the last timing
Fig. 56 Timing using FLD blanking interrupt
56
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P64 to P6 7 Expansion Function
(3) P64 to P6 7 FLD output reverse function
Ports P6 4 to P6 7 are CMOS output structure. FLD digit outputs
can be increased as many as 16 lines by connecting a decoder
converting 4-bit to 16-bit data to these ports. P64 to P67 have the
function to allow for connection to a decoder converting 4-bit to
16-bit data.
P64 to P67 have the function to reverse the polarity of the FLD output. This function is useful in adjusting the polarity when using an
externally installed driver.
The output polarity can be reversed by setting the P6 4 to P67 output reverse bit of the FLD output control register (bit 0 of address
0EFC 16) to “1”.
(1) P64 to P67 Toff invalid function
This function disables the Toff1 time and Toff2 time and outputs
display data for the duration of Tdisp. (See Figure 57.) This can be
achieved by setting the P64 to P67 Toff invalid bit (bit 2 of address
0EFC 16) to “1”.
■ Note
In the case of gradation display mode and dark display, P64 to P67
Toff invalid function is disabled.
(2) Dimmer signal output function
This function allows a dimmer signal creation signal to be output
from DIM OUT (P73 ). The dimmer function can be achieved by controlling the decoder with this signal. (See Figure 57.) This function
can be set by setting P73 dimmer output control bit (bit 4 of address 0EFC 16) to “1”.
Unlike the Toff section generating/nothing function, this function
disables all display data.
•Gradation display mode is not selected
•Gradation display mode is selected and
set for bright display
(gradation display control data = “0”)
FLD output
•Gradation display mode is selected and
set for dark display
(gradation display control data = “1”)
•Gradation display mode is selected and
Toff2 SET/RESET switch bit is “1”
(gradation display control data = “1”)
Toff1
Toff2
Tdisp
Output selecting P64 to P67
Toff invalid
For dimmer signal
DIMOUT (P73)
Fig. 57 P64 to P67 FLD output pulses
57
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Toff Section Generate/Nothing Function
The function is for reduction of useless noises which generated as
every switching of ports, because of the combined capacity of
among FLD ports. When the continuous data is output to each
FLD port, the Toff1 section of the continuous parts is not generated. (See Figure 58)
If it needs Toff1 section on FLD pulses, set the generating /not of
CMOS port Toff section selection bit (bit 5 of address 0EFC 16) to
“1” and set the generating /not of high-breakdown-voltage port Toff
section selection bit to “1”.
High-breakdown-voltage ports (P2, P0, P1, P3, P4, P5, P63 to
P60, total 52 pins) generate Toff1 section by setting the generating
/not of high-breakdown-voltage port Toff section selection bit to
“1”.
The CMOS ports (P64 to P6 7, total 4 pins ) generate Toff1 section
by setting the generating /not of CMOS port Toff section selection
bit to “1”.
Tdisp
Toff1
“H” output
“L” output
“H” output
“H” output
“H” output
“H” output
“L” output
“H” output
“H” output
“L” output
“H” output
“H” output
P1X
Output waveform when
generating/not of high-breakdown
voltage port Toff section selection
P2X
bit (bit 6 of address 0EFC16) is “1”.
P1X
Output waveform when
generating/not of high-breakdown
voltage port Toff section selection
bit (bit 6 of address 0EFC16) is “0”.
Section of Toff1 is not generated because of output is the same.
“H” output
“H” output
“L” output
“H” output
P2X
Section of Toff1 is not generated because of output is the same.
Fig. 58 Toff section generating/nothing function
Toff2 SET/RESET Switch Function
In gradation display mode, the values set by the Toff2 time set register (TOFF2) are effective. When the Toff2 SET/RESET switch bit
of FLD output control register (bit 7 of address 0EFC16) is “0”,
RAM data is output to the FLD output ports (SET) at the time that
is set by TOFF1 and it is turned to “0” (RESET) at the time that is
set by TOFF2.
When Toff2 SET/RESET switch bit is “1”, RAM data is output
(SET) at the time that is set by TOFF2 and it is turned to “0” (RESET) when the Tdisp time expires.
■ Note
In the case of gradation display mode and dark display, the Toff
section generate/nothing function is disabled.
58
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Digit Pulses Output Function
This function is effective in 16-timing•ordinary mode and 16-timing
gradation display mode. If a value is set exceeding the timing
count (FLD data pointer reload register’s set value + 1) for any
port, the output of such port is “L”.
P0 0 to P0 7 and P2 0 to P2 7 can output digit pulses by using the
digit output set switch registers. Set the digit output set switch registers by setting as many consecutive 1s as the timing count from
P20. The contents of FLD automatic display RAM for the ports that
have been selected for digit output are disabled, and the pulse
shown in Figure 59 is output automatically.
The output timing consists of Tdisp time and Toff1 time, and Toff2
time does not exist.
Because the contents of FLD automatic display RAM are disabled, the segment data can be changed easily even when
segment data and digit data coexist at the same address in the
FLD automatic display RAM.
Tdisp
Toff1
P07
P06
P05
P04
P03
P02
P01
P00
P27
P26
P25
P24
P23
P22
P21
P20
Low-order 4bits
of the data pointer
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Fig. 59 Digit pulses output function
59
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The 38B7 group has a 10-bit A-D converter. The A-D converter
performs successive approximation conversion.
Note that the comparator is constructed linked to a capacitor, so
that set f(X IN) to at least 250 kHz during A-D conversion. Additionally, bit 7 of the CPU mode register (address 003B16) must be set
to “0”.
[A-D Conversion Register] ADH, ADL
One of these registers is a high-order register, and the other is a
low-order register. The high-order 8 bits of a conversion result is
stored in the A-D conversion register (high-order) (address
003416 ), and the low-order 2 bits of the same result are stored in
bit 7 and bit 6 of the A-D conversion register (low-order) (address
003316 ).
During A-D conversion, do not read these registers.
b7 b6 b5 b4 b3 b2 b1 b0
b3b2b1b0
0 0 0 0 : PA0/AN0
0 0 0 1 : PA1/AN1
0 0 1 0 : PA2/AN2
0 0 1 1 : PA3/AN3
0 1 0 0 : PA4/AN4
0 1 0 1 : PA5/AN5
0 1 1 0 : PA6/AN6
0 1 1 1 : PA7/AN7
1 0 0 0 : P90/SIN3/AN8
1 0 0 1 : P91/SOUT3/AN9
1 0 1 0 : P92/SCLK3/AN10
1 0 1 1 : P93/SRDY3/AN11
1 1 0 0 : P94/RTP1/AN12
1 1 0 1 : P95/RTP0/AN13
1 1 1 0 : P96/PWM0/AN14
1 1 1 1 : P97/BUZ02/AN15
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
DA output enable bit
0 : DA output disabled
1 : DA output enabled
Not used (returns “0” when read)
[AD/DA Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input
pin selection bits. Bit 4 is an AD conversion completion bit and “0”
during A-D conversion. This bit is set to “1” upon completion of AD conversion.
A-D conversion is started by writing “0” in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVss and VREF by 1024, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports PA7 /AN7–PA0 /
AN0 , and P9 7/BUZ02/AN 15 to P9 0/S IN3/AN8 and inputs it to the
comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog
inputvoltage with the comparison voltage and stores the result in
the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit
and the AD conversion interrupt request bit to “1”.
AD/DA control register
(ADCON: address 003216)
Analoginput pin selection bits
AD conversion register (high-order)
(ADH: address 003416)
b7
AD conversion register (low-order)
(ADL: address 003316)
b7
Note: When reading the low-order 6 bits at address 003316,
“0” is read out.
Data bus
b0
AD/DA control register
4
Fig. 61 Block diagram of A-D converter
60
A-D control circuit
Comparator
Channel selector
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
P90/SIN3/AN8
P91/SOUT3/AN9
P92/SCLK3/AN10
P93/SRDY3/AN11
P94/RTP1/AN12
P95/RTP0/AN13
P96/PWM0/AN14
P97/BUZ02/AN15
b0
b1 b0
Fig. 60 Structure of AD/DA control register
b7
b0
b9 b8 b7 b6 b5 b4 b3 b2
A-D interrupt request
A-D conversion register (H) A-D conversion register (L)
(Address 003416)
(Address 003316)
Resistor ladder
AVSS VREF
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER
Data bus
The 38B7 group has one internal D-A converter with 8-bit resolution.
The D-A conversion is performed by setting the value in the D-A
conversion register. The result of D-A conversion is output from
the DA pin by setting the DA output enable bit to “1”.
When using the D-A converter, the PB 0/DA port direction register
bit must be set to “0” (input status).
The output analog voltage V is determined by the value n (decimal notation) in the D-A conversion register as follows:
D-A conversion register (8)
R-2R resistor ladder
DA output enable bit
PB0/DA
V = V REF ✕ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
At reset, the D-A conversion register is cleared to “0016 ”, and the
DA output enable bit is cleared to “0”, and PB0 /DA pin becomes
high impedance.
The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load.
Set VCC to 3.0 V or more when using the D-A converter.
“0” DA output enable bit
R
R
Fig. 62 Block diagram of D-A converter
R
R
R
R
R
2R
PB0/DA
“1”
2R
2R
“0”
2R
2R
2R
2R
2R
LSB
MSB
D-A conversion register
2R
“1”
AVSS
VREF
Fig. 63 Equivalent connection circuit of D-A converter
61
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PWM (Pulse Width Modulation)
The 38B7 group has a PWM function with a 14-bit resolution. When
the oscillation frequency XIN is 4 MHz, the minimum resolution bit
width is 250 ns and the cycle period is 4096 µs. The PWM timing
generator supplies a PWM control signal based on a signal that is
the frequency of the XIN clock.
The explanation in the rest assumes XIN = 4 MHz.
Data bus
It is set to “1”
when write.
PWM register (low-order)
(address 003616)
bit7
bit5
bit0
bit0
bit7
PWM register (high-order)
(address 003516)
PWM latch (14-bit)
MSB
LSB
14
P96 latch
P96/PWM0
14-bit PWM circuit
XCIN
1/2
“1”
XIN
(4MHz)
“0”
Fig. 64 PWM block diagram
62
When the internal
system clock
selection bit is set
(64 µs cycle)
Timing
to “0”
generating
unit for PWM (4096 µs cycle)
PWM
P96/PWM output
selection bit
P96/PWM output
selection bit
P96 direction
register
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MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data Setup
Transfer From Register to Latch
The PWM output pin also function as port P96 . Set port P96 to be
the PWM output pin by setting bit 0 of the PWM control register
(address 0026 16) to “1”. The high-order 8 bits of output data are
set in the high-order PWM register PWMH (address 0035 16 ) and
the low-order 6 bits are set in the low-order PWM register PWML
(address 0036 16).
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch once in each subperiod (every 64 µs). Pulses output from the PWM output pin
correspond to this latch contents.
When the PWML register is read, the contents of the latch are
read. However, bit 7 of the PWML register indicates whether the
transfer to the PWM latch is completed: the transfer is completed
when bit 7 is “0”, it is not done when bit 7 is “1”.
PWM Operation
The timing of the 14-bit PWM function is shown in Figure 65.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
The high-order 8 bits of data determine how long an “H” level signal is output during each sub-period. There are 64 sub-periods in
each period, and each sub-period t is 256 ✕ τ (= 64 µs) long. The
signal’s “H” has a length equal to N times τ, and its minimum resolution = 250 ns.
The last bit of the sub-period becomes the ADD bit which is specified either “H” or “L,” by the contents of PWML. As shown in Table
11, the ADD bit is decided either “H” or “L.”
That is, only in the sub-period tm shown in Table 11 in the PWM
cycle period T = 64 t, the “H” duration is lengthened during the
minimum resolution width τ period in comparison with the other
period.
For example, if the high-order eight bits of the 14-bit data are
“03 16” and the low-order six bits are “05 16,” the length of the “H”
level output in sub-periods t8, t24, t32, t40 and t56 is 4 τ, and its
length 3 τ in all other sub-periods.
Time at the “H” level of each sub-period almost becomes equal
because the time becomes length set in the high-order 8 bits or
becomes the value plus t, and this sub-period t (= 64 µs, approximate 15.6 kHz) becomes cycle period approximately.
Table 11 Relationship between low-order 6-bit data and setting
period of ADD bit
Low-order
Sub-periods tm lengthened (m = 0 to 63)
6-bit data
LSB
000000
None
000001
000010
000100
001000
010000
m = 32
100000
m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
m = 16, 48
m = 8, 24, 40, 56
m = 4, 12, 20, 28, 36, 44, 52, 60
m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
4096 µs
64 µs
64 µs
m=0
15.75 µs
m=7
15.75 µs
15.75 µs
64 µs
m=8
16.0 µs
64 µs
64 µs
m=9
15.75 µs
m = 63
15.75 µs
15.75 µs
Pulse width modulation register H: 00111111
Pulse width modulation register L: 000101
Sub-periods where “H” pulse width is 16.0 µs: m = 8, 24, 32, 40, 56
Sub-periods where “H” pulse width is 15.75 µs: m = all other values
Fig. 65 PWM timing
63
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
PWM control register
(PWMCON: address 002616)
P96/PWM0 output selection bit
0: I/O port
1: PWM0 output
Not used (return “0” when read)
Fig. 66 Structure of PWM control register
Data 6A16 stored at address 003516
PWM register
(high-order)
5916
Data 7B16 stored at address 003516
6A16
7B16
Data 2416 stored at address 003616
PWM register
(low-order)
1316
Bit 7 cleared after transfer
A416
Data 3516 stored at address 003616
2416
3516
Transfer from register to latch
PWM latch
(14-bit)
165316
1A9316
Transfer from register to latch
B516
1AA416
1AA416
1EE416
1EF516
When bit 7 of PWML is “0,” transfer
from register to latch is disabled.
T = 4096 µs
(64 ✕ 64 µs)
t = 64 µs
6A
(Example 1)
6B
6A
6B
6A
6B
6A
6B
6A
6B
6B
5
2
5
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
PWM output
1
Low-order 6-bits
output
H = 6A16
L = 2416
5
6A
(Example 2)
5
5
5
6B16............36 times
(107)
6A
6A
6A
6B
6A
5
5
6A16............28 times
(106)
6B
6A
6B
6A
6A
6A
5
106 ✕ 64
6B
6A
6B
6A
6B
5
5
5
5
36
6A
6A
6A
6B
6A
6B
6A
6B
PWM output
Low-order 6 bits
output
H = 6A16
L = 1816
4
3
4
6B16............24 times
4
3
4
6A16............40 times
4
106 ✕ 64
3
4
24
t = 64 µs
(256 ✕ 0.25 µs)
Minimum bit width
PWM output
6B
τ = 0.25 µs
6A
69
68
67
02
01
6A
69
68
67
02
01
FF
FE
FD
FC
97
96
2
ADD
8-bit counter
02
01
The ADD portions with
additional τ are determined
either “H” or “L” by low-order
6-bit data.
00
ADD
FF
FE
FD
FC
97
64
95
“H” period length specified by PWMH
256
Fig. 67 14-bit PWM timing
96
τ (64 µs), fixed
02
01
5
00
95
6A
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPT INTERVAL DETERMINATION FUNCTION
Noise Filter
The 38B7 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from
the rising edge (falling edge) of an input signal pulse on the P7 2/
INT 2 pin to the rising edge (falling edge) of the signal pulse that is
input next.
How to determine the interrupt interval is described below.
1. Enable the INT2 interrupt by setting bit 2 of the interrupt control
register 1 (address 003E16 ). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A16 ).
2. Set bit 0 of the interrupt interval determination control register
(address 003116 ) to “1” (interrupt interval determination operating).
3. Select the sampling clock of 8-bit binary up counter by setting
bit 1 of the interrupt interval determination control register.
4. When the signal of polarity which is set on the INT 2 pin (rising
or falling edge) is input, the 8-bit binary up counter starts counting up of the selected counter sampling clock.
5. When the signal of polarity selected above is input again, the
value of the 8-bit binary up counter is transferred to the interrupt interval determination register (address 0030 16 ), and the
remote control interrupt request occurs. Immediately after that,
the 8-bit binary up counter continues to count up again from
“00 16”.
6. When count value reaches “FF 16”, the 8-bit binary up counter
stops counting up. Then, simultaneously when the next counter
sampling clock is input, the counter sets value “FF16 ” to the interrupt interval determination register to generate the counter
overflow interrupt request.
The P7 2/INT2 pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt interval determination control register. When not
using the noise filter, set “00 16 ”.
2. The P7 2/INT 2 input signal is sampled in synchronization with
the selected clock. When sampling the same level signal in a
series of three sampling, the signal is recognized as the interrupt signal, and the interrupt request occurs.
Counter sampling
clock selection bit
1/1
Internal system
clock selection bit
f(XIN)/128
f(XCIN)
Divider
1/2
Noise filter
INT2 interrupt input
When setting bit 4 of interrupt interval determination control register to “1”, the interrupt request can occur at both rising and falling
edges.
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 3 cycles or more of the sample clock.
8-bit binary up
counter
Counter overflow
interrupt request
or remote control
interrupt request
Interrupt interval
determination register
address 003016
Noise filter sampling
clock selection bit
1/1
One-sided/both-sided
edge detection
selection bit
1
1/2 /4
Data bus
Divider
f(XIN)/32
f(XCIN)
Internal system
clock selection bit
Fig. 68 Interrupt interval determination circuit block diagram
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt interval determination control register
(IIDCON: address 003116)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(XIN)/128 or f(XCIN)
1 : f(XIN)/256 or f(XCIN)/2
Noise filter sampling clock selection bits (INT2)
b3b2
0 0 : Filter stop
0 1 : f(XIN)/32 or f(XCIN)
1 0 : f(XIN)/64 or f(XCIN)/2
1 1 : f(XIN)/128 or f(XCIN)/4
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection (can be used when using a noise filter)
Not used (return “0” when read)
(Do not write “1” to these bits.)
Fig. 69 Structure of interrupt interval determination control register
(When IIDCON4 = “0”)
Noise filter
sampling clock
INT2 pin
Acceptance of
interrupt
Counter sampling
clock
N
8-bit binary up
counter value
0
1
3
2
5
4
0
1
FF
3
2
0
N
FF
6
Counter overflow
interrupt request
Remote control
interrupt request
Remote control
interrupt request
1
FF
6
N
Interrupt interval
determination
register value
FE
6
Fig. 70 Interrupt interval determination operation example (at rising edge active)
(When IIDCON4 = “1”)
Noise filter
sampling clock
INT2 pin
Acceptance of
interrupt
Counter sampling
clock
FE
N
8-bit binary up
counter value
0
1
N
Interrupt interval
determination
register value
2
0
2
N
Remote control
interrupt request
2
1
0
1
3
2
Remote control
interrupt request
3
2
0
2
2
Remote control
interrupt request
Remote control
interrupt request
0
FF
2
3
Fig. 71 Interrupt interval determination operation example (at both-sided edge active)
66
1
FF
FF
Counter overflow
interrupt request
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software runaway). The watchdog timer consists of an
8-bit watchdog timer L and a 8-bit watchdog timer H.
Standard Operation Of Watchdog Timer
When any data is not written into the watchdog timer control register (address 0EEE 16) after reset, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register and an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register may be started before an underflow. When the watchdog timer control register is read, the
values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection
bit are read.
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
0EEE 16), a watchdog timer H is set to “FF16” and a watchdog
timer L to “FF16 ”.
(2) Watchdog timer H count source selection
bit operation
Bit 7 of the watchdog timer control register (address 0EEE 16) permits selecting a watchdog timer H count source. When this bit is
set to “0”, the underflow signal of watchdog timer L becomes the
count source. The detection time is set to 131.072 ms at f(XIN) = 4
MHz frequency, and 32.768 s at f(XCIN ) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal divided by 8 for f(X IN) or divided by 16 for f(X CIN ). The detection
time in this case is set to 512 µs at f(XIN) = 4 MHz frequency, and
128 ms at f(XCIN ) = 32 kHz frequency.
This bit is cleared to “0” after reset.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 0EEE 16) permits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
If the STP instruction is executed, an internal resetting occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after reset.
■ Note
When releasing the stop mode, the watchdog timer performs its
count operation even in the stop release waiting time. Be careful
not to cause the watchdog timer H to underflow in the stop release
waiting time, for example, by writing any data in the watchdog
timer control register (address 0EEE16) before executing the STP
instruction.
XCIN
1/2
“1”
Internal system clock
selection bit
(Note)
“0”
“FF16” is set when
watchdog timer
control register is
written to.
Data bus
“0”
Watchdog timer L (8)
1/8
“1”
Watchdog timer H (8)
“FF16” is set
when watchdog
timer control
register is written
to.
Watchdog timer H count
source selection bit
XIN
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Internal reset
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
Fig. 72 Block diagram of watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 0EEE16)
Watchdog timer H (for read-out of high-order 6 bits)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/8 or f(XCIN)/16
Fig. 73 Structure of watchdog timer control register
67
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
BUZZER OUTPUT CIRCUIT
Note: In the low-speed mode, a buzzer output is made OFF.
The 38B7 group has a buzzer output circuit. One of 1 kHz, 2 kHz
and 4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the
buzzer output control register (address 0EFD16 ). Either P77/BUZ01
or P97/B UZ02/AN 15 can be selected as a buzzer output port by the
output port selection bits (b2 and b3 of address 0EFD16 ).
The buzzer output is controlled by the buzzer output ON/OFF bit
(b4).
Port latch
f(XIN)
Divider
1/1024
1/2048
1/4096
Buzzer output
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Fig. 74 Block diagram of buzzer output circuit
b7
b0
Buzzer output control register
(BUZCON: address 0EFD16)
Output frequency selection bits (XIN = 4.19 MHz)
b1b0
0 0 : 1 kHz (f(XIN)/4096)
0 1 : 2 kHz (f(XIN)/2048)
1 0 : 4 kHz (f(XIN)/1024)
1 1 : Not available
Output port selection bits
b3b2
0 0 : P77 and P97 function as ordinary ports.
0 1 : P77/BUZ01 functions as a buzzer output.
1 0 : P97/BUZ02/AN15 functions as a buzzer output.
1 1 : Not available
Buzzer output ON/OFF bit
b4
0 : Buzzer output OFF (“0” output)
1 : Buzzer output ON
Not used (returns “0” when read)
Fig. 75 Structure of buzzer output control register
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between 2.7 V and 5.5
V, and the oscillation should be stable), reset is released. After the
reset is completed, the program starts from the address contained
in address FFFD 16 (high-order byte) and address FFFC16 (loworder byte). Make sure that the reset input voltage is less than
0.54 V for Vcc of 2.7 V (switching to the high-speed mode, a
power source voltage must be between 4.0 V and 5.5 V).
Poweron
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 76 Reset circuit example
XIN
φ
RESET
Internal
reset
?
Address
?
?
?
FFFC
FFFD
ADL
Data
ADH, ADL
ADH
SYNC
XIN: about 4000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=4 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 77 Reset sequence
69
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Address Register contents
(1) Port P0
000016
0016
(38) D-A conversion register
002B16
0016
FF16
(2) Port P1
000216
0016
(39) Timer X (low-order)
002C16
(3) Port P1 direction register
000316
0016
(40) Timer X (high-order)
002D16
FF16
(4) Port P2
000416
0016
(41) Timer X mode register 1
002E16
0016
(5) Port P3
000616
0016
(42) Timer X mode register 2
002F16
0016
(6) Port P3 direction register
000716
0016
003016
0016
(7) Port P4
000816
0016
003116
0016
(8) Port P4 direction register
000916
0016
(43) Interrupt interval determination
register
(44) Interrupt interval determination
control register
(45) AD/DA control register
003216
1016
(9) Port P5
000A16
0016
(46) UART control register
003816
8016
(10) Port P5 direction register
000B16
0016
(47) Interrupt source switch register
003916
0016
(11) Port P6
000C16
0016
(48) Interrupt edge selection register
003A16
0016
(12) Port P6 direction register
000D16
0016
(49) CPU mode register
003B16 0 1 0 0 1 0 0 0
(13) Port P7
000E16
0016
(50) Interrupt request register 1
003C16
0016
(14) Port P7 direction register
000F16
0016
(51) Interrupt request register 2
003D16
0016
(15) Port P8
001016
0016
(52) Interrupt control register 1
003E16
0016
(16) Port P8 direction register
001116
0016
(53) Interrupt control register 2
003F16
0016
(17) Port P9
001216
0016
(54) Serial I/O3 control register
0EEC16
0016
(18) Port P9 direction register
001316
0016
(55) Watchdog timer control register
0EEE16
3F16
(19) Port PA
001416
0016
(56) Pull-up control register 3
0EEF16
0016
(20) Port PA direction register
001516
0016
(57) Pull-up control register 1
0EF016
0016
(21) Port PB
001616
0016
(58) Pull-up control register 2
0EF116
0016
(22) Port PB direction register
001716
0016
0EF216
0016
(23) Serial I/O1 control register 1
001916
0016
0EF316
0016
(24) Serial I/O1 control register 2
001A16
0016
(59) Port P0 digit output set switch
register
(60) Port P2 digit output set switch
register
(61) FLDC mode register
0EF416
0016
(25) Serial I/O1 control register 3
001C16
0016
(62) Tdisp time set register
0EF516
0016
(26) Serial I/O2 control register
001D16
0016
(63) Toff1 time set register
0EF616
FF16
(27) Serial I/O2 status register
001E16
8016
(64) Toff2 time set register
0EF716
FF16
(28) Timer 1
002016
FF16
(65) Port P4 FLD/Port switch register 0EF916
0016
(29) Timer 2
002116
0116
(66) Port P5 FLD/Port switch register 0EFA16
0016
(30) Timer 3
002216
FF16
(67) Port P6 FLD/Port switch register 0EFB16
0016
(31) Timer 4
002316
FF16
(68) FLD output control register
0EFC16
0016
(32) Timer 5
002416
FF16
(69) Buzzer output control register
0EFD16
0016
(33) Timer 6
002516
FF16
(70) Flash memory control register
0EFE16
0016
(34) PWM control register
002616
0016
(71) Flash command register
0EFF16
0016
(35) Timer 12 mode register
002816
0016
(72) Processor status register
(36) Timer 34 mode register
002916
0016
(73) Program counter
(37) Timer 56 mode register
002A16
0016
(PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
✕: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 78 Internal status at reset
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Oscillation Control
The 38B7 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between X IN and
XOUT or XCIN and XCOUT. Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No external resistor is needed between X IN and X OUT since a feedback
resistor exists on-chip. However, an external feedback resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the X IN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
(1) Stop mode
If the STP instruction is executed, the internal system clock stops
at an “H” level, and X IN and XCIN oscillators stop. Timer 1 is set to
“FF16 ” and timer 2 is set to “0116 ”.
Either X IN divided by 8 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2.
The bits of the timer 12 mode register are cleared to “0”. Set the
interrupt enable bits of the timer 1 and timer 2 to disabled (“0”) before executing the STP instruction. Oscillator restarts when an
external interrupt is received, but the internal system clock is not
supplied to the CPU until timer 2 underflows. This allows time for
the clock circuit oscillation to stabilize.
Frequency Control
(1) Middle-speed mode
The internal system clock is the frequency of X IN divided by 4. After reset, this mode is selected.
(2) High-speed mode
The internal system clock is the frequency of X IN.
(3) Low-speed mode
The internal system clock is the frequency of X CIN divided by 2.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops
at an “H” level. The states of X IN and XCIN are the same as the
state before executing the WIT instruction. The internal system
clock restarts at reset or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immediately after the clock is restarted.
■ Note
If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3 • f(X CIN).
XCIN
XCOUT
Rf
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
the main clock stop bit (bit 5) of the CPU mode register to “1”.
When the main clock X IN is restarted (by setting the main clock
stop bit to “0”), set enough time for oscillation to stabilize.
XIN
XOUT
Rd
CCIN
CCOUT
CIN
COUT
Fig. 79 Ceramic resonator circuit
XCIN
XCOUT
open
XIN
XOUT
open
External oscillation circuit
External oscillation circuit
or external pulse
VCC
VCC
VSS
VSS
Fig. 80 External clock input circuit
71
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
“0”
“1”
Port XC
switch bit (Note 3)
1/2
XOUT
XIN
“1”
“0”
Low-speed mode
“1
”
Timer 2 count source
selection bit (Note 2)
Timer 1 count source
selection bit (Note 2)
Internal system clock
selection bit (Notes 1, 3)
Timer 1
1/4
1/2
“0”
Timer 2
“0
“1”
”
High-speed
or
middle-speed
mode
Main clock division ratio
selection bits (Note 3)
Middle-speed mode
“1”
Timing φ (internal clock)
“0”
Main clock stop bit
(Note 3)
Q
High-speed or
low-speed mode
S
R
S Q
STP instruction
WIT instruction
R
Q S
R
Reset
Interrupt disable flag l
Interrupt request
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to “1”.
2: Refer to the structure of the timer 12 mode register.
3: Refer to the structure of the CPU mode register.
Fig. 81 Clock generating circuit block diagram
72
STP instruction
MITSUBISHI MICROCOMPUTERS
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.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
C M4
“1”
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=0(32 kHz stopped)
“0
”
4 “0”
CM
6
0”
”
M “
“1 C
”
“1
Middle-speed mode
(φ =1 MHz)
“0”
“1
”
CM
4
CM
“1
”
6
“0
”
High-speed mode
(φ =4 MHz)
C M6
“1”
“0”
C M7
“1”
“1”
C M7
“0”
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
“0”
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=0(32 kHz stopped)
High-speed mode
(φ =4 MHz)
C M4
C M6
“1”
“1”
Middle-speed mode
(φ =1 MHz)
5
C
M
“0
”
”
“0
CM
”
“1
6
“1
”
”
“0
CM
CM
5
6
“0
”
Low-power dissipation mode
(φ =16 kHz)
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=1(XIN stopped)
CM4=1(32 kHz oscillating)
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
Low-power dissipation mode
(φ =16 kHz)
C M6
“1”
“1
”
“0”
“0”
“1”
”
“1
“0”
CM5
“1”
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
CM5
Low-speed mode
(φ =16 kHz)
C M6
“1”
Low-speed mode
(φ =16 kHz)
“0”
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=1(XIN stopped)
CM4=1(32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0: I/O port function
1: XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0: Oscillating
1: Stopped
CM6: Main clock division ratio selection bit
0: f(XIN) (High-speed mode)
1: f(XIN)/4 (Middle-speed mode)
CM7: Internal system clock selection bit
0: XIN–XOUT selected (Middle-/High-speed mode)
1: XCIN–XCOUT selected (Low-speed mode)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait
mode is ended.
3: Timer operates in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 in low-speed mode.
6: The example assumes that 4 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal system clock.
Fig. 82 State transitions of system clock
73
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MASK OPTION OF PULL-DOWN RESISTOR
(object product: mask ROM version)
Whether built-in pull-down resistors are connected or not to highbreakdown voltage ports P40 to P47, P5 0 to P57, and P6 0 to P63
can be specified in ordering mask ROM. The option type can be
specified from among 7 types; A to G.
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
P60
P61
P62
P63
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
D
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
E
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
G
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes 1: The electrical characteristics of high-breakdown voltage ports P40 to P47, P50 to P57 , and P60 to P6 3’s built-in pull-down resistors
are the same as that of high-breakdown voltage ports P00 to P07 .
2: The absolute maximum ratings of power dissipation may be exceed owing to the number of built-in pull-down resistor. After calculating the power dissipation, specify the option type.
3: The flash memory version cannot select whether built-in pull-down resistors are connected or not. This is the same as option type
A.
Power Dissipation Calculating Method
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.)
= 5 V ✕ 15 mA = 75 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: e (= a ✕ c)
• Total number of built-in resistor: for digit, f; for segment, g
• Digit pin current value h (mA)
• Segment pin current value i (mA)
74
(1) Digit pin power dissipation
{h ✕ b ✕ (1 – Toff / Tdisp) ✕ voltage} / a
(2) Segment pin power dissipation
{i ✕ d ✕ (1–Toff / Tdisp) ✕ voltage} / a
(3) Pull-down resistor power dissipation (digit)
{power dissipation per 1 digit ✕ (b ✕ f / b) ✕ (1–Toff / Tdisp) } / a
(4) Pull-down resistor power dissipation (segment)
{power dissipation per 1 segment ✕ (d ✕ g / c) ✕ (1–Toff /
Tdisp) } / a
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.)
= 190 mW
(1) + (2)+ (3) + (4) + (5) = X mW
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Power Dissipation Calculating Example 1
(Fixed number depending on microcomputer’s standard)
• V OH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µs = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.)
= 5 V ✕ 15 mA = 75 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment number during repeat cycle: 340 (= 17 ✕ 20)
• Total number of built-in resistor: for digit, 16; for segment, 20
• Digit pin current value 18 (mA)
• Segment pin current value 3 (mA)
(1) Digit pin power dissipation
{18 ✕ 16 ✕ (1 – 1 / 16) ✕ 2} / 17 = 31.77 mW
(2) Segment pin power dissipation
{3 ✕ 31 ✕ (1– 1 / 16) ✕ 2} / 17 = 10.26 mW
(3) Pull-down resistor power dissipation (digit)
[{45 – 2}2/ 48 ✕ (16 ✕ 16 / 16) ✕ (1 – 1 / 16)] / 17 = 33.94 mW
(4) Pull-down resistor power dissipation (segment)
[{45 – 2}2/ 48 ✕ (31 ✕ 20 / 20) ✕ (1 – 1 / 16)] / 17 = 65.86 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.)
= 75 mW
(1) + (2)+ (3) + (4) + (5) = 217 mW
DIG0
DIG1
DIG2
DIG3
DIG13
DIG14
DIG15
Timing
number
1
2
14
3
15
16
17
Repeat cycle
Tscan
Fig. 83 Digit timing waveform (1)
75
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Power Dissipation Calculating Example 2
(2 or more digits turned ON at the same time)
(1) Digit pin power dissipation
{18 ✕ 12 ✕ (1 – 1 / 16) ✕ 2} / 11 = 36.82 mW
(2) Segment pin power dissipation
{3 ✕ 114 ✕ (1– 1 / 16) ✕ 2} / 11 = 58.30 mW
(3) Pull-down resistor power dissipation (digit)
[{45 – 2}2/ 48 ✕ (12 ✕ 10 / 12) ✕ (1 – 1 / 16)] / 11 = 32.84 mW
(4) Pull-down resistor power dissipation (segment)
[{45 – 2}2/ 48 ✕ (114 ✕ 22 / 24) ✕ (1 – 1 / 16)] / 11 = 343.08 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.)
= 75 mW
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µs = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.)
= 5 V ✕ 15 mA = 75 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 ✕ 24)
• Total number of built-in resistor: for digit, 10; for segment, 22
• Digit pin current value 18 (mA)
• Segment pin current value 3 (mA)
(1) + (2)+ (3) + (4) + (5) = 547 mW
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
Timing
number
1
2
3
4
5
6
7
8
9
10
11
Repeat cycle
Tscan
Fig. 84 Digit timing waveform (2)
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLASH MEMORY MODE
Functional Outline (parallel input/output mode)
The M38B79FF has the flash memory mode in addition to the normal operation mode (microcomputer mode). The user can use this
mode to perform read, program, and erase operations for the internal flash memory.
The M38B79FF has three modes the user can choose: the parallel input/output and serial input/output mode, where the flash
memory is handled by using the external programmer, and the
CPU reprogramming mode, where the flash memory is handled by
the central processing unit (CPU). The following explains these
modes.
In the parallel input/output mode, the M38B79FF allow the user to
choose an operation mode between the read-only mode and the
read/write mode (software command control mode) depending on
the voltage applied to the VPP pin. When VPP = VPP L, the readonly mode is selected, and the user can choose one of three
states ___
(e.g.,___
read, output
disable, or standby) depending on inputs
___
to the CE, OE, and WE pins. When VPP = V PP H, the read/write
mode is selected, and the user can choose one of four states
(e.g., read,
output disable,
standby, or write) depending on inputs
__ __
___
to the CE, OE, and WE pins. Table 13 shows assignment states of
control input and each state.
(1) Flash memory mode 1 (parallel I/O mode)
● Read
__
The
microcomputer enters
the read state by driving the CE, and
__
___
OE pins low and the WE pin high; and the contents of memory
corresponding to the address to be input to address input pins
(A0 –A16 ) are output to the data input/output pins (D0 –D7 ).
The parallel I/O mode can be selected by connecting wires as
shown in Figures 85 and supplying power to the VCC and V PP
pins. In this mode, the M38B79FF operates as an equivalent of
MITSUBISHI’s CMOS flash memory M5M28F101. However, because the M38B79FF’s internal memory has a capacity of 60
Kbytes, programming is available for addresses 0100016 to
0FFFF16, and make sure that the data in addresses 0000016 to
00FFF16 and addresses 10000 16 to 1FFFF16 are FF16 . Note also
that the M38B79FF does not contain a facility to read out a device
identification code by applying a high voltage to address input
(A9 ). Be careful not to erratically set program conditions when using a general-purpose PROM programmer.
Table 12 shows the pin assignments when operating in the parallel input/output mode.
● Output disable
The
microcomputer___
enters the
output disable state by driving the
__
__
CE pin low and the WE and OE pins high; and the data input/output pins enter the floating state.
● Standby
__
The microcomputer enters the standby state by driving the CE pin
high. The M38B79FF is placed in a power-down state consuming
only a minimal supply current. At this time, the data input/output
pins enter the floating state.
Table 12 Pin assignments of M38B79FF when operating in
the parallel input/output mode
VCC
VPP
VSS
Address input
Data
I/O
__
CE
___
OE
___
WE
M38B79FF
VCC
CNVSS
VSS
Ports P0, P1, P31
Port P2
P36
P37
P33
● Write
The microcomputer enters the write
state by driving the__
VPP pin
___
high (VPP = __
VPP H) and then the WE pin low when the CE pin is
low and the OE pin is high. In this state, software commands can
be input from the data input/output pins, and the user can choose
program or erase operation depending on the contents of this software command.
M5M28F101
VCC
VPP
VSS
A0–A16
D0__
–D7
CE
__
OE
___
WE
Table 13 Assignment states of control input and each state
Pin
Mode
Read-only
Read/Write
State
Read
Output disable
Standby
Read
Output disable
Standby
Write
__
__
___
CE
OE
WE
VPP
Data I/O
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
×
VIL
VIH
×
VIH
VIH
VIH
×
VIH
VIH
×
VIL
VPPL
VPPL
VPPL
VPPH
VPPH
VPPH
VPPH
Output
Floating
Floating
Output
Floating
Floating
Input
Note: × can be VIL or VIH .
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Pin description (flash memory parallel I/O mode)
Pin
Name
Input
/Output
—
Input
Input
Input
Output
—
Input
Input
Input
I/O
VCC, VSS
CNVSS
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20–P27
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Address input (A0–A7)
Address input (A8–A15)
Data I/O (D0–D7 )
P30–P37
Control signal input
Input
P40–P47
P50–P57
P60–P67
Input port P4
Input port P5
Input port P6
Input
Input
Input
P70–P77
P80–P83
P90–P97
PA0–PA7
PB0–PB 6
VEE
Input port P7
Input port P8
Input port P9
Input port PA
Input port PB
Pull-down power supply
Input
Input
Input
Input
Input
78
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to 5 V ± 10 % in read-only mode, connect to 11.7 V to 12.6 V in read/write mode.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Connect to VSS.
Port P0 functions as 8-bit address input (A0 –A7).
Port P1 functions as 8-bit address input (A8 –A15).
Function as 8-bit data’s I/O pins (D0–D 7).
Connect them to Vss through each resistor of 6.8 kΩ.
P37, P36 and P33 function as the OE, CE and WE input pins respectively. P3 1 functions as
the A16 input pin. Connect P30 and P32 to VSS. Input “H” or “L” to P34, P35, or keep
them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Connect P64 and P66 to VSS. Input “H” or “L” to P6 0–P63, P6 5, P67, or keep them
open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Keep this open.
MITSUBISHI MICROCOMPUTERS
.
38B7 Group
CE
OE
WE
A15
A16
A14
A12
A13
A9
A11
A8
A10
A7
A6
A5
A4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
*P00/FLD8
*P01/FLD9
*P02/FLD10
*P03/FLD11
*P04/FLD12
*P05/FLD13
*P06/FLD14
*P07/FLD15
*P10/FLD16
*P11/FLD17
*P12/FLD18
*P13/FLD19
*P14/FLD20
*P15/FLD21
*P16/FLD22
*P17/FLD23
*P30/FLD24
*P31/FLD25
*P32/FLD26
*P33/FLD27
*P34/FLD28
*P35/FLD29
*P36/FLD30
*P37/FLD31
*P40/FLD32
*P41/FLD33
*P42/FLD34
*P43/FLD35
*P44/FLD36
*P45/FLD37
A2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A0
A1
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6.8 kΩ
*P27/FLD7
*P26/FLD6
D5
*P25/FLD5
D4
*P24/FLD4
D3
*P23/FLD3
D2
*P22/FLD2
D1
*P21/FLD1
D0
*P20/FLD0
VE E
PB6/SIN1
PB5/SOUT1
PB4/SCLK11
PB3/SSTB1
PB2/SBUSY1
PB1/SRDY1
PB0/SCLK12/SVIN/DA
AVSS
VREF
PA7/AN7
PA6/AN6
D7
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
M38B79FFFP
*P46/FLD38
*P47/FLD39
*P50/FLD40
*P51/FLD41
*P52/FLD42
*P53/FLD43
*P54/FLD44
*P55/FLD45
*P56/FLD46
*P57/FLD47
*P60/FLD48
*P61/FLD49
*P62/FLD50
*P63/FLD51
P64/RxD/FLD52
P65/TxD/FLD53
P66/SCLK21/FLD54
P67/SRDY2/SCLK22/FLD55
P70/INT0
P71/INT1
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
P97/BUZ02/AN15
P96/PWM0/AN14
P95/RTP0/AN13
P94/RTP1/AN12
P93/SRDY3/AN11
P92/SCLK3/AN10
P91/SOUT3/AN9
P90/SIN3/AN8
P83/CNTR0/CNTR2
P82/CNTR1
Vpp
C N VS S
RESET
P81/XCOUT
P80/XCIN
VS S
XIN
XOUT
VCC
P77/INT4/BUZ01
P76/T3OUT
P75/T1OUT
P74/PWM1
P73/INT3/DIMOUT
P72/INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D6
Vcc
Vss
✱
✱ :Connect to the ceramic oscillation circuit.
* : High-breakdown-voltage output port: Totaling 52
Package type: 100P6S-A
indicates the flash memory pin.
Fig. 85 Pin connection of M38B79FF when operating in parallel input/output mode
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.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Read-only Mode
shown in Figure 86, and the M38B79FF will output the contents of
the user’s specified address from data I/O pin to the external. In
this mode, the user cannot perform any operation other than read.
The microcomputer enters the read-only mode by applying VPPL
to the V PP pin. In this mode, the user can input the address of a
memory location to be read and the control signals at the timing
VIH
Address
Valid address
VIL
tRC
VIH
CE
VIL
ta(CE)
VIH
OE
VIL
tWRR
tDF
VIH
WE
VIL
VOH
Data
ta(OE)
tDH
tOLZ
Floating
Dout
tCLZ
VOL
Floating
ta(AD)
Fig. 86 Read timing
Read/Write Mode
The microcomputer enters the read/write mode by applying VPP H
to the VPP pin. In this mode, the user must first input a software
command to choose the operation (e. g., read, program, or erase)
to be performed on the flash memory (this is called the first cycle),
and then input the information necessary for execution of the command (e.g, address and data) and control signals (this is called
the second cycle). When this is done, the M38B79FF executes the
specified operation.
Table 15 shows the software commands and the input/output information in the first and the second cycles. The
input address is
___
latched internally at the falling edge of the WE input; software
commands ___
and other input data are latched internally at the rising
edge of the WE input.
The following explains each software command. Refer to Figures 87
to 89 for details about the signal input/output timings.
Table 15 Software command (parallel input/output mode)
Symbol
Read
Program
Program verify
Erase
Erase verify
Reset
Device identification
First cycle
Address input
×
×
×
×
Verify address
×
×
Data input
0016
4016
C0 16
2016
A016
FF16
9016
Note: ADI = Device identification address : manufacturer’s code 0000016, device code 00001 16
DDI = Device identification data : manufacturer’s code 1C16, device code D0 16
× can be V IL or VIH.
80
Second cycle
Address input
Data I/O
Read address
Read data (Output)
Program address
Program data (Input)
×
Verify data (Output)
×
2016 (Input)
×
Verify data (Output)
×
FF16 (Input)
ADI
DDI (Output)
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Read command
The microcomputer enters the read mode by inputting command
code “0016” in the first cycle. The command code is latched
into
___
the internal command latch at the rising edge of the WE input.
When the address of a memory location to be read is input in the
second cycle, with control signals input at the timing shown in
Figure 87, the M38B79FF outputs the contents of the specified address from the data I/O pins to the external.
The read mode is retained until any other command is latched into
the command latch. Consequently, once the M38B79FF enters the
read mode, the user can read out the successive memory contents
simply by changing the input address and executing the second
cycle only. Any command other than the read command must be input beginning from its command code over again each time the user
execute it. The contents of the command latch immediately after
power-on is 0016.
VIH
Address
Valid address
VIL
tRC
tWC
VIH
CE
VIL
tCH
ta(CE)
tCS
VIH
OE
VIL
tRRW
tWP
tWRR
tDF
VIH
WE
VIL
ta(OE)
tDS
VIH
Data
tOLZ
0016
VIL
tDH
tVSC
tCLZ
Dout
tDH
ta(AD)
VPPH
VPP
VPPL
Fig. 87 Timings during reading
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Program command
The microcomputer enters the program mode by inputting command code “4016” in the first cycle. The command code ___
is latched
into the internal command latch at the rising edge of the WE input.
When the address which indicates a program location and data is
input in the second cycle, the M38B79FF
internally latches the ad___
dress at the ___
falling edge of the WE input and the data at the rising
edge of the WE input.
The M38B79FF starts programming at the
___
rising edge of the WE input in the second cycle and finishes programming within 10 µs as measured by its internal timer.
Programming is performed in units of bytes.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer
to Figure 90 for the programming flowchart.
● Program verify command
The microcomputer enters the program verify mode by inputting
command code “C0 16” in the first cycle. This command is used to
verify the programmed data after executing the program command. The command code is___
latched into the internal command
latch at the rising edge of the WE input. When control signals are
input in the second cycle at the timing shown in Figure 88, the
M38B79FF outputs the programmed address’s contents to the external. Since the address is internally latched when the program
command is executed, there is no need to input it in the second
cycle.
Program verify
VIH
Program
address
Address
VIL
tAS
tWC
Program
tAH
VIH
CE
VIL
tCS
tCS
tCS
tCH
tCH
tCH
VIH
OE
VIL
tRRW
tWP
tWPH
tWP
tDP
tWP
tWRR
VIH
WE
VIL
tDS
tDS
tDS
VIH
4016
Data
VIL
DIN
tDH
C016
tDH
Dout
tDH
tVSC
VPPH
VPP
VPPL
Fig. 88 Input/output timings during programming (Verify data is output at the same timing as for read.)
82
Verify data output
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Erase command
The erase command is executed by inputting command code 2016
in the first cycle and command code 2016 again in the second
cycle. The command code is latched
into the internal command
___
latch at the rising edges of the WE input in the first cycle and in
the second cycle, respectively.
The erase operation is initiated at
___
the rising edge of the WE input in the second cycle, and the
memory contents are collectively erased within 9.5 ms as measured by the internal timer. Note that data 0016 must be written to
all memory locations before executing the erase command.
Note: An erase operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 90
for the erase flowchart.
● Erase verify command
The user must verify the contents of all addresses after completing the erase command. The microcomputer enters the erase
verify mode by inputting the verify address and command code
A016 in the first cycle.
The address is internally latched at the fall___
ing edge of the WE input, and the
command code is internally
___
latched at the rising edge of the WE input. When control signals
are input in the second cycle at the timing shown in Figure 89, the
M38B79FF outputs the contents of the specified address to the
external.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
Erase verify
VIH
Address
Erase
VIL
Verify
address
tAS
tWC
tAH
VIH
CE
VIL
tCS
tCS
tCS
tCH
tCH
tCH
VIH
OE
VIL
tRRW
tWP
tWPH
tWP
tDE
tWP
tWRR
VIH
WE
VIL
tDS
tDS
tDS
VIH
2016
Data
2016
A016
VIL
Dout
Verify data output
tVSC
tDH
tDH
tDH
VPPH
VPP
VPPL
Fig. 89 Input/output timings during erasing (verify data is output at the same timing as for read.)
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MITSUBISHI MICROCOMPUTERS
.
● Reset command
The reset command provides a means of stopping execution of
the erase or program command safely. If the user inputs command
code FF 16 in the second cycle after inputting the erase or program
command in the first cycle and again input command code FF16 in
the third cycle, the erase or program command is disabled (i.e.,
reset), and the M38B79FF is placed in the read mode. If the reset
command is executed, the contents of the memory does not
change.
● Device identification code command
By inputting command code 9016 in the first cycle, the user can
read out the device identification code. The command code is
latched into the internal command latch at the rising edge of the
___
WE input. At this time, the user can read out manufacture’s code
1C16 (i.e., MITSUBISHI) by inputting 000016 to the address input
pins in the second cycle; the user can read out device code D016
(i. e., 1M-bit flash memory) by inputting 000116 .
These command and data codes are input/output at the same timing as for read.
84
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Program
Erase
START
START
VCC = 5 V, VPP = VPPH
VCC = 5 V, VPP = VPPH
ADRS = first location
ALL
BYTES = 0016 ?
YES
X=0
NO
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
PROGRAM
ALL BYTES = 0016
ADRS = first location
X=0
DURATION = 10 µs
X=X+1
WRITE PROGRAM-VERIFY
COMMAND
C016
WRITE ERASE
COMMAND
2016
WRITE ERASE
COMMAND
2016
DURATION = 9.5 ms
DURATION = 6 µs
YES
X=X+1
X = 25 ?
WRITE ERASE-VERIFY
COMMAND
NO
PASS
FAIL
VERIFY BYTE ?
DURATION = 6 µs
VERIFY BYTE ?
PASS
FAIL
YES
X = 1000 ?
NO
INC ADRS
A016
LAST ADRS ?
NO
YES
WRITE READ COMMAND
PASS
FAIL
VERIFY BYTE ?
0016
VERIFY BYTE ?
FAIL
PASS
VPP = VPPL
NO
INC ADRS
DEVICE
PASSED
DEVICE
FAILED
LAST ADRS ?
YES
WRITE READ COMMAND
0016
VPP = VPPL
DEVICE
PASSED
DEVICE
FAILED
Fig. 90 Programming/Erasing algorithm flow chart
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16 DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Symbol
Parameter
Test conditions
__
ISB1
ISB2
VCC supply current (at read)
ICC2
ICC3
VCC supply current (at program)
VCC supply current (at erase)
IPP1
VPP supply current (at read)
IPP2
IPP3
VIL
VIH
VOH1
VOH2
VPPL
VPPH
VPP supply current (at program)
VPP supply current (at erase)
“L” input voltage
“H” input voltage
“H” output voltage
Limits
Typ.
VCC = 5.5 V, CE = VIH
V
CC = 5.5 V,
__
CE = VCC ± 0.2
V
__
VCC = 5.5 V, CE = VIL,
tRC = 150 ns, I OUT = 0 mA
VPP = VPPH
VPP = VPPH
0≤VPP≤VCC
VCC <VPP≤VCC + 1.0 V
VPP = VPPH
VPP = VPPH
VPP = VPPH
VCC supply current (at standby)
ICC1
Min.
I OH = –400 µA
I OH = –100 µA
VPP supply voltage (read only)
VPP supply voltage (read/write)
0
0.52Vcc
2.4
VCC –0.4
VCC
11.7
12.0
Max.
1
100
Unit
mA
µA
15
mA
15
15
10
100
100
30
30
0.2Vcc
VCC
mA
mA
µA
µA
µA
mA
mA
V
V
V
V
V
V
VCC + 1.0
12.6
AC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Table 17 Read-only mode
Symbol
tRC
ta(AD)
ta(CE)
ta(OE)
tCLZ
tOLZ
tDF
tDH
tWRR
Parameter
Read cycle time
Address
access time
__
CE
access
time
__
OE access time
__
Output enable time (after CE)
__
Output enable time (after OE)
__
Output floating time (after
OE)
__ __
Output valid time (after CE, OE, address)
Write recovery time (before read)
Limits
Min.
500
Max.
500
500
200
0
0
70
0
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
Table 18 Read/Write mode
Symbol
tWC
tAS
tAH
tDS
tDH
tWRR
t RRW
tCS
tCH
tWP
tWPH
tDP
tDE
tVSC
Parameter
Write cycle time
Address set up time
Address hold time
Data setup time
Data hold time
Write recovery time (before read)
Read
recovery time (before write)
__
CE
setup
time
__
CE hold time
Write pulse width
Write pulse waiting time
Program time
Erase time
VPP setup time
Note: Read timing of Read/Write mode is same as Read-only mode.
86
Limits
Min.
300
0
120
100
20
6
0
40
0
120
40
10
9.5
1
Max.
Unit
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
µs
ms
µs
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Flash memory mode 2 (serial I/O mode)
wires as shown in Figures 91 and powering on the VCC pin and
then applying VPP H to the VPP pin.
In the serial I/O mode, the user can use six types of software commands: read, program, program verify, erase, erase verify and
error check.
Serial input/output is accomplished synchronously with the clock,
beginning from the LSB (LSB first).
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
*P00/FLD8
*P01/FLD9
*P02/FLD10
*P03/FLD11
*P04/FLD12
*P05/FLD13
*P06/FLD14
*P07/FLD15
*P10/FLD16
*P11/FLD17
*P12/FLD18
*P13/FLD19
*P14/FLD20
*P15/FLD21
*P16/FLD22
*P17/FLD23
*P30/FLD24
*P31/FLD25
*P32/FLD26
*P33/FLD27
*P34/FLD28
*P35/FLD29
*P36/FLD30
*P37/FLD31
*P40/FLD32
*P41/FLD33
*P42/FLD34
*P43/FLD35
*P44/FLD36
*P45/FLD37
OE
The M38B79FF has a function to serially input/output the software
commands, addresses, and data required for operation on the internal flash memory (e. g., read, program, and erase) using only a
few pins. This is called the serial I/O (input/output) mode. This
mode can be selected by driving the__SDA (serial data input/output), SCLK (serial clock input ), and OE pins high after connecting
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
M38B79FFFP
*P46/FLD38
*P47/FLD39
*P50/FLD40
*P51/FLD41
*P52/FLD42
*P53/FLD43
*P54/FLD44
*P55/FLD45
*P56/FLD46
*P57/FLD47
*P60/FLD48
*P61/FLD49
*P62/FLD50
*P63/FLD51
P64/RxD/FLD52
P65/TxD/FLD53
P66/SCLK21/FLD54
P67/SRDY2/SCLK22/FLD55
P70/INT0
P71/INT1
SDA
SCLK
BUSY
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
P97/BUZ02/AN15
P96/PWM0/AN14
P95/RTP0/AN13
P94/RTP1/AN12
P93/SRDY3/AN11
P92/SCLK3/AN10
P91/SOUT3/AN9
P90/SIN3/AN8
P83/CNTR0/CNTR2
P82/CNTR1
Vpp
C N VS S
RESET
P81/XCOUT
P80/XCIN
VSS
XIN
XOUT
VCC
P77/INT4/BUZ01
P76/T3OUT
P75/T1OUT
P74/PWM1
P73/INT3/DIMOUT
P72/INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
*P27/FLD7
*P26/FLD6
*P25/FLD5
*P24/FLD4
*P23/FLD3
*P22/FLD2
*P21/FLD1
*P20/FLD0
VEE
PB6/SIN1
PB5/SOUT1
PB4/SCLK11
PB3/SSTB1
PB2/SBUSY1
PB1/SRDY1
PB0/SCLK12/SVIN/DA
AVSS
VREF
PA7/AN7
PA6/AN6
Vcc
Vss
✱
✱ :Connect to the ceramic oscillation circuit.
*: High-breakdown-voltage output port: Totaling 52
Package type: 100P6S-A
indicates the flash memory pin.
Fig. 91 Pin connection of M38B79FF when operating in serial I/O mode
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19 Pin description (flash memory serial I/O mode)
Pin
Name
VCC, VSS
CNV
SS
_____
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20–P27
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
P30–P36
P37
P40–P47
P50–P57
P60–P63, P65
P64
P66
P67
P70–P77
P80–P83
P90–P97
PA0–PA7
PB0–PB 6
Input port P3
Control signal input
Input port P4
Input port P5
Input port P6
SDA I/O
SCLK input
BUSY output
Input port P7
Input port P8
Input port P9
Input port PA
Input port PB
Pull-down power supply
VEE
88
Input
/Output
—
Input
Input
Input
Output
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Input
Output
Input
Input
Input
Input
Input
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to 11.7 V to 12.6 V.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Input an arbitrary level between the range of VSS and V CC.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input
“H” or “L”, or keep them open.
__
OE input pin
Input “H” or “L” , or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L” to P60–P63, P6 5, or keep them open.
This pin is for serial data I/O.
This pin is for serial clock input.
This pin is for BUSY signal output.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Keep this open.
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Functional Outline (serial I/O mode)
Data is transferred in units of eight bits.
In the first transfer, the user inputs the command code. This is followed by address input and data input/output according to the
contents of the command. Table 20 shows the software commands used in the serial I/O mode. The following explains each
software command.
In the serial I/O mode, data is transferred synchronously with the
clock using serial input/output. The input data is read from the
SDA pin into the internal circuit synchronously with the rising edge
of the serial clock pulse; the output data is output from the SDA
pin synchronously with the falling edge of the serial clock pulse.
Table 20 Software command (serial I/O mode)
Number of transfers First command
Command
code input
Read
0016
Program
4016
Program verify
C016
Erase
2016
Erase verify
A016
Error check
8016
Second
Third
Read address L (Input)
Program address L (Input)
Verify data (Output)
2016 (Input)
Verify address L (Input)
Error code (Output)
Fourth
Read address H (Input)
Program address H (Input)
—————
—————
Verify address H (Input)
—————
Read data (Output)
Program data (Input)
—————
—————
Verify data (Output)
—————
__
● Read command
Input command code 00 16 in the first transfer. Proceed and input
the low-order
8 bits and the high-order 8 bits of the address and
__
pull the OE pin low. When this is done, the M38B79FF reads out
the contents of the specified address, and then latchs it into the in-
ternal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the read data that has been
latched into the data latch is serially output from the SDA pin.
tCH
tCH
SCLK
A0
SDA
A7
0 0 0 0 0 0 0 0
Command code input (0016) Read address input (L)
A8
A15
Read address input (H)
tCR
D0
tWR
tRC
D7
Read data output
OE
Read
BUSY “L”
Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 92 Timings during reading
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Program command
Input command code 40 16 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
then program data. Programming is initiated at the last rising edge
of the serial clock during program data transfer. The BUSY pin is
driven high during program operation. Programming is completed
within 10 µs as measured by the internal timer, and the BUSY pin
is pulled low.
tCH
Note : A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in the verification, the user must repeatedly execute the program command until the pass in the
verification. Refer to Figure 90 for the programming flowchart.
tCH
tCH
SCLK
tPC
A0
SDA
0 0 0 0 0 0 1 0
Command code input (4016)
A7
A8
D0
A15
Program address input (L) Program address input (H)
D7
Program data input
OE
tWP
Program
BUSY
Fig. 93 Timings during programming
__
● Program verify command
Input__
command code C0 16 in the first transfer. Proceed and drive
the OE pin low. When this is done, The M38B79FF verify-reads
the programmed address’s contents, and then latchs it into the in-
ternal data latch. When the OE pin is released back high and serial clock is input to the SCLK pin, the verify data that has been
latched into the data latch is serially output from the SDA pin.
SCLK
D0
SDA
0 0 0 0 0 0 1 1
Command code input (C016)
D7
Verify data output
tCRPV
tWR
tRC
OE
Verify read
BUSY
“L”
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 94 Timings during program verify
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Erase command
Input command code 2016 in the first transfer and command code
20 16 again in the second transfer. When this is done, the
M38B79FF executes an erase command. Erase is initiated at the
last rising edge of the serial clock. The BUSY pin is driven high
during the erase operation. Erase is completed within 9.5 ms as
measured by the internal timer, and the BUSY pin is pulled low.
Note that data 0016 must be written to all memory locations before
executing the erase command.
Note: A erase operation is not completed by executing the erase
command once. Always be sure to execute a erase verify
command after executing the erase command. When the failure is found in the verification, the user must repeatedly execute the erase command until the pass in the verification.
Refer to Figure 90 for the erase flowchart.
tCH
SCLK
tEC
SDA
0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0
Command code input (2016) Command code input (2016)
“H”
OE
twE
BUSY
Erase
Fig. 95 Timings at erasing
● Erase verify command
The user must verify the contents of all addresses after completing the erase command. Input command code A016 in the first
transfer. Proceed and input the low-order
8 bits and the high-order
__
8 bits of the address and pull the OE pin low. When this is done,
the M38B79FF reads out the contents of the specified __
address,
and then latchs it into the internal data latch. When the OE pin is
released back high and serial clock is input to the SCLK pin, the
tCH
verify data that has been latched into the data latch is serially output from the SDA pin.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the operation of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
tCH
SCLK
A0
SDA
A7
0 0 0 0 0 1 0 1
Command code input (A016) Verify address input (L)
A8
A15
Verify address input (H)
tCREV
D0
tWR
tRC
D7
Verify data output
OE
Verify read
BUSY “L”
Note : When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 96 Timings during erase verify
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Error check command
Input command code 8016 in the first transfer, and the M38B79FF
outputs error information from the SDA pin, beginning at the next
falling edge of the serial clock. If the LSB bit of the 8-bit error information is 1, it indicates that a command error has occurred. A
command error means that some invalid commands other than
commands shown in Table 20 has been input.
When a command error occurs, the serial communication circuit
sets the corresponding flag and stops functioning to avoid an erroneous programming or erase. When being placed in this state, the
serial communication circuit does not accept the subsequent serial
clock and data (even including an error check command). Therefore, if the user wants to execute an error check command,
temporarily drop the VPP pin input to the V PPL level to terminate
the serial input/output mode. Then, place the M38B79FF into the
serial I/O mode back again. The serial communication circuit is reset by this operation and is ready to accept commands. The error
flag alone is not cleared by this operation, so the user can examine the serial communication circuit’s error conditions before reset.
This examination is done by the first execution of an error check
command after the reset. The error flag is cleared when the user
has executed the error check command. Because the error flag is
undefined immediately after power-on, always be sure to execute
the error check command.
tCH
SCLK
E0
SDA
OE
0 0 0 0 0 0 0 1
Command code input (8016)
? ? ? ? ? ? ?
Error flag output
“H”
BUSY “L”
Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit).
Fig. 97 Timings at error checking
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, unless otherwise noted)
I CC, IPP -relevant standards during
read, program, and erase are the same as in the parallel input/output mode. VIH, VIL, VOH, VOL , IIH, and
__
I IL for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes.
Table 21 AC Electrical characteristics
(T a = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, f(X IN) = 4 MHz, unless otherwise noted)
Symbol
tCH
tCR
tWR
tRC
tCRPV
tWP
tPC
tCREV
tWE
tEC
tc(CK)
tw(CKH)
tw(CKL)
tr(CK)
tf(CK)
td(C-Q)
th(C-Q)
th(C-E)
tsu(D-C)
th(C-D)
Limits
Parameter
Min.
625(Note 1)
625(Note 1)
500(Note 2)
625(Note 1)
6
Serial transmission interval
Read waiting time after transmission
Read pulse width
Transfer waiting time after read
Waiting time before program verify
Programming time
Transfer waiting time after programming
Waiting time before erase verify
Erase time
Transfer waiting time after erase
SCLK input cycle time
SCLK high-level pulse width
SCLK low-level pulse width
SCLK rise time
SCLK fall time
SDA output delay time
SDA output hold time
SDA output hold time (only the 8th bit)
SDA input set up time
SDA input hold time
Max.
10
625(Note 1)
6
9.5
625(Note 1)
250
100
100
20
20
90
0
0
187.5 (Note 3) 312.5(Note 4)
30
90
Unit
ns
ns
ns
ns
µs
µs
ns
µs
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When f(XIN) = 4 MHz or less, calculate the minimum value according to formula 1.
2500
× 106
f(XIN)
2: When f(XIN) = 4 MHz or less, calculate the minimum value according to formula 2.
Formula 1 :
2000
× 106
f(XIN)
3: When f(XIN) = 4 MHz or less, calculate the minimum value according to formula 3.
Formula 2 :
750
× 106
f(XIN)
4: When f(XIN) = 4 MHz or less, calculate the minimum value according to formula 4
Formula 3 :
Formula 4 :
1250
f(XIN)
× 106
AC waveforms
tf(CK)
tw(CKL)
tc(CK)
tr(CK)
tw(CKH)
SCLK
th(C-Q)
td(C-Q)
th(C-E)
Test conditions for AC characteristics
SDA output
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
tsu(D-C)
th(C-D)
• Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC
SDA input
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(3) Flash memory mode 3 (CPU reprogramming
mode)
The M38B79FF has the CPU reprogramming mode where a builtin flash memory is handled by the central processing unit (CPU).
In CPU reprogramming mode, the flash memory is handled by
writing and reading to/from the flash memory control register (see
Figure 98) and the flash command register (see Figure 99).
The CNV SS pin is used as the VPP power supply pin in CPU reprogramming mode. It is necessary to apply the power-supply voltage
of VPPH from the external to this pin.
by checking this flag after each command of erase and the program is executed.
Bits 4, 5 of the flash memory control register are the erase/program area select bits. These bits specify an area where erase and
program is operated. When the erase command is executed after
an area is specified by these bits, only the specified area is
erased. Only for the specified area, programming is enabled; for
the other areas, programming is disabled.
Figure 100 shows the CPU mode register bit configuration in the
CPU reprogramming mode.
Functional Outline (CPU reprogramming mode)
Figure 98 shows the flash memory control register bit configuration. Figure 99 shows the flash command register bit
configuration.
Bit 0 of the flash memory control register is the CPU reprogramming mode select bit. When this bit is set to “1” and VPP H is
applied to the CNVss/V PP pin, the CPU reprogramming mode is
selected. Whether the CPU reprogramming mode is realized or
not is judged by reading the CPU reprogramming mode monitor
flag (bit 2 of the flash memory control register).
Bit 1 is a busy flag which becomes “1” during erase and program
execution.
Whether these operations have been completed or not is judged
7
6
0
5
4
3
0
2
1
0
Flash memory control regsiter
(FCON : address 0EFE16)
CPU reprogramming mode select bit (Note)
0 : CPU reprogramming mode is invalid. (Normal operation mode)
1 : When applying 0 V or VPPL to CNVSS/VPP pin, CPU reprogramming mode is
invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid.
Erase/Program busy flag
0 : Erase and program are completed or not have been executed.
1 : Erase/program is being executed.
CPU reprogramming mode monitor flag
0 : CPU reprogramming mode is invalid.
1 : CPU reprogramming mode is valid.
Fix this bit to “0”.
Erase/Program area select bits
0 0 : Addresses 100016 to FFFF16 (total 60 Kbytes)
0 1 : Addresses 100016 to 7FFF16 (total 28 Kbytes)
1 0 : Addresses 800016 to FFFF16 (total 32 Kbytes)
1 1 : Not available
Fix this bit to “0”.
Not used (returns “0” when read)
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
Fig. 98 Flash memory control register bit configuration
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● CPU reprogramming mode operation procedure
The operation procedure in CPU reprogramming mode is described below.
< Beginning procedure >
➀ Apply 0 V to the CNVss/VPP pin for reset release.
➁ Set the CPU mode register. (see Figure 100)
➂ After CPU reprogramming mode control program is transferred to
internal RAM, jump to this control program on RAM. (The following operations are controlled by this control program).
➃ Set “1” to the CPU reprogramming mode select bit.
➄ Apply VPPH to the CNV SS/VPP pin.
➅ Wait till CNVSS/V PP pin becomes 12 V.
➆ Read the CPU reprogramming mode monitor flag to confirm
whether the CPU reprogramming mode is valid.
➇ The operation of the flash memory is executed by software-command-writing to the flash command register .
Note: The following are necessary other than this:
•Control for data which is input from the external (serial I/O
etc.) and to be programmed to the flash memory
•Initial setting for ports etc.
•Writing to the watchdog timer
< Release procedure >
➀ Apply 0V to the CNVSS/VPP pin.
➁ Wait till CNVSS/V PP pin becomes 0V.
➂ Set the CPU reprogramming mode select bit to “0”.
Each software command is explained as follows.
● Read command
When “00 16 ” is written to the flash command register, the
M38B79FF enters the read mode. The contents of the corresponding address can be read by reading the flash memory (For
instance, with the LDA instruction etc.) under this condition.
The read mode is maintained until another command code is written
to the flash command register. Accordingly, after setting the read
mode once, the contents of the flash memory can continuously be
read.
After reset and after the reset command is executed, the read
mode is set.
b7
7
6
5
4
3
2
1
0
Flash command register
(FCMD : address 0EFF16)
Writing of software command
<Software command name>
<Command code>
• Read command
“0016”
• Program command
“4016”
• Program verify command
“C016”
• Erase command
“2016” + “2016”
• Erase verify command
“A016”
• Reset command
“FF16” + “FF16”
Note: The flash command register is write-only register.
Fig. 99 Flash command register bit configuration
b0
0
0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Not available
1 X : Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Reserved
(Do not write “0” to this bit when using
XCIN–XCOUT oscillation function.)
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN) (high-speed mode)
0 1 : φ = f(XIN)/4 (middle-speed mode)
1 0 : φ = f(XCIN)/2 (low-speed mode)
1 1 : Not available
Fig. 100 CPU mode register bit configuration in CPU rewriting
mode
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● Program command
When “40 16 ” is written to the flash command register, the
M38B79FF enters the program mode.
Subsequently to this, if the instruction (for instance, STA
instruction) for writing byte data in the address to be programmed
is executed, the control circuit of the flash memory executes the
program. The erase/program busy flag of the flash memory control
register is set to “1” when the program starts, and becomes “0”
when the program is completed. Accordingly, after the write instruction is executed, CPU can recognize the completion of the
program by polling this bit.
The programmed area must be specified beforehand by the erase/
program area select bits.
During programming, watchdog timer stops with “FFFF16” set.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a program verify command after executing the program command.
When the failure is found in this verification, the user must repeatedly execute the program command until the pass. Refer
to Figure 101 for the flow chart of the programming.
● Program verify command
When “C016 ” is written to the flash command register, the
M38B79FF enters the program verify mode. Subsequently to this,
if the instruction (for instance, LDA instruction) for reading byte
data from the address to be verified (i.e., previously programmed
address), the contents which has been written to the address actually is read.
CPU compares this read data with data which has been written by
the previous program command. In consequence of the comparison, if not agreeing, the operation of “program → program verify”
must be executed again.
● Erase command
When writing “2016 ” twice continuously to the flash command register, the flash memory control circuit performs erase to the area
specified beforehand by the erase/program area select bits.
Erase/program busy flag of the flash memory control register becomes “1” when erase begins, and it becomes “0” when erase
completes. Accordingly, CPU can recognize the completion of
erase by polling this bit.
Data “0016 ” must be written to all areas to be erased by the program and the program verify commands before the erase
command is executed.
During erasing, watchdog timer stops with “FFFF16 ” set.
Note: The erasing operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the failure is found in this verification, the user must repeatedly execute the erase command until the pass. Refer to Figure 101
for the erasing flowchart.
96
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Erase verify command
When “A0 16” is written to the flash command register, the
M38B79FF enters the erase verify mode. Subsequently to this, if
the instruction (for instance, LDA instruction) for reading byte data
from the address to be verified, the contents of the address is
read.
CPU must erase and verify to all erased areas in a unit of address.
If the address of which data is not “FF 16” (i.e., data is not erased)
is found, it is necessary to discontinue erasure verification there,
and execute the operation of “erase → erase verify” again.
Note: By executing the operation of “erase → erase verify” again
when the memory not erased is found. It is unnecessary to
write data “0016” before erasing in this case.
● Reset command
The reset command is a command to discontinue the program or
erase command on the way. When “FF16 ” is written to the command
register two times continuously after “4016” or “2016” is written to the
flash command register, the program, or erase command becomes
invalid (reset), and the M38B79FF enters the reset mode.
The contents of the memory does not change even if the reset command is executed.
DC Electric Characteristics
Note: The characteristic concerning the flash memory part are the
same as the characteristic of the parallel I/O mode.
AC Electric Characteristics
Note: The characteristics are the same as the characteristic of the
microcomputer mode.
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Program
Erase
START
START
ADRS = first location
ALL
BYTES = 0016 ?
YES
X=0
NO
WRITE PROGRAM
COMMAND
4016
WRITE PROGRAM
DATA
DIN
PROGRAM
ALL BYTES = 0016
ADRS = first location
X=0
WAIT 1µs
NO
ERASE PROGRAM
BUSY FLAG = 0
YES
X=X+1
WRITE ERASE
COMMAND
2016
WRITE ERASE
COMMAND
2016
WAIT 1µs
WRITE PROGRAM-VERIFY
COMMAND
C016
NO
ERASE PROGRAM
BUSY FLAG = 0
DURATION = 6 µs
YES
X=X+1
X = 25 ?
YES
WRITE ERASE-VERIFY
COMMAND
NO
PASS
FAIL
VERIFY BYTE ?
DURATION = 6 µs
VERIFY BYTE ?
PASS
A016
FAIL
YES
X = 1000 ?
INC ADRS
NO
LAST ADRS ?
NO
YES
WRITE READ COMMAND
PASS
FAIL
VERIFY BYTE ?
VERIFY BYTE ?
0016
FAIL
PASS
DEVICE
PASSED
DEVICE
FAILED
NO
INC ADRS
LAST ADRS ?
YES
WRITE READ COMMAND
DEVICE
PASSED
0016
DEVICE
FAILED
Fig. 101 Flowchart of program/erase operation at CPU reprogramming mode
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NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value
of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O
•Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
•Using an internal clock
When using an internal clock, set the synchronous clock to the internal clock, then clear the serial I/O interrupt request bit before
executing serial I/O transfer and serial I/O automatic transfer.
Automatic Transfer Serial I/O
When using the automatic transfer serial I/O mode of the serial I/
O1, set an automatic transfer interval as the following.
Otherwise the serial data might be incorrectly transmitted/received.
•Set an automatic transfer interval for each 1-byte data transfer as
the following:
(1) Not using FLD controller
Keep the interval for 5 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
(2) Using FLD controller
(a) Not using gradation display
Keep the interval for 17 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
(b) Using gradation display
Keep the interval for 27 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 250 kHz during an
A-D conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
D-A Converter
The accuracy of the D-A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0 V
is recommended. When a D-A converter is not used, set the value
of D-A conversion register to “0016”.
Instruction Execution Time
The instruction execution time is obtained by multiplying the period of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock φ is half of the XIN period in highspeed mode.
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MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON USAGE
Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin), between power
source pin (VCC pin) and analog power source input pin (AVSS
pin), and between program power source pin (CNVss/V PP) and
GND pin for flash memory version when on-board reprogramming
is executed. Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far
from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1
µF is recommended.
Flash Memory Version
The CNVSS pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNV SS
pin and VSS pin or VCC pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNV SS pin has no operational interference even if it is connected to Vss pin or Vcc pin via a
resistor.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1.Mask ROM Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical copies) or in one floppy disk.
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 22 Absolute maximum ratings
Symbol
VCC
VEE
VI
Pd
Parameter
Power source voltages
Pull-down power source voltages
Input voltage P64–P67, P70 –P77, P80–P83 ,
P90–P97 , PA0–PA7 , PB0–PB6
Input voltage P10–P17, P30 –P37, P40–P47 ,
P50–P57, P60 –P63
Input voltage RESET, XIN, CNV SS
Input voltage XCIN
Output voltage P00–P07, P10 –P17, P20–P27 ,
P30–P37, P40 –P47, P50–P57 ,
P60–P63
Output voltage P64–P67, P80–P83 , P70–P77,
P90–P97 , PA0–PA7, PB 0–PB6,
XOUT, XCOUT
Power dissipation
Topr
Tstg
Operating temperature
Storage temperature
VI
VI
VI
VO
VO
Conditions
All voltages are based on VSS.
Output transistors are cut off.
Ta = –20 to 65 °C
Ta = 65 to 85 °C
Ratings
–0.3 to 6.5
VCC –48 to VCC +0.3
–0.3 to V CC +0.3
Unit
V
V
V
VCC –48 to VCC +0.3
V
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VCC –48 to VCC +0.3
V
V
V
–0.3 to VCC +0.3
V
800
800 –12.5 ✕ (Ta –65)
–20 to 85
–40 to 125
mW
mW
°C
°C
Table 23 Recommended operating conditions
(V CC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
VCC
Power source voltage (mask ROM version)
VCC
VSS
VEE
VREF
Power source voltage (flash memory version)
Power source voltage
Pull-down power source voltage
Analog reference voltage
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Analog power source voltage
Analog input voltage AN 0–AN 15
“H” input voltage
P70–P7 7, P80–P83 , P90–P97 , PA0–PA7, PB0 –PB6
“H” input voltage
P64–P67
“H” input voltage
P10–P17 , P30–P37, P40 –P47, P50–P57, P6 0–P63
“H” input voltage
RxD, S CLK21, SCLK22
“H” input voltage
XIN, XCIN , RESET, CNVss
“L” input voltage
P70–P7 7, P80–P83 , P90–P97 , PA0–PA7, PB0 –PB6
“L” input voltage
P64–P67
“L” input voltage
P10–P17 , P30–P37, P40 –P47, P50–P57, P6 0–P63
“L” input voltage
RxD, S CLK21, SCLK22
“L” input voltage
XIN, XCIN , RESET, CNVss
100
High-speed mode
Middle/Low-speed mode
when A-D converter is used
when D-A converter is used
Min.
4.0
2.7
4.0
Limits
Typ.
5.0
5.0
5.0
0
Vcc –43
2.0
3.0
Max.
5.5
5.5
5.5
VCC
VCC
VCC
0
0
0.75V CC
0.4V CC
0.52V CC
0.8V CC
0.8V CC
0
0
0
0
0
VCC
VCC
VCC
VCC
VCC
VCC
0.25VCC
0.16VCC
0.2V CC
0.2V CC
0.2VCC
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
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MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 24 Recommended operating conditions
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
ΣI OH(peak)
ΣI OH(peak)
ΣI OL(peak)
ΣI OL(peak)
ΣI OH(avg)
ΣI OH(avg)
ΣI OL(avg)
I OH(peak)
I OH(peak)
I OL(peak)
I OH(avg)
I OH(avg)
I OL(avg)
f(CNTR)
f(XIN )
f(XCIN )
Parameter
“H” total peak output current (Note 1) P00–P07, P10–P17, P20–P27, P3 0–P37, P40–P47,
P50–P57, P60–P67, P70–P77
“H” total peak output current (Note 1) P80–P83, P90–P97, PA 0–PA7, PB0–PB6
“L” total peak output current (Note 1) P64–P67, P70–P7 7
“L” total peak output current (Note 1) P80–P83, P90–P97, PA 0–PA7, PB0–PB6
“H” total average output current (Note 1) P0 0–P07, P10–P17, P20–P27, P3 0–P37, P40–P47,
P50–P57, P60–P63
“H” total average output current (Note 1) P6 4–P67, P7 0–P7 7, P8 0–P8 3, P9 0–P97, PA0–PA7,
PB0–PB 6
“L” total average output current (Note 1) P64–P67, P70–P77, P80–P83, P90–P97, PA0–PA7,
PB0–PB 6
“H” peak output current (Note 2) P00–P07, P10–P17, P2 0–P27, P30–P37, P40–P47,
P5 0–P57, P60–P63
“H” peak output current (Note 2) P6 4–P6 7, P7 0–P77, P80–P83, P90–P97, PA0–PA7,
PB0–PB 6
“L” peak output current (Note 2) P6 4–P67, P70–P77, P80–P83, P90–P97, PA0–PA7,
PB0–PB 6
“H” average output current (Note 3) P0 0–P07, P10–P17, P20–P27, P3 0–P37, P40–P47,
P50–P57, P60–P63
“H” average output current (Note 3) P6 4–P67, P70–P77, P8 0–P83, P90–P97, PA0–PA7,
PB0–PB 6
“L” average output current (Note 3) P6 4–P67, P70–P77, P80–P83, P9 0–P97, PA 0–PA7,
PB0–PB 6
Clock input frequency for timers 2, 4, and X (duty cycle 50 %)
Main clock input oscillation frequency (Note 4)
Sub-clock input oscillation frequency (Notes 4, 5)
Min.
Limits
Typ.
32.768
Max.
–240
Unit
mA
–60
100
60
–120
mA
mA
mA
mA
–30
mA
50
mA
–40
mA
–10
mA
10
mA
–18
mA
–5
mA
5
mA
250
4.2
50
kHz
MHz
kHz
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH(avg) are average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
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MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 25 Electrical characteristics
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VOH
VOH
VOL
VT+ –VT–
VT+ –VT–
VT+ –VT–
I IH
I IH
I IH
I IH
I IL
Parameter
“H” output voltage
P00–P07, P1 0–P17, P20–P27 ,
P30–P37, P4 0–P47, P50-P5 7,
P60–P63
“H” output voltage
P64–P67, P7 0–P77, P80–P83 ,
P90–P97 , PA0–PA7 , PB0–PB6
“L” output voltage
P64–P67, P7 0–P77, P80–P83 ,
P90–P97 , PA0–PA7 , PB0–PB6
Hysteresis
RxD, S CLK21, SCLK22, SRDY1, P70 –
P73, P7 7, P82–P83, P9 0–P92, PB0,
PB 2, PB4–PB6
Hysteresis
RESET, XIN
Hysteresis
XCIN
“H” input current
P64–P67, P7 0–P77, P80–P83 ,
P90–P97 , PA0–PA7 , PB0–PB6
“H” input current
P10–P17, P3 0–P37, P40–P47 ,
P50-P5 7, P60–P63 (Note)
“H” input current
RESET, CNVss, XCIN
“H” input current
XIN
“L” input current
P64–P67, P7 0–P77, P80–P83 ,
P90–P97 , PA0–PA7 , PB0–PB6
I IL
“L” input current
I IL
I IL
“L” input current
“L” input current
P10–P17, P3 0–P37, P40–P47 ,
P50–P57, P60 –P63 (Note)
RESET, CNVss, XCIN
XIN
Note: Except when reading ports P1, P3, P4, P5 or P6.
102
Test conditions
Limits
IOH = –18 mA
Min.
VCC–2.0
IOH = –10 mA
VCC–2.0
Typ.
Max.
Unit
V
V
IOL = 10 mA
2.0
V
0.4
V
0.5
0.5
VI = V CC
5.0
V
V
µA
VI = V CC
5.0
µA
5.0
–5.0
µA
µA
µA
VI = V CC
VI = V CC
VI = V SS
Pull-up “off”
VCC = 5 V, VI = VSS
Pull-up “on”
VCC = 3 V, VI = VSS
Pull-up “on”
VI = V SS
VI = V SS
VI = V SS
4.0
–30
–70
–140
µA
–6.0
–25
–45
µA
–5.0
µA
–5.0
µA
µA
–4.0
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MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 26 Electrical characteristics
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
I LOAD
I LEAK
I READH
VRAM
I CC
Limits
Parameter
Output load current
P00 –P07, P10–P17,
P20 –P27, P30–P37,
(P4 0–P47, P50 –P57,
P60 –P63 at option)
Output leak current
P00 –P07, P10–P17,
P20 –P27, P30–P37,
P40 –P47, P50–P57,
P60 –P63
“H” read current
P10 –P17, P30–P37,
P40 –P47, P50–P57,
P60 –P63
RAM hold voltage
Power source current
Test conditions
VEE = VCC–43 V, VOL =VCC
Output transistors “off”
Typ.
Max.
400
600
900
µA
–10
µA
VEE = VCC–43 V, VOL =VCC–43 V
Output transistors “off”
VI = 5 V
When clock is stopped
High-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz
f(XCIN ) = 32.768 kHz
Output transistors “off”
High-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN ) = 32.768 kHz
Output transistors “off”
Middle-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz
f(XCIN ) = stopped
Output transistors “off”
Middle-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN ) = stopped
Output transistors “off”
Low-speed mode, Vcc = 3 V,
f(XIN) = stopped
f(XCIN ) = 32.768 kHz
Output transistors “off”
Low-speed mode, Vcc = 3 V,
f(XIN) = stopped
f(XCIN ) = 32.768 kHz (in WIT state)
Output transistors “off”
Increment when A-D conversion is
executed
All oscillation stopped
Ta = 25 °C
(in STP state)
Output transistors “off” Ta = 85 °C
Unit
Min.
µA
1
2
7.0
5.5
15
V
mA
1
mA
3
mA
1
mA
20
55
µA
8
20
µA
mA
0.6
0.1
1
µA
10
µA
103
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MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 27 A-D converter characteristics
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 250 kHz to 4.2 MHz in high-speed mode, unless otherwise noted)
Symbol
Parameter
—
Resolution
—
Absolute accuracy (excluding quantization error)
Test conditions
Limits
Min.
VCC = VREF = 5.12 V
Typ.
Bits
±2.5
LSB
62
tc(φ )
150
200
µA
5.0
µA
±1
Conversion time
61
IVREF
Reference input current
I IA
Analog port input current
0.5
RLADDER
Ladder resistor
35
50
Unit
10
TCONV
VREF = 5.0 V
Max.
kΩ
Table 28 D-A converter characteristics
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 to Vcc, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
–
–
tsu
RO
I VREF
Parameter
Resolution
Absolute accuracy
(excluding quantization error)
Setting time
Output resistor
Reference power source input current (Note)
Note: Except ladder resistor for A-D converter
104
Test conditions
Min.
Limits
Typ.
VCC = 4.0–5.5 V
VCC = 3.0–5.5 V
1
2.5
Max.
8
1.0
2.5
3
4
3.2
Unit
Bits
%
%
µs
kΩ
mA
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MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 29 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
t W(RESET)
t C(X IN)
t WH (XIN)
t WL (XIN)
t C(X CIN)
t WH (XCIN)
t WL (XCIN)
t C(CNTR)
t WH (CNTR)
t WL(CNTR)
t WH (INT)
t WL (INT)
t WH (INT2 )
t WL (INT2 )
t C(S CLK1)
t WH (SCLK1 )
t WL (SCLK1)
t su(SIN1-S CLK1)
t h(S CLK1-S IN1)
t C(S CLK2)
t WH (SCLK2 )
t WL (SCLK2)
t su(RxD-SCLK2 )
t h(S CLK2-RxD)
t C(S CLK3)
t WH (SCLK3 )
t WL (SCLK3)
t su(SIN3-S CLK3)
t h(S CLK3-S IN3)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0–CNTR2 input cycle time
CNTR0–CNTR2 input “H” pulse width
CNTR0–CNTR2 input “L” pulse width
INT0–INT 4 input “H” pulse width (INT2 when noise filter is not used)
(Note 1)
INT0–INT 4 input “L” pulse width (INT2 when noise filter is not used)
(Note 1)
INT2 input “H” pulse width (when noise filter is used) (Notes 1, 2)
INT2 input “L” pulse width (when noise filter is used) (Notes 1, 2)
Serial I/O1 clock input cycle time
Serial I/O1 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
Serial I/O2 input hold time
Serial I/O3 clock input cycle time
Serial I/O3 clock input “H” pulse width
Serial I/O3 clock input “L” pulse width
Serial I/O3 input setup time
Serial I/O3 input hold time
Min.
2.0
238
60
60
20
5.0
5.0
4.0
1.6
1.6
80
Limits
Typ.
Max.
Unit
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
80
ns
3
3
950
400
400
200
200
800
370
370
220
100
1000
400
400
200
200
CLKs
CLKs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: IIDCON2, IIDCON3 = “00” when noise filter is not used
IIDCON2, IIDCON3 = “01” or “10” when noise filter is used
2: Unit indicates sample clock number of noise filter.
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MITSUBISHI MICROCOMPUTERS
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 30 Switching characteristics
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
t WH (S CLK)
t WL (SCLK)
t d (SCLK1 -SOUT1)
t V (S CLK1-S OUT1)
t d (SCLK2 -TxD)
t V (S CLK2-TxD)
t d (SCLK3 -SOUT3)
t V (S CLK3-S OUT3)
t r (SCLK )
t f (S CLK)
t r (Pch–strg)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O3 output delay time (Note 3)
Serial I/O3 output valid time (Note 3)
Serial I/O clock output rising time
Serial I/O clock output falling time
P-channel high-breakdodwn-voltage output
rising time (Note 4)
P-channel high-breakdodwn-voltage output
rising time (Note 5)
CL = 100 pF
CL = 100 pF
t r (Pch–weak)
Notes 1: When
2: When
3: When
4: When
5: When
the
the
the
the
the
Limits
Min.
Typ.
t C(S CLK)/2–160
t C(S CLK)/2–160
55
1.8
µs
200
0
140
–30
200
0
40
40
CL = 100 pF
CL = 100 pF
CL = 100 pF
VEE = Vcc –43 V
CL = 100 pF
VEE = Vcc –43 V
High-breakdown voltage
P-channel open-drain output port
P66/SCLK21,
P67/SCLK22,
P92/SCLK3,
PB0/SCLK12,
PB4/SCLK11
P0, P1, P2, P3,
P4, P5, P60–P63
CL
CL
(Note)
VEE
Note: Ports P4, P5, P60–P63 need external resistors.
Fig. 102 Circuit for measuring output switching characteristics
106
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PB 5/S OUT1 P-channel output disable bit of the serial I/O1 control register (bit 7 of address 001A16) is “0”.
P65/TxD P-channel output disable bit of the UART control register (bit 4 of address 0038 16) is “0”.
P91/S OUT3 P-channel output disable bit of the serial I/O3 control register (bit 7 of address 0EEC16) is “0”.
high-breakdown voltage port drivability selection bit of the FLDC mode register (bit 7 of address 0EF416) is “0”.
high-breakdown voltage port drivability selection bit of the FLDC mode register (bit 7 of address 0EF416) is “1”.
Serial I/O clock output port
Max.
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MITSUBISHI MICROCOMPUTERS
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0,CNTR1
0.8VCC
0.2VCC
tWL(INT)
tWH(INT)
INT0–INT4
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
XIN
0.8VCC
0.2VCC
tC(XCIN)
tWL(X CIN)
tWH(XCIN)
XCIN
0.8VCC
0.2VCC
tC(SCLK)
tf(SCLK)
SCLK
tWL(SCLK)
tr
tWH(SCLK)
0.8VCC
0.2VCC
tsu(SIN-SCLK)
tsu(RxD-S CLK)
th(SCLK-SIN)
th(SCLK-RxD)
0.8VCC
0.2VCC
SIN, RxD
td(SCLK-SOUT)
td(SCLK-TxD)
tv(SCLK-SOUT)
tv(SCLK-TxD)
SOUT, TxD
Fig. 103 Timing diagram
107
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
QFP100-P-1420-0.65
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
ME
HD
D
1
b2
81
100
80
I2
Recommended Mount Pad
E
HE
Symbol
51
30
50
A
L1
c
A2
31
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
b
y
x
M
A1
F
e
L
Detail F
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
3.05
–
–
0.1
0.2
0
2.8
–
–
0.25
0.3
0.4
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.65
–
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.13
0.1
–
–
0°
10°
–
0.35
–
–
1.3
–
–
14.6
–
–
–
–
20.6
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
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•
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Notes regarding these materials
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© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective Apr. 2000.
Specifications subject to change without notice.
REVISION HISTORY
Rev.
No.
1.0
38B7 GROUP DATA SHEET
Revision Description
First Edition
Rev.
date
10/04/00
(1/1)