MOTOROLA MC14001BD B-suffix series cmos gate Datasheet

SEMICONDUCTOR TECHNICAL DATA
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The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
• Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix
Devices (Exceptions: MC14068B and MC14078B)
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L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
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D SUFFIX
SOIC
CASE 751A
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ORDERING INFORMATION
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MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
lin, lout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
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This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14001B
7
LOGIC DIAGRAMS
NAND
OR
AND
MC14001B
Quad 2–Input NOR Gate
MC14011B
Quad 2–Input NAND Gate
MC14071B
Quad 2–Input OR Gate
MC14081B
Quad 2–Input AND Gate
2 INPUT
NOR
1
2
3
1
2
3
1
2
3
1
2
3
5
6
4
5
6
4
5
6
4
5
6
4
8
9
10
8
9
10
8
9
10
8
9
10
12
13
11
12
13
11
12
13
11
12
13
11
3 INPUT
MC14025B
Triple 3–Input NOR Gate
1
2
8
3
4
5
11
12
13
9
6
10
4 INPUT
MC14002B
Dual 4–Input NOR Gate
2
3
4
5
9
10
11
12
1
13
NC = 6, 8
MC14023B
Triple 3–Input NAND Gate
1
2
8
3
4
5
11
12
13
8 INPUT
MC14001B
8
10
2
3
4
5
9
10
11
12
1
13
NC = 6, 8
1
2
8
3
4
5
11
12
13
9
6
10
MC14072B
Dual 4–Input OR Gate
2
3
4
5
9
10
11
12
1
13
NC = 6, 8
MC14073B
Triple 3–Input AND Gate
1
2
8
3
4
5
11
12
13
9
6
10
MC14082B
Dual 4–Input AND Gate
2
3
4
5
9
10
11
12
1
13
NC = 6, 8
MC14068B
8–Input NAND Gate
13
NC = 6, 8
6
MC14012B
Dual 4–Input NAND Gate
MC14078B
8–Input NOR Gate
2
3
4
5
9
10
11
12
9
MC14075B
Triple 3–Input OR Gate
2
3
4
5
9
10
11
12
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
13
NC = 6, 8
MOTOROLA CMOS LOGIC DATA
PIN ASSIGNMENTS
MC14001B
Quad 2–Input NOR Gate
MC14002B
Dual 4–Input NOR Gate
IN 1A
1
14
VDD
OUTA
1
14
VDD
MC14011B
Quad 2–Input NAND Gate
MC14012B
Dual 4–Input NAND Gate
IN 1A
1
14
VDD
OUTA
1
14
VDD
IN 2A
2
13
IN 2D
IN 1A
2
13
OUTB
IN 2A
2
13
IN 2D
IN 1A
2
13
OUTB
OUTA
3
12
IN 1D
IN 2A
3
12
IN 4B
OUTA
3
12
IN 1D
IN 2A
3
12
IN 4B
OUTB
4
11
OUTD
IN 3A
4
11
IN 3B
OUTB
4
11
OUTD
IN 3A
4
11
IN 3B
IN 1B
5
10
OUTC
IN 4A
5
10
IN 2B
IN 1B
5
10
OUTC
IN 4A
5
10
IN 2B
IN 2B
6
9
IN 2C
NC
6
9
IN 1B
IN 2B
6
9
IN 2C
NC
6
9
IN 1B
VSS
7
8
IN 1C
VSS
7
8
NC
VSS
7
8
IN 1C
VSS
7
8
NC
MC14023B
Triple 3–Input NAND Gate
MC14025B
Triple 3–Input NOR Gate
MC14068B
8–Input NAND Gate
MC14071B
Quad 2–Input OR Gate
IN 1A
1
14
VDD
IN 1A
1
14
VDD
IN 1A
1
14
VDD
NC
1
14
VDD
IN 2A
2
13
IN 3C
IN 2A
2
13
IN 3C
IN 1
2
13
OUT
IN 2A
2
13
IN 2D
IN 1B
3
12
IN 2C
IN 1B
3
12
IN 2C
IN 2
3
12
IN 8
OUTA
3
12
IN 1D
IN 2B
4
11
IN 1C
IN 2B
4
11
IN 1C
IN 3
4
11
IN 7
OUTB
4
11
OUTD
IN 3B
5
10
OUTC
IN 3B
5
10
OUTC
IN 4
5
10
IN 6
IN 1B
5
10
OUTC
OUTB
6
9
OUTA
OUTB
6
9
OUTA
NC
6
9
IN 5
IN 2B
6
9
IN 2C
VSS
7
8
IN 3A
VSS
7
8
IN 3A
VSS
7
8
NC
VSS
7
8
IN 1C
MC14072B
Dual 4–Input OR Gate
MC14073B
Triple 3–Input AND Gate
MC14075B
Triple 3–Input OR Gate
MC14078B
8–Input NOR Gate
OUTA
1
14
VDD
IN 1A
1
14
VDD
IN 1A
1
14
VDD
NC
1
14
VDD
IN 1A
2
13
OUTB
IN 2A
2
13
IN 3C
IN 2A
2
13
IN 3C
IN 1
2
13
OUT
IN 2A
3
12
IN 4B
IN 1B
3
12
IN 2C
IN 1B
3
12
IN 2C
IN 2
3
12
IN 8
IN 3A
4
11
IN 3B
IN 2B
4
11
IN 1C
IN 2B
4
11
IN 1C
IN 3
4
11
IN 7
IN 4A
5
10
IN 2B
IN 3B
5
10
OUTC
IN 3B
5
10
OUTC
IN 4
5
10
IN 6
NC
6
9
IN 1B
OUTB
6
9
OUTA
OUTB
6
9
OUTA
NC
6
9
IN 5
VSS
7
8
NC
VSS
7
8
IN 3A
VSS
7
8
IN 3A
VSS
7
8
NC
MC14081B
Quad 2–Input AND Gate
MC14082B
Dual 4–Input AND Gate
IN 1A
1
14
VDD
OUTA
1
14
VDD
IN 2A
2
13
IN 2D
IN 1A
2
13
OUTB
OUTA
3
12
IN 1D
IN 2A
3
12
IN 4B
OUTB
4
11
OUTD
IN 3A
4
11
IN 3B
IN 1B
5
10
OUTC
IN 4A
5
10
IN 2B
IN 2B
6
9
IN 2C
NC
6
9
IN 1B
VSS
7
8
IN 1C
VSS
7
8
NC
MOTOROLA CMOS LOGIC DATA
NC = NO CONNECTION
MC14001B
9
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Total Supply Current**†
(Dynamic plus Quiescent,
Per Gate, CL = 50 pF)
Sink
mAdc
IT = (0.3 µA/kHz) f + IDD/N
IT = (0.6 µA/kHz) f + IDD/N
IT = (0.9 µA/kHz) f + IDD/N
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.
MC14001B
10
MOTOROLA CMOS LOGIC DATA
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B–SERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise Time, All B–Series Gates
tTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/PF) CL + 20 ns
tTLH
Output Fall Time, All B–Series Gates
tTHL = (1.35 ns/pF) CL + 33 ns
tTHL = (0.60 ns/pF) CL + 20 ns
tTHL = (0.40 ns/pF) CL + 20 ns
tTHL
Propagation Delay Time
MC14001B, MC14011B only
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns
tPLH, tPHL = (0.36 ns/pF) CL + 32 ns
tPLH, tPHL = (0.26 ns/pF) CL + 27 ns
All Other 2, 3, and 4 Input Gates
tPLH, tPHL = (0.90 ns/pF) CL + 115 ns
tPLH, tPHL = (0.36 ns/pF) CL + 47 ns
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
8–Input Gates (MC14068B, MC14078B)
tPLH, tPHL = (0.90 ns/pF) CL + 155 ns
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns
tPLH, tPHL = (0.26 ns/pF) CL + 47 ns
VDD
Vdc
Min
Typ #
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
ns
tPLH, tPHL
ns
5.0
10
15
—
—
—
125
50
40
250
100
80
5.0
10
15
—
—
—
160
65
50
300
130
100
5.0
10
15
—
—
—
200
80
60
350
150
110
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
14
PULSE
GENERATOR
20 ns
VDD
20 ns
INPUT
INPUT
OUTPUT
CL
*
7
VSS
* All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to VSS.
VDD
90%
50%
10%
0V
tPHL
OUTPUT
INVERTING
tPLH
VOH
90%
50%
10%
tTHL
tPLH
OUTPUT
NON–INVERTING
tTLH
tTLH
tPHL
90%
50%
10%
tTHL
VOL
VOH
VOL
Figure 1. Switching Time Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14001B
11
CIRCUIT SCHEMATIC
NOR, OR GATES
MC14001B, MC14071B
One of Four Gates Shown
VDD
14
VDD
1, 6, 8, 13
*
2, 5, 9, 12
3, 4, 10, 11
MC14025B, MC14075B
One of Three Gates Shown
VSS
7
VDD
VSS
1, 3, 11
* Inverter omitted in MC14001B
2, 4, 12
14
VDD
*
MC14002B, MC14072B
One of Two Gates Shown
VSS
9, 6, 10
VDD
VDD
3, 9
8, 5, 13
2, 10
14
7
VDD
VSS
*
* Inverter omitted in MC14025B
1, 13
VSS
5, 11
4, 12
VSS
SAME AS
ABOVE
7
VSS
* Inverter omitted in MC14002B
VDD
2
MC14078B
Eight Input Gate
3
14
MC14001B
12
4
5
VSS
SAME AS
ABOVE
9
10
SAME AS
ABOVE
11
12
SAME AS
ABOVE
VDD
13
7
VSS
MOTOROLA CMOS LOGIC DATA
CIRCUIT SCHEMATIC
NAND, AND GATES
MC14011B, MC14081B
One of Four Gates Shown
14
VDD
*
MC14023B, MC14073B
One of Three Gates Shown
3, 4, 10, 11
VDD
2, 5, 9, 12
1, 6, 8, 13
7 VSS
* Inverter omitted in MC14011B
2, 4, 12
1, 3, 11
14
VSS
VDD
*
VDD
9, 6, 10
MC14012B, MC14082B
One of Two Gates Shown
8, 5, 13
7
VSS
VDD
VSS
* Inverter omitted in MC14023B
14
VDD
MC14068B
Eight Input Gate
VDD
2, 10
*
3, 9
VSS
VDD
4, 12
5, 11
1, 13
SAME AS
ABOVE
2
* Inverter omitted in MC14012B
7
VSS
3
VSS
5
4
SAME AS
ABOVE
14
VDD
VSS
9
10
SAME AS
ABOVE
11
12
SAME AS
ABOVE
VDD
13
7 VSS
VSS
MOTOROLA CMOS LOGIC DATA
MC14001B
13
TYPICAL B–SERIES GATE CHARACTERISTICS
N–CHANNEL DRAIN CURRENT
(SINK)
P–CHANNEL DRAIN CURRENT
(SOURCE)
– 10
5.0
ID , DRAIN CURRENT (mA)
ID , DRAIN CURRENT (mA)
– 9.0
4.0
TA = – 55°C
3.0
– 40°C
+ 85°C + 25°C
2.0
+ 125°C
1.0
– 8.0
TA = – 55°C
– 7.0
– 40°C
– 6.0
– 5.0
+ 25°C
+ 85°C
– 4.0
– 3.0
+ 125°C
– 2.0
– 1.0
0
0
1.0
2.0
3.0
4.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
0
5.0
0
Figure 2. VGS = 5.0 Vdc
– 50
– 45
TA = – 55°C
16
14
– 40°C
12
+ 25°C
+ 85°C
10
ID , DRAIN CURRENT (mA)
ID , DRAIN CURRENT (mA)
18
+ 125°C
8.0
6.0
– 40
– 35
– 25
+ 85°C
– 15
2.0
– 5.0
1.0
2.0 3.0 4.0 5.0
6.0
7.0 8.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
9.0
0
10
– 40°C
+ 25°C
– 20
– 10
0
TA = – 55°C
– 30
4.0
+ 125°C
0
Figure 4. VGS = 10 Vdc
– 100
45
– 90
40
– 80
35
TA = – 55°C
30
– 40°C
25
+ 25°C
ID , DRAIN CURRENT (mA)
ID , DRAIN CURRENT (mA)
– 1.0 – 2.0 – 3.0 – 4.0 – 5.0 – 6.0 – 7.0 – 8.0 – 9.0 – 10
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
Figure 5. VGS = – 10 Vdc
50
+ 85°C
20
+ 125°C
15
10
5.0
0
– 5.0
Figure 3. VGS = – 5.0 Vdc
20
0
– 1.0
– 2.0
– 3.0
– 4.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
– 70
– 60
TA = – 55°C
– 50
– 40°C
+ 25°C
– 40
+ 85°C
– 30
+ 125°C
– 20
– 10
0
2.0
4.0 6.0 8.0 10
12
14
16
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
Figure 6. VGS = 15 Vdc
18
20
0
0
– 2.0 – 4.0 – 6.0 – 8.0 – 10 – 12 – 14 – 16
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
– 18 – 20
Figure 7. VGS = – 15 Vdc
These typical curves are not guarantees, but are design aids.
Caution: The maximum rating for output current is 10 mA per pin.
MC14001B
14
MOTOROLA CMOS LOGIC DATA
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
V out , OUTPUT VOLTAGE (Vdc)
V out , OUTPUT VOLTAGE (Vdc)
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
5.0
4.0
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
3.0
2.0
1.0
0
0
1.0
2.0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
10
8.0
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
6.0
4.0
2.0
0
3.0
4.0
5.0
Vin, INPUT VOLTAGE (Vdc)
0
2.0
Figure 8. VDD = 5.0 Vdc
V out , OUTPUT VOLTAGE (Vdc)
6.0
8.0
10
Vin, INPUT VOLTAGE (Vdc)
Figure 9. VDD = 10 Vdc
DC NOISE MARGIN
16
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
14
12
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
10
8.0
6.0
4.0
2.0
0
4.0
0
2.0
4.0
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a
fixed voltage VO are given in the Electrical Characteristics
table. VIL and VIH are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
6.0
8.0
10
Vin, INPUT VOLTAGE (Vdc)
Figure 10. VDD = 15 Vdc
VDD
Vout
VDD
Vout
VO
VO
VO
VO
VDD
VDD
Vin
0
VIL
Vin
0
VIL
VIH
VIH
VSS = 0 VOLTS DC
(a) Inverting Function
(b) Non–Inverting Function
Figure 11. DC Noise Immunity
MOTOROLA CMOS LOGIC DATA
MC14001B
15
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
14
9
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
–T–
L
K
SEATING
PLANE
F
G
D
N
M
J
14 PL
0.25 (0.010)
M
T A
S
14 PL
0.25 (0.010)
M
T B
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
8
1
7
B
A
F
L
C
J
N
H
MC14001B
16
G
D
SEATING
PLANE
K
M
S
DIM
A
B
C
D
F
G
J
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.245
0.280
0.155
0.200
0.015
0.020
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15_
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.94
6.23
7.11
3.94
5.08
0.39
0.50
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15_
0.51
1.01
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
M
F
–T–
0.25 (0.010)
M
K
D 14 PL
M
T B
S
M
R X 45 _
C
SEATING
PLANE
B
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
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MOTOROLA CMOS LOGIC DATA
◊
*MC14001B/D*
MC14001B
MC14001B/D
17