LPC11U1x
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; 6 kB
SRAM; USB device; USART
Rev. 1 — 11 April 2011
Objective data sheet
1. General description
The LPC11U1x are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11U1x operate at CPU frequencies of up to 50 MHz.
Equipped with a highly flexible and configurable Full Speed USB 2.0 device controller, the
LPC11U1x brings unparalleled design flexibility and seamless integration to today’s
demanding connectivity solutions.
The peripheral complement of the LPC11U1x includes up to 32 kB of flash memory, 6 kB
of SRAM data memory, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485
USART with support for synchronous mode and smart card interface, two SSP interfaces,
four general purpose counter/timers, a 10-bit ADC, and up to 40 general purpose I/O pins.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 32 kB on-chip flash program memory.
Total of 6 kB SRAM data memory (4 kB main SRAM and 2 kB USB SRAM).
16 kB boot ROM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Debug options:
Standard JTAG test/debug interface.
Serial Wire Debug.
Boundary scan for simplified board testing.
Digital peripherals:
Up to 40 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
Up to 8 GPIO pins can beselected as edge and level sensitive interrupt sources.
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
LPC11U1X
Objective data sheet
Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
High-current source output driver (20 mA) on one pin (P0_7).
High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5).
Four general purpose counter/timers with a total of up to 5 capture inputs and 13
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
Analog peripherals:
10-bit ADC with input multiplexing among eight pins.
Serial interfaces:
USB 2.0 full-speed device controller.
USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
Two SSP controllers with FIFO and multi-protocol capabilities.
I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as
a system clock.
Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
A second, dedicated PLL is provided for USB.
Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Power control:
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Power profiles residing in boot ROM allow optimized performance and minimized
power consumption for any given application through one simple function call.
Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, watchdog interrupt, or USB port activity.
Processor wake-up from Deep power-down mode using one special function pin.
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
Power-On Reset (POR).
Brownout detect with four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Temperature range −40 °C to +85 °C.
Available as 48-pin LQFP, 48-pin TFBGA, and 33-pin HVQFN package.
Pin compatible to the LPC134x series.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
2 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
3. Applications
Consumer peripherals
Medical
Industrial control
Handheld scanners
USB audio devices
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC11U12FHN33/201
HVQFN33
plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 × 7 × 0.85 mm
n/a
LPC11U12FBD48/201
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
LPC11U13FBD48/201
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
LPC11U14FHN33/201
HVQFN33
plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 × 7 × 0.85 mm
n/a
LPC11U14FBD48/201
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
LPC11U14FET48/201
TFBGA48
plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 × 4.5 SOT1155-2
× 0.7 mm
4.1 Ordering options
Table 2.
Ordering options
Type number
LPC11U12FHN33/201
Flash
16 kB
SRAM
CPU
USB
Total
4 kB
2 kB
6 kB
USART
I2C-bus
FM+
SSP
USB
device
ADC
channels
GPIO
pins
1
1
2
1
8
26
LPC11U12FBD48/201
16 kB
4 kB
2 kB
6 kB
1
1
2
1
8
40
LPC11U13FBD48/201
24 kB
4 kB
2 kB
6 kB
1
1
2
1
8
40
LPC11U14FHN33/201
32 kB
4 kB
2 kB
6 kB
1
1
2
1
8
26
LPC11U14FBD48/201
32 kB
4 kB
2 kB
6 kB
1
1
2
1
8
40
LPC11U14FET48/201
32 kB
4 kB
2 kB
6 kB
1
1
2
1
8
40
LPC11U1X
Objective data sheet
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Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
3 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
SWD, JTAG
XTALIN XTALOUT
LPC11U12/13/14
RESET
SYSTEM OSCILLATOR
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
IRC, WDO
TEST/DEBUG
INTERFACE
BOD
POR
ARM
CORTEX-M0
PLL0
FLASH
16/24/32 kB
system bus
slave
GPIO ports 0/1
HIGH-SPEED
GPIO
CLKOUT
ROM
16 kB
SRAM
6 kB
slave
USB PLL
master
slave
slave
AHB-LITE BUS
slave
USB_DP
USB_DM
USB_VBUS
USB_FTOGGLE,
USB_CONNECT
USB DEVICE
CONTROLLER
slave
RXD
TXD
DCD(1), DSR(1), RI(1)
CTS, RTS, DTR
SCLK
CT16B0_MAT[1:0]
CT16B0_CAP0
CT16B1_MAT[1:0]
CT16B1_CAP0
CT32B0_MAT[3:0]
CT32B0_CAP0
CT32B1_MAT[3:0]
CT32B1_CAP[1:0](2)
AHB TO APB
BRIDGE
USART/
SMARTCARD INTERFACE
AD[7:0]
10-bit ADC
SCL, SDA
I2C-BUS
16-bit COUNTER/TIMER 0
SSP0
SCK0, SSEL0,
MISO0, MOSI0
SSP1
SCK1, SSEL1,
MISO1, MOSI1
16-bit COUNTER/TIMER 1
32-bit COUNTER/TIMER 0
IOCON
32-bit COUNTER/TIMER 1
SYSTEM CONTROL
WINDOWED WATCHDOG
TIMER
GPIO pins
GPIO INTERRUPTS
GPIO pins
GPIO GROUP0 INTERRUPTS
GPIO pins
GPIO GROUP1 INTERRUPTS
PMU
002aaf885
(1) Not available on HVQFN33 packages.
(2) CT32B1_CAP1 available in TFBGA48 only.
Fig 1.
Block diagram
LPC11U1X
Objective data sheet
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Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
4 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
PIO0_19/TXD/CT32B0_MAT1
PIO0_18/RXD/CT32B0_MAT0
PIO0_17/RTS/CT32B0_CAP0/SCLK
VDD
PIO1_15/DCD/CT16B0_MAT2/SCK1
PIO0_23/AD7
PIO0_16/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO0_15/AD4/CT32B1_MAT2
31
30
29
28
27
26
25
terminal 1
index area
32
6.1 Pinning
PIO1_19/DTR/SSEL1
1
24
TRST/PIO0_14/AD3/CT32B1_MAT1
RESET/PIO0_0
2
23
TDO/PIO0_13/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
3
22
TMS/PIO0_12/AD1/CT32B1_CAP0
XTALIN
4
21
TDI/PIO0_11/AD0/CT32B0_MAT3
XTALOUT
5
20
PIO0_22/AD6/CT16B1_MAT1/MISO1
VDD
6
19
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_20/CT16B1_CAP0
7
18
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_2/SSEL0/CT16B0_CAP0
8
17
PIO0_8/MISO0/CT16B0_MAT0
LPC11U1x
9
10
11
12
13
14
15
16
PIO0_3/USB_VBUS
PIO0_4/SCL
PIO0_5/SDA
PIO0_21/CT16B1_MAT0/MOSI1
USB_DM
USB_DP
PIO0_6/USB_CONNECT/SCK0
PIO0_7/CTS
33 VSS
002aaf888
Transparent top view
Fig 2.
Pin configuration (HVQFN33)
LPC11U1X
Objective data sheet
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Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
5 of 64
LPC11U1x
NXP Semiconductors
37 PIO1_14/DSR/CT16B0_MAT1/RXD
38 PIO1_22/RI/MOSI1
39 SWDIO/PIO0_15/AD4/CT32B1_MAT2
40 PIO0_16/AD5/CT32B1_MAT3/WAKEUP
41 VSS
42 PIO0_23/AD7
44 VDD
43 PIO1_15/DCD/CT16B0_MAT2/SCK1
45 PIO0_17/RTS/CT32B0_CAP0/SCLK
46 PIO0_18/RXD/CT32B0_MAT0
47 PIO0_19/TXD/CT32B0_MAT1
48 PIO1_16/RI/CT16B0_CAP0
32-bit ARM Cortex-M0 microcontroller
PIO1_25/CT32B0_MAT1
1
36 PIO1_13/DTR/CT16B0_MAT0/TXD
PIO1_19/DTR/SSEL1
2
35 TRST/PIO0_14/AD3/CT32B1_MAT1
RESET/PIO0_0
3
34 TDO/PIO0_13/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
4
33 TMS/PIO0_12/AD1/CT32B1_CAP0
VSS
5
32 TDI/PIO0_11/AD0/CT32B0_MAT3
XTALIN
6
XTALOUT
7
VDD
8
29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_20/CT16B1_CAP0
9
28 PIO0_9/MOSI0/CT16B0_MAT1
PIO0_2/SSEL0/CT16B0_CAP0 10
27 PIO0_8/MISO0/CT16B0_MAT0
30 PIO0_22/AD6/CT16B1_MAT1/MISO1
PIO1_28/CT32B0_CAP0/SCLK 24
PIO0_7/CTS 23
PIO0_6/USB_CONNECT/SCK0 22
PIO1_24/CT32B0_MAT0 21
USB_DP 20
USB_DM 19
PIO1_23/CT16B1_MAT1/SSEL1 18
PIO0_21/CT16B1_MAT0/MOSI1 17
PIO0_5/SDA 16
25 PIO1_31
PIO0_4/SCL 15
26 PIO1_21/DCD/MISO1
PIO1_27/CT32B0_MAT3/TXD 12
PIO0_3/USB_VBUS 14
PIO1_26/CT32B0_MAT2/RXD 11
PIO1_20/DSR/SCK1 13
Fig 3.
31 PIO1_29/SCK0/CT32B0_CAP1
LPC11U1x
002aaf884
Pin configuration (LQFP48)
LPC11U1X
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
6 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
ball A1
index area
LPC11U1x
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
002aag101
Transparent top view
Fig 4.
LPC11U1X
Objective data sheet
Pin configuration (TFBGA48)
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
7 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 3 shows all pins and their assigned digital or analog functions ordered by GPIO port
number. The default function after reset is listed first. All port pins have internal pull-up
resistors enabled after reset with the exception of the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register through which the digital or analog
function, pull-up/pull-down configuration, repeater, and open-drain modes can be
programmed.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 4 shows how peripheral functions are assigned to port pins.
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2/
USB_FTOGGLE
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3/USB_VBUS
LPC11U1X
Objective data sheet
Pin TFBGA48
Symbol
Pin LQFP48
Pin description
Pin HVQFN33
Table 3.
2
3
C1
3
8
9
4
10
14
C2
F1
H2
Reset
state
Type
Description
I; PU
I
RESET — External reset input with 20 ns glitch
filter. A LOW-going pulse as short as 50 ns on
this pin resets the device, causing I/O ports and
peripherals to take on their default states, and
processor execution to begin at address 0. This
pin also serves as the debug select input. LOW
level selects the JTAG boundary scan. HIGH
level selects the ARM SWD debug mode.
-
I/O
PIO0_0 — General purpose digital input/output
pin.
I; PU
I/O
PIO0_1 — General purpose digital input/output
pin. A LOW level on this pin during reset starts
the ISP command handler or the USB device
enumeration.
-
O
CLKOUT — Clockout pin.
-
O
CT32B0_MAT2 — Match output 2 for 32-bit
timer 0.
-
O
USB_FTOGGLE — USB 1 ms Start-of-Frame
signal.
I; PU
I/O
PIO0_2 — General purpose digital input/output
pin.
-
I/O
SSEL0 — Slave select for SSP0.
-
I
CT16B0_CAP0 — Capture input 0 for 16-bit
timer 0.
I; PU
I/O
PIO0_3 — General purpose digital input/output
pin. A LOW level on this pin during reset starts
the ISP command handler, a HIGH level starts
the USB device enumeration.
-
I
USB_VBUS — Monitors the presence of USB
bus power.
[1]
[2]
[3]
[3]
[3]
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Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
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LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/USB_CONNECT/
SCK0
PIO0_7/CTS
PIO0_8/MISO0/
CT16B0_MAT0
PIO0_9/MOSI0/
CT16B0_MAT1
SWCLK/PIO0_10/SCK0/
CT16B0_MAT2
TDI/PIO0_11/AD0/
CT32B0_MAT3
LPC11U1X
Objective data sheet
Pin TFBGA48
Symbol
Pin LQFP48
Pin description
Pin HVQFN33
Table 3.
10
15
G3
11
15
16
17
18
19
21
16
22
23
27
28
29
32
H3
H6
Reset
state
[4]
[4]
[3]
G7
F8
[3]
E7
D8
Description
I; IA
I/O
PIO0_4 — General purpose digital input/output
pin (open-drain).
-
I/O
SCL — I2C-bus clock input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
I; IA
I/O
PIO0_5 — General purpose digital input/output
pin (open-drain).
-
I/O
SDA — I2C-bus data input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
I; PU
I/O
PIO0_6 — General purpose digital input/output
pin.
-
O
USB_CONNECT — Signal used to switch an
external 1.5 kΩ resistor under software control.
Used with the SoftConnect USB feature.
-
I/O
SCK0 — Serial clock for SSP0.
I; PU
I/O
PIO0_7 — General purpose digital input/output
pin (high-current output driver).
-
I
CTS — Clear To Send input for USART.
I; PU
I/O
PIO0_8 — General purpose digital input/output
pin.
-
I/O
MISO0 — Master In Slave Out for SSP0.
-
O
CT16B0_MAT0 — Match output 0 for 16-bit
timer 0.
I; PU
I/O
PIO0_9 — General purpose digital input/output
pin.
-
I/O
MOSI0 — Master Out Slave In for SSP0.
-
O
CT16B0_MAT1 — Match output 1 for 16-bit
timer 0.
I; PU
I
SWCLK — Serial wire clock and test clock TCK
for JTAG interface.
-
I/O
PIO0_10 — General purpose digital
input/output pin.
-
O
SCK0 — Serial clock for SSP0.
-
O
CT16B0_MAT2 — Match output 2 for 16-bit
timer 0.
I; PU
I
TDI — Test Data In for JTAG interface.
-
I/O
PIO0_11 — General purpose digital input/output
pin.
-
I
AD0 — A/D converter, input 0.
-
O
CT32B0_MAT3 — Match output 3 for 32-bit
timer 0.
[1]
[5]
F7
Type
[3]
[3]
[6]
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Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
9 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
TMS/PIO0_12/AD1/
CT32B1_CAP0
TDO/PIO0_13/AD2/
CT32B1_MAT0
TRST/PIO0_14/AD3/
CT32B1_MAT1
SWDIO/PIO0_15/AD4/
CT32B1_MAT2
PIO0_16/AD5/
CT32B1_MAT3/WAKEUP
PIO0_17/RTS/
CT32B0_CAP0/SCLK
LPC11U1X
Objective data sheet
Pin TFBGA48
Symbol
Pin LQFP48
Pin description
Pin HVQFN33
Table 3.
22
33
C7
23
24
25
26
30
34
35
39
40
45
C8
B7
B6
A6
A3
Reset
state
Type
Description
I; PU
I
TMS — Test Mode Select for JTAG interface.
-
I/O
PIO_12 — General purpose digital input/output
pin.
-
I
AD1 — A/D converter, input 1.
-
I
CT32B1_CAP0 — Capture input 0 for 32-bit
timer 1.
I; PU
O
TDO — Test Data Out for JTAG interface.
-
I/O
PIO0_13 — General purpose digital
input/output pin.
-
I
AD2 — A/D converter, input 2.
-
O
CT32B1_MAT0 — Match output 0 for 32-bit
timer 1.
I; PU
I
TRST — Test Reset for JTAG interface.
-
I/O
PIO0_14 — General purpose digital
input/output pin.
-
I
AD3 — A/D converter, input 3.
-
O
CT32B1_MAT1 — Match output 1 for 32-bit
timer 1.
I; PU
I/O
SWDIO — Serial wire debug input/output.
-
I/O
PIO0_15 — General purpose digital
input/output pin.
-
I
AD4 — A/D converter, input 4.
-
O
CT32B1_MAT2 — Match output 2 for 32-bit
timer 1.
I; PU
I/O
PIO0_16 — General purpose digital
input/output pin.
-
I
AD5 — A/D converter, input 5.
-
O
CT32B1_MAT3 — Match output 3 for 32-bit
timer 1.
-
I
WAKEUP — Deep power-down mode wake-up
pin with 20 ns glitch filter. This pin must be
pulled HIGH externally to enter Deep
power-down mode and pulled LOW to exit Deep
power-down mode. A LOW-going pulse as short
as 50 ns wakes up the part.
I; PU
I/O
PIO0_17 — General purpose digital
input/output pin.
-
O
RTS — Request To Send output for USART.
-
I
CT32B0_CAP0 — Capture input 0 for 32-bit
timer 0.
-
I/O
SCLK — Serial clock input/output for USART in
synchronous mode.
[1]
[6]
[6]
[6]
[6]
[6]
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
10 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
PIO0_18/RXD/
CT32B0_MAT0
PIO0_19/TXD/
CT32B0_MAT1
PIO0_20/CT16B1_CAP0
PIO0_21/CT16B1_MAT0/
MOSI1
PIO0_22/AD6/
CT16B1_MAT1/MISO1
PIO0_23/AD7
PIO1_0/CT32B1_MAT0
PIO1_1/CT32B1_MAT1
PIO1_2/CT32B1_MAT2
LPC11U1X
Objective data sheet
Pin TFBGA48
Symbol
Pin LQFP48
Pin description
Pin HVQFN33
Table 3.
31
46
B3
32
7
12
20
27
-
-
-
47
9
17
30
42
-
-
-
B2
F2
G4
E8
Reset
state
[3]
[3]
[3]
[3]
[6]
[6]
-
[3]
-
Description
I; PU
I/O
PIO0_18 — General purpose digital
input/output pin.
-
I
RXD — Receiver input for USART.
-
O
CT32B0_MAT0 — Match output 0 for 32-bit
timer 0.
I; PU
I/O
PIO0_19 — General purpose digital
input/output pin.
-
O
TXD — Transmitter output for USART.
-
O
CT32B0_MAT1 — Match output 1 for 32-bit
timer 0.
I; PU
I/O
PIO0_20 — General purpose digital
input/output pin.
-
I
CT16B1_CAP0 — Capture input 0 for 16-bit
timer 1.
I; PU
I/O
PIO0_21 — General purpose digital
input/output pin.
-
O
CT16B1_MAT0 — Match output 0 for 16-bit
timer 1.
-
I/O
MOSI1 — Master Out Slave In for SSP1.
I; PU
I/O
PIO0_22 — General purpose digital
input/output pin.
-
I
AD6 — A/D converter, input 6.
-
O
CT16B1_MAT1 — Match output 1 for 16-bit
timer 1.
-
I/O
MISO1 — Master In Slave Out for SSP1.
I; PU
I/O
PIO0_23 — General purpose digital
input/output pin.
-
I
AD7 — A/D converter, input 7.
I; PU
I/O
PIO1_0 — General purpose digital input/output
pin.
-
O
CT32B1_MAT0 — Match output 0 for 32-bit
timer 1.
I; PU
I/O
PIO1_1 — General purpose digital input/output
pin.
-
O
CT32B1_MAT1 — Match output 1 for 32-bit
timer 1.
I; PU
I/O
PIO1_2 — General purpose digital input/output
pin.
-
O
CT32B1_MAT2 — Match output 2 for 32-bit
timer 1.
[1]
A5
-
Type
[3]
[3]
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LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
PIO1_3/CT32B1_MAT3
PIO1_4/CT32B1_CAP0
PIO1_5/CT32B1_CAP1
Pin TFBGA48
Symbol
Pin LQFP48
Pin description
Pin HVQFN33
Table 3.
-
-
-
-
-
-
-
-
H8
Reset
state
Type
Description
I; PU
I/O
PIO1_3 — General purpose digital input/output
pin.
-
O
CT32B1_MAT3 — Match output 3 for 32-bit
timer 1.
I; PU
I/O
PIO1_4 — General purpose digital input/output
pin.
-
I
CT32B1_CAP0 — Capture input 0 for 32-bit
timer 1.
I; PU
I/O
PIO1_5 — General purpose digital input/output
pin.
-
I
CT32B1_CAP1 — Capture input 1 for 32-bit
timer 1.
[1]
[3]
[3]
[3]
PIO1_6
-
-
-
[3]
I; PU
I/O
PIO1_6 — General purpose digital input/output
pin.
PIO1_7
-
-
-
[3]
I; PU
I/O
PIO1_7 — General purpose digital input/output
pin.
PIO1_8
-
-
-
[3]
I; PU
I/O
PIO1_8 — General purpose digital input/output
pin.
PIO1_9
-
-
-
[3]
I; PU
I/O
PIO1_9 — General purpose digital input/output
pin.
PIO1_10
-
-
-
[3]
I; PU
I/O
PIO1_10 — General purpose digital
input/output pin.
PIO1_11
-
-
-
[3]
I; PU
I/O
PIO1_11 — General purpose digital input/output
pin.
PIO1_12
-
-
-
[3]
I; PU
I/O
PIO1_12 — General purpose digital
input/output pin.
PIO1_13/DTR/
CT16B0_MAT0/TXD
-
36
B8
[3]
I; PU
I/O
PIO1_13 — General purpose digital
input/output pin.
-
O
DTR — Data Terminal Ready output for USART.
-
O
CT16B0_MAT0 — Match output 0 for 16-bit
timer 0.
-
O
TXD — Transmitter output for USART.
I; PU
I/O
PIO1_14 — General purpose digital
input/output pin.
-
I
DSR — Data Set Ready input for USART.
-
O
CT16B0_MAT1 — Match output 1 for 16-bit
timer 0.
-
I
RXD — Receiver input for USART.
PIO1_14/DSR/
CT16B0_MAT1/RXD
LPC11U1X
Objective data sheet
-
37
A8
[3]
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12 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
PIO1_15/DCD/
CT16B0_MAT2/SCK1
PIO1_16/RI/
CT16B0_CAP0
PIO1_17/CT16B0_CAP1/
RXD
PIO1_18/CT16B1_CAP1/
TXD
PIO1_19/DTR/SSEL1
PIO1_20/DSR/SCK1
PIO1_21/DCD/MISO1
PIO1_22/RI/MOSI1
LPC11U1X
Objective data sheet
Pin TFBGA48
Symbol
Pin LQFP48
Pin description
Pin HVQFN33
Table 3.
28
43
A4
-
-
-
1
-
-
-
48
-
-
2
13
26
38
A2
-
-
B1
H1
G8
A7
Reset
state
Type
Description
I/O
PIO1_15 — General purpose digital
input/output pin.
I
DCD — Data Carrier Detect input for USART.
-
O
CT16B0_MAT2 — Match output 2 for 16-bit
timer 0.
-
I/O
SCK1 — Serial clock for SSP1.
I; PU
I/O
PIO1_16 — General purpose digital
input/output pin.
[1]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
I; PU
-
I
RI — Ring Indicator input for USART.
-
I
CT16B0_CAP0 — Capture input 0 for 16-bit
timer 0.
I; PU
I/O
PIO1_17 — General purpose digital
input/output pin.
-
I
CT16B0_CAP1 — Capture input 1 for 16-bit
timer 0.
-
I
RXD — Receiver input for USART.
I; PU
I/O
PIO1_18 — General purpose digital
input/output pin.
-
I
CT16B1_CAP1 — Capture input 1 for 16-bit
timer 1.
-
O
TXD — Transmitter output for USART.
I; PU
I/O
PIO1_19 — General purpose digital
input/output pin.
-
O
DTR — Data Terminal Ready output for USART.
-
I/O
SSEL1 — Slave select for SSP1.
I; PU
I/O
PIO1_20 — General purpose digital
input/output pin.
-
I
DSR — Data Set Ready input for USART.
-
I/O
SCK1 — Serial clock for SSP1.
I; PU
I/O
PIO1_21 — General purpose digital
input/output pin.
-
I
DCD — Data Carrier Detect input for USART.
-
I/O
MISO1 — Master In Slave Out for SSP1.
I; PU
I/O
PIO1_22 — General purpose digital
input/output pin.
-
I
RI — Ring Indicator input for USART.
-
I/O
MOSI1 — Master Out Slave In for SSP1.
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LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
PIO1_23/CT16B1_MAT1/
SSEL1
PIO1_24/CT32B0_MAT0
PIO1_25/CT32B0_MAT1
PIO1_26/CT32B0_MAT2/
RXD
PIO1_27/CT32B0_MAT3/
TXD
PIO1_28/CT32B0_CAP0/
SCLK
PIO1_29/SCK0/
CT32B0_CAP1
Pin TFBGA48
Symbol
Pin LQFP48
Pin description
Pin HVQFN33
Table 3.
-
18
H4
-
-
-
-
-
-
21
1
11
12
24
31
G6
A1
G2
G1
H7
D7
Reset
state
Type
Description
I; PU
I/O
PIO1_23 — General purpose digital
input/output pin.
-
O
CT16B1_MAT1 — Match output 1 for 16-bit
timer 1.
-
I/O
SSEL1 — Slave select for SSP1.
I; PU
I/O
PIO1_24 — General purpose digital
input/output pin.
-
O
CT32B0_MAT0 — Match output 0 for 32-bit
timer 0.
I; PU
I/O
PIO1_25 — General purpose digital
input/output pin.
-
O
CT32B0_MAT1 — Match output 1 for 32-bit
timer 0.
I; PU
I/O
PIO1_26 — General purpose digital
input/output pin.
-
O
CT32B0_MAT2 — Match output 2 for 32-bit
timer 0.
-
I
RXD — Receiver input for USART.
I; PU
I/O
PIO1_27 — General purpose digital
input/output pin.
-
O
CT32B0_MAT3 — Match output 3 for 32-bit
timer 0.
-
O
TXD — Transmitter output for USART.
I; PU
I/O
PIO1_28 — General purpose digital
input/output pin.
-
I
CT32B0_CAP0 — Capture input 0 for 32-bit
timer 0.
-
I/O
SCLK — Serial clock input/output for USART in
synchronous mode.
I; PU
I/O
PIO1_29 — General purpose digital
input/output pin.
-
I/O
SCK0 — Serial clock for SSP0.
-
I
CT32B0_CAP1 — Capture input 1 for 32-bit
timer 0.
[1]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
PIO1_31
-
25
-
[3]
I; PU
I/O
PIO1_31 — General purpose digital
input/output pin.
USB_DM
13
19
G5
[7]
F
-
USB_DM — USB bidirectional D− line.
USB_DP
14
20
H5
[7]
F
-
USB_DP — USB bidirectional D+ line.
D1
[8][9]
-
-
Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not
exceed 1.8 V.
XTALIN
LPC11U1X
Objective data sheet
4
6
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LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin description
Description
Pin TFBGA48
Type
Pin LQFP48
Reset
state
Pin HVQFN33
Symbol
XTALOUT
5
7
E1
-
-
Output from the oscillator amplifier.
VDD
6;
29
8;
44
B4,
E2
-
-
Supply voltage to the internal regulator, the
external rail, and the ADC. Also used as the
ADC reference voltage.
VSS
33
5;
41
B5,
D2
-
-
Ground.
[1]
[8][9]
[1]
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
[2]
See Figure 31 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
[3]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 30).
[4]
I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.
[5]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 30);
includes high-current output driver.
[6]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 30); includes digital
input glitch filter.
[7]
Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
[8]
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
[9]
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
To select a port pin for a peripheral function from Table 4, program the FUNC bits in the
port pin’s IOCON register with this function. The user must ensure that the assignment of
a function to a port pin is unambiguous. Only the debug functions for JTAG and SWD are
selected by default in their corresponding IOCON registers. All other functions must be
programmed in the IOCON block before they can be used. For details see the LPC11U1x
user manual.
Table 4.
LPC11U1X
Objective data sheet
Multiplexing of peripheral functions
Peripheral
Function
Type Default Available on ports
USART
RXD
I
no
PIO0_18
PIO1_14
PIO1_17
PIO1_26
TXD
O
no
PIO0_19
PIO1_13
PIO1_18
PIO1_27
CTS
I
no
PIO0_7
-
-
-
RTS
O
no
PIO0_17
-
-
-
DTR
O
no
PIO1_13
PIO1_19
-
-
DSR
I
no
PIO1_14
PIO1_20
-
-
DCD
I
no
PIO1_15
PIO1_21
-
-
RI
I
no
PIO1_16
PIO1_22
-
-
SCLK
I/O
no
PIO0_17
PIO1_28
-
-
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LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
Peripheral
Function
Type Default Available on ports
SSP0
SCK0
I/O
no
PIO0_6
PIO0_10
PIO1_29
SSEL0
I/O
no
PIO0_2
-
-
-
MISO0
I/O
no
PIO0_8
-
-
-
SSP1
CT16B0
CT16B1
CT32B0
CT32B1
ADC
USB
CLKOUT
LPC11U1X
Objective data sheet
Multiplexing of peripheral functions
MOSI0
I/O
no
PIO0_9
-
-
-
SCK1
I/O
no
PIO1_15
PIO1_20
-
-
SSEL1
I/O
no
PIO1_19
PIO1_23
-
-
MISO1
I/O
no
PIO0_22
PIO1_21
-
-
MOSI1
I/O
no
PIO0_21
PIO1_22
-
-
CT16B0_CAP0
I
no
PIO0_2
PIO1_16
-
-
CT16B0_CAP1
I
no
PIO1_17
-
-
-
CT16B0_MAT0
O
no
PIO0_8
PIO1_13
-
-
CT16B0_MAT1
O
no
PIO0_9
PIO1_14
-
-
CT16B0_MAT2
O
no
PIO0_10
PIO1_15
-
-
CT16B1_CAP0
I
no
PIO0_20
-
-
-
CT16B1_CAP1
I
no
PIO1_18
-
-
-
CT16B1_MAT0
O
no
PIO0_21
-
-
-
CT16B1_MAT1
O
no
PIO0_22
PIO1_23
-
-
CT32B0_CAP0
I
no
PIO0_17
PIO1_28
-
-
CT32B0_CAP1
I
no
PIO1_29
-
-
-
CT32B0_MAT0
O
no
PIO0_18
PIO1_24
-
-
CT32B0_MAT1
O
no
PIO0_19
PIO1_25
-
-
CT32B0_MAT2
O
no
PIO0_1
PIO1_26
-
-
CT32B0_MAT3
O
no
PIO0_11
PIO1_27
-
-
CT32B1_CAP0
I
no
PIO0_12
PIO1_4
-
-
CT32B1_CAP1
I
no
PIO1_5
-
-
-
CT32B1_MAT0
O
no
PIO0_13
PIO1_0
-
-
CT32B1_MAT1
O
no
PIO0_14
PIO1_1
-
-
CT32B1_MAT2
O
no
PIO0_15
PIO1_2
-
-
CT32B1_MAT3
O
no
PIO0_16
PIO1_3
-
-
AD0
I
no
PIO0_11
-
-
-
AD1
I
no
PIO0_12
-
-
-
AD2
I
no
PIO0_13
-
-
-
AD3
I
no
PIO0_14
-
-
-
AD4
I
no
PIO0_15
-
-
-
AD5
I
no
PIO0_16
-
-
-
AD6
I
no
PIO0_22
-
-
-
AD7
I
no
PIO0_23
-
-
-
USB_VBUS
I
no
PIO0_3
-
-
-
USB_FTOGGLE
O
no
PIO0_1
-
-
-
USB_CONNECT
O
no
PIO0_6
-
-
-
CLKOUT
O
no
PIO0_1
-
-
-
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16 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
Multiplexing of peripheral functions
Peripheral
Function
Type Default Available on ports
JTAG
TDI
I
yes
PIO0_11
-
-
-
TMS
I
yes
PIO0_12
-
-
-
TDO
O
yes
PIO0_13
-
-
-
TRST
I
yes
PIO0_14
-
-
-
TCK
I
yes
PIO0_10
-
-
-
SWCLK
I
yes
PIO0_10
-
-
-
SWDIO
I/O
yes
PIO0_15
-
-
-
SWD
7. Functional description
7.1 Memory map
The LPC11U1x incorporates several distinct memory regions, shown in the following
figures. Figure 5 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
LPC11U1X
Objective data sheet
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© NXP B.V. 2011. All rights reserved.
17 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
LPC11U12/13/14
4 GB
0xFFFF FFFF
reserved
0xE010 0000
private peripheral bus
0xE000 0000
reserved
APB peripherals
0x5000 4000
GPIO
25 - 31 reserved
0x5000 0000
reserved
0x4008 4000
USB
23
GPIO GROUP1 INT
22
SSP1
20 - 21 reserved
0x4000 0000
19
GPIO interrupts
18
system control
0x2000 4800
17
IOCON
0x2000 4000
16
15
SSP0
flash controller
14
PMU
reserved
2 kB USB RAM
reserved
0.5 GB
GPIO GROUP0 INT
0x4008 0000
APB peripherals
1 GB
24
0x2000 0000
reserved
0x4008 0000
0x4006 4000
0x4006 0000
0x4005 C000
0x4005 8000
0x4004 C000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
10 - 13 reserved
0x1FFF 4000
16 kB boot ROM
0x4002 8000
0x1FFF 0000
9
reserved
8
reserved
0x4002 0000
7
ADC
0x4001 C000
6
32-bit counter/timer 1
0x4001 8000
0x1000 1000
5
32-bit counter/timer 0
0x4001 4000
0x1000 0000
4
16-bit counter/timer 1
0x4001 0000
3
16-bit counter/timer 0
0x4000 C000
2
USART/SMART CARD
0x4000 8000
1
0
WWDT
0x4000 4000
I2C-bus
0x4000 0000
reserved
4 kB SRAM
reserved
0x0000 8000
32 kB on-chip flash (LPC11U14)
0x0000 6000
24 kB on-chip flash (LPC11U13)
0x0000 4000
16 kB on-chip flash (LPC11U12)
0x4002 4000
0x0000 00C0
active interrupt vectors
0x0000 0000
0x0000 0000
0 GB
002aaf891
Fig 5.
LPC11U1x memory map
7.2 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.2.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC11U1x, the NVIC supports 24 vectored interrupts.
LPC11U1X
Objective data sheet
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18 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
• Four programmable interrupt priority levels, with hardware priority level masking.
• Software interrupt generation.
7.2.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
7.3 IOCON block
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.4 General Purpose Input/Output GPIO
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC11U1x use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
• Entire port value can be written in one instruction.
Any GPIO pin providing a digital function can be programmed to generate an interrupt on
a level, a rising or falling edge, or both.
7.4.1 Features
•
•
•
•
GPIO pins can be configured as input or output by software.
All GPIO pins default to inputs with interrupt disabled at reset.
Pin registers allow pins to be sensed and set individually.
Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
• Port interrupts can be triggered by any pin or pins in each port.
7.5 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC11U1x USB interface is a device controller with on-chip PHY for device functions.
LPC11U1X
Objective data sheet
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© NXP B.V. 2011. All rights reserved.
19 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
7.5.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
7.5.1.1
Features
•
•
•
•
•
•
Dedicated USB PLL available.
Fully compliant with USB 2.0 specification (full speed).
Supports 5 physical (10 logical) endpoints including one control endpoint.
Single and double buffering supported.
Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
Supports wake-up from Deep-sleep mode and Power-down mode on USB activity
and remote wake-up.
• Supports SoftConnect.
7.6 USART
The LPC11U1x contains one USART.
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.
The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.6.1 Features
•
•
•
•
•
Maximum USART data bit rate of 3.125 Mbit/s.
16-byte receive and transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
•
•
•
•
LPC11U1X
Objective data sheet
Support for RS-485/9-bit mode.
Support for modem control.
Support for synchronous mode.
Includes smart card interface.
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7.7 SSP serial I/O controller
The SSP controllers are capable of operation on a SSP, 4-wire SSI, or Microwire bus. It
can interact with multiple masters and slaves on the bus. Only a single master and a
single slave can communicate on the bus during a given data transfer. The SSP supports
full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.7.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
•
•
•
•
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
7.8 I2C-bus serial I/O controller
The LPC11U1x contain one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.8.1 Features
• The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
•
•
•
•
•
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
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7.9 10-bit ADC
The LPC11U1x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.9.1 Features
•
•
•
•
•
•
•
•
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to VDD.
10-bit conversion time ≥ 2.44 μs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
7.10 General purpose external event counter/timers
The LPC11U1x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.10.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
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7.11 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.12 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.12.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•
•
•
•
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 224 × 4) in
multiples of Tcy(WDCLK) × 4.
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). This gives a wide range of potential timing choices of
watchdog operation under different power conditions.
7.13 Clocking and power control
7.13.1 Integrated oscillators
The LPC11U1x include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for
more than one purpose as required in a particular application.
Following reset, the LPC11U1x will operate from the internal RC oscillator until switched
by software. This allows systems to operate without any external crystal and the
bootloader code to operate at a known frequency.
See Figure 6 for an overview of the LPC11U1x clock generation.
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SYSTEM CLOCK
DIVIDER
CPU, system control,
PMU
system clock
n
memories,
peripheral clocks
SYSAHBCLKCTRLn
(AHB clock enable)
IRC oscillator
main clock
SSP0 PERIPHERAL
CLOCK DIVIDER
SSP0
USART PERIPHERAL
CLOCK DIVIDER
UART
SSP1 PERIPHERAL
CLOCK DIVIDER
SSP1
USB 48 MHz CLOCK
DIVIDER
USB
CLKOUT PIN CLOCK
DIVIDER
CLKOUT pin
watchdog oscillator
MAINCLKSEL
(main clock select)
IRC oscillator
SYSTEM PLL
system oscillator
SYSPLLCLKSEL
(system PLL clock select)
USB PLL
system oscillator
USBPLLCLKSEL
(USB clock select)
USBUEN
(USB clock update enable)
IRC oscillator
system oscillator
watchdog oscillator
CLKOUTUEN
(CLKOUT update enable)
IRC oscillator
WDT
watchdog oscillator
WDCLKSEL
(WDT clock select)
002aaf892
Fig 6.
LPC11U1x clocking generation block diagram
7.13.1.1
Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz.
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11U1x
use the IRC as the clock source. Software may later switch to one of the other available
clock sources.
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7.13.1.2
System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL. On the LPC11U1x, the system oscillator must be used to provide the clock
source to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
7.13.1.3
Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is ±40 % (see also Table 13).
7.13.2 System PLL and USB PLL
The LPC11U1x contain a system PLL and a dedicated PLL for generating the 48 MHz
USB clock. The system and USB PLLs are identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output
frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100 μs.
7.13.3 Clock output
The LPC11U1x features a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.13.4 Wake-up process
The LPC11U1x begin operation at power-up and when awakened from Deep power-down
mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation
to resume quickly. If the main oscillator or the PLL is needed by the application, software
will need to enable these features and wait for them to stabilize before they are used as a
clock source.
7.13.5 Power control
The LPC11U1x support a variety of power control features. There are four special modes
of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate may also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, a register is provided for shutting down the clocks to individual
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on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic
power use in any peripherals that are not required for the application. Selected
peripherals have their own clock divider which provides even better power control.
7.13.5.1
Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11U1x for one of the following power modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
7.13.5.2
Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.13.5.3
Deep-sleep mode
In Deep-sleep mode, the LPC11U1x is in Sleep-mode and all peripheral clocks and all
clock sources are off with the exception of the IRC. The IRC output is disabled unless the
IRC is selected as input to the watchdog timer. In addition all analog blocks are shut down
and the flash is in stand-by mode. In Deep-sleep mode, the user has the option to keep
the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD
protection.
The LPC11U1x can wake up from Deep-sleep mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.
Deep-sleep mode saves power and allows for short wake-up times.
7.13.5.4
Power-down mode
In Power-down mode, the LPC11U1x is in Sleep-mode and all peripheral clocks and all
clock sources are off with the exception of watchdog oscillator if selected. In addition all
analog blocks and the flash are shut down. In Power-down mode, the user has the option
to keep the BOD circuit running for BOD protection.
The LPC11U1x can wake up from Power-down mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.
Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
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7.13.5.5
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC11U1x can wake up from Deep power-down mode via the
WAKEUP pin.
The LPC11U1x can be prevented from entering Deep power-down mode by setting a lock
bit in the PMU block. Locking out Deep power-down mode enables the user to always
keep the watchdog timer or the BOD running.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
7.13.6 System control
7.13.6.1
Reset
Reset has four sources on the LPC11U1x: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
An external pull-up resistor is required on the RESET pin if Deep power-down mode is
used.
7.13.6.2
Brownout detection
The LPC11U1x includes four levels for monitoring the voltage on the VDD pin. If this
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
7.13.6.3
Code security (Code Read Protection - CRP)
This feature of the LPC11U1x allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC11U1x user manual.
There are three levels of Code Read Protection:
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1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11U1x user manual.
7.13.6.4
APB interface
The APB peripherals are located on one APB bus.
7.13.6.5
AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
7.13.6.6
External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
7.14 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11U1x is in reset.
Remark: Boundary scan operations should not be started until 250 μs after POR, and the
test TAP should be reset after the boundary scan. Boundary scan is not affected by Code
Read Protection.
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8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage (core and
external rail)
1.8
3.6
V
VI
input voltage
5 V tolerant I/O pins; only valid
when the VDD supply voltage is
present
[2]
−0.5
+5.5
V
IDD
supply current
per supply pin
[3]
ISS
-
100
mA
ground current
per ground pin
[3]
-
100
mA
Ilatch
I/O latch-up current
−(0.5VDD) < VI < (1.5VDD);
-
100
mA
Tstg
storage temperature
−65
+150
°C
Tj(max)
maximum junction temperature
-
150
°C
Ptot(pack)
total power dissipation (per
package)
based on package heat transfer, not
device power consumption
-
1.5
W
VESD
electrostatic discharge voltage
human body model; all pins
−6500
+6500
V
Tj < 125 °C
[1]
[4]
[5]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2]
Including voltage on outputs in 3-state mode.
[3]
The peak current is limited to 25 times the corresponding maximum current.
[4]
Dependent on package type.
[5]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
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9. Static characteristics
Table 6.
Static characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol Parameter
VDD
supply voltage (core
and external rail)
IDD
supply current
Conditions
Min
Typ[1]
Max
Unit
1.8
3.3
3.6
V
-
2
-
mA
-
8
-
mA
-
1
-
mA
-
360
-
μA
-
2
-
μA
-
220
-
nA
Active mode; VDD = 3.3 V;
Tamb = 25 °C; code
while(1){}
executed from flash;
system clock = 12 MHz
[2][3][4]
[5][6][7]
system clock = 50 MHz
[3][4][5]
[6][7][8]
Sleep mode;
VDD = 3.3 V; Tamb = 25 °C;
[2][3][4]
[5][6][7]
system clock = 12 MHz
Deep-sleep mode; VDD = 3.3 V;
Tamb = 25 °C
[3][6]
Power-down mode; VDD = 3.3 V;
Tamb = 25 °C
Deep power-down mode;
VDD = 3.3 V; Tamb = 25 °C
[9]
Standard port pins, RESET
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
0.5
10
nA
IIH
HIGH-level input
current
VI = VDD; on-chip pull-down resistor
disabled
-
0.5
10
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
0.5
10
nA
VI
input voltage
pin configured to provide a digital
function
0
-
5.0
V
0
-
VDD
V
0.7VDD
-
-
V
[10][11]
[12]
VO
output voltage
VIH
HIGH-level input
voltage
VIL
LOW-level input voltage
-
-
0.3VDD
V
Vhys
hysteresis voltage
-
0.4
-
V
VOH
HIGH-level output
voltage
2.0 V ≤ VDD ≤ 3.6 V; IOH = −4 mA
VDD − 0.4 -
-
V
1.8 V ≤ VDD < 2.0 V; IOH = −3 mA
VDD − 0.4 -
-
V
LOW-level output
voltage
2.0 V ≤ VDD ≤ 3.6 V; IOL = 4 mA
-
-
0.4
V
1.8 V ≤ VDD < 2.0 V; IOL = 3 mA
-
-
0.4
V
HIGH-level output
current
VOH = VDD − 0.4 V;
−4
-
-
mA
−3
-
-
mA
VOL
IOH
output active
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
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Table 6.
Static characteristics …continued
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
IOL
VOL = 0.4 V
4
-
-
mA
LOW-level output
current
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
3
-
-
mA
-
-
−45
mA
-
-
50
mA
IOHS
HIGH-level short-circuit VOH = 0 V
output current
[13]
IOLS
LOW-level short-circuit
output current
VOL = VDD
[13]
Ipd
pull-down current
VI = 5 V
10
50
150
μA
Ipu
pull-up current
VI = 0 V;
−15
−50
−85
μA
−10
−50
−85
μA
0
0
0
μA
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
VDD < VI < 5 V
High-drive output pin (PIO0_7)
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
0.5
10
nA
IIH
HIGH-level input
current
VI = VDD; on-chip pull-down resistor
disabled
-
0.5
10
nA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD; on-chip
pull-up/down resistors disabled
-
0.5
10
nA
VI
input voltage
pin configured to provide a digital
function
0
-
5.0
V
0
-
VDD
V
0.7VDD
-
-
V
[10][11]
[12]
VO
output voltage
VIH
HIGH-level input
voltage
VIL
LOW-level input voltage
-
-
0.3VDD
V
Vhys
hysteresis voltage
0.4
-
-
V
VOH
HIGH-level output
voltage
2.5 V ≤ VDD ≤ 3.6 V; IOH = −20 mA
VDD − 0.4 -
-
V
1.8 V ≤ VDD < 2.5 V; IOH = −12 mA
VDD − 0.4 -
-
V
LOW-level output
voltage
2.0 V ≤ VDD ≤ 3.6 V; IOL = 4 mA
-
-
0.4
V
1.8 V ≤ VDD < 2.0 V; IOL = 3 mA
-
-
0.4
V
IOH
HIGH-level output
current
VOH = VDD − 0.4 V;
2.5 V ≤ VDD ≤ 3.6 V
20
-
-
mA
1.8 V ≤ VDD < 2.5 V
12
-
-
mA
IOL
LOW-level output
current
VOL = 0.4 V
4
-
-
mA
3
-
-
mA
IOLS
LOW-level short-circuit
output current
VOL = VDD
-
-
50
mA
Ipd
pull-down current
VI = 5 V
10
50
150
μA
Ipu
pull-up current
VI = 0 V
−15
−50
−85
μA
−10
−50
−85
μA
0
0
0
μA
VOL
output active
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
[13]
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
VDD < VI < 5 V
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Table 6.
Static characteristics …continued
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol Parameter
I2C-bus
Conditions
Min
Typ[1]
Max
Unit
pins (PIO0_4 and PIO0_5)
VIH
HIGH-level input
voltage
0.7VDD
-
-
V
VIL
LOW-level input voltage
-
-
0.3VDD
V
Vhys
hysteresis voltage
-
0.05VDD
-
V
3.5
-
-
mA
3
-
-
20
-
-
16
-
-
-
2
4
μA
-
10
22
μA
LOW-level output
current
IOL
I2C-bus
VOL = 0.4 V;
pins configured
as standard mode pins
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
LOW-level output
current
IOL
I2C-bus
VOL = 0.4 V;
pins configured
as Fast-mode Plus pins
mA
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
input leakage current
ILI
[14]
VI = VDD
VI = 5 V
Oscillator pins
Vi(xtal)
crystal input voltage
−0.5
1.8
1.95
V
Vo(xtal)
crystal output voltage
−0.5
1.8
1.95
V
-
-
±10
μA
-
-
5.25
V
USB pins
IOZ
OFF-state output
current
VBUS
bus supply voltage
VDI
differential input
sensitivity voltage
|(D+) − (D−)|
0.2
-
-
V
VCM
differential common
mode voltage range
includes VDI range
0.8
-
2.5
V
Vth(rs)se
single-ended receiver
switching threshold
voltage
0.8
-
2.0
V
VOL
LOW-level output
voltage
for low-/full-speed;
RL of 1.5 kΩ to 3.6 V
-
-
0.18
V
VOH
HIGH-level output
voltage
driven; for low-/full-speed;
RL of 15 kΩ to GND
2.8
-
3.5
V
Ctrans
transceiver capacitance pin to GND
-
-
20
pF
ZDRV
driver output
with 33 Ω series resistor; steady state
impedance for driver
drive
which is not high-speed
capable
36
-
44.1
Ω
[1]
0 V < VI < 3.3 V
[15]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[2]
IRC enabled; system oscillator disabled; system PLL disabled.
[3]
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4]
BOD disabled.
[5]
All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the syscon block.
[6]
USB_DP and USB_DM pulled LOW externally.
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[7]
Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[8]
IRC disabled; system oscillator enabled; system PLL enabled.
[9]
WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[10] Including voltage on outputs in 3-state mode.
[11] VDD supply voltage must be present.
[12] 3-state outputs go into 3-state mode in Deep power-down mode.
[13] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[14] To VSS.
[15] Includes external resistors of 33 Ω ± 1 % on USB_DP and USB_DM.
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Table 7.
ADC static characteristics
Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol
Parameter
VIA
analog input voltage
0
-
VDD
V
Cia
analog input capacitance
-
-
1
pF
ED
differential linearity error
[1][2]
-
-
±1
LSB
integral non-linearity
[3]
-
-
±1.5
LSB
EO
offset error
[4]
-
-
±3.5
LSB
EG
gain error
[5]
-
-
0.6
%
ET
absolute error
[6]
-
-
±4
LSB
Rvsi
voltage source interface
resistance
-
-
40
kΩ
Ri
input resistance
-
-
2.5
MΩ
EL(adj)
Conditions
Min
[7][8]
[1]
The ADC is monotonic, there are no missing codes.
Typ
Max
Unit
[2]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7.
[3]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 7.
[4]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 7.
[5]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 7.
[6]
The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 7.
[7]
Tamb = 25 °C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF.
[8]
Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs × Cia).
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offset
error
EO
gain
error
EG
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
(5)
4
(4)
3
(3)
2
1 LSB
(ideal)
1
0
1
2
3
4
5
6
7
1018
1019
1020
1021
1022
1023
1024
VIA (LSBideal)
offset error
EO
1 LSB =
VDD − VSS
1024
002aaf426
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 7.
ADC characteristics
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9.1 BOD static characteristics
Table 8.
BOD static characteristics[1]
Tamb = 25 °C.
Symbol
Parameter
Conditions
Vth
threshold voltage
interrupt level 0
Min
Typ
Max
Unit
assertion
-
1.65
-
V
de-assertion
-
1.80
-
V
assertion
-
2.22
-
V
de-assertion
-
2.35
-
V
assertion
-
2.52
-
V
de-assertion
-
2.66
-
V
assertion
-
2.80
-
V
de-assertion
-
2.90
-
V
interrupt level 1
interrupt level 2
interrupt level 3
reset level 0
assertion
-
1.46
-
V
de-assertion
-
1.63
-
V
assertion
-
2.06
-
V
de-assertion
-
2.15
-
V
assertion
-
2.35
-
V
de-assertion
-
2.43
-
V
assertion
-
2.63
-
V
de-assertion
-
2.71
-
V
reset level 1
reset level 2
reset level 3
[1]
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see
LPC11U1x user manual.
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC11U1x user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.
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001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: Tamb = 25 °C; active mode entered executing code while(1){} from flash;
internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled;
all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all
peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally.
Fig 8.
Typical supply current versus regulator supply voltage VDD in active mode
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal
pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all
peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally.
Fig 9.
LPC11U1X
Objective data sheet
Typical supply current versus temperature in Active mode
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001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system
oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled; USB_DP
and USB_DM pulled LOW externally.
Fig 10. Typical supply current versus temperature in Sleep mode
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register; PDSLEEPCFG = <tbd>; USB_DP and USB_DM pulled LOW externally.
Fig 11. Typical supply current versus temperature in Deep-sleep mode
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32-bit ARM Cortex-M0 microcontroller
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register; PDSLEEPCFG = <tbd>; USB_DP and USB_DM pulled LOW externally.
Fig 12. Typical supply current versus temperature in Power-down mode
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Fig 13. Typical supply current versus temperature in Deep power-down mode
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Table 9.
Power consumption for individual analog and digital blocks
The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and
the peripheral block disabled in the SYSAHBCLKCTRL or PDRUNCFG (for analog blocks) registers. All other blocks are
disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 °C. Unless noted otherwise,
the system oscillator and PLL are running in both measurements.
Typical supply current per peripheral
in mA for different system clock
frequencies
Notes
n/a
12 MHz
<tbd>
MHz
<tbd>
MHz
IRC
<tbd>
-
-
-
System oscillator running; PLL off; independent of main clock
frequency.
System oscillator
at 12 MHz
<tbd>
-
-
-
IRC running; PLL off; independent of main clock frequency.
Watchdog
oscillator at
500 kHz/2
<tbd>
-
-
-
System oscillator running; PLL off; independent of main clock
frequency.
BOD
<tbd>
-
-
-
Independent of main clock frequency.
Main PLL
-
<tbd>
-
-
USB PLL
-
<tbd>
<tbd>
<tbd>
ADC
-
<tbd>
<tbd>
<tbd>
CLKOUT
-
<tbd>
<tbd>
<tbd>
CT16B0
-
<tbd>
<tbd>
<tbd>
CT16B1
-
<tbd>
<tbd>
<tbd>
CT32B0
-
<tbd>
<tbd>
<tbd>
CT32B1
-
<tbd>
<tbd>
<tbd>
GPIO
-
<tbd>
<tbd>
<tbd>
IOCON
-
<tbd>
<tbd>
<tbd>
I2C
-
<tbd>
<tbd>
<tbd>
ROM
-
<tbd>
<tbd>
<tbd>
SSP0
-
<tbd>
<tbd>
<tbd>
SSP1
-
<tbd>
<tbd>
<tbd>
USART
-
<tbd>
<tbd>
<tbd>
Main clock divided by 4 in the CLKOUTDIV register.
GPIO pins configured as outputs and set to LOW. Direction
and pin state are maintained if the GPIO is disabled in the
SYSAHBCLKCFG register.
WDT
-
<tbd>
<tbd>
<tbd>
Main clock selected as clock source for the WDT.
USB
-
-
<tbd>
-
Main clock selected as clock source for the USB. USB_DP
and USB_DM pulled LOW externally.
USB
-
<tbd>
<tbd>
<tbd>
Dedicated USB PLL selected as cock source for the USB.
USB_DP and USB_DM pulled LOW externally.
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9.3 Electrical pin characteristics
002aae990
3.6
VOH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
10
20
30
40
50
60
IOH (mA)
Conditions: VDD = 3.3 V; on pin PIO0_7.
Fig 14. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH.
002aaf019
60
T = 85 °C
25 °C
−40 °C
IOL
(mA)
40
20
0
0
0.2
0.4
0.6
VOL (V)
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.
Fig 15. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL
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002aae991
15
IOL
(mA)
T = 85 °C
25 °C
−40 °C
10
5
0
0
0.2
0.4
0.6
VOL (V)
Conditions: VDD = 3.3 V; standard port pins and PIO0_7.
Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL
002aae992
3.6
VOH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
8
16
24
IOH (mA)
Conditions: VDD = 3.3 V; standard port pins.
Fig 17. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
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002aae988
10
Ipu
(μA)
−10
−30
T = 85 °C
25 °C
−40 °C
−50
−70
0
1
2
3
4
5
VI (V)
Conditions: VDD = 3.3 V; standard port pins.
Fig 18. Typical pull-up current Ipu versus input voltage VI
002aae989
80
T = 85 °C
25 °C
−40 °C
Ipd
(μA)
60
40
20
0
0
1
2
3
4
5
VI (V)
Conditions: VDD = 3.3 V; standard port pins.
Fig 19. Typical pull-down current Ipd versus input voltage VI
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10. Dynamic characteristics
10.1 Flash memory
Table 10. Flash characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Nendu
endurance
tret
retention time
Conditions
Min
[1]
ter
erase time
tprog
programming time
Typ
Max
Unit
10000
100000
-
cycles
powered
10
-
-
years
unpowered
20
-
-
years
sector or multiple
consecutive sectors
95
100
105
ms
0.95
1
1.05
ms
[2]
[1]
Number of program/erase cycles.
[2]
Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
10.2 External clock
Table 11. Dynamic characteristic: external clock
Tamb = −40 °C to +85 °C; VDD over specified ranges.[1]
Min
Typ[2]
Max
Unit
oscillator frequency
1
-
25
MHz
Tcy(clk)
clock cycle time
40
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk) × 0.4
-
-
ns
tCLCX
clock LOW time
Tcy(clk) × 0.4
-
-
ns
tCLCH
clock rise time
-
-
5
ns
tCHCL
clock fall time
-
-
5
ns
Symbol
Parameter
fosc
Conditions
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 20. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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10.3 Internal oscillators
Table 12. Dynamic characteristics: IRC
Tamb = −40 °C to +85 °C; 2.7 V ≤ VDD ≤ 3.6 V[1].
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc(RC)
internal RC oscillator
frequency
-
<tbd>
12
<tbd>
MHz
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
001aac984
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X (X)
Conditions: Frequency values are typical values. 12 MHz ± <tbd> % accuracy is guaranteed for
2.7 V ≤ VDD ≤ 3.6 V and Tamb = −40 °C to +85 °C. Variations between parts may cause the IRC to
fall outside the 12 MHz ± <tbd> % accuracy specification for voltages below 2.7 V.
Fig 21. Internal RC oscillator frequency versus temperature
LPC11U1X
Objective data sheet
Table 13.
Dynamic characteristics: Watchdog oscillator
Symbol
Parameter
Conditions
fosc(int)
internal oscillator
frequency
DIVSEL = 0x1F, FREQSEL = 0x1
in the WDTOSCCTRL register;
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
Min
Typ[1] Max Unit
[2][3]
-
7.8
-
kHz
[2][3]
-
1700
-
kHz
[1]
Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2]
The typical frequency spread over processing and temperature (Tamb = −40 °C to +85 °C) is ±40 %.
[3]
See the LPC11U1x user manual.
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10.4 I/O pins
Table 14. Dynamic characteristics: I/O pins[1]
Tamb = −40 °C to +85 °C; 3.0 V ≤ VDD ≤ 3.6 V.
[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
pin configured as output
3.0
-
5.0
ns
tf
fall time
pin configured as output
2.5
-
5.0
ns
Applies to standard port pins and RESET pin.
10.5 I2C-bus
Table 15. Dynamic characteristic: I2C-bus pins[1]
Tamb = −40 °C to +85 °C.[2]
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock
frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
of both SDA and SCL
signals
-
300
ns
Fast-mode
20 + 0.1 × Cb
300
ns
Fast-mode Plus
-
120
ns
Standard-mode
4.7
-
μs
Fast-mode
1.3
-
μs
Fast-mode Plus
0.5
-
μs
Standard-mode
4.0
-
μs
Fast-mode
0.6
-
μs
Fast-mode Plus
0.26
-
μs
Standard-mode
0
-
μs
Fast-mode
0
-
μs
Fast-mode Plus
0
-
μs
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
fall time
tf
[4][5][6][7]
Standard-mode
tLOW
tHIGH
tHD;DAT
tSU;DAT
LOW period of the
SCL clock
HIGH period of the
SCL clock
data hold time
data set-up time
[3][4][8]
[9][10]
[1]
See the I2C-bus specification UM10204 for details.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
[3]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[5]
Cb = total capacitance of one bus line in pF.
[6]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[7]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
LPC11U1X
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[8]
The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
tf
SDA
tSU;DAT
70 %
30 %
70 %
30 %
tHD;DAT
tf
70 %
30 %
SCL
tVD;DAT
tHIGH
70 %
30 %
70 %
30 %
70 %
30 %
tLOW
S
1 / fSCL
002aaf425
Fig 22. I2C-bus pins clock timing
LPC11U1X
Objective data sheet
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10.6 SSP interface
Table 16.
Dynamic characteristics: SSP pins in SPI mode
Symbol
Parameter
Conditions
Min
Max
Unit
clock cycle time
when only receiving
[1]
<tbd>
-
ns
when only transmitting
[1]
<tbd>
-
ns
in SPI mode;
[2]
<tbd>
-
ns
[2]
<tbd>
-
ns
in SPI mode
[2]
<tbd>
-
ns
in SPI mode
[2]
-
<tbd>
ns
in SPI mode
[2]
<tbd>
-
ns
<tbd>
-
ns
in SPI mode
[3][4]
<tbd>
-
ns
<tbd> × Tcy(PCLK) +
<tbd>
-
ns
SSP master
Tcy(clk)
data set-up time
tDS
2.4 V ≤ VDD ≤ 3.6 V
2.0 V ≤ VDD < 2.4 V
data hold time
tDH
tv(Q)
th(Q)
data output valid time
data output hold time
SSP slave
Tcy(PCLK)
PCLK cycle time
data set-up time
tDS
tDH
data hold time
in SPI mode
[3][4]
tv(Q)
data output valid time
in SPI mode
[3][4]
-
<tbd> × Tcy(PCLK) +
<tbd>
ns
th(Q)
data output hold time
in SPI mode
[3][4]
-
<tbd> × Tcy(PCLK) +
<tbd>
ns
[1]
Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
Tamb = −40 °C to 85 °C.
[3]
Tcy(clk) = 12 × Tcy(PCLK).
[4]
Tamb = 25 °C; VDD = 3.3 V.
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Tcy(clk)
tclk(H)
tclk(L)
SCK (CPOL = 0)
SCK (CPOL = 1)
tv(Q)
th(Q)
DATA VALID
MOSI
DATA VALID
tDS
DATA VALID
MISO
tDH
DATA VALID
th(Q)
tv(Q)
MOSI
DATA VALID
DATA VALID
tDH
tDS
MISO
CPHA = 1
DATA VALID
CPHA = 0
DATA VALID
002aae829
Fig 23. SSP master timing in SPI mode
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Tcy(clk)
tclk(H)
tclk(L)
tDS
tDH
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
DATA VALID
DATA VALID
tv(Q)
MISO
th(Q)
DATA VALID
DATA VALID
tDS
MOSI
DATA VALID
tDH
DATA VALID
tv(Q)
MISO
DATA VALID
CPHA = 1
th(Q)
CPHA = 0
DATA VALID
002aae830
Fig 24. SSP slave timing in SPI mode
LPC11U1X
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10.7 USB interface
Table 17. Dynamic characteristics: USB pins (full-speed)
CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
10 % to 90 %
<tbd>
-
<tbd>
ns
tf
fall time
10 % to 90 %
<tbd>
-
<tbd>
ns
tFRFM
differential rise and fall time
matching
tr / tf
-
-
<tbd>
%
VCRS
output signal crossover voltage
<tbd>
-
<tbd>
V
tFEOPT
source SE0 interval of EOP
see Figure 25
<tbd>
-
<tbd>
ns
tFDEOP
source jitter for differential transition
to SE0 transition
see Figure 25
<tbd>
-
<tbd>
ns
tJR1
receiver jitter to next transition
<tbd>
-
<tbd>
ns
tJR2
receiver jitter for paired transitions
10 % to 90 %
<tbd>
-
<tbd>
ns
tEOPR1
EOP width at receiver
must reject as
EOP; see
Figure 25
[1]
<tbd>
-
-
ns
tEOPR2
EOP width at receiver
must accept as
EOP; see
Figure 25
[1]
<tbd>
-
-
ns
[1]
Characterized but not implemented as production test. Guaranteed by design.
TPERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: tFEOPT
differential data to
SE0/EOP skew
n × TPERIOD + tFDEOP
receiver EOP width: tEOPR1, tEOPR2
002aab561
Fig 25. Differential data-to-EOP transition skew and EOP width
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11. Application information
11.1 Suggested USB interface solutions
VDD
USB_CONNECT
LPC11U1x
soft-connect switch
R1
1.5 kΩ
USB_VBUS
USB_DP RS = 33 Ω
USB_DM
USB-B
connector
RS = 33 Ω
VSS
002aaf893
Fig 26. USB interface on a self-powered device
VDD
LPC11U1x
R1
1.5 kΩ
USB_VBUS
USB-B
connector
USB_DP RS = 33 Ω
USB_DM RS = 33 Ω
VSS
002aaf894
Fig 27. USB interface on a bus-powered device
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV(RMS) is needed.
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LPC1xxx
XTALIN
Ci
100 pF
Cg
002aae788
Fig 28. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 28), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 29 and in
Table 18 and Table 19. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 29 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.
LPC1xxx
L
XTALIN
XTALOUT
=
CL
CP
XTAL
RS
CX2
CX1
002aaf424
Fig 29. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 18.
LPC11U1X
Objective data sheet
Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
1 MHz - 5 MHz
10 pF
< 300 Ω
18 pF, 18 pF
20 pF
< 300 Ω
39 pF, 39 pF
30 pF
< 300 Ω
57 pF, 57 pF
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Table 18.
Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
5 MHz - 10 MHz
10 pF
< 300 Ω
18 pF, 18 pF
20 pF
< 200 Ω
39 pF, 39 pF
30 pF
< 100 Ω
57 pF, 57 pF
10 pF
< 160 Ω
18 pF, 18 pF
20 pF
< 60 Ω
39 pF, 39 pF
10 pF
< 80 Ω
18 pF, 18 pF
10 MHz - 15 MHz
15 MHz - 20 MHz
Table 19.
Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
15 MHz - 20 MHz
10 pF
< 180 Ω
18 pF, 18 pF
20 pF
< 100 Ω
39 pF, 39 pF
20 MHz - 25 MHz
10 pF
< 160 Ω
18 pF, 18 pF
20 pF
< 80 Ω
39 pF, 39 pF
11.3 XTAL Printed-Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
LPC11U1X
Objective data sheet
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11.4 Standard I/O pad configuration
Figure 30 shows the possible pin modes for standard I/O pins with analog input function:
•
•
•
•
•
Digital output driver
Digital input: Pull-up enabled/disabled
Digital input: Pull-down enabled/disabled
Digital input: Repeater mode enabled/disabled
Analog input
VDD
ESD
output enable
pin configured
as digital output
driver
output
PIN
ESD
VDD
VSS
weak
pull-up
pull-up enable
pin configured
as digital input
weak
pull-down
repeater mode
enable
pull-down enable
data input
select analog input
pin configured
as analog input
analog input
002aaf304
Fig 30. Standard I/O pad configuration
LPC11U1X
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11.5 Reset pad configuration
VDD
VDD
VDD
Rpu
ESD
20 ns RC
GLITCH FILTER
reset
PIN
ESD
VSS
002aaf274
Fig 31. Reset pad configuration
11.6 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 7:
• The ADC input trace must be short and as close as possible to the LPC11U1x chip.
• The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
• Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
• To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
LPC11U1X
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12. Package outline
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
A
B
D
terminal 1
index area
A
E
A1
c
detail X
e1
e
9
16
C
C A B
C
v
w
b
y
y1 C
L
8
17
e
e2
Eh
33
1
terminal 1
index area
24
32
X
25
Dh
0
2.5
scale
Dimensions
Unit
mm
5 mm
A(1)
A1
b
max 1.00 0.05 0.35
nom 0.85 0.02 0.28
min 0.80 0.00 0.23
c
D(1)
Dh
E(1)
0.2
7.1
7.0
6.9
4.85
4.70
4.55
7.1
7.0
6.9
Eh
e
e1
e2
L
0.75
4.85
4.70 0.65 4.55 4.55 0.60
0.45
4.55
v
0.1
w
y
0.05 0.08
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
References
IEC
JEDEC
JEITA
---
hvqfn33_po
European
projection
Issue date
09-03-17
09-03-23
Fig 32. Package outline HVQFN33
LPC11U1X
Objective data sheet
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LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
1
detail X
12
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
o
0
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 33. Package outline LQFP48 (SOT313-2)
LPC11U1X
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TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm
B
D
SOT1155-2
A
ball A1
index area
E
A
A2
A1
detail X
e1
C
e
C A B
C
Øv
Øw
1/2 e b
y1 C
y
H
e
G
F
E
e2
D
1/2 e
C
B
A
ball A1
index area
1
2
3
4
5
6
7
8
X
0
5 mm
scale
Dimensions
Unit
mm
A
A1
A2
b
max 1.10 0.30 0.80 0.35
nom 0.95 0.25 0.70 0.30
min 0.85 0.20 0.65 0.25
D
E
e
e1
e2
4.6
4.5
4.4
4.6
4.5
4.4
0.5
3.5
3.5
v
w
y
0.15 0.05 0.08
y1
0.1
sot1155-2_po
Outline
version
SOT1155-2
References
IEC
JEDEC
JEITA
European
projection
Issue date
11-01-18
11-03-01
---
Fig 34. Package outline TFBGA48 (SOT1155-2)
LPC11U1X
Objective data sheet
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13. Abbreviations
Table 20.
LPC11U1X
Objective data sheet
Abbreviations
Acronym
Description
A/D
Analog-to-Digital
ADC
Analog-to-Digital Converter
AHB
Advanced High-performance Bus
APB
Advanced Peripheral Bus
BOD
BrownOut Detection
GPIO
General Purpose Input/Output
JTAG
Joint Action Test Group
PLL
Phase-Locked Loop
RC
Resistor-Capacitor
SPI
Serial Peripheral Interface
SSI
Serial Synchronous Interface
SSP
Synchronous Serial Port
TAP
Test Access Port
USART
Universal Synchronous Asynchronous Receiver/Transmitter
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14. Revision history
Table 21.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
LPC11U1X v.1
20110411
Objective data sheet
-
-
LPC11U1X
Objective data sheet
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
LPC11U1X
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
62 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
LPC11U1X
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 April 2011
© NXP B.V. 2011. All rights reserved.
63 of 64
LPC11U1x
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
17. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional description . . . . . . . . . . . . . . . . . . 17
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Nested Vectored Interrupt Controller
(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19
7.3
IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.4
General Purpose Input/Output GPIO . . . . . . . 19
7.4.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5
USB interface . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5.1
Full-speed USB device controller . . . . . . . . . . 20
7.5.1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.6
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.6.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.7
SSP serial I/O controller . . . . . . . . . . . . . . . . . 21
7.7.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.8
I2C-bus serial I/O controller . . . . . . . . . . . . . . 21
7.8.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.9
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.9.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.10
General purpose external event
counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.10.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.11
System tick timer . . . . . . . . . . . . . . . . . . . . . . 23
7.12
Windowed WatchDog Timer
(WWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.12.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.13
Clocking and power control . . . . . . . . . . . . . . 23
7.13.1
Integrated oscillators . . . . . . . . . . . . . . . . . . . 23
7.13.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 24
7.13.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 25
7.13.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 25
7.13.2
System PLL and USB PLL . . . . . . . . . . . . . . . 25
7.13.3
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.13.4
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 25
7.13.5
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.13.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.13.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.13.5.3
7.13.5.4
7.13.5.5
7.13.6
7.13.6.1
7.13.6.2
7.13.6.3
Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . .
Power-down mode . . . . . . . . . . . . . . . . . . . . .
Deep power-down mode . . . . . . . . . . . . . . . .
System control . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Brownout detection . . . . . . . . . . . . . . . . . . . .
Code security
(Code Read Protection - CRP) . . . . . . . . . . .
7.13.6.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . .
7.13.6.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13.6.6 External interrupt inputs . . . . . . . . . . . . . . . . .
7.14
Emulation and debugging . . . . . . . . . . . . . . .
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
9
Static characteristics . . . . . . . . . . . . . . . . . . .
9.1
BOD static characteristics . . . . . . . . . . . . . . .
9.2
Power consumption . . . . . . . . . . . . . . . . . . .
9.3
Electrical pin characteristics. . . . . . . . . . . . . .
10
Dynamic characteristics. . . . . . . . . . . . . . . . .
10.1
Flash memory . . . . . . . . . . . . . . . . . . . . . . . .
10.2
External clock. . . . . . . . . . . . . . . . . . . . . . . . .
10.3
Internal oscillators . . . . . . . . . . . . . . . . . . . . .
10.4
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6
SSP interface . . . . . . . . . . . . . . . . . . . . . . . . .
10.7
USB interface. . . . . . . . . . . . . . . . . . . . . . . . .
11
Application information . . . . . . . . . . . . . . . . .
11.1
Suggested USB interface solutions . . . . . . . .
11.2
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3
XTAL Printed-Circuit Board (PCB) layout
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4
Standard I/O pad configuration . . . . . . . . . . .
11.5
Reset pad configuration . . . . . . . . . . . . . . . . .
11.6
ADC usage notes. . . . . . . . . . . . . . . . . . . . . .
12
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
14
Revision history . . . . . . . . . . . . . . . . . . . . . . .
15
Legal information . . . . . . . . . . . . . . . . . . . . . .
15.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
15.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
15.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Contact information . . . . . . . . . . . . . . . . . . . .
17
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
27
27
27
27
28
28
28
28
29
30
36
36
41
44
44
44
45
46
46
48
51
52
52
52
54
55
56
56
57
60
61
62
62
62
62
63
63
64
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 April 2011
Document identifier: LPC11U1X