AD AD7225KN Lc2mos quad 8-bit dac with separate reference input Datasheet

LC2MOS Quad 8-Bit DAC
with Separate Reference Inputs
AD7225
FUNCTIONAL BLOCK DIAGRAM
VREF A VREFB VREF C VREFD
DB7
DATA
(8-BIT)
DB0
WR
A1
A2
DATA BUS
Four 8-bit DACs with output amplifiers
Separate reference input for each DAC
Microprocessor compatible with double-buffered inputs
Simultaneous update of all 4 outputs
Operates with single or dual supplies
Extended temperature range operation
No user trims required
Skinny 24-lead PDIP, CERDIP, SOIC, and SSOP packages
28-lead PLCC package
VDD
INPUT
LATCH A
DAC
LATCH A
DAC A
A
VOUTA
INPUT
LATCH B
DAC
LATCH B
DAC B
B
VOUTB
INPUT
LATCH C
DAC
LATCH C
DAC C
C
VOUTC
INPUT
LATCH D
DAC
LATCH D
DAC D
D
VOUTD
AD7225
CONTROL
LOGIC
LDAC
VSS
AGND DGND
00986-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7225 contains four 8-bit voltage output digital-toanalog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. Each DAC has a separate
reference input terminal. No external trims are required to
achieve full specified performance for the part.
1.
DACs and Amplifiers on CMOS Chip.
The single-chip design of four 8-bit DACs and amplifiers
allows a dramatic reduction in board space requirements
and offers increased reliability in systems using multiple
converters. Its pinout is aimed at optimizing board layout
with all analog inputs and outputs at one end of the
package and all digital inputs at the other.
2.
Single- or Dual-Supply Operation.
The voltage-mode configuration of the AD7225 allows
single-supply operation. The part can also be operated with
dual supplies, giving enhanced performance for some
parameters.
3.
Versatile Interface Logic.
The AD7225 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. The double-buffered
interface allows simultaneous update of the four outputs.
4.
Separate Reference Input for Each DAC.
The AD7225 offers great flexibility in dealing with input
signals, with a separate reference input provided for each
DAC and each reference having variable input voltage
capability.
The double-buffered interface logic consists of two 8-bit
registers per channel—an input register and a DAC register.
Control Input A0 and Control Input A1 determine which input
register is loaded when WR goes low. Only the data held in the
DAC registers determines the analog outputs of the converters.
The double-buffering allows simultaneous update of all four
outputs under control of LDAC. All logic inputs are TTL and
CMOS (5 V) level compatible, and the control logic is speed
compatible with most 8-bit microprocessors.
Specified performance is guaranteed for input reference
voltages from 2 V to 12.5 V when using dual supplies. The part
is also specified for single-supply operation using a reference of
10 V. Each output buffer amplifier is capable of developing 10 V
across a 2 kΩ load.
The AD7225 is fabricated on an all ion-implanted, high speed,
linear-compatible CMOS (LC2MOS) process, which is
specifically developed to integrate high speed digital logic
circuits and precision analog circuitry on the same chip.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD7225
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Inputs Section ...................................................................9
Functional Block Diagram .............................................................. 1
Interface Logic Information .......................................................... 10
General Description ......................................................................... 1
Ground Management and Layout ................................................ 11
Product Highlights ........................................................................... 1
Specification Ranges ...................................................................... 12
Revision History ............................................................................... 2
Unipolar Output Operation .......................................................... 13
Specifications..................................................................................... 3
Bipolar Output Operation ............................................................. 14
Single Supply ................................................................................. 4
AGND Bias ...................................................................................... 15
Absolute Maximum Ratings............................................................ 5
AC Reference Signal ....................................................................... 16
ESD Caution .................................................................................. 5
Applications Information .............................................................. 17
Pin Configurations and Function Descriptions ........................... 6
Programmable Transversal Filter ............................................. 17
Typical Performance Characteristics ............................................. 7
Digital Word Multiplication ..................................................... 18
Terminology ...................................................................................... 8
Microprocesser Interface ............................................................... 19
Circuit Information .......................................................................... 9
VSS Generation ................................................................................ 20
Digital-to-Analog Section ........................................................... 9
Outline Dimensions ....................................................................... 21
Op Amp Section ........................................................................... 9
Ordering Guide .......................................................................... 23
REVISION HISTORY
3/10—Rev. B to Rev. C
Updated Format .................................................................. Universal
Deleted 28-Terminal Leadless Ceramic Chip Carrier
Package ................................................................................. Universal
Added 24-Lead SSOP Package .......................................... Universal
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Pin Configurations and Function Descriptions
Section ................................................................................................ 6
Added Table 4; Renumbered Sequentially .................................... 6
Changes to Specification Ranges section .................................... 12
Changes to Programmable Transversal Filter Section and
Figure 21 .......................................................................................... 17
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 23
Rev. C | Page 2 of 24
AD7225
SPECIFICATIONS
VDD = 11.4 V to 16.5 V, VSS = −5 V ± 10%; AGND = DGND = 0 V; VREFx = +2 V to (VDD − 4 V) 1, unless otherwise noted. All specifications
TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale Temperature Coefficient
Zero Code Error
Zero Code Error Temperature Coefficient
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance3
Channel-to-Channel Isolation3
AC Feedthrough3
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance3
Input Coding
DYNAMIC PERFORMANCE
Voltage Output Slew Rate3
Voltage Output Settling Time3
Digital Feedthrough3
Digital Crosstalk3
Minimum Load Resistance
POWER SUPPLIES
VDD Range
IDD
ISS
SWITCHING CHARACTERISTICS3, 4
t1
t2
t3
t4
t5
t6
K, B
Versions2
L, C
Versions2
Unit
8
±2
±1
±1
±1
±5
±30
±30
8
±1
±1/2
±1
±1/2
±5
±20
±30
Bits
LSB max
LSB max
LSB max
LSB max
ppm/°C typ
mV max
μV/°C typ
2 to (VDD − 4)
11
50
60
−70
2 to (VDD − 4)
11
50
60
−70
V min to V max
kΩ min
pF max
dB min
dB max
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
V min
V max
μA max
pF max
2.5
4
50
50
2
2.5
4
50
50
2
V/μs min
μs max
nV sec typ
nV sec typ
kΩ min
VREF = 10 V; settling time to ±½ LSB
Code transition all 0s to all 1s
Code transition all 0s to all 1s
VOUT = 10 V
11.4/16.5
10
9
11.4/16.5
10
9
V min to V max
mA max
mA max
For specified performance
Outputs unloaded; VIN = VINL or VINH
Outputs unloaded; VIN = VINL or VINH
50
0
0
50
0
50
50
0
0
50
0
50
ns min
ns min
ns min
ns min
ns min
ns min
Write pulse width
Address to write setup time
Address to write hold time
Data valid to write setup time
Data valid to write hold time
Load DAC pulse width
Maximum possible reference voltage.
Temperature range is as follows for all versions: −40°C to +85°C.
Sample tested at 25°C to ensure compliance.
4
Switching characteristics apply for single-supply and dual-supply operation.
1
2
3
Rev. C | Page 3 of 24
Conditions/Comments
VDD = 15 V ± 5%, VREF = 10 V
Guaranteed monotonic
VDD = 14 V to 16.5 V, VREF = 10 V
Occurs when each DAC is loaded with all 1s
VREF = 10 V p-p sine wave at 10 kHz
VREF = 10 V p-p sine wave at 10 kHz
VIN = 0 V or VDD
AD7225
SINGLE SUPPLY
VDD = 15 V ± 5%; VSS = AGND = DGND = 0 V; VREFx = 10 V, unless otherwise noted. All specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error2
Differential Nonlinearity2
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance3
Channel-to-Channel Isolation2, 3
AC Feedthrough2, 3
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance3
Input Coding
DYNAMIC PERFORMANCE
Voltage Output Slew Rate3
Voltage Output Settling Time3
Digital Feedthrough2, 3
Digital Crosstalk2, 3
Minimum Load Resistance
POWER SUPPLIES
VDD Range
IDD
SWITCHING CHARACTERISTICS3
t1
t2
t3
t4
t5
t6
1
2
3
K, B Versions1
L, C Versions1
Unit
Conditions/Comments
8
±2
±1
8
±1
±1
Bits
LSB max
LSB max
Guaranteed monotonic
2 to (VDD − 4)
11
50
60
−70
2 to (VDD − 4)
11
50
60
−70
V min to V max
kΩ min
pF max
dB min
dB max
Occurs when each DAC is loaded with all 1s
VREF = 10 V p-p sine wave at 10 kHz
VREF = 10 V p-p sine wave at 10 kHz
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
V min
V max
μA max
pF max
2
4
10
10
2
2
4
10
10
2
V/μs min
μs max
nV sec typ
nV sec typ
kΩ min
Code transition all 0s to all 1s
Code transition all 0s to all 1s
VOUT = 10 V
14.25/15.75
10
14.25/15.75
10
V min to V max
mA max
For specified performance
Outputs unloaded; VIN = VINL or VINH
50
0
0
50
0
50
50
0
0
50
0
50
ns min
ns min
ns min
ns min
ns min
ns min
Write pulse width
Address to write setup time
Address to write hold time
Data valid to write setup time
Data valid to write hold time
Load DAC pulse width
Temperature range is as follows for all versions: −40°C to +85°C.
Sample tested at 25°C to ensure compliance.
Switching characteristics apply for single-supply and dual-supply operation.
Rev. C | Page 4 of 24
VIN = 0 V or VDD
AD7225
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to AGND
VDD to DGND
VDD to VSS
AGND to DGND
Digital Input Voltage to DGND
VREFx to AGND
VOUTx to AGND1
Power Dissipation (Any Package) to 75°C
Derates Above 75°C by
Operating Temperature
Commercial (K, L Versions)
Industrial (B, C Versions)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
1
Rating
−0.3 V, +17 V
−0.3 V, +17 V
−0.3 V, +24 V
−0.3 V, VDD
−0.3 V, VDD + 0.3 V
−0.3 V, VDD + 0.3 V
VSS, VDD
500 mW
2.0 mW/°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +85°C
−40°C to +85°C
−65°C to +150°C
300°C
Outputs can be shorted to any voltage in the range VSS to VDD provided that
the power dissipation of the package is not exceeded. Typical short-circuit
current for a short to AGND or VSS is 50 mA.
Rev. C | Page 5 of 24
AD7225
AD7225
21
VREF C
20
VREF D
4
3
2
1
28
27
26
PIN 1
INDENTFIER
VREF A 6
AGND 7
AD7225
NC 8
25
VREF C
24
VREF D
23
A0
22
NC
21
A1
TOP VIEW 19 A0
AGND 6
(Not to Scale)
18 A1
DGND 7
DGND 9
LDAC 8
17
WR
LDAC 10
20
WR
DB7 9
16
DB0
DB7 11
19
DB0
DB6 10
15
DB1
DB5 11
14
DB2
DB4 12
13
DB3
13
14
15
16
17
18
DB4
NC
DB3
DB2
DB1
00986-002
DB6
12
DB5
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Figure 2. PDIP, SOIC, CERDIP, and SSOP
00986-003
VREF B 4
VREF A 5
VREF B
VDD
VDD
VOUTD
22
VOUTC
VSS 3
5
NC
VOUTC
VOUTD
VOUTB
24
23
VOUTA
VOUTB 1
VOUTA 2
VSS
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. PLCC
Table 4. Pin Function Descriptions
Pin No.
PDIP, SOIC,
CERDIP, SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
N/A
PLCC
2
3
4
5
6
7
9
10
11
12
13
14
16
17
18
19
20
21
23
24
25
26
27
28
1, 8, 15, 22
Mnemonic
VOUTB
VOUTA
VSS
VREFB
VREFA
AGND
DGND
LDAC
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
WR
A1
A0
VREFD
VREFC
VDD
VOUTD
VOUTC
NC
Description
DAC Channel B Voltage Output.
DAC Channel A Voltage Output.
Negative Power Supply Connection.
Reference Voltage Connection for DAC Channel B.
Reference Voltage Connection for DAC Channel A.
Analog Ground Reference Connection.
Digital Ground Reference Connection.
Active Low Load DAC Signal. DAC register data is latched on the rising edge of LDAC.
Data Bit 7 (Most Significant Data Bit).
Data Bit 6.
Data Bit 5.
Data Bit 4.
Data Bit 3.
Data Bit 2.
Data Bit 1.
Data Bit 0 (Least Significant Data Bit).
Active Low Data Write Signal. Input register data is latched on the rising edge of WR.
DAC Address Select Pin.
DAC Address Select Pin.
Reference Voltage Connection for DAC Channel D.
Reference Voltage Connection for DAC Channel C.
Positive Power Supply Connection.
DAC Channel D Voltage Output.
DAC Channel C Voltage Output.
No Internal Connection.
Rev. C | Page 6 of 24
AD7225
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 15 V, VSS = −5 V, unless otherwise noted.
8
VREF x = 10V
7
6
POWER SUPPLY CURRENT (mA)
TOTAL UNADJUSTED ERROR (LSB)
1.0
0.5
0
–0.5
IDD
5
4
3
2
1
0
–1
–2
–3
ISS
–4
–5
32
64
96
128
160
192
–7
–60
00986-004
0
224
INPUT CODE
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 4. Channel-to-Channel Matching
00986-007
–6
–1.0
Figure 7. Power Supply Current vs. Temperature
5
4
1.0
VOUTA
ZERO CODE ERROR (mV)
0.5
0
–0.5
2
1
0
–1
VOUTD
–2
VOUTC
–3
VDD = 5V
VDD = 12V
VDD = 15V
–5
–60
–1.0
1
2
3
4
5
6
7
8
9
10
11
12
13
VREF (V)
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
00986-005
0
VOUTB
–4
Figure 5. Relative Accuracy vs. VREF
00986-008
RELATIVE ACCURACY (LSB)
3
Figure 8. Zero Code Error vs. Temperature
0.25
100
90
0
300µV
–0.25
VDD = 5V
VDD = 12V
VDD = 15V
10
–0.50
0
1
2
3
4
5
6
7
8
9
10
11
VREF (V)
12
13
Figure 6. Differential Nonlinearity vs. VREF
1ms/DIV
Figure 9. Broadband Noise
Rev. C | Page 7 of 24
00986-009
0%
00986-006
DIFFERENTIAL NONLINEARITY (LSB)
0.50
AD7225
TERMINOLOGY
Total Unadjusted Error
Total unadjusted error is a comprehensive specification that
includes full-scale error, relative accuracy, and zero code error.
Maximum output voltage is VREF − 1 LSB (ideal), where 1 LSB
(ideal) is VREF/256. The LSB size varies over the VREF range.
Therefore, the zero code error, relative to the LSB size, increases
as VREF decreases. Accordingly, the total unadjusted error, which
includes the zero code error, also varies in terms of LSB over the
VREF range. As a result, total unadjusted error is specified for a
fixed reference voltage of 10 V.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
allowing for zero code error and full-scale error and is normally
expressed in LSB or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Digital Feedthrough
Digital feedthrough is the glitch impulse transferred to the
output of the DAC due to a change in its digital input code. It is
specified in nV sec and is measured at VREF = 0 V.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one converter (not addressed) due to a change in the digital
input code to another addressed converter. It is specified in nV
sec and is measured at VREF = 0 V.
AC Feedthrough
AC feedthrough is the proportion of reference input signal that
appears at the output of a converter when that DAC is loaded
with all 0s.
Channel-to-Channel Isolation
Channel-to-channel isolation is the proportion of input signal
from the reference of one DAC (loaded with all 1s) that appears
at the output of one of the other three DACs (loaded with all 0s)
The figure given is the worst case for the three other outputs
and is expressed as a ratio in dB.
Full-Scale Error
Full-scale error is defined as
FSE = Measured Value − Zero Code Error − Ideal Value
Rev. C | Page 8 of 24
AD7225
CIRCUIT INFORMATION
DIGITAL-TO-ANALOG SECTION
The AD7225 contains four identical, 8-bit voltage mode digitalto-analog converters. Each DAC has a separate reference input.
The output voltages from the converters have the same polarity
as the reference voltages, allowing single-supply operation. A novel
DAC switch pair arrangement on the AD7225 allows a reference voltage range from 2 V to 12.5 V on each reference input.
Each DAC consists of a highly stable, thin-film, R-2R ladder and
eight high speed NMOS, single-pole, double-throw switches. The
simplified circuit diagram for Channel A is shown in Figure 10.
Note that AGND is common to all four DACs.
Settling time for negative-going output signals approaching
AGND is similarly affected by VSS. Negative-going settling time
for single-supply operation is longer than for dual-supply operation. Positive-going settling time is not affected by VSS.
500
400
VOUTA
R
2R
2R
2R
2R
DB0
DB5
DB6
DB7
VREF A
AGND
SHOWN FOR ALL 1s ON DAC
VDD = +15V
TA = 25°C
VSS = –5V
VSS = 0V
ISINK (µA)
2R
R
00986-010
R
parameters that cannot be achieved with single-supply operation. In single-supply operation (VSS = 0 V = AGND), the sink
capability of the amplifier, which is normally 400 μA, is reduced
as the output voltage nears AGND. The full sink capability of
400 μA is maintained over the full output voltage range by tying
VSS to −5 V. This is shown in Figure 11.
300
200
Figure 10. Digital-to-Analog Simplified Circuit Diagram
Each VOUTx pin can be considered a digitally programmable
voltage source with an output voltage of
100
0
0
2
4
6
8
10
VOUT (V)
00986-011
The input impedance at any of the reference inputs is code
dependent and can vary from 11 kΩ minimum to infinity. The
lowest input impedance at any reference input occurs when that
DAC is loaded with Digital Code 01010101. Therefore, it is
important that the reference presents a low output impedance
under changing load conditions. The nodal capacitance at the
reference terminals is also code dependent and typically varies
from 15 pF to 35 pF.
Figure 11. Variation of ISINK with VOUT
Additionally, the negative VSS gives more headroom to the
output amplifiers, which results in better zero code performance and improved slew rate at the output than can be
obtained in the single-supply mode.
DIGITAL INPUTS SECTION
VOUTX = DX × VREFX
where DX is a fractional representation of the digital input code
and can vary from 0 to 255/256.
The output impedance is that of the output buffer amplifier.
OP AMP SECTION
Each voltage mode DAC output is buffered by a unity gain
noninverting CMOS amplifier. This buffer amplifier is capable
of developing 10 V across a 2 kΩ load and can drive capacitive
loads of 3300 pF.
The AD7225 digital inputs are compatible with either TTL or
5 V CMOS levels. All logic inputs are static protected MOS
gates with typical input currents of less than 1 nA. Internal
input protection is achieved by an on-chip distributed diode
between DGND and each MOS gate. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (VDD and DGND) as practically possible.
The AD7225 can be operated single or dual supply; operating
with dual supplies results in enhanced performance in some
Rev. C | Page 9 of 24
AD7225
INTERFACE LOGIC INFORMATION
TO INPUT
LATCH C
Function
High
High
High
High
Low
High
Low
Low
No operation. Device not selected.
Input register of selected DAC transparent.
Input register of selected DAC latched.
All four DAC registers Transparent (that is,
outputs respond to data held in respective
input registers). Input registers are latched.
All four DAC registers latched.
DAC registers and selected input register
transparent output follows input data for
selected channel.
5V
VINH
VINL
0V
t2
t3
t1
5V
WR
t6
t5
LDAC
5V
t4
DATA IN
DATA
VALID
5V
0V
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
10% TO 90% OF 5V.
tR = tF = 20ns OVER VDD RANGE.
2. TIMING MEASUREMENT REFERENCE LEVEL IS
VINH + VINL
2
3. IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR,
THEN IT MUST STAY LOW FOR t6 OR LONGER AFTER WR
GOES HIGH.
Table 6. Truth Table
LDAC
TO INPUT
LATCH D
ADDRESS
Only the data held in the DAC register determines the analog
output of the converter. The LDAC signal is common to all four
DACs and controls the transfer of information from the input
registers to the DAC registers. Data is latched into all four DAC
registers simultaneously on the rising edge of LDAC. The LDAC
signal is level triggered and therefore the DAC registers can be
made transparent by tying LDAC low (in this case, the outputs
of the converters respond to the data held in their respective
input latches). LDAC is an asynchronous signal and is independent of WR. This is useful in many applications. However, in
systems where the asynchronous LDAC can occur during a
write cycle (or vice versa), care must be taken to ensure that
incorrect data is not latched through to the output. If LDAC is
activated prior to the rising edge of WR (or WR occurs during
LDAC), LDAC must stay low for t6 or longer after WR goes high
to ensure correct data is latched through to the output. Table 6
shows the truth table for AD7225 operation. Figure 12 shows
the input control logic for the part; the write cycle timing
diagram is given in Figure 13.
High
Low
TO INPUT
LATCH B
A1
Figure 12. Input Control Logic
Selected Input Register
DAC A
DAC B
DAC C
DAC D
WR
TO INPUT
LATCH A
Rev. C | Page 10 of 24
Figure 13. Write Cycle Timing Diagram
00986-013
A0
Low
High
Low
High
A0
WR
Table 5. AD7225 Addressing
A1
Low
Low
High
High
TO ALL
DAC LATCHES
LDAC
00986-012
The AD7225 contains two registers per DAC, an input register
and a DAC register. The A0 and A1 address lines select which
input register accepts data from the input port. When the WR
signal is low, the input latches of the selected DAC are transparent. The data is latched into the addressed input register on the
rising edge of WR. Table 5 shows the addressing for the input
registers on the AD7225.
AD7225
GROUND MANAGEMENT AND LAYOUT
Because the AD7225 contains four reference inputs that can be
driven from ac sources (see the AC Reference Signal section),
careful layout and grounding is important to minimize analog
crosstalk between the four channels. The dynamic performance
of the four DACs depends on the optimum choice of board
layout. Figure 14 shows the relationship between input frequency and channel-to-channel isolation. Figure 15 shows a
printed circuit board layout that minimizes crosstalk and
feedthrough. The four input signals are screened by AGND.
VREF was limited to between 2 V and 3.24 V to avoid slew rate
limiting effects from the output amplifier during measurements.
SYSTEM
GND
PIN 1
VOUTA
VOUTD
VDD
VREF B
VREF C
VREF A
VREF D
AGND
DGND
MSB
LSB
00986-015
–70
Figure 15. Suggested PCB Layout for AD7225, Component Side (Top View)
–60
–50
–40
VREF = 1.24V p-p
–30
20k
50k
100k
200k
500k
INPUT FREQUENCY (Hz)
1M
00986-014
ISOLATION (dB)
VOUTC
VSS
VDD = +15V
VSS = –5V
TA = 25°C
–80
VOUTB
Figure 14. Channel-to-Channel Isolation
Rev. C | Page 11 of 24
AD7225
SPECIFICATION RANGES
For the AD7225 to operate to rated specifications, its input
reference voltage must be at least 4 V below the VDD power
supply voltage. This voltage differential is the overhead voltage
required by the output amplifiers.
The AD7225 is specified to operate over a VDD range from 12 V
± 5% to 15 V ± 10% (that is, from 11.4 V to 16.5 V) with a VSS
of −5 V ± 10%. Operation is also specified for a single 15 V ±
5% VDD supply. Applying a VSS of −5 V results in improved zero-
code error, improved output sink capability with outputs near
AGND, and improved negative-going settling time.
Performance is specified over a wide range of reference voltages
from 2 V to (VDD − 4 V) with dual supplies. This allows a range
of standard reference generators to be used, such as the AD780,
a 2.5 V band gap reference, and the AD584, a precision 10 V
reference. Note that an output voltage range of 0 V to 10 V
requires a nominal 15 V ± 5% power supply voltage.
Rev. C | Page 12 of 24
AD7225
UNIPOLAR OUTPUT OPERATION
VREF A VREF B VREF C VREF D
This is the basic mode of operation for each channel of the
AD7225, with the output voltage having the same positive
polarity as VREFx. The AD7225 can be operated single supply
(VSS = AGND) or with positive/negative supplies (see the Op
Amp Section, which outlines the advantages of having negative
VSS). Connections for the unipolar output operation are shown
in Figure 16. The voltage at any of the reference inputs must
never be negative with respect to DGND. Failure to observe this
precaution may cause parasitic transistor action and possible
device destruction. The code table for unipolar output
operation is shown in Table 7.
DB7
(MSB)
DB0
(LSB)
WR
VDD
DAC A
VOUTA
DAC B
VOUTB
DAC C
VOUTC
DAC D
VOUTD
A1
A2
LDAC
VSS
1 
1 LSB = (V REF )(2 −8 ) = V REF 

 256 
AGND
DGND
00986-016
AD7225
Note,
Figure 16. Unipolar Output Circuit
Table 7. Unipolar Code Table
MSB
1111
DAC Latch Contents
LSB
1111
Analog Output
255
)
+ V REF ( 256
1000
0001
+ V REF ( 129
256 )
1000
0000
+ V REF ( 128
256 ) = +
0111
1111
+ V REF ( 127
256 )
0000
0001
0000
0000
Rev. C | Page 13 of 24
1
)
+ V REF ( 256
0V
V REF
2
AD7225
BIPOLAR OUTPUT OPERATION
VREF
Each of the DACs of the AD7225 can be individually configured to provide bipolar output operation. This is possible
using one external amplifier and two resistors per channel.
Figure 17 shows a circuit used to implement offset binary
coding (bipolar operation) with DAC A (DAC Channel A)
of the AD7225. In this case,
R1
VREF A
R2
VDD
+15V
AD7225*
VOUTA
DAC A
VSS
With R1 = R2
AGND
–15V
DGND
R1, R2 = 10kΩ ± 0.1%.
*DIGITAL INPUTS OMITTED
FOR CLARITY.
Figure 17. Bipolar Output Circuit
VOUT = (2D A − 1) × (VREF )
where DA is a fractional representation of the digital word in
Latch A (0 ≤ DA ≤ 255/256).
Table 8. Bipolar (Offset Binary) Code Table
Mismatch between R1 and R2 causes gain and offset errors and,
therefore, these resistors must match and track over temperature. The AD7225 can be operated in single supply or from
positive/negative supplies. Table 8 shows the digital code vs.
output voltage relationship for the circuit of Figure 17 with
R1 = R2.
MSB
1111
DAC Latch Contents
LSB
1111
Analog Output
+ V REF (127
128 )
1
)
+ VREF (128
1000
0001
1000
0111
0000
1111
0V
0000
0001
− VREF (127
128 )
0000
0000
Rev. C | Page 14 of 24
1
)
− VREF (128
− VREF (128
128 ) = 1 − V REF
00986-017
R2 
 R2 
VOUT = 1 +
 × (D AVREF ) −   × (VREF )
 R1 
 R1 
VOUT
AD7225
AGND BIAS
The AD7225 AGND pin can be biased above system ground
(AD7225 DGND) to provide an offset zero analog output
voltage level. Figure 18 shows a circuit configuration to achieve
this for DAC Channel A of the AD7225. The output voltage,
VOUTA, can be expressed as:
VREF A
VDD
AD7225*
VIN
VOUTA
DAC A
AGND
VOUTA = VBIAS + DA(VIN)
VSS
DGND
*DIGITAL INPUTS OMITTED FOR CLARITY.
00986-018
VBIAS
where DA is a fractional representation of the digital word in
DAC Latch A (0 ≤ DA ≤ 255/256).
Figure 18. AGND Bias Circuit
For a given VIN, increasing AGND above system ground reduces
the effective VDD − VREF, which must be at least 4 V to ensure
specified operation. Note that, because the AGND pin is
common to all four DACs, this method biases up the output
voltages of all the DACs in the AD7225. Note that VDD and VSS
of the AD7225 should be referenced to DGND.
Rev. C | Page 15 of 24
AD7225
AC REFERENCE SIGNAL
+15V
+4V
15kΩ
REFERENCE
INPUT
–4V
+15V
10kΩ
VREF A
VDD
AD7225*
VOUTA
DAC A
VSS
AGND
DGND
*DIGITAL INPUTS OMITTED FOR CLARITY.
Figure 19. Applying an AC Signal to the AD7225
Rev. C | Page 16 of 24
00986-019
In some applications, it may be desirable to have ac reference
signals. The AD7225 has multiplying capability within the
upper (VDD − 4 V) and lower (2 V) limits of reference voltage
when operated with dual supplies. Therefore, ac signals need to
be ac-coupled and biased up before being applied to the
reference inputs. Figure 19 shows a sine wave signal applied to
VREFA. For input signal frequencies up to 50 kHz, the output
distortion typically remains less than 0.1%. The typical 3 dB
bandwidth figure for small signal inputs is 800 kHz.
AD7225
APPLICATIONS INFORMATION
INPUT
AD7820
AM29520
AD7225
ADC
TLC
QUAD DAC
SAMPLES
VREF A
VREF A
h2
VOUTA
AM7224 VOUT
DAC
VREF A
h3
VOUTA
VREF
AD585 OUTPUT
+
VOUTC
SHA
VOUTD
h1
REF
FILTER
VOUTB
SAMPLES
AD584 10V
ACCUMULATOR
OUTPUT
VOUTA
DELAYED
INPUT
VREF A
h4
VOUTA
VOUTA
Xn
FILTER
INPUT
Xn – 3
Xn – 2
T
1
T
2
h1
AD7225
Xn – 1
T
3
h2
4
h3
h4
QUAD DAC
VREF
FILTER
OUTPUT
GAIN SET
00986-020
+
y(n)
TAP WEIGHT
Figure 20. Programmable Transversal Filter
0
PROGRAMMABLE TRANSVERSAL FILTER
A discrete time filter can be described by either multiplication
in the frequency domain or by convolution in the time domain:
–20
–30
Xn
h1
Xn – 2
Xn – 1
T
1
–90
–100
0
3
0.25
0.30
0.35
0.40
0.45
0.50
0.45
0.50
Figure 22. Predicted (Theoretical) Response
N
–30
hk Xn – k + 1
k=1
00986-021
N
yn =
0.20
–10
+
FILTER
OUTPUT
0.15
0
hN
hN – 1
0.10
–20
N –1
h3
0.05
NORMALIZED FREQUENCY (f/fS)
T
2
h2
–80
Xn – N + 1
Xn – N
T
–60
–70
GAIN (dB)
FILTER
INPUT
–50
00986-022
The convolution sum can be implemented using the special structure known as the transversal filter (see Figure 21). It consists
of an N-stage delay line with N taps weighted by N coefficients,
the resulting products being accumulated to form the output.
The tap weights or coefficients hk are the nonzero elements of
the impulse response and therefore determine the filter transfer
function. A particular filter frequency response is realized by
setting the coefficients to the appropriate values. This property
leads to the implementation of transversal filters whose frequency response is programmable.
–40
00986-023
k =1
GAIN (dB)
N
Y (ω) = H (ω) X (ω) or y n = ∑ hk X n − k +1
h1 = 0.117
h2 = 0.417
h3 = 0.417
h4 = 0.417
–10
–40
h1 (DAC A) = 00011110
h2 (DAC B) = 01101011
h3 (DAC C) = 01101011
h4 (DAC D) = 00011110
–50
–60
–70
–80
Figure 21. Transversal Filter
A four-tap programmable transversal filter can be implemented
using the AD7225 (see Figure 20). The input signal is first sampled
and converted to allow the tapped delay line function to be
provided by the AM29520. The multiplication of delayed input
samples by fixed, programmable up weights is accomplished by
the AD7225, the four coefficients or reference inputs being set
by the digital codes stored in the AD7226. The resultant products
are accumulated to yield the convolution sum output sample,
which is held by the AD585.
–90
–100
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
FREQUENCY (f/fS)
0.40
Figure 23. Actual Response
Low-pass, band-pass, and high-pass filters can be synthesized
using this arrangement. The particular up weights needed for
any desired transfer function can be obtained using the standard
Remez exchange algorithm. Figure 22 shows the theoretical
low-pass frequency response produced by a four-tap transversal
filter with the coefficients indicated. Although the theoretical
prediction does not take into account the quantization of the
input samples and the truncation of the coefficients, neverthe-
Rev. C | Page 17 of 24
AD7225
less, there exists a good correlation with the actual performance
of the transversal filter (see Figure 23).
15V
DIGITAL WORD MULTIPLICATION
25kΩ
VDD
Because each DAC of the AD7225 has a separate reference input,
the output of one DAC can be used as the reference input for
another. This means that multiplication of digital words can be
performed (with the result given in analog form). For example,
if the output from DAC A is applied to VREFB, then the output
from DAC B, VOUTB, can be expressed as:
AD7225*
VIN
VREF A
VOUTA
VREF B
VOUTB
VREF C
VOUTC
100kΩ
50kΩ
33kΩ
Y
50kΩ
100kΩ
VREF D
VOUTD
AGND DGND VSS
where DA and DB are the fractional representations of the digital
words in DAC Latch A and DAC Latch B, respectively.
*DIGITAL INPUTS OMITTED FOR CLARITY.
Figure 24. Complex Waveform Generation
If DA = DB = D, the result is D × VREFA.
2
In this manner, the four DACs can be used on their own or in
conjunction with an external summing amplifier to generate
complex waveforms. Figure 24 shows one such application.
In this case, the output waveform, Y, is represented by
Y = −(x4 + 2x3 + 3x2 + 2x + 4) × VIN
where x is the digital code that is applied to all four DAC
latches.
Rev. C | Page 18 of 24
00986-024
VOUTB = DA × DB × VREFA
AD7225
MICROPROCESSER INTERFACE
A15
A15
ADDRESS BUS
8085A/
8088
ADDRESS
DECODE
WR
ALE
A0
A1
LDAC
A0
A1
Z-80
ADDRESS
DECODE
AD7225*
MREQ
WR
LATCH
EN
ADDRESS BUS
A8
WR
WR
DB7
DB7
DB0
DB0
ADDRESS DATA BUS
AD0
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
00986-025
D7
AD7
LDAC
AD7225*
EN
Figure 25. AD7225-to-8085A/8088 Interface, Double-Buffered Mode
DATA BUS
D0
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
00986-026
A8
Figure 26. AD7225-to-Z-80 Interface, Double-Buffered Mode
A23
A15
ADDRESS BUS
ADDRESS BUS
A1
A0
R/W
A0
A1
ADDRESS
DECODE
68008
LDAC
AS
AD7225*
EN
EN
DB7
DB0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
DB0
00986-027
D0
AD7225*
R/W
DB7
D7
A0
A1
WR
LDAC
DTACK
WR
E OR Φ2
ADDRESS
DECODE
Figure 27. AD7225-to-6809/6502 Interface, Single-Buffered Mode
Rev. C | Page 19 of 24
D7
D0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY.
Figure 28. AD7225-to-68008 Interface, Single-Buffered Mode
00986-028
6809/
6502
AD7225
VSS GENERATION
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
1/6
CD4049AE
Rev. C | Page 20 of 24
5.1kΩ
1/6
CD4049AE
47µF
+
510Ω
–VOUT
1N4001
1N4001
Figure 29. VSS Generation Circuit
47µF
5V1
00986-029
0.02µF
+
510kΩ
+
Operating the AD7225 from dual supplies results in enhanced
performance over single-supply operation on a number of
parameters as previously outlined. Some applications may
require this enhanced performance, but may only have a single
power supply rail available. The circuit of Figure 29 shows a
method of generating a negative voltage using one CD4049,
operated from a VDD of 15 V. Two inverters of the hex inverter
chip are used as an oscillator. The other four inverters are in
parallel and used as buffers for higher output current. The
square wave output is level translated to a negative-going signal,
then rectified and filtered. The circuit configuration shown
provides an output voltage of −5.1 V for current loadings in the
range of 0.5 mA to 9 mA. This satisfies the AD7225 ISS requirement over the commercial operating temperature range.
AD7225
OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
13
1
12
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
071006-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 30. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
0.098 (2.49)
MAX
0.005 (0.13)
MIN
24
13
1
12
PIN 1
0.200 (5.08)
MAX
0.310 (7.87)
0.220 (5.59)
1.280 (32.51) MAX
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.290 (7.37)
0.150 (3.81)
MIN
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78) SEATING
0.030 (0.76) PLANE
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 24-Lead Ceramic Dual In-Line Package [CERDIP]
Narrow Body
(Q-24-1)
Dimensions shown in inches and (millimeters)
Rev. C | Page 21 of 24
100808-A
0.200 (5.08)
0.125 (3.18)
AD7225
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
4
0.048 (1.22)
0.042 (1.07)
5
PIN 1
IDENTIFIER
26
25
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
11
12
0.020 (0.51)
MIN
0.032 (0.81)
0.026 (0.66)
19
18
0.456 (11.582)
SQ
0.450 (11.430)
0.495 (12.57)
SQ
0.485 (12.32)
0.120 (3.04)
0.090 (2.29)
BOTTOM
VIEW
(PINS UP)
0.430 (10.92)
0.390 (9.91)
0.045 (1.14)
R
0.025 (0.64)
042508-A
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 32. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
15.60 (0.6142)
15.20 (0.5984)
13
24
7.60 (0.2992)
7.40 (0.2913)
12
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
⋅ 45°
0.25 (0.0098)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 33. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
Rev. C | Page 22 of 24
1.27 (0.0500)
0.40 (0.0157)
06-07-2006-A
1
AD7225
8.50
8.20
7.90
13
24
5.60
5.30
5.00
1
8.20
7.80
7.40
12
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
0.95
0.75
0.55
060106-A
0.05 MIN
COPLANARITY
0.10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
COMPLIANT TO JEDEC STANDARDS MO-150-AG
Figure 34. 24-Lead Shrink Small Outline Package [SSOP]
(RS-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
AD7225BQ
AD7225BRS
AD7225BRS-REEL
AD7225BRSZ
AD7225CRS
AD7225CRS-REEL
AD7225CRSZ
AD7225CRSZ-RL
AD7225KN
AD7225KNZ
AD7225KP
AD7225KP-REEL
AD7225KPZ
AD7225KR
AD7225KR-REEL
AD7225KRZ
AD7225KRZ-REEL
AD7225LN
AD7225LNZ
AD7225LP
AD7225LP-REEL
AD7225LPZ
AD7225LPZ-REEL
AD7225LR
AD7225LR-REEL
AD7225LRZ
AD7225LRZ-REEL
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Total Unadjusted Error
±2 LSB
±2 LSB
±2 LSB
±2 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
Package Description
24-Lead CERDIP
24-Lead SSOP
24-Lead SSOP
24-Lead SSOP
24-Lead SSOP
24-Lead SSOP
24-Lead SSOP
24-Lead SSOP
24-Lead PDIP
24-Lead PDIP
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead PDIP
24-Lead PDIP
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
To order MIL-STD-883 processed parts, add /883B to part number. Contact your local sales office for military data sheet.
Z = RoHS Compliant Part.
Rev. C | Page 23 of 24
Package Option
Q-24-1
RS-24
RS-24
RS-24
RS-24
RS-24
RS-24
RS-24
N-24-1
N-24-1
P-28
P-28
P-28
RW-24
RW-24
RW-24
RW-24
N-24-1
N-24-1
P-28
P-28
P-28
P-28
RW-24
RW-24
RW-24
RW-24
AD7225
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00986-0-3/10(C)
Rev. C | Page 24 of 24