ON MC74HCT74ADG Dual d flip-flop with set and reset Datasheet

MC74HCT74A
Dual D Flip-Flop with Set
and Reset with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
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The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
Features
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 136 FETs or 34 Equivalent Gates
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
SOIC−14 NB
D SUFFIX
CASE 751A
PIN ASSIGNMENT
RESET 1
1
14
VCC
DATA 1
2
13
RESET 2
CLOCK 1
3
12
DATA 2
SET 1
4
11
CLOCK 2
Q1
5
10
SET 2
Q1
6
9
Q2
GND
7
8
Q2
MARKING DIAGRAM
14
LOGIC DIAGRAM
RESET 1
HCT74AG
AWLYWW
1
1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
2
5
3
6
Q1
A
WL
Y, YY
WW
G
Q1
4
13
PIN 14 = VCC
PIN 7 = GND
12
9
11
8
FUNCTION TABLE
Inputs
Q2
Value
Units
Internal Gate Count†
34
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
.0075
pJ
Speed Power Product
Outputs
Set Reset Clock Data
Q2
L
H
L
H
H
H
H
H
10
Design Criteria
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
H
L
L
H
H
H
H
H
X
X
X
L
H
X
X
X
H
L
X
X
X
Q
Q
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
†Equivalent to a two−input NAND gate.
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 12
1
Publication Order Number:
MC74HCT74A/D
MC74HCT74A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
–0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
_C
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
circuit. For proper operation, Vin and
Vout should be constrained to the
range GND ≤ (Vin or Vout) ≤ VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Max
Unit
4.5
5.5
V
0
VCC
V
–55
+125
_C
0
500
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
–55 to
25_C
≤ 85_C
≤ 125_C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| ≤ 20 mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| ≤ 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| ≤ 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout| ≤ 4.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout| ≤ 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| ≤ 4.0 mA
VOL
Maximum Low−Level Output
Voltage
V
4.5
0.26
0.33
0.4
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
5.5
2.0
20
80
mA
DICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 mA
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2
5.5
≥ −55_C
25_C to 125_C
2.9
2.4
mA
MC74HCT74A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
–55 to
25_C
≤ 85_C
≤ 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
24
30
36
ns
tPLH,
tPHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
24
30
36
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
15
19
22
ns
Maximum Input Capacitance
10
10
10
pF
Cin
Typical @ 25°C, VCC = 5.0 V
CPD
32
Power Dissipation Capacitance (Per Enabled Output)*
pF
1. Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC .
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
–55 to
25_C
Symbol
Parameter
Fig.
Min
Max
≤ 85_C
Min
≤ 125_C
Max
Min
Max
Units
tsu
Minimum Setup Time, Data to Clock
3
15
19
22
ns
th
Minimum Hold Time, Clock to Data
3
3
3
3
ns
trec
Minimum Recovery Time, Set or Reset Inactive to Clock
2
6
8
9
ns
tw
Minimum Pulse Width, Clock
1
15
19
22
ns
tw
Minimum Pulse Width, Set or Reset
2
15
19
22
ns
tr, tf
Maximum Input Rise and Fall Times
1
500
500
500
ns
ORDERING INFORMATION
Package
Shipping†
MC74HCT74ADG
SOIC−14 NB
(Pb−Free)
55 Units / Rail
MC74HCT74ADR2G
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
MC74HCT74A
SWITCHING WAVEFORMS
tw
tr
CLOCK
3V
tf
SET OR
RESET
3V
2.7 V
1.3 V
0.3 V
1.3 V
GND
tPHL
GND
Q OR Q
tw
1.3 V
1/fmax
tPLH
Q OR Q
tPLH
tPHL
1.3 V
Q OR Q
90%
1.3 V
10%
trec
3V
1.3 V
CLOCK
tTLH
tTHL
GND
Figure 1.
Figure 2.
VALID
TEST POINT
3V
DATA
1.3 V
OUTPUT
GND
tsu
DEVICE
UNDER
TEST
th
3V
1.3 V
CL*
GND
CLOCK
*Includes all probe and jig capacitance
Figure 3.
SET
Figure 5.
4, 10
2, 12
5, 9
Q
DATA
3, 11
CLOCK
6, 8
Q
1, 13
RESET
Figure 4. Expanded Logic Diagram
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4
MC74HCT74A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
DETAIL A
h
A
X 45 _
M
A1
e
DIM
A
A1
A3
b
D
E
e
H
h
L
M
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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MC74HCT74A/D
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