42 CY29942 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features 200-MHz clock support 2.5V or 3.3V operation LVCMOS/LVTTL clock input LVCMOS-/LVTTL-compatible inputs 18 clock outputs: drive up to 36 clock lines 200 ps max. output-to-output skew Output Enable control Pin compatible with MPC942C Available in Industrial and Commercial 32-pin LQFP package Block Diagram The CY29942 is a low-voltage 200-MHz clock distribution buffer with an LVCMOS or LVTTL compatible input clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and can drive 50 Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the devices an effective fanout of 1:36. Low output-to-output skews make the CY29942 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. Cypress Semiconductor Corporation Document #: 38-07284 Rev. *B • 3901 North First Street • Q0 Q1 Q2 VDD Q3 Q4 Q5 VSS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 • 13 14 15 16 Q13 Q12 VDD 12 VSS San Jose Q14 11 CY29942 Q15 Q0-Q17 OE 9 18 1 2 3 4 5 6 7 8 10 TCLK VSS VSS TCLK NC OE NC VDD VDD Q16 VDD 32 Pin Configuration Q17 • • • • • • • • • • Description Q6 Q7 Q8 VDD Q9 Q10 Q11 VSS CA 95134 • 408-943-2600 Revised December 21, 2002 CY29942 Pin Description[1] Pin Name PWR 3 TCLK I, PD External Reference/Test Clock Input 5 OE I, PU Output Enable. When HIGH, all the outputs are enabled. When set LOW, the outputs are at high impedance. 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 Q(17:0) 7, 8, 16, 21, 29 VDD 3.3V or 2.5V Power Supply 1, 2, 12, 17, 25 VSS Common Ground 4, 6 NC No Connection VDD I/O O Description Clock Outputs Note: 1. PD = Internal Pull-Down, PU = Internal Pull-up. Document #: 38-07284 Rev. *B Page 2 of 7 CY29942 Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD protection ............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................±20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, Over the specified temperature range. Parameter Description Conditions Min. Typ. Max. Unit VIL Input Low Voltage VSS 0.8 V VIH Input High Voltage 2.0 VDD V –200 µA 200 µA 0.5 V [3] IIL Input Low Current IIH Input High Current[3] Voltage[4] VOL Output Low VOH Output High Voltage[4] IDDQ Quiescent Supply Current IDD Dynamic Supply Current Zout Output Impedance Cin Input Capacitance IOL = 20 mA IOH = –20 mA, VDDC = 3.3V 2.4 IOH = –16 mA, VDDC = 2.5V 2.0 V 5 VDD = 3.3V, Outputs @ 150 MHz, CL = 15 pF 285 VDD = 3.3V, Outputs @ 200 MHz, CL = 15 pF 335 VDD = 2.5V, Outputs @ 150 MHz, CL = 15pF 200 VDD = 2.5V, Outputs @ 200 MHz, CL = 15pF 240 7 mA mA VDD = 3.3V 8 12 16 VDD = 2.5V 10 15 20 Ω 4 pF Notes: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Document #: 38-07284 Rev. *B Page 3 of 7 CY29942 AC Parameters[5]: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, Over the specified temperature range Parameter Description Conditions Fmax Input Frequency Tpd TTL_CLK to Q Delay[6, 7] FoutDC Output Duty Cycle[6, 7, 8] Tskew Output-to-Output Skew[6, 7] Tskew(pp) Part-to-Part Skew[9] Tskew(pp) Part-to-Part Skew[10] Tr/Tf Output Clocks Rise/Fall Time[6, 7] Min. Typ. Max. Unit 200 MHz ns VDD = 3.3V 1.8 3.3 3.8 VDD = 2.5V 2.3 3.8 4.4 Measured at VDD/2 45 55 % 200 ps VDD = 3.3V 1.0 ns VDD = 2.5V 1.3 0.8V to 2.0V, VDD = 3.3V 0.2 600 ps 1.1 ns 0.5V to 1.8V, VDD = 2.5V Notes: 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Outputs driving 50Ω transmission lines. 7. See Figure 1. 8. 50% input duty cycle. 9. Across temperature and voltage ranges, includes output skew. 10. For a specific temperature and voltage, includes output skew. CY29942 DUT Zo = 50 ohm Pulse Generator Z = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. LVCMOS_CLK CY29942 Test Reference for VCC = 3.3V and VCC = 2.5V VCC LVCMOS_CLK VCC /2 GND VCC Q VCC /2 tPD GND Figure 2. LVCMOS Propagation Delay (TPD) Test Reference VCC VCC /2 tP GND T0 DC = tP / T0 x 100% Figure 3. Output Duty Cycle (FoutDC) Document #: 38-07284 Rev. *B Page 4 of 7 CY29942 VCC VCC /2 GND VCC VCC /2 tSK(0) GND Figure 4. Output-to-Output Skew tsk(0) Document #: 38-07284 Rev. *B Page 5 of 7 CY29942 Ordering Information Part Number CY29942AI CY29942AIT CY29942AC CY29942ACT Package Type Production Flow 32 Pin LQFP Industrial, -40°C to +85°C 32 Pin LQFP - Tape and Reel Industrial, -40°C to +85°C 32 Pin LQFP Commercial, 0°C to +70°C 32 Pin LQFP - Tape and Reel Commercial, 0°C to +70°C Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07284 Rev. *B Page 6 of 7 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29942 Revision History Document Title: CY29942 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Document Number: 38-07284 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 111095 02/07/02 BRK New data sheet *A 116777 08/14/02 HWT Added a Commercial Temp. Range in the Ordering Information *B 122876 12/21/02 RBI Document #: 38-07284 Rev. *B Add power up requirements to maximum rating information. Page 7 of 7