ATMEL ATA6661 Lin transceiver Datasheet

Features
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Operating Range from 5 V to 18 V
Baud Rate up to 20 Kbaud
Improved Slew Rate Control According to LIN Specification 2.0
Fully Compatible with 3.3 V and 5 V Devices
Dominant Time-out Function at Transmit Data (TXD)
Normal and Sleep Mode
Wake-up Capability via LIN Bus (90 µs Dominant)
External Wake-up via WAKE Pin (130 µs Low Level)
Control of External Voltage Regulator via INH Pin
Very Low Standby Current During Sleep Mode (10 µA)
60 V Load Dump Protection at LIN Pin (42-V Power Net)
Wake-up Source Recognition
Bus Pin Short-circuit Protected versus GND and Battery
LIN Input Current <3 µA if VBAT Is Disconnected
Overtemperature Protection
High EMC Level
Interference and Damage Protection According to ISO/CD 7637
ESD HBM 6 kV at LIN Bus Pin and Supply VS Pin
LIN Transceiver
ATA6661
Description
The ATA6 66 1 is a fu lly int egrat ed LIN tran sce iver acc or din g to th e L IN
specification 2.0. It interfaces the LIN protocol handler and the physical layer. The
device is designed to handle the low-speed data communication in vehicles, e.g., in
convenience electronics. Improved slope control at the LIN bus ensures secure data
communication up to 20 kBaud with an RC-oscillator for protocol handling. In order to
comply with the 42-V power net requirements, the bus output is capable of withstanding high voltages. Sleep mode guarantees minimal current consumption.
Figure 1. Block Diagram
ATA6661
7
VS
6
LIN
Receiver
RXD
1
Filter
Short circuit and overtemperature protection
Wake-up bus timer
TXD
4
TXD
Time-out
Timer
Slew rate control
VS
VS
Control unit
WAKE
3
Wake-up
Timer
Standby mode
2
EN
5
GND
8
INH
Rev. 4729D–AUTO–10/04
Pin Configuration
Figure 2. Pinning SO8
RXD
EN
WAKE
TXD
1
2
3
4
8
7
6
5
INH
VS
LIN
GND
Pin Description
Pin
Symbol
1
RXD
2
EN
3
WAKE
Function
Receive data output (open drain)
Enables normal mode, when the input is open or low, the device is in sleep mode
High voltage input for local wake-up request
4
TXD
Transmit data input; active low output (strong pull-down) after a local wake-up request
5
GND
Ground
6
LIN
LIN bus line input/output
7
VS
Battery supply
8
INH
Battery related inhibit output for controlling an external voltage regulator; active high after a wake-up
request
Functional Description
Supply Pin (VS)
Undervoltage detection is implemented to disable transmission if VS is falling to a value
below 5 V to avoid false bus messages. After switching on V S the IC switches to
pre-normal mode and INHIBIT is switched on. The supply current in sleep mode is
typically 10 µA.
Ground Pin (GND)
The ATA6661 is neutral on the LIN pin in case of a GND disconnection. It is able to handle a ground shift up to 3 V for VS > 9 V.
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an
internal pull-up resistor according to LIN specification 2.0 are implemented. The voltage
range is from -27 V to +60 V. This pin exhibits no reverse current from the LIN bus to VS,
even in case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible to the LIN protocol specification.The fall time (from recessive to dominant) and
the rise time (from dominant to recessive) are slope controlled. The output has a short
circuit limitation. This is a self adapting current limitation; i.e., during current limitation as
the chip temperature increases so the current reduces.
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ATA6661
4729D–AUTO–10/04
ATA6661
Input Pin (TXD)
This pin is the microcontroller interface to control the state of the LIN output. TXD is low
to bring LIN low. If TXD is high, the LIN output transistor is turned off. In this case, the
bus is in recessive mode via the internal pull-up resistor. The TXD pin is compatible to a
3.3 V and 5 V supply.
TXD Dominant Time-out
Function
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line
from being driven permanently in dominant state. If TXD is forced low longer than
tdom > 4 ms, the pin LIN will be switched off to recessive mode. To reset this mode
switch TXD to high (>10 µs) before switching LIN to dominant again.
Output Pin (RXD)
This pin reports to the microcontroller the state of the LIN bus. LIN high (recessive) is
reported by a high level at RXD, LIN low (dominant) is reported by a low voltage at RXD.
The output is an open drain, therefore, it is compatible to a 3.3 V or 5 V power supply.
The AC characteristics are defined with a pull-up resistor of 5 kΩ to 5 V and a load
capacitor of 20 pF. The output is short-current protected. In unpowered mode
(VS = 0 V), RXD is switched off. For ESD protection a Zener diode is implemented with
VZ = 6.1 V.
Enable Input Pin (EN)
This pin controls the operation mode of the interface. If EN = 1, the interface is in normal
mode, with the transmission path from TXD to LIN and from LIN to Rx both active. If
EN = 0, the device is switched to sleep mode and no transmission is possible. In sleep
mode, the LIN bus pin is connected to VS with a weak pull-up current source. The device
can transmit only after being woken up (see “Inhibit Output Pin (INH)” on page 3).
During sleep mode the device is still supplied from the battery voltage. The supply
current is typically 10 µA. The pin EN provides a pull-down resistor in order to force the
transceiver into sleep mode in case the pin is disconnected.
Inhibit Output Pin (INH)
This pin is used to control an external switchable voltage regulator having a wake-up
input. The inhibit pin provides an internal switch towards pin VS. If the device is in normal
mode, the inhibit high-side switch is turned on and the external voltage regulator is activated. When the device is in sleep mode, the inhibit switch is turned off and disables the
voltage regulator.
A wake-up event on the LIN bus or at pin WAKE will switch the INH pin to the VS level.
After a system power-up (VS rises from zero), the pin INH switches automatically to the
VS level. The RDSon of the highside output is <1 kΩ.
Wake-up Input Pin
(WAKE)
This pin is a high-voltage input used to wake-up the device from sleep mode. It is usually connected to an external switch in the application to generate a local wake-up. If you
do not need a local wake-up in your application, connect pin WAKE directly to pin VS. A
pull-up current source with typically -10 µA is implemented. The voltage threshold for a
wake-up signal is 3 V below the VS voltage with an output current of typival -3 µA.
Wake-up events from sleep mode:
•
LIN bus
•
EN pin
•
WAKE pin
Figure 3 on page 5, Figure 4 on page 6 and Figure 5 on page 6 show details of wake-up
operations.
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4729D–AUTO–10/04
Mode of Operation
1. Normal mode
This is the normal transmitting and receiving mode. All features are available.
2. Sleep mode
In this mode the transmission path is disabled and the device is in low power
mode. Supply current from VBatt is typically 10 µA. A wake-up signal from the LIN
bus or via pin WAKE will be detected and switches the device to pre-normal
mode. If EN, then switches to high, normal mode is activated. Input debounce
timers at pin WAKE (TWAKE), LIN (TBUS) and EN (Tsleep,Tnom) prevent unwanted
wake-up events due to automotive transients or EMI. In sleep mode the INH pin
is floating. The internal termination between pin LIN and pin VS is disabled to
minimize the power dissipation in case pin LIN is short-circuited to GND. Only a
weak pull-up current (typical 10 µA) between pin LIN and pin VS is present.
3. Pre-normal mode
At system power-up, the device automatically switches to pre-normal mode. It
switches the INH pin to a high state, to the VS level. The microcontroller of the
application will then confirm the normal mode by setting the EN pin to high.
Remote Wake-up via
Dominant Bus State
A falling edge at pin LIN, followed by a dominant bus level maintained for a certain time
period (TBUS), results in a remote wake-up request. The device switches to pre-normal
mode. Pin INH is activated (switches to VS) and the internal termination resistor is
switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (see Figure 4 on page 6). The voltage threshold for a wake-up
signal is 3 V below the VS voltage with an output current of typival -3 µA.
Local Wake-up via Pin
WAKE
A falling edge at pin WAKE, followed by a low level maintained for a certain time period
(T WAKE ), results in a local wake-up request. The extra long wake-up time (T WAKE )
ensures that no transient, according to ISO7637, creates a wake-up. The device
switches to pre-normal mode. Pin INH is activated (switches to VS) and the internal termination resistor is switched on. The local wake-up request is indicated by a low level at
pin RXD to interrupt the microcontroller and a strong pull-down at pin TXD (see Figure 5
on page 6).
Wake-up Source
Recognition
The device can distinguish between a local wake-up request (pin WAKE) and a remote
wake-up request (dominant LIN bus). The wake-up source can be read on pin TXD in
pre-normal mode. If an external pull-up resistor (typically 5 kΩ) on pin TXD to the power
supply of the microcontroller has been added, a high level indicates a remote wake-up
request (weak pull-down at pin TXD) and a low level indicates a local wake-up request
(strong pull-down at pin TXD).
The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag
(signalled on pin TXD) are reset immediately, if the microcontroller sets pin EN to high
(see Figure 4 on page 6 and Figure 5 on page 6).
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ATA6661
4729D–AUTO–10/04
ATA6661
Figure 3. Mode of Operation
a: VS > 5 V
b: VS < 5 V
c: Bus wake-up event
d: Wake-up from Wake switch
Unpowered Mode, VBatt = 0 V
b
a
Pre-normal Mode
INH: high (INH internal High Side switch ON)
Communication: OFF
b
b
c
EN = 1
d
Go To sleep command
EN = 0
Normal Mode
INH: high (INH HS switch ON)
Communication: ON
Fail-safe Features
EN = 1
Local wake-up event
Sleep Mode
INH: high impedance (INH HS switch OFF)
Communication: OFF
•
There are now reverse currents <3 µA at pin LIN during loss of VBAT or GND.
Optimal behavior for bus systems where some slave modes supplied from battery or
ignition.
•
Pin EN provides pull-down resistor to force the transceiver into sleep mode if EN is
disconnected.
•
Pin RXD is set floating if VBAT is disconnected.
•
Pin TXD provides a pull-down resistor to provide a static low if TXD is disconnected.
•
The LIN output driver has a current limitation and if the junction temperature Tj
exceeds the thermal shut-down temperature Toff the output driver switches off.
•
The implemented hysteresis Thys enables the LIN output again after the temperature
has been decreased.
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4729D–AUTO–10/04
Figure 4. LIN Wake-up Waveform Diagram
LIN bus
INH
Low or floating
RXD
High or floating
High
Low
High
Bus Wake-up filtering time
(TBUS)
Voltage
Regulator
On state
Off state
Node ln
Operation
Regulator Wake-up time
delay
EN High
EN
Node ln sleep state
Microcontroller start-up time delay
Figure 5. LIN Wake-up from Wake-up Switch
Wake pin
INH
RXD
TXD
State change
High
Low or floating
High or floating
Low
TXD weak pull-down resistor
TXD strong pull down
High
weak
pull down
Wake filtering time
TWAKE
On state
Voltage
Regulator
Off state
Regulator Wake-up time
delay
Node ln
Operation
EN High
EN
Node ln sleep state
Microcontroller start-up time delay
6
ATA6661
4729D–AUTO–10/04
ATA6661
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Max.
Unit
-0.3
+40
V
Wake DC and transient voltage (with 33 kΩ serial resistor)
- Transient voltage due to ISO7637 (coupling 1 nF)
-40
-150
+40
+100
V
V
Logic pins (RXD, TXD, EN)
-0.3
+6
V
LIN
- DC voltage
- Transient voltage due to ISO7637 (coupling 1 nF)
-40
-150
+60
+100
V
V
INH
- DC voltage
-0.3
+40
V
ESD HBM (DIN EN 61000-4-2)
According LIN EMC Test Specification V1.3
- Pin VS, LIN
- Pin Wake (with 33 kΩ serial resistor)
-6000
-5000
+6000
+5000
V
V
HBM ESD S5.1 - All pins
-3000
+3000
V
CDM ESD STM 5.3.1-1999 - All pins
FCDM ESD STM 5.3.1- All pins
MM JEDEC A115A - All pins
-500
-1000
-200
+500
+1000
+200
V
V
V
Tj
-40
+150
°C
Storage temperature
Tstg
-55
+150
°C
Operating ambient temperature
Tamb
-40
+125
°C
Thermal shutdown
Toff
150
165
180
°C
Thermal shutdown hysteresis
Thys
5
10
20
°C
VS
- Continuous supply voltage
Junction temperature
Symbol
Min.
Typ.
Thermal Resistance
Parameters
Thermal resistance junction ambient
Symbol
Value
Unit
RthJA
160
K/W
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4729D–AUTO–10/04
Electrical Characteristics
5 V < VS < 18 V, Tamb = -40°C to +125°C
No.
1
Parameters
Nominal DC voltage range
1.2
Supply current in sleep mode
1.3
Supply current in normal mode
1.5
VS undervoltage threshold
1.6
VS undervoltage threshold
hysteresis
2
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
7
VS
5
13.5
18
V
A
Sleep mode
Vlin > VBatt - 0.5 V
VBatt < 14 V
7
IVSstby
10
20
µA
A
Bus recessive
7
IVSrec
1.6
3
mA
A
Bus dominant
Total bus load > 500 Ω
7
IVSdom
1.6
3
mA
A
4.6
5
V
A
V
A
8
mA
A
0.4
V
A
VS Pin
1.1
1.4
Test Conditions
VSth
7
VSth_hys
4
0.2
RXD Output Pin (Open Drain)
2.1
Low level input current
Normal mode
VLIN = 0 V, VRXD = 0.4 V
1
IRXDL
2.2
RXD saturation voltage
5 kΩ pull-up resistor to 5 V
1
VsatRXD
2.3
High level leakage current
Normal mode
VLIN = VBAT, VRXD = 5 V
1
IRXDH
-3
+3
µA
A
2.4
ESD zener diode
IRXD = 100 µA
1
VZRXD
6.1
8.6
V
A
4
VTXDL
-0.3
+0.8
V
A
3
2
TXD Input Pin
3.1
Low level voltage input
3.2
High level voltage input
4
VTXDH
2
3.3
Pull-down resistor
VTXD = 5 V
4
RTXD
125
3.4
Low level leakage current
VTXD = 0 V
4
ITXD
-3
3.5
Low-level input current at local
wake-up request
Pre-normal mode
VLIN = VBAT; VWAKE = 0 V
4
ITXDwake
2
4
5
250
5
7
V
A
600
kΩ
A
+3
µA
A
8
mA
A
EN Input Pin
4.1
Low level voltage input
2
VENL
-0.3
+0.8
V
A
4.2
High level voltage input
2
VENH
2
7
V
A
4.3
Pull-down resistor
VEN = 5 V
2
REN
125
600
kΩ
A
4.4
Low level input current
VEN = 0 V
2
IEN
-3
+3
µA
A
5
250
INH Output Pin
5.1
High level voltage
Normal mode
IINH = -200 µA
8
VINHH
VS - 0.8
VS
V
A
5.2
High level leakage current
Sleep mode
VINH = 27 V, VBatt = 27 V
8
IINHL
-3
+3
µA
A
3
VWAKEH
VS 1V
VS +
0.3 V
V
A
VS 3V
V
A
µA
A
6
WAKE Pin
6.1
High level input voltage
6.2
Low level input voltage
IWAKE = Typically -3 µA
3
VWAKEL
-27 V
6.3
Wake pull-up current
VS < 27 V
3
IWAKE
-30
-10
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8
ATA6661
4729D–AUTO–10/04
ATA6661
Electrical Characteristics (Continued)
5 V < VS < 18 V, Tamb = -40°C to +125°C
No.
Parameters
Test Conditions
6.4
High level leakage current
7
Pin
Symbol
Min.
VS = 27 V, VWAKE = 27 V
3
IWAKE
Typ.
Max.
Unit
Type*
-5
+5
µA
A
0.9 ×
VS
VS
V
A
LIN Bus Driver
7.1
Driver recessive output voltage
VTXD = 0 V, ILIN = 0 mA
6
VBUSrec
7.2
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVS = 7.3 V, Rload = 500 Ω
6
V_LoSUP
1.2
V
A
7.3
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVS = 18 V, Rload = 500 Ω
6
V_HiSUP
2
V
A
7.4
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVS = 7.3 V, Rload = 1000 Ω
6
V_LoSUP_1k
0.6
V
A
7.5
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVS = 18 V, Rload = 1000 Ω
6
V_HiSUP_1k_
0.8
V
A
7.6
Pull-up resistor to VS
The serial diode is
mandatory
6
RLIN
20
60
kΩ
A
7.7
Self-adapting current limitation
VBUS = VBAT_max
Tj = 125°C
Tj = 27°C
Tj = -40°C
6
IBUS_LIM
52
100
150
110
170
230
mA
mA
mA
A
7.8
Input leakage current at the
receiver, inclusive pull-up
resistor as specified
Input leakage current
Driver off
VBUS = 0 V, VBatt = 12 V
6
IBUS_PAS_dom
-1
mA
A
7.9
Leakage current LIN recessive
Driver off
8 V < VBAT < 18 V
8 V < VBUS < 18 V
VBUS ≥ VBAT
6
IBUS_PAS_rec
7.10
Leakage current at ground loss,
Control unit disconnected from
GNDDevice = VS
ground,
VBAT =12 V
Loss of local ground must not
0 V < VBUS < 18 V
affect communication in the
residual network
6
IBUS_NO_gnd
7.11
Node has to sustain the current
that can flow under this
condition, bus must remain
operational under this condition
VBAT disconnected
VSUP_Device = GND
0 V < VBUS < 18 V
6
IBUS
8
-10
30
15
20
µA
A
+0.5
+10
µA
A
0.5
3
µA
A
0.5 ×
VS
0.525
× VS
V
A
LIN Bus Receiver
8.1
Center of receiver threshold
VBUS_CNT =
(Vth_dom + Vth_rec)/2
6
VBUS_CNT
0.475 ×
VS
8.2
Receiver dominant state
VEN = 5 V
6
VBUSdom
-27
0.4 ×
VS
V
A
8.3
Receiver recessive state
VEN = 5 V
6
VBUSrec
0.6 ×
VS
40
V
A
8.4
Receiver input hysteresis
VHYS = Vth_rec - Vth_dom
6
VBUShys
0.028 ×
VS
0.175
× VS
V
A
8.5
Wake detection LIN
High level input voltage
6
VZINH
VS 1V
VS +
0.3 V
V
A
0.1 ×
VS
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
9
4729D–AUTO–10/04
Electrical Characteristics (Continued)
5 V < VS < 18 V, Tamb = -40°C to +125°C
No.
Parameters
Test Conditions
8.6
Wake detection LIN
Low level input voltage
8.7
LIN pull-up current
9
Pin
Symbol
Min.
Typ.
ILIN = Typically -3 µA
6
VLINL
-27 V
VS < 27 V
6
ILIN
-30
-10
Max.
Unit
Type*
VS 3V
V
A
µA
A
Internal Timers
9.1
Dominant time for wake-up via
LIN bus
VLIN = 0 V
6
TBUS
30
90
150
µs
A
9.2
Time of low pulse for wake-up
via pin WAKE
VWAKE = 0 V
3
TWAKE
60
130
200
µs
A
9.3
Time delay for mode change
from pre-normal mode to normal VEN = 5 V
mode via pin EN
2
Tnorm
4
10
15
µs
A
9.4
Time delay for mode change
from normal mode into sleep
mode via pin EN
VEN = 0 V
2
Tsleep
2
10
12
µs
A
9.5
TXD dominant time out timer
VTXD = 0 V
4
Tdom
4
9
20
ms
A
9.6
Power-up delay between
VS = 5 V until INH switches to
high
VVS = 5 V
200
µs
A
10
LIN Bus Driver (see Figure 6 on page 11)
Bus load conditions: Load1 small 1 nF 1 kΩ, Load2 big 10 nF 500 Ω, RRXD = 5 kΩ, CRXD = 20 pF;
The following two rows specifies the timing parameters for proper operation at 20.0 kBit/s.
10.1
10.2
11
TVS
Duty cycle 1
THRec(max) = 0.744 × VS
THDom(max) = 0.581 × VS
VS = 7.0 V to 18 V
tBit = 50 µs
D1 = tbus_rec(min)/(2 × tBit)
D1
Duty cycle 1
THRec(min) = 0.422 × VS
THDom(min) = 0.284 × VS
VS = 7.0 V to 18 V
tBit = 50 µs
D2 = tbus_rec(max)/(2 × tBit)
D2
0.581
6
µs
A
2
µs
A
0.396
A
A
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN receiver, RXD load conditions (CRXD): 20 pF, Rpull-up = 5 kΩ
11.1
Propagation delay of receiver
(see Figure 6 on page 11)
trec_pd = max(trx_pdr, trx_pdf)
trx_pd
11.2
Symmetry of receiver
propagation delay rising edge
minus falling edge
trx_sym = trx_pdr - trx_pdf
trx_sym
-2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
10
ATA6661
4729D–AUTO–10/04
ATA6661
Figure 6. Definition of Bus Timing Parameter
tBit
tBit
tBit
TXD
(Input to transmitting Node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
THRec(max)
receiving node 1
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
THRec(min)
receiving node 2
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving Node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving Node2)
trx_pdr(2)
trx_pdf(2)
11
4729D–AUTO–10/04
VBattery
10k
5V
I/O
SCI
Microcontroller
Vdd
12V
33k
WAKE
TXD
RXD
5k
3
4
1
VS
Wake-up
Timer
TXD
Time-out
Timer
ATA6661
EN
2
Standby mode
Control unit
Slew rate
control
Wake-up bus
timer
Receiver
INH
8
VS
Short circuit and
over- temperature
protection
Filter
5
6
7
GND
220pF
LIN
VS
1k
LIN sub bus
12
External
switch
22µF
100pF
Master node
pull up
Figure 7. Application Circuit
ATA6661
4729D–AUTO–10/04
ATA6661
Ordering Information
Extended Type Number
Package
ATA6661-TAQJ
Remarks
SO8
LIN transceiver
Package Information
Package SO8
Dimensions in mm
5.2
4.8
5.00
4.85
3.7
1.4
0.25
0.10
0.4
1.27
6.15
5.85
3.81
8
0.2
3.8
5
technical drawings
according to DIN
specifications
1
4
13
4729D–AUTO–10/04
Revision History
Please note that the referring page numbers in this section are referred to the specific
revision mentioned, not to this document.
Changes from Rev.
4729B - 05/04 to Rev.
4729C - 06/04
1. Table “Ordering Information” on page 13 changed.
Changes from Rev.
4729C - 06/04 to Rev.
4729D - 10/04
1. Put datasheet into new template (new last page)
2. Page 1: Features changed, Block diagram changed
3. Page 2: Bus Pin (LIN): Text changed
4. Page 3: TX Dominant Time-out Function: Text changed
5. Page 3: Output Pin (RXD): Text changed
6. Page 3: Inhibit Output Pin (INH): Text changed
7. Page 3: Wake-up Input Pin (WAKE): Text changed
8. Page 4: Remote Wake-up via Dominant Bus State: Text changed
9. Page 5: Section Fail-safe Features added
10. Page 7: Abs. Max. Ratings Tabelle: some changes
11. Pages 8-10: El. characteristics: changed rows: 1.3, 1.4, 1.5, 6.2, 7.9, 7.10, 7.11,
9.3
12. Pages 8-10: El. characteristics: changed rows: 2.4 (added), 8.5 (added), 8.6
(added), 8.7 (added)
13. Page 12: Application Circuit changed
14
ATA6661
4729D–AUTO–10/04
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4729D–AUTO–10/04