ICST ICS8430252CG-45LFT Femtoclocksâ ¢ crystal-to-3.3v lvpecl frequency synthesizer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8430252-45 is a 2 output LVPECL and
LVCMOS/LVTTL Synthesizer optimized to genHiPerClockS™ erate Ethernet reference clock frequencies and
is a member of the HiPerClocks™ family of high
performance clock solutions from ICS. Using a
25MHz, 18pF parallel resonant crystal, the following frequencies can be generated: 156.25MHz LVPECL output
and, 125MHz LVCMOS output. The 8430252-45 uses ICS’
3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS8430252-45 is
packaged in a small 16-pin TSSOP package.
• One differential 3.3V LVPECL output and
One LVCMOS/LVTTL output
ICS
• Crystal oscillator interface designed for a 25MHz,
18pF parallel resonant crystal
• A 25MHz crystal generates both an output frequency of
156.25MHz (LVPECL) and 125MHz (LVCMOS)
• VCO frequency: 625MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz) using
a 25MHz crystal: 0.39ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
OE
XTAL_IN
PIN ASSIGNMENT
Pullup
25MHz
÷5
OSC
Phase
Detector
VCO
625MHz
XTAL_OUT
CLK_EN
QB
÷4
Pullup
QA
Feedback Divider
÷25
nQB
OE
VEE
QA
VCCO_A
nc
nc
VCCA
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK_EN
VEE
QB
nQB
VCCO_B
XTAL_IN
XTAL_OUT
VEE
ICS8430252-45
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430252CG-45
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REV. B DECEMBER 9, 2005
1
PRELIMINARY
Integrated
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Systems, Inc.
ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
OE
2, 9, 15
VEE
Power
Description
Output enable pin. LVCMOS/LVTTL interface levels.
See Table 3A Function Table.
Negative supply pin.
3
QA
Output
LVCMOS/LVTTL clock output.
4
VCCO_A
Power
Output supply pin for QA output.
5, 6
nc
Unused
7
VCCA
Power
Analog supply pin.
8
Power
Core supply pin.
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
12
VCC
XTAL_OUT,
XTAL_IN
VCCO_B
Power
Output supply pin for QB, nQB outputs.
13, 14
nQB, QB
Output
16
CLK_EN
Input
Differential clock outputs. LVPECL interface levels.
Clock enable pin. LVCMOS/LVTTL interface levels.
See Table 3B Function Table.
10, 11
Type
Input
Pullup
No connect.
Pullup
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
RPULLUP
Input Pullup Resistor
VCC, VCCA, VCCO_A, VCCO_B = 3.465V
Minimum
Typical
Maximum
Units
4
pF
10
pF
51
kΩ
TABLE 3A. OE SELECT FUNCTION TABLE
Input
Output
OE
QA
0
Hi-Z
1
Active
TABLE 3B. CLK_EN SELECT FUNCTION TABLE
Input
Outputs
CLK_EN
QB
nQB
0
Low
High
1
Active
Active
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REV. B DECEMBER 9, 2005
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ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
89°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VCC
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO_A, VCCO_B
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
75
mA
ICCA
Analog Supply Current
8
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
Test Conditions
VIL
Input Low Voltage
IIH
Input High Current
OE, CLK_EN
VCC = VIN = 3.465V
IIL
Input Low Current
OE, CLK_EN
VCC = 3.465V, VIN = 0V
VOH
Output High Voltage; NOTE 1
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
5
-150
2.6
V
VOL
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50Ω to VCCO_A/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
0.5
V
Maximum
Units
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO_B - 2V.
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REV. B DECEMBER 9, 2005
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ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V±5%, TA = 0°C TO 70°C
Symbol
fOUT
tjit(Ø)
t R / tF
Parameter
Test Conditions
Minimum
Output Frequency Range
RMS Phase Jitter
(Random); NOTE 1
QA
Output
Rise/Fall Time
QA
QB, nQB
8430252CG-45
156.25
MHz
125
MHz
125MHz (1.875MHz - 20MHz)
0.41
ps
156.25MHz (1.875MHz - 20MHz)
0.39
ps
775
ps
390
ps
50
50
%
%
QB, nQB
20% to 80%
QA
QB, nQB
NOTE 1: Please refer to the Phase Noise Plots.
odc
Typical
Output Duty Cycle
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REV. B DECEMBER 9, 2005
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ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
➤
0
-10
-20
10Gb Ethernet Filter
-30
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.39ps (typical)
-80
-90
-100
-110
Raw Phase Noise Data
➤
NOISE POWER dBc
Hz
-40
-50
-60
-70
-120
-130
-140
➤
-150
-160
-170
-180
-190
Phase Noise Result by adding
10Gb Ethernet Filterto raw data
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV. B DECEMBER 9, 2005
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ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
1.65V±5%
V CC ,
VCCA, VCCO_B
Qx
SCOPE
SCOPE
VCC ,
VCCA , VCCO_A
LVPECL
VEE
Qx
LVCMOS
nQx
VEE
-1.3V±0.165V
-1.65V±5%
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
V
Noise Power
CCO_LVCMOS
2
QA
t PW
Phase Noise Mask
f1
Offset Frequency
t
odc =
f2
PERIOD
t PW
x 100%
t PERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQB
80%
QB
80%
t PW
t
odc =
PERIOD
t PW
Clock
Outputs
20%
20%
tR
tF
x 100%
t PERIOD
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
LVCMOS OUTPUT RISE/FALL TIME
80%
VSW I N G
Clock
Outputs
20%
20%
tR
tF
LVPECL OUTPUT RISE/FALL TIME
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REV. B DECEMBER 9, 2005
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ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430252-45 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
10 Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
parallel resonant crystal and were chosen to minimize the
ppm error.
The ICS8430252-45 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 25MHz, 18pF
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
8430252CG-45
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REV. B DECEMBER 9, 2005
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ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT
INPUTS:
AND
OUTPUT PINS
OUTPUTS:
SELECT PINS:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
TERMINATION
FOR
3.3V LVPECL OUTPUT
designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
8430252CG-45
FIN
50Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. B DECEMBER 9, 2005
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ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430252-45.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430252-45 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 75mA = 259.88mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 90mW
Total Power_MAX (3.465V, with all outputs switching) = 259.9mW + 60mW = 319.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.320W * 81.8°C/W = 96.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA
FOR
16-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(V
CCO_MAX
•
-V
OH_MAX
) = 0.9V
For logic low, VOUT = V
OL_MAX
(V
CCO_MAX
-V
OL_MAX
=V
CC_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))/R ] * (V
– (V
- 2V))/R ] * (V
-V
) = [(2V - (V
-V
-V
)=
Pd_H = [(V
OH_MAX
CC_MAX
CC_MAX
OH_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC_MAX
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430252-45 is: 2070
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PACKAGE OUTLINE - G SUFFIX
FOR
ICS8430252-45
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
16 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
16
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS8430252CG-45
30252C45
16 Lead TSSOP
tube
0°C to 70°C
ICS8430252CG-45T
30252C45
16 Lead TSSOP
2500 tape & reel
0°C to 70°C
ICS8430252CG-45LF
TBD
16 Lead "Lead-Free" TSSOP
tube
0°C to 70°C
ICS8430252CG-45LFT
TBD
16 Lead "Lead-Free" TSSOP
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
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