DS90CP04 www.ti.com SNLS154I – JANUARY 2002 – REVISED APRIL 2013 DS90CP04 1.5 Gbps 4x4 LVDS Crosspoint Switch Check for Samples: DS90CP04 FEATURES DESCRIPTION • • DS90CP04 is a 4x4 digital cross-point switch with broadside input and output pins for efficient board layout. It utilizes Low Voltage Differential Swing (LVDS) technology for low power, high-speed operation. Data paths are fully differential from input to output for low noise. The non-blocking architecture allows connections of any input to any output or outputs. The switch matrix consists of four differential 4:1 multiplexes. Each output channel connects to one of the four inputs common to all multiplexers. 1 2 • • • • • • • DC - 1.5 Gbps Low Jitter, Low Skew Operation Pin and Serial Interface Configurable, Fully Differential, Non-blocking Architecture Wide Input Common Mode Voltage Range Enables Easy Interface to LVDS/LVPECL/2.5VCML Drivers TRI-STATE LVDS Outputs Serial Control Interface with Read-back Capability Double Register Loading Single +2.5V Supply Small 6x6 mm WQFN-32 Space Saving Package Fabricated with Advanced CMOS Process Technology A simple serial control interface or a configuration select port is activated by the state of the MODE pin. When utilizing the serial control interface a single load command will update the new switch configuration for all outputs simultaneously. Functional Block Diagrams IN1+ IN1IN2+ IN2IN3+ IN3IN4+ IN4- 4:1 MUX4 EN4 OUT4+ OUT4- EN3 RSO RSCLK CSO CSCLK 4:1 MUX3 EN2 OUT2+ OUT2- EN1 Digital Control Interface OUT1+ OUT1- SCLK SI/SEL1 SEL0 LOAD MODE 4:1 MUX2 OUT3+ OUT3- 4:1 MUX1 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2013, Texas Instruments Incorporated DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 www.ti.com DIGITAL CONTROL INTERFACE SI/SEL1 INPUT REGISTER ROW DECREMENT ROW OUTPUT REGISTER RSO RSCLK COLUMN DECREMENT SEL0 SCLK CLOCK AND CONTROL COLUMN OUTPUT REGISTER MODE CSO CSCLK LOAD LOAD REGISTER SWITCH CONFIGURATION REGISTER Figure 1. Functional Block Diagram 2 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 DS90CP04 www.ti.com SNLS154I – JANUARY 2002 – REVISED APRIL 2013 VDD SI/SEL1 SCLK SEL0 GND RSCLK RSO VDD Connection Diagram 8 7 6 5 4 3 2 1 DAP = GND IN4- 9 32 OUT4- IN4+ 10 31 OUT4+ IN3- 11 30 OUT3- IN3+ 12 29 OUT3+ IN2- 13 28 OUT2- IN2+ 14 27 OUT2+ IN1- 15 26 OUT1- IN1+ 16 25 OUT1+ 21 22 23 LOAD MODE 24 VDD 20 GND CSO 19 GND 18 CSCLK 17 VDD DS90CP04 WQFN-32 6x6x0.75mm body size 0.5mm pitch Top View Shown Figure 2. Connection Diagram - 32 Pin (Top View) See Package Number NJE0032A PIN DESCRIPTIONS Pin Name Pin Number I/O, Type Description DIFFERENTIAL INPUTS COMMON TO ALL MUXES IN1+ IN1− 16 15 I, LVDS Inverting and non-inverting differential inputs. IN2+ IN2− 14 13 I, LVDS Inverting and non-inverting differential inputs. IN3+ IN3− 12 11 I, LVDS Inverting and non-inverting differential inputs. IN4+ IN4− 10 9 I, LVDS Inverting and non-inverting differential inputs. SWITCHED DIFFERENTIAL OUTPUTS OUT1+ OUT1− 25 26 O, LVDS Inverting and non-inverting differential outputs. OUT1± can be connected to any one pair IN1±, IN2±, IN3±, or IN4± OUT2+ OUT2− 27 28 O, LVDS Inverting and non-inverting differential outputs. OUT2± can be connected to any one pair IN1±, IN2±, IN3±, or IN4± OUT3+ OUT3− 29 30 O, LVDS Inverting and non-inverting differential outputs. OUT3± can be connected to any one pair IN1±, IN2±, IN3±, or IN4 OUT4+ OUT4− 31 32 O, LVDS Inverting and non-inverting differential outputs. OUT4± can be connected to any one pair IN1±, IN2±, IN3±, or IN4± Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 3 DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O, Type Description DIGITAL CONTROL INTERFACE SCLK 6 I, LVCMOS Control clock to latch in programming data at SI. SCLK can be 0 MHz to 100 MHz. SCLK should be burst of clock pulses active only while accessing the device. After completion of programming, SCLK should be kept at logic low to minimize potential noise injection into the high-speed differential data paths. SI / SEL1 7 I, LVCMOS Programming data to select the switch configuration. Data is latched into the input buffer register at the rising edge of SCLK. SEL0 5 I, LVCMOS Programming data to select the switch configuration. CSO RSO 18 2 O, LVCMOS With MODE low, control data is shifted out at CSO (RSO) for cascading to the next device in the serial chain. The control data at CSO (RSO) is identical to that shifted in at SI with the exception of the device column (row) address being decremented by one internally before propagating to the next device in the chain. CSO (RSO) is clocked out at the rising edge of SCLK. CSCLK RSCLK 19 3 O, LVCMOS With MODE low, these pins function as a buffered control clock from SCLK. CSCLK (RSCLK) is used for cascading the serial control bus to the next device in the serial chain. LOAD 22 I, LVCMOS When LOAD is high and SCLK makes a LH transition, the device transfers the programming data in the load register into the configuration registers. The new switch configuration for all outputs takes effect. LOAD needs to remain high for only one SCLK cycle to complete the process, holding LOAD high longer repeats the transfer to the configuration register. MODE 23 I, LVCMOS When MODE is low, the SCLK is active and a buffered SCLK signal is present at the CLKOUT output. When MODE is high, the SCLK signal is uncoupled from register and state machine internals. Internal registers will see an active low signal until MODE is brought Low again. VDD 1, 8, 17, 24 I, Power VDD = 2.5V ±5%. At least 4 low ESR 0.01 µF bypass capacitors should be connected from VDD to GND plane. GND 4, 20, 21, DAP I, Power Ground reference to LVDS and CMOS circuitry. DAP is the exposed metal contact at the bottom of the WQFN-32 package. The DAP is used as the primary GND connection to the device. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. POWER Serial Interface Truth Table LOAD MODE SCLK 0 0 LH The current state on SI is clocked into the input shift register. Resulting Action 0 1 LH Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and CSCLK outputs will drive an active Low signal until MODE is brought Low again. See Configuration Select Truth Table below. LH 0 X 1 1 LH Loads OUT1–OUT4 configuration information from last valid frame. Places contents of load register into the configuration register. The switch configuration is updated asynchronously from the SCLK input. Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and CSCLK outputs will drive an active Low signal until MODE is brought Low again. See Configuration Select Truth Table below. Configuration Select Truth Table 4 MODE SEL1 SEL0 0 X X The SEL0/1 pins only function in configuration select mode. See below. Resulting Action 1 0 0 Distribution: IN1 - OUT1 OUT2 OUT3 OUT4 1 0 1 Distribution: IN2 - OUT1 OUT2 OUT3 OUT4 1 1 0 Redundancy: IN1 - OUT1 OUT2 and IN3 - OUT3 OUT4 1 1 1 Broadside: IN1 - OUT1, IN2 - OUT2, IN3 - OUT3, IN4 - OUT4 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 DS90CP04 www.ti.com SNLS154I – JANUARY 2002 – REVISED APRIL 2013 SEL0 = 1 SEL1 = 1 IN1+ SEL0 = 0 SEL1 = 0 OUT1+ IN1+ OUT1+ IN1- OUT1- IN1- OUT1- IN2+ OUT2+ OUT2+ IN2- OUT2- OUT2- IN3+ OUT3+ OUT3+ IN3- OUT3- OUT3- IN4+ OUT4+ OUT4+ IN4- OUT4- OUT4- SEL0 = 0 SEL1 = 1 SEL0 = 1 SEL1 = 0 IN1+ OUT1+ OUT1+ IN1- OUT1- OUT1- OUT2+ IN2+ OUT2+ OUT2- IN2- OUT2- IN3+ OUT3+ OUT3+ IN3- OUT3- OUT3- OUT4+ OUT4+ OUT4- OUT4- Figure 3. DS90CP04 Configuration Select Decode These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 5 DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 Absolute Maximum Ratings www.ti.com (1) (2) −0.3V to +3V Supply Voltage (VDD) −0.3V to (VDD +0.3V) CMOS/TTL Input Voltage −0.3V to +3.3V LVDS Receiver Input Voltage −0.3V to +3V LVDS Driver Output Voltage LVDS Output Short Circuit Current 40mA Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 sec.) +260°C Maximum Package Power Dissipation at 25°C WQFN-32 3200 mW Derating above 25°C 38 mW/°C Thermal Resistance, θJA 26.4°C/W ESD Rating HBM, 1.5 kΩ, 100 pF LVDS Outputs >1.0 kV LVDS Inputs >1.5 kV All Other Pins >4.0 kV EIAJ, 0Ω, 200 pF >100V (1) (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. Recommended Operating Conditions Min Typ Max Unit Supply Voltage (VDD– GND) 2.375 2.5 2.625 V Receiver Input Voltage 0.05 3.3 V Operating Free Air Temperature −40 85 °C 110 °C 25 Junction Temperature Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions (1) Min Typ (2) Max Units LVCMOS/LVTTL DC SPECIFICATIONS (SCLK, SI/SEL1, SEL0, LOAD, MODE , CSCLK, RSCLK, CSO, RSO) VIH High Level Input Voltage 1.7 VDD V VIL Low Level Input Voltage GND 0.7 V IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA CIN1 Input Capacitance Any Digital Input Pin to VSS COUT1 Output Capacitance Any Digital Output Pin to VSS VCL Input Clamp Voltage ICL = −18 mA VOH High Level Output Voltage IOH = −4.0 mA, VDD = VDDMIN 1.9 V IOH = −100 µA, VDD = 2.5V 2.4 V VOL Low Level Output Voltage −1.5 3.5 pF 5.5 pF −0.8 V IOL = 4.0 mA, VDD = VDDMIN 0.4 V IOL = 100 µA, VDD = 2.5V 0.1 V LVDS INPUT DC SPECIFICATIONS (IN1±, IN2±, IN3±, IN4±) (1) (2) 6 “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. Typical parameters are measured at VDD = 2.5V, TA = 25°C. They are for reference purposes, and are not production-tested. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 DS90CP04 www.ti.com SNLS154I – JANUARY 2002 – REVISED APRIL 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless other specified. (1) Symbol Parameter Conditions Min Typ (2) Max Units 50 mV VTH Differential Input High Threshold VCM = 0.05V or 1.2V or 2.45V, VDD = 2.5V VTL Differential Input Low Threshold VCM = 0.05V or 1.2V or 2.45V, VDD = 2.5V VID Differential Input Voltage VDD = 2.5V, VCM = 0.05V to 2.45V 100 VDD VCMR Common Mode Voltage Range VID = 100 mV, VDD = 2.5V 0.05 3.25 CIN2 Input Capacitance IN+ or IN− to VSS IIN Input Current VIN = 2.5V, VDD = VDDMAX or 0V −10 +10 µA VIN = 0V, VDD = VDDMAX or 0V −10 +10 µA 475 mV 35 mV 1.375 V −35 35 mV +10 µA (3) 0 −50 0 mV 3.5 mV V pF LVDS OUTPUT DC SPECIFICATIONS (OUT1±, OUT2±, OUT3±, OUT4±) VOD Differential Output Voltage ΔVOD Change in VOD between Complementary States (3) RL = 100Ω between OUT+ and OUT− (see Figure 4) 250 400 −35 (4) VOS Offset Voltage ΔVOS Change in VOS between Complementary States IOZ Output TRI-STATE Current TRI-STATE Output VOUT = VDD or VSS −10 IOFF Power Off Leakage Current VDD = 0V, VOUT = 2.5V or GND −10 +10 µA IOS Output Short Circuit Current, One Complementary Output OUT+ or OUT− Short to GND −15 -40 mA OUT+ or OUT− Short to VDD 15 40 mA Output Short Circuit Current, both Complementary Outputs OUT+ and OUT− Short to GND −15 -30 mA OUT+ and OUT− Short to VCM 15 30 mA Output Capacitance OUT+ or OUT− to GND when TRISTATE 5.5 All inputs and outputs enabled, terminated with differential load of 100Ω between OUT+ and OUT-. 220 300 mA TRI-STATE All Outputs 10 20 mA 100 135 160 ps 100 135 160 ps 500 750 1200 ps 500 750 1200 ps 0 30 ps IOSB COUT2 1.125 1.25 pF SUPPLY CURRENT ICCD ICCZ Total Supply Current TRI-STATE Supply Current SWITCHING CHARACTERISTICS—LVDS OUTPUTS ( (5), tLHT Differential Low to High Transition Time tHLT Differential High to Low Transition Time tPLHD Differential Low to High Propagation Delay tPHLD Differential High to Low Propagation Delay tSKD1 Pulse Skew (3) (4) (5) (6) (7) (6) (7) , ) Use an alternating 1 and 0 pattern at 200 Mb/s, measure between 20% and 80% of VOD. Use an alternating 1 and 0 pattern at 200 Mb/s, measure at 50% VOD between input to output. |tPLHD–tPHLD| Differential output voltage VOD is defined as |OUT+–OUT−|. Differential input voltage VID is defined as |IN+–IN−|. Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Differential output voltage VOD is defined as |OUT+–OUT−|. Differential input voltage VID is defined as |IN+–IN−|. Characterized from any input to any one differential LVDS output running at the specified data rate and data pattern, with all other 3 channels running K28.5 pattern at 1.25 Gb/s asynchronously to the channel under test. Jitter is not production-tested, but ensured through characterization on sample basis. Random Jitter is measured peak to peak with a histogram including 1000 histogram window hits. K28.5 pattern is repeating bit streams of (0011111010 1100000101). This deterministic jitter or DJ pattern is measured to a histogram mean with a sample size of 350 hits. Like RJ the Total Jitter or TJ is measured peak to peak with a histogram including 3500 window hits. The LVCMOS input and output AC specifications may also be verified and tested using an input attenuation network instead of a power splitter. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 7 DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless other specified. (1) Symbol tSKCC tJIT Parameter Output Channel to Channel Skew Jitter (6) Conditions Min Difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to all outputs). 0 Typ (2) Max Units 50 100 ps 750 MHz 1.6 2.5 psrms 1.25 GHz 1.6 2.5 psrms 1.5 Gb/s 10 40 psp-p 2.5 Gb/s 27 60 psp-p 1.5 Gb/s 25 40 psp-p 2.5 Gb/s 40 70 psp-p 150 300 ns Time from LOAD = LH or SELx to OUT± change from active to TRISTATE. 3 5 ns Alternating 1 and 0 Pattern K28.5 Pattern PRBS 223-1 Pattern tON LVDS Output Enable Time tOFF LVDS Output Disable Time Time from LOAD = LH or SELx to OUT± change from TRI-STATE to active. 50 tSW LVDS Switching Time Time from LOAD = LH to new switch configuration effective for OUT±. 50 150 ns tSEL SELx to OUT± Configuration select to new data at OUT±. 50 150 ns 0 100 MHz 45 55 % SWITCHING CHARACTERISTICS — Serial control Interface ( (8) ) FSCLK SCLK Clock Frequency TDCCLK CSCLK Duty Cycle RSCLK Duty Cycle Input SCLK Duty Cycle set at 50% tS SI–SCLK or MODE–SCLK Setup Time From SI or MODE Input Data to SCLK Rising Edge 1.5 ns tH SCLK–SI or SCLK–MODE Hold Time From SCLK Rising Edge to SI or MODE Input Data 1 ns tDSO SCLK to RSO or CSO Delay From SCLK to RSO or CSO 1.5 4 ns tDSCLK SCLK to RSCLK or CSCLK Delay From SCLK to RSCLK or CSCLK 4.0 8.5 ns tDSDIF |SCLK to RSCLK or CSCLK–SCLK to RSO or CSO| Propagation Delay Difference between tDSO and tDSCLK 1.5 4.5 ns TRISE Logic Low to High Transition Time 20% to 80% at RSO, CSO, RSCLK, or CSCLK 1.5 ns TFALL Logic High to Low Transition Time 80% to 20% at RSO, CSO, RSCLK, or CSCLK 1.5 ns (8) 8 Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 DS90CP04 www.ti.com SNLS154I – JANUARY 2002 – REVISED APRIL 2013 DC Source >100K IN+ VDC1 IN- R VDC2 M U X OUT+ RL/2 OUT- RL/2 >100K 49.99 VOUT+ D VOS VOD = |VOUT+ - VOUT-| 49.99 VOUT>100K Figure 4. Differential Driver DC Test Circuit OUT+ and OUT- are connected to a 100: differential transmission line VDD = 2.50V ADVANTEST D3186 Data Generator CSA8000 DC BLOCK VID=250mV VOS=1.20V + TRIG M U X IN+ R IN- Coax 50 OUT+ D OUTDC BLOCK 50: Coax 50: DUT 50 VSS = 0.0V VOD = |VOUT+ - VOUT-| Coax 50 Figure 5. Differential Driver AC Test Circuit Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 9 DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 www.ti.com 950: resistors provide a 20:1 attenuation network with CSA8000. 50: Tek DG2020 Pulse Generator VOH = VDD VOL = GND VDD= 2.50V CL is a lumped capacitance placed as close as possible to the device output. CSA8000 950: MODE MODE RSO LOAD LOAD RSCLK SI/SEL1 SI/SEL1 SCLK SEL0 CSO SCLK SEL0 TRIG 50: Scope Termination CSCLK DUT CL = 15pF VSS= 0.0V 50: Scope Termination 450: 450: resistors provide a 10:1 attenuation network with CSA8000. Figure 6. LVCMOS Driver AC Test Circuit (9) (9) ) The LVCMOS input and output AC specifications may also be verified and tested using an input attenuation network instead of a power splitter. Parameter Measurement Information IN+ VOS=1.2V typical IN- IN+ VID IN- Figure 7. LVDS Signals 10 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 DS90CP04 www.ti.com SNLS154I – JANUARY 2002 – REVISED APRIL 2013 (OUT+ - OUT-) 80% 80% 0V 20% 20% tLHT tHLT OUT+ VOD OUT- Figure 8. LVDS Output Transition Time (IN+ - IN-) 0.0V tPLHD tPHLD (OUT+ - OUT-) 0.0V Figure 9. LVDS Output Propagation Delay SCLK tS SI tH VALID DATA WINDOW VALID DATA WINDOW tDSO RSO CSO tDSCLK RSCLK CSCLK tDSDIF Figure 10. Serial Interface Propagation Delay and Input Timing Waveforms Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 11 DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 www.ti.com SCLK tS tH MODE SCLK (Internal) tDSCLK RSCLK CSCLK Figure 11. Serial Interface— MODE Timing and Functionality Load Configuration "A" Load Configuration "B" LOAD or SELx tSW tSW OUT± Configuration "A" tOFF Configuration "B" tON 50% OUT+ 50% 1.2V 1.2V OUT- 50% 50% Figure 12. Configuration and Output Enable/Disable Timing 12 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 DS90CP04 www.ti.com SNLS154I – JANUARY 2002 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTIONS Programming with the Serial Interface The configuration of the internal multiplexer is programmed through a simple serial interface consisting of serial clock SCLK and serial input data line SI. The serial interface is designed for easy expansion to larger switch array. A replicated output serial interface (RSCLK, RSO) is provided for propagating the control data to the downstream device in the row of an array of DS90CP04 devices in a matrix. A similar replicated serial interface (CSCLK, CSO) is provided for propagating the control data to the downstream devices in the first column of the device matrix. Through this scheme, user can program all the devices in the matrix through one serial control bus (SCLK and SI) with the use of the feed-through replicated control bus at RSCLK and RSO, CSCLK and CSO. To program the configuration of the switch, a 30-bit control word is sent to the device. The first 6 bits shift the start frame into SI. The only two valid start frames are 1F'h for a configuration load and 1E'h for a configuration read. The start frame is followed by the row and column addresses of the device to be accessed, as well as the switch configuration of the four channels of the device. Table 1 and Table 2 are the bit definitions of the control word. D29 is the first bit that shifts into SI. Table 1. 30-Bit Control Word Bit Bit Length Descriptions D29–D24 6 The start frame for control word synchronization (01 1111'b = LOAD). D23–D18 6 Specify the row address of the device to be access. The serial interface can access up to 64 devices in the row. D17–D12 6 Specify the column address of the device to be access. The serial interface can access up to 64 devices in the column. D11–D9 3 Specify the switch configuration for Output 1. See Table 2. D8–D6 3 Specify the switch configuration for Output 2. See Table 2. D5–D3 3 Specify the switch configuration for Output 3. See Table 2. D2–D0 3 Specify the switch configuration for Output 4. See Table 2. Table 2. Switch Configuration Data MSB LSB OUT1± Connects to OUT2± Connects to OUT3± Connects to OUT4± Connects to 0 0 0 Output 1 Tri-Stated Output 2 Tri-Stated Output 3 Tri-Stated Output 4 Tri-Stated 0 0 1 IN1± IN1± IN1± IN1± 0 1 0 IN2± IN2± IN2± IN2± 0 1 1 IN3± IN3± IN3± IN3± 1 0 0 IN4± IN4± IN4± IN4± 1 0 1 Invalid. 1 1 0 Use of these invalid combinations may cause loss of synchronization. 1 1 1 Row and Column Addressing The upper left device in an array of NxN devices is assigned row address 0, and column address 0. The devices to its right have column addresses of 1 to N, whereas devices below it have row addresses of 1 to N. The Serial Control Interface (SCLK and SI) is connected to the first device with the row and column addresses of 0. The Serial Control Interface shifts in a control word containing the row and column address of the device it wants to access. When the control data propagates through each device, the control word's address is internally decremented by one before it is sent to the next row or column device. When the control data is sent out the column interface (CSO and CSCLK) the row address is decremented by one. Similarly, when the column address data is shifted out the row interface (RSO and RSCLK) the column address is decremented by one. By the time the control word reaches the device it has been intended to program, both the row and column addresses have been decremented to 0. Each device constantly checks for the receipt of a frame start (D29-24=01 1111'b or 01 1110'b). When it detects the proper start frame string, and the row and column addresses it receives are both 0, the device responds by storing the switch configuration data of the 30-bit control word into its load register. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 13 DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 www.ti.com Each device in the array is sequentially programmed through the serial interface. When programming is completed for the entire array, LOAD is pulsed high and the load register's content is transferred to the configuration register of each device. The LOAD pulse must wait until the final bit of the control word has been placed into the "load" register. This timing is ensured to take place two clock cycles after programming has been completed. Due to internal shift registers additional SCLK cycles will be necessary to complete array programming. It takes 7 clock (SCLK) positive edge transitions for the control data to appear at RSO and CSO for its near neighbor. Users must provide the correct number of clock transitions for the control data word to reach its destination in the array. Table 3 shows an example of the control data words for a 4 device serial chain with connections (OUT1=IN1, OUT2=IN2, OUT16=IN16). To program the array, it requires four 30-bit control words to ripple through the serial chain and reach their destinations. In order to completely program the array in the 120 clock cycles associated with the 30-bit control words it is important to program the last device in the chain first. The following programming data pushes the initial data through the chain into the correct devices. Read-Back Switch Configuration The DS90CP04 is put into read-back mode by sending a special “Read” start frame (01 1110'b). Upon receipt of the special read start frame the configuration register information is transferred into the shift register and output at both RSO and CSO in the OUT1 to OUT4 bit segments of the read control word. Each time the read-back data from a device passes through its downstream device, its default address (11 1111'b) is internally decremented by one. The “relative” column address emerges at RSO of the last device in the row and is used to determine (11 1111'b - N) the column of the sending device. Similarly, the row address emerges at CSO of the sending device. After inserting the channel configuration information in the “read” control word, the device will automatically revert to write mode, ready to accept a new control word at SI. Table 4 shows an example of reading back the configuration registers of 4 devices in the first row of a 4x4 device array. Again, due to internal shift registers additional SCLK cycles will be necessary to complete the array read. It takes 4x30 SCLK clock cycles to shift out 4 30-bit configuration registers plus 7 SCLK cycles per device to account for device latency making for a total SCLK count of 148. The serialized read data is sampled at RSO and synchronized with RSCLK of the last device in the row. The user is recommended to backfill with all 0's at SI after the four reads have been shifted in. Table 3. Example to Program a 4 Device Array OUT4 D2:D0 Number of SCLK Cycles Control Word Destination Device in Array Row, Column 011 100 30 0, 3 010 011 100 30 0, 2 010 011 100 30 0, 1 010 011 100 30 0, 0 Frame D29:D24 Row Address D23:D18 Column Address D17:D12 OUT1 D11:D9 OUT2 D8:D6 OUT3 D5:D3 01 1111 00 0000 00 0011 001 010 01 1111 00 0000 00 0010 001 01 1111 00 0000 00 0001 001 01 1111 00 0000 00 0000 001 Shift in configuration information from device furthest from system SI input first to minimize array latency during the programming process. The 2 clock cycle delay ensures all channel information has reached the “load” register and all switches are ready to be configured. 2 Table 4. A Read-Back Example from a 4 Device Array 14 Frame D29:D24 Row Address D23:D18 Column Address D17:D12 OUT1 D11:D9 OUT2 D8:D6 OUT3 D5:D3 OUT4 D2:D0 Number of SCLK Cycles Descriptions 01 1110 00 0000 11 1111 000 000 000 000 30 Read-Back (R,C)=0, 3 01 1110 00 0000 11 1110 000 000 000 000 30 Read-Back (R,C)=0, 2 01 1110 00 0000 11 1101 000 000 000 000 30 Read-Back (R,C)=0, 1 01 1110 00 0000 11 1100 001 010 011 100 30 Read-Back (R,C)=0, 0 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 DS90CP04 www.ti.com SNLS154I – JANUARY 2002 – REVISED APRIL 2013 Switch Expansion For Minimum Programming Latency Programming data ripples through the array through RSO and RSCLK in the row and CSO and CSCLK in the first column. LOAD pins of all devices are electrically tied together and driven by the same “load” signal. To prevent excessive stub length in the array from affecting the signal quality of LOAD, it is recommended that the load signal is distributed to each row or column in large crosspoint array applications. NUMBER OF SCLK POSITIVE EDGE TRANSITIONS 0 DEVICE 0 DEVICE 1 (+7 Clocks) 30 60 CONTROL WORD 1 CONTROL WORD 1 [01 F] [1][0] [1][1][1][1] [01 F] [0][0] [2][2][4][4] [01 F] [0][0] [1][1][1][1] [01 F] [3F][0] [2][2][4][4] Device 1 Configuration Ready to Load Device 0 Configuration Ready to Load Programming Example CONFIGURATION WRITE 30 Bit Control Word: [WRITE FRAME] [ROW ADDRESS][COLUMN ADDRESS] [OUT1][OUT2][OUT3][OUT4] ARRAY WRITE [01 1111] [0][1] [1][1][1][1] //*Array position 1, Broadcast IN1 *// [01 1111] [0][0] [2][2][4][4] //*Array position 0, Connect IN2 to OUT1 and 2, IN4 to OUT3 and OUT4 *// LOAD = H and SCLK = LH NUMBER OF SCLK POSITIVE EDGE TRANSITIONS 0 DEVICE 0 DEVICE 1 (+7 Clocks) DEVICE 2 (+14 Clocks) DEVICE 3 (+21 Clocks) 30 60 90 120 CONTROL WORD 1 CONTROL WORD 2 CONTROL WORD 3 CONTROL WORD 4 [01 F] [0][3] [4][4][4][4] [01 F] [0][2] [0][3][0][0] [01 F] [0][1] [0][0][2][0] [01 F] [0][0] [1][2][3][4] [01 F] [0][2] [4][4][4][4] [01 F] [0][1] [0][3][0][0] [01 F] [0][1] [4][4][4][4] [01 F] [0][0] [0][0][2][0] [01 F] [0][0] [0][3][0][0] [01 F] [0][0] [4][4][4][4] Device 3 Configuration Ready to Load [01 F] [0][3F] [1][2][3][4] [01 F] [0][3F] [0][0][2][0] [01 F] [0][3F] [0][3][0][0] Device 2 Configuration Ready to Load 150 [01 F] [0][3E] [1][2][3][4] [01 F] [0][3E] [0][0][2][0] Device 1 Configuration Ready to Load [01 F] [0][3D] [1][2][3][4] Device 0 Configuration Ready to Load Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 15 DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 www.ti.com DEVICE 0 WRITE PROGRAMMING SEQUENCE SCLK Number Event Description 6 Device 0 (R=0, C=0) detects “WRITE” frame of first Control Word. 18 Device 0 (R=0, C=0) sees Row = 1, Column = 0 of first Control Word. The Row address of the first Control Word is decremented by 1 (Row Address = 0) and sent out RSO. 36 Device 0 (R=0, C=0) detects “WRITE” frame of second Control Word. 48 Device 0 (R=0, C=0) sees Row = 0, Column = 0 of second Control Word. This is a valid configuration write address, Device 1 prepares to receive configuration information. 60 Device 0 (R=0, C=0) has received configuration information and is waiting for a LOAD. DEVICE 1 WRITE PROGRAMMING SEQUENCE SCLK Number Event Description 13 Device 1 (R=1, C=0) detects “WRITE” frame of first Control Word. 25 Device 1 (R=1,C=0) sees Row = 0, Column = 0 of first Control Word. This is a valid configuration write address, Device 1 prepares to receive configuration information. 37 Device 1 (R=1,C=0) has received configuration information and is waiting for a LOAD. 43 Device 1 (R=1, C=0) detects “WRITE” frame of second Control Word. 55 Device 1 (R=1,C=0) sees Row = 3F, Column = 0 of second Control Word. The Row address of the second Control Word is decremented by 1 (Row Address = 3E) and sent out RSO. CONFIGURATION READ 30 Bit Control Word: [READ FRAME] [ROW ADDRESS][COLUMN ADDRESS] [OUT1][OUT2][OUT3][OUT4] ARRAY WRITE [01 1110] [1][0] [0][0][0][0] //*Array position 1, Return Configuration Information *// [01 1110] [0][0] [0][0][0][0] //*Array position 0, Return Configuration Information *// NUMBER OF SCLK POSITIVE EDGE TRANSITIONS 0 DEVICE 0 DEVICE 1 (+7 Clocks) DEVICE 2 (+14 Clocks) DEVICE 3 (+21 Clocks) 30 60 90 CONTROL WORD 1 CONTROL WORD 2 CONTROL WORD 3 [01 E] [0][3] [0][0][0][0] [01 E] [0][2] [0][0][0][0] [01 E] [0][1] [0][0][0][0] [01 E] [0][2] [0][0][0][0] [01 E] [0][1] [0][0][0][0] [01 E] [0][1] [0][0][0][0] [01 E] [0][0] [0][0][0][0] [01 E] [0][3F] [1][2][3][4] [01 F] [0][3F] [0][0][2][0] [01 E] [0][3F] [0][3][0][0] [01 E] [0][3E] [1][2][3][4] [01 E] [0][3E] [0][0][2][0] Device 3 Configuration Read Out [01 E] [0][3F] [4][4][4][4] Device 2 Configuration Read Out [01 E] [0][3E] [0][3][0][0] Device 1 Configuration Read Out [01 E] [0][3D] [0][0][2][0] 16 150 CONTROL WORD 4 [01 E] [0][0] [0][0][0][0] [01 E] [0][0] [0][0][0][0] [01 E] [0][0] [0][0][0][0] 120 Submit Documentation Feedback [01 E] [0][3D] [1][2][3][4] Device 0 Configuration Read Out [01 E] [0][3C] [1][2][3][4] Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 DS90CP04 www.ti.com SNLS154I – JANUARY 2002 – REVISED APRIL 2013 DEVICE 0 READ PROGRAMMING SEQUENCE SCLK Number Event Description 6 Device 0 (R=0, C=0) detects “READ” frame of first Control Word. 18 Device 0 (R=0,C=0) sees Row = 1, Column = 0 of first Control Word. The Row address of the first Control Word is decremented by 1 (Row Address = 0) and sent out RSO. 36 Device 0 (R=0,C=0) detects "READ" frame of second Control Word. 48 Device 0 (R=0,C=0) sees Row = 0, Column = 0 of second Control Word. This is a valid configuration read address, Device 0 prepares to transmit configuration information. The Row address of the last Control Word is decremented by 1 (Row Address = 3F) and sent out RSO. 60 Device 0 (R=0,C=0) has transmitted configuration information. 74 Finished transmitting configuration information at Array Output (RSO of Device 1). DEVICE 1 READ PROGRAMMING SEQUENCE SCLK Number Event Description 13 Device 1 (R=1, C=0) detects “READ” frame of first Control Word. 25 Device 1 (R=1,C=0) sees Row = 0, Column = 0 of first Control Word. This is a valid configuration read address, Device 1 prepares to transmit configuration information. The Row address of the last Control Word is decremented by 1 (Row Address = 3F) and sent out RSO. 37 Device 1 (R=1,C=0) has transmitted configuration information at Array Output (RSO of Device 1). Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 17 DS90CP04 SNLS154I – JANUARY 2002 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision H (April 2013) to Revision I • 18 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 17 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: DS90CP04 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS90CP04TLQ NRND WQFN NJE 32 250 TBD Call TI Call TI -40 to 85 90CP04T DS90CP04TLQ/NOPB ACTIVE WQFN NJE 32 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 90CP04T DS90CP04TLQX/NOPB ACTIVE WQFN NJE 32 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 90CP04T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS90CP04TLQ WQFN NJE 32 DS90CP04TLQ/NOPB WQFN NJE DS90CP04TLQX/NOPB WQFN NJE SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 32 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 32 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90CP04TLQ WQFN NJE 32 250 213.0 191.0 55.0 DS90CP04TLQ/NOPB WQFN NJE 32 250 213.0 191.0 55.0 DS90CP04TLQX/NOPB WQFN NJE 32 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA NJE0032A LQA32A (REV A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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