ICST ICS674R-01IT User configurable divider Datasheet

PRELIMINARY INFORMATION
ICS674-01
User Configurable Divider
Description
Features
The ICS674-01 consists of 2 separate
configurable dividers. The A Divider is a 7 bit
divider and can divide by 3 to 129. The
B Divider consists of a 9 bit divider followed by a
post divider. The 9 bit divider can divide by 12
to 519. The post divider has eight settings of
1, 2, 4, 5, 6, 7, 8 and 10 giving a maximum total
divide of 5190. The A and B Dividers can be
cascaded to give a maximum divide of 669510.
The ICS674-01 supports the ICS673 PLL
Building Block and enables the user to build a full
custom PLL synthesizer.
• Packaged as 28 pin SSOP (150 mil body)
• Supports ICS673 PLL Building Block
• User determines the divide by setting input pins
• Pull-ups on all select inputs
• Includes one 7-bit Divider for OUTA
• Includes one 9-bit Divider and one selectable
Post Divider for OUTB
• Operating voltages of 3.3 V or 5.0 V
• Industrial temperature range available
• 25mA drive capability at TTL levels
• Advanced, low power CMOS process
Block Diagram
A6:A0
7
INA
INB
VDD
2
GND
3
Divider A
(7-Bit)
Divider B
(9-Bit)
Post
Divider
9
3
B8:B0
S2:S0
Output
Buffer
OUTA
Output
Buffer
OUTB
1
Revision 033199
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
MDS 674-01 A
PRELIMINARY INFORMATION
Pin Assignment
A5
A6
S0
S1
S2
VDD
INA
INB
GND
B0
B1
B2
B3
B4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ICS674-01
User Configurable Divider
Post Divider Table
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A4
A3
A2
A1
A0
VDD
OUTA
OUTB
GND
GND
B8
B7
B6
B5
S2
pin 5
0
0
0
0
1
1
1
1
S1
pin 4
0
0
1
1
0
0
1
1
S0
pin 3
0
1
0
1
0
1
0
1
Post
Divide
10
2
8
4
5
7
1
6
Pin Description
Pin #
Name
1, 2, 24-28
A5, A6, A0-A4
3, 4, 5
S0, S1, S2
6, 23
VDD
P
Connect to VDD.
7
INA
I
Divider A input.
8
INB
I
Divider B input.
9, 19, 20
GND
P
Connect to ground.
10-18
B0-B8
21
OUTB
O
Divider B output.
22
OUTA
O
Divider A output.
Key:
Type Description
I(PU) Divider A word input pins. Forms a binary number from 3 to 129.
I(PU) Select pins for Post Divider. See table above.
I(PU) Divider B word input pins. Forms a binary number from 12 to 519.
I(PU) = Input with internal pull-up resistor; I=Input (no pull-up); O = Output;
P = Power supply connection
External Components
The ICS674-01 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It
must be connected close to the ICS674-01 to minimize lead inductance. Terminating resistors of 33Ω can
be used in series with the OUTA and OUTB pins.
2
Revision 033199
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
MDS 674-01 A
PRELIMINARY INFORMATION
ICS674-01
User Configurable Divider
Determining (setting) the divider
The user has full control in setting the desired divide. The user should connect the appropriate divider select
input pins directly to ground (or VDD, although this is not required because of internal pull-ups) during
Printed Circuit Board layout, so that the ICS674-01 automatically produces the correct divide when all
components are soldered. It is also possible to connect the inputs to parallel I/O ports in order to change
divides.
The divides of the ICS674-01 can be determined by the following simple equations:
Divide A = DAW+2
Where
Divider A Word (DAW) = 1 to 127 (0 is not permitted).
Divide B = (DBW+8)•PD
Where
Divider B Word (DBW) = 4 to 511 (0,1,2,3, are not permitted).
Post Divider (PD) = values on Page 2
For example, suppose Divide A is desired to be 61 and Divide B is desired to be 284, then
DAW = 59, DBW = 276 and PD = 1. This means A6:A0 is 0111011, B8:B0 is
100010100 and S2:S0 is 110. Since all inputs have pull-ups, it is only necessary to ground
the zero pins, namely A6, A2, B7, B6, B5, B3, B1, B0 and S0.
3
Revision 033199
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
MDS 674-01 A
PRELIMINARY INFORMATION
ICS674-01
User Configurable Divider
Using the ICS674-01 with the ICS673-01:
The ICS674-01 may be used with the ICS673-01 to build a frequency synthesizer. The following example
shows a typical application when the reference clock is in the MHz range:
Reference
Clock
REFIN
Divide A
Output
Clock
CLK1
ICS673-01
CLK2
FBIN
Post
Divide
ICS674-01
Divide B
If the reference is in the kHz range, for example 8 kHz, the following configuration may be more
typical:
Reference
Clock
REFIN
CLK1
Output
Clock
ICS673-01
CLK2
FBIN
Divide A
Post
Divide
Divide B
ICS674-01
Note that in both examples Divide B is connected to the output of the ICS673. This is because Divide B
has a higher operating frequency than Divide A.
4
Revision 033199
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
MDS 674-01 A
PRELIMINARY INFORMATION
ICS674-01
User Configurable Divider
Parameter
Conditions
Minimum
Typical
ABSOLUTE MAXIMUM RATINGS (stresses be ond these can permanentl damage the deevice)
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
-0.5
Clock Output
Referenced to GND
-0.5
Ambient Operating Temperature
0
Ambient Operating Temperature
I version
-40
Soldering Temperature
Max of 10 seconds
Storage Temperature
-65
DC CHARACTERISTICS (VDD = 5.0V unless oth
herwise noted)
Operating Voltage, VDD
3
Input High Voltage, VIH
All A, B, and S pins
2
Input Low Voltage, VIL
All A, B, and S pins
Input High Voltage, VIH, INA and INB only
(VDD/2)+1
VDD/2
Input Low Voltage, VIL, INA and INB only
VDD/2
Output High Voltage, VOH
IOH=-25mA
2.4
Output Low Voltage, VOL
IOL=25mA
IDD, Op. Supply Cur., DivA=DivB=20 at 3.3 V
No Load, fin=100 MHz
3
5
IDD, Op. Supply Cur., DivA=DivB=20 at 5 V
No Load, fin=100 MHz
Short Circuit Current, outputs
±70
On-Chip Pull-up Resistor
A, B, S select pins
270
Input Capacitance
A, B, S select pins
5
AC CHARACTERISTICS (VDD = 5.0V unless oth
herwise noted)
Input Frequency, Divider A
at 3.3 V
0
Input Frequency, Divider B
at 3.3 V
0
Input Frequency, Divider A
at 5 V
0
Input Frequency, Divider B
at 5 V
0
Input Frequency, Divider A (Industrial temperature) at 3.3 V at 85 °C
0
Input Frequency, Divider B (Industrial temperature) at 3.3 V at 85 °C
0
Input Frequency, Divider A (Industrial temperature) at 5 V at 85 °C
0
Input Frequency, Divider B (Industrial temperature) at 5 V at 85 °C
0
Output Clock Rise Time
0.8 to 2.0V
1
Output Clock Fall Time
2.0 to 0.8V
1
OUTB Clock Duty Cycle (see note)
at VDD/2
45
49 to 51
OUTB Clock Duty Cycle, odd post dividers
at VDD/2, except PD=1
40
OUTA Clock Duty Cycle (see note)
at VDD/2
20
Maximum
Units
7
VDD+0.5
VDD+0.5
70
85
260
150
V
V
V
°C
°C
°C
°C
5.5
V
V
V
V
V
V
V
mA
mA
mA
kΩ
pF
0.8
(VDD/2)-1
0.4
135
180
200
235
125
170
190
220
55
60
98.5
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
%
%
%
Note:
The duty cycle of OUTA is dependent on the selected divide. This is because OUTA goes low for 2 input
clock cycles on INA. So, for example, if a divide of 20 is selected, the duty cycle will be 90%.
Similarly, if PD=1 is selected for OUTB, the duty cycle will be dependent on the selected divide. In this
case OUTB goes high for approximately 8 input clock cycles on INB.
5
Revision 033199
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
MDS 674-01 A
PRELIMINARY INFORMATION
Package Outline and Package Dimensions
E
Q
e
28 pin SSOP
Symbol
A
b
c
D
E
H
e
h
Q
L
H
h x 45°
D
b
ICS674-01
User Configurable Divider
Inchees
Min
Max
0.061 0.068
0.008 0.012
0.007 0.010
0.385 0.400
0.150 0.160
0.230 0.245
.025 BSSC
0.016
0.004
0.01
0.016 0.035
Millim
meters
Min
Max
1.55
1.73
0.203
0.305
0.191
0.254
9.779 10.160
3.810
4.064
5.842
6.223
0.635 BSC
0.406
0.102
0.254
0.406
0.889
c
L
Ordering Information
Part/Order Number
ICS674R-01
ICS674R-01T
ICS674R-01I
ICS674R-01IT
Marking *
674R-01
674R-01
674R-01I
674R-01I
Package
28 pin narrow SSOP
28 pin SSOP on tape and reel
28 pin narrow SSOP
28 pin SSOP on tape and reel
Temperature
0 to 70 °C
0 to 70 °C
-40 to 85 °C
-40 to 85 °C
*This
shows the top line marking. The part will have the letters ICS in a box on the upper left
hand corner.
While the information presented herein has been checked for both accuracy and reliability, ICS assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.
6
Revision 033199
Printed 11/15/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA • 95126 •(408)295-9800tel•(408)295-9818fax
MDS 674-01 A
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