HT1382 I2C/3-Wire Real Time Clock Features · Real Time Clock/Calendar Functions - Includes: Sec, Minutes, Hours, Day, Date, Month, and year in BCD format · Clock operating voltage: 2.0V~5.5V · Supply voltage VDD=2.7V~5.5V · Automatic leap year correction, valid until year 2099 · Automatic supply switch over · Integrated oscillator load capacitors - CL=12.5pF · Clock compensation · Programmable alarm and interrupt function · 15 selectable frequency outputs · 4 Bytes EEPROM for user · Serial commutation via I2C or 3-wire interface · 8-pin DIP, SOP and MSOP package for I2C interface · 10-pin MSOP package for 3-wire interface Applications · Utility meters · Consumer electronics · Portable equipment · Wireless equipment · POS equipment · Computer products · Other industrial/Medical/Automotive applications General Description The HT1382 is a low power real time clock device with two serial interface: I2C or 3-wire. The interface mode is selected by the chosen chip version. The device provides both clock and calendar information in BCD format and also includes alarm functions. The calendar is accurate until the year 2099 and includes automatic leap year correction. An external 32768Hz crystal is used as the device oscillator for device timing for which is provided an integrated crystal load capacitance of 12.5pF. The device includes a crystal oscillator temperature compensation function and internal power control circuitry detects power failures and automatically switches to the battery supply when a power failure occurs. Rev. 1.40 1 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Block Diagram Internal power supply VDD VCOMP Switch RTC Register VBAT X1 Oscillator Compensation Crystal Oscillator X2 Control & Status Register Divider Circuit Alarm Register CE IRQ /FOUT 2 I C or 3-wire Interface SCL/SCLK SDA/I/O DT & USER EEPROM IFS VSS Note: 2 IFS pin is used for selecting I C interface or 3-wire interface. I2C interface is selected when IFS is unconnected. 3-wire interface is selected when IFS is connected to VSS. Pin Assignment I2 C 3 -W ir e In te r fa c e In te r fa c e X 1 1 1 0 X 2 2 9 IR Q /F O U T V B A T 3 8 S C L K S C L C E 4 7 I/O S D A V S S 5 6 N C X 1 1 8 V D D X 2 2 7 IR Q /F O U T V B A T 3 6 V S S 4 5 H T 1 3 8 2 8 D IP -A /S O P -A /M S O P -A Rev. 1.40 V D D H T 1 3 8 2 1 0 M S O P -A 2 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Pad Assignment (0 ,0 ) X 1 1 X 2 V B A T C E 2 8 5 S C L K 7 6 V D D IR Q /F O U T 9 4 IF S V S S 1 0 3 S D A Chip size: 1245 ´ 1520 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Pad Coordinates Unit: mm Pad No. X Y Pad No. X Y 1 -520.005 -161.460 6 -520.005 -646.610 2 -520.005 -256.460 7 521.000 -625.000 3 -520.005 -360.130 8 521.000 -530.000 4 -520.005 -455.130 9 521.000 -425.300 5 -520.005 -550.130 10 516.450 -288.400 Pad Description Pad No. Pad Name I/O 1 X1 I 32768Hz crystal input pin 2 X2 O 32768Hz crystal output pin 3 VBAT ¾ Battery power supply 4 VSS ¾ Negative power supply, ground 5 IFS I Interface selection pin. 2 I C interface is selected when IFS is unconnected, 3-wire interface is selected when IFS is connected to VSS. 6 CE I Chip Enable for 3-wire interface 2 Not used for I C interface 7 SDA/I/O I/O Serial Data Input/Output for I C and 3-wire interfaces 8 SCL/SCLK I/O Serial Clock Input for I C and 3-wire interfaces 9 IRQ/FOUT O Interrupt/Frequency Output, this pin is open drain output 10 VDD ¾ Positive power supply Rev. 1.40 Description 2 2 3 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Approximate Internal Connections S C L , S C L K S D A , I/O IF S , C E V D D V D D V D D G N D G N D X 1 , X 2 G N D IR Q /F O U T X 2 X 1 G N D G N D Absolute Maximum Ratings Supply Voltage ...............................................................................................VSS-0.3V to VSS+6.0V Input Voltage .................................................................................................VSS-0.3V to VDD+0.3V Storage Temperature .................................................................................................-50°C to 125°C Operating Temperature................................................................................................-40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.40 4 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock D.C. Characteristics Symbol Ta=-40°C~85°C Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit VDD Supply Voltage ¾ ¾ 2.7 ¾ 5.5 V VBAT Battery Supply Voltage ¾ ¾ 2.0 ¾ 5.5 V ISTB Standby Current ¾ VBAT=3V, ²CH²=1 ¾ ¾ 0.1 mA IBAT Battery Supply Current ¾ VBAT=3V, ²CH²=0 Supply Current (Low Power Mode) 3V IDD1 5V 3V IDD2 Supply Current 5V 2 IDD3 SCL/SCLK=0Hz, ²LPM²=1 SCL/SCLK=0Hz, ²LPM²=0 3V Supply Current with I C Active SCL=400kHz ¾ 0.8 1.2 mA ¾ 5 15 mA ¾ 15 30 mA ¾ 50 100 mA ¾ 70 150 mA ¾ 80 150 mA ¾ 150 300 mA Supply Current with 3-Wire Active 3V SCLK=1MHz ¾ 100 200 mA 5V SCLK=2MHz ¾ 300 500 mA VIH ²H² Input Voltage ¾ ¾ 0.7VDD ¾ ¾ V VIL ²L² Input Voltage ¾ ¾ ¾ ¾ 0.3VDD V VOH IOH1= -1.5mA 2.7 ¾ ¾ V I/O High Level Output Voltage 5V IDD4 3V VOL1 VOL2 VCOMP VBATHYS 5V IOH1= -3.0mA 4.5 ¾ ¾ V I/O, SCL and SDA Low Level Output Voltage 3V IOL1= 3.0mA 0 ¾ 0.4 V 5V IOL1= 6.0mA 0 ¾ 0.4 V IRQ Low Level Output Voltage 3V IOL2= 1.5mA 0 ¾ 0.4 V 5V IOL2= 3.0mA 0 ¾ 0.4 V VBAT Mode Compared Voltage ¾ ¾ 2.40 2.55 2.70 V Hysteresis ¾ ¾ ¾ 25 ¾ mV VBAT Hysteresis ¾ ¾ ¾ 40 ¾ mV A.C. Characteristics VDD=2.7V~5.5V, Ta=-40°C~85°C Power-Down Timing Test Conditions Symbol tFSR Parameter VDD Falling Slew Rate VDD Conditions ¾ ¾ Min. Typ. Max. Unit ¾ ¾ 10 V/ms Note: in order to ensure proper timekeeping, the tFSR specification must be followed. Rev. 1.40 5 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock I2C Interface Symbol Parameter Remark Min. Typ. Max. Unit fSCL Clock frequency ¾ ¾ ¾ 400 kHz tHIGH Clock High Time ¾ 600 ¾ ¾ ns tLOW Clock Low Time ¾ 1300 ¾ ¾ ns tr SDA and SCL Rise Time Note ¾ ¾ 300 ns tf SDA and SCL Fall Time Note ¾ ¾ 300 ns tHD:STA START Condition Hold Time After this period, the first clock pulse is generated. 600 ¾ ¾ ns tSU:STA START Condition Setup Time Only relevant for repeated START condition. 600 ¾ ¾ ns tHD:DAT Data Input Hold Time ¾ 0 ¾ ¾ ns tSU:DAT Data Input Setup Time ¾ 100 ¾ ¾ ns tSU:STO STOP Condition Setup Time ¾ 600 ¾ ¾ ns tAA Output Valid from Clock ¾ ¾ ¾ 900 ns tBUF Bus Free Time Time in which the bus must be free before a new transmission can start 1300 ¾ ¾ ns tSP Input Filter Time Constant (SDA and SCL Pins) Noise suppression time ¾ ¾ 50 ns Note: These parameters are periodically sampled but not 100% tested 3-wire Interface Ta=-40°C~85°C Test Conditions Symbol fSCLK tDC tCDH tCDD tCL tCH Parameter Min. Typ. Max. Unit ¾ ¾ ¾ 1 MHz 5V ¾ ¾ ¾ 2 MHz 3V ¾ 100 ¾ ¾ ns 5V ¾ 50 ¾ ¾ ns 3V ¾ 140 ¾ ¾ ns 5V ¾ 70 ¾ ¾ ns 3V ¾ ¾ ¾ 400 ns 5V ¾ ¾ ¾ 200 ns 3V ¾ 500 ¾ ¾ ns 5V ¾ 250 ¾ ¾ ns 3V ¾ 500 ¾ ¾ ns 5V ¾ 250 ¾ ¾ ns 3V ¾ ¾ ¾ 1000 ns 5V ¾ ¾ ¾ 500 ns VDD Conditions 3V Serial Clock Data to Clock Setup Clock to Data Hold Clock to Data Delay Clock Low Time Clock High Time tr Clock Rise and Fall time tf Rev. 1.40 6 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Test Conditions Symbol tCC Parameter Min. Typ. Max. Unit ¾ 2 ¾ ¾ ms 5V ¾ 1 ¾ ¾ ms 3V ¾ 120 ¾ ¾ ns 5V ¾ 60 ¾ ¾ ns 3V ¾ 2 ¾ ¾ ms 5V ¾ 1 ¾ ¾ ms 3V ¾ ¾ ¾ 140 ns 5V ¾ ¾ ¾ 70 ns VDD Conditions 3V CE to Clock Setup tCCH Clock to CE Hold tCWH CE Inactive Time tCDZ CE to I/O High Impedance Timing Diagrams Power-Down Timing V D D tF S R 0 V I2C Interface SDA tBUF tSU:DAT tf tLOW tHD:STA tr tSP SCL tHD:SDA tSU:STO tHD:DAT S tHIGH tAA tSU:STA Sr P S SDA OUT Rev. 1.40 7 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock 3-wire Interface Read Data Transfer C E tC C S C L K tC D H tC D D tD C 7 0 I/O tC D Z 7 0 C o m m a n d B y te O u tp u t D a ta B y te Write Data Transfer tC W H C E tr tC H tC C tC C H S C L K tC D H tD C I/O tf tC L 7 0 7 0 C o m m a n d B y te In p u t D a ta B y te Crystal Specifications Symbol Parameter Min. Typ. Max. Unit fO Nominal Frequency ¾ 32.768 ¾ kHz ESR Series Resistance ¾ 50 65 kW CL Load Capacitance ¾ 12.5 ¾ pF Note: 1. It is strongly recommended to use a crystal with load capacitance 12.5pF. 2. The oscillator selection can be optimized using a high quality resonator with small ESR value. Refer to crystal manufacturer for more details: www.microcrystal.com Rev. 1.40 8 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Functional Description The HT1382 is a low power real time clock device which provides full date and time functions. Communication with the device is provided through two integral serial interfaces, I2C or 3-wire. The device version selects the type of interface. The clock and calendar information is generated in BCD format and also has alarm features. The calendar is accurate until the year 2099, with automatic leap year correction. Basic timing is provided using an external 32768Hz crystal, for which the device includes load capacitances of 12.5pF. An oscillator compensation function is provided to compensate for crystal oscillator temperatures. With fully integrated power control circuitry which can detect power failures, the device can automatically switch to a reserve battery supply when a power failure occurs. Power Control Function The internal battery switchover circuit continually monitors the main power supply on the VDD pin and automatically switches to the backup battery supply when a power failure condition is detected. In the battery backup mode, the interface is disabled to minimise power consumption. The interface inputs will not be recognized which prevents extraneous data being written to the device. The interface outputs are high-impedance. All RTC function are operational when the device is in the battery backup mode. Normal Mode (VDD) to Battery Backup Mode (VBAT) To switch from the VDD to VBAT Mode , both of the following conditions must be valid: VDD < VBAT-VBATHYS and VDD < VCOMP Battery Backup Mode (VBAT) to Normal Mode (VDD) To switch from the VBAT to VDD Mode, one of the following conditions must be valid: VDD > VBAT + VBATHYS or VDD > VCOMP + VCOMPHYS The power control situation is illustrated graphically below: Battery Backup Mode VDD VCOMP VBAT VBAT-VBATHYS Battery Backup Mode VDD VBAT 2.55V 2.0V 3.0V 2.55V VCOMP VCOMP VBAT+VBATHYS Note: Battery switchover when VBAT < VCOMP VCOMP+VCOMPHYS Note: Battery switchover when VBAT > VCOMP Low Power Mode In normal mode, the HT1382 switched into battery backup mode when the VDD power is lost. This will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. Another mode, called Low Power Mode, is available to allow direct switching from VDD to VBAT without requiring VDD to drop below VCOMP. The power switchover circuit is disabled and less power is used while operating from VDD. Low Power Mode is activated via the LPM bit. Low Power Mode is useful when VDD is normally higher than VBAT. The device will switch from VDD to VBAT when VDD drops below VBAT, with about 40mVof hysteresis to prevent any switchback of VDD after switchover. In a system with VDD=5V and VBAT=3V, Low Power Mode can be used. However, it is not recommended to use Low Power Mode in VDD=3.3V±10%, VBAT³3V. Rev. 1.40 9 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Clock Compensation The device includes a digital trimming method for clock error correction due to temperature variations of the crystal oscillator. This can be implemented as manufacturing calibration or user active calibration. The crystal accuracy to temperature characteristic is similar to that shown in the diagram. The Digital Trimming Register, DT, is used for clock compensation. Correction is performed once every 10 seconds or 30 seconds. The minimum resolution is 3.052ppm or 1.017ppm and the device has a correction in the range of ±192.276ppm or ±64.071ppm. Set FO3~FO0= ²1010², the FOUT pin will have 1Hz clock pulse output. Measure the FOUT frequency using a high-accuracy frequency counter with 7 or more digits. The correction value is calculated using the formula shown below. Correction value = integral value ( 1Hz - (measured value) minimum resolution (3.052ppm or 1.014ppm) ) When clock compensation is used, set FO3~FO0=²1010², and the FOUT pin will have 1Hz clock pulse output. The cycle changes once in 10 seconds or in 30 seconds as shown below. In the diagram ²a² denotes a non-correctional cycle, and ²b² denotes a correctional cycle. Measure ²a² and ²b² using a high-accuracy frequency counter of 7 or more digits. Calculate the average frequency based on the measured result. For DTS = 0, the average period = (a ´ 9 + b) ¸ 10 For DTS = 1, the average period = (a ´ 29 + b) ¸ 30 Rev. 1.40 10 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Register Description The device includes 16 registers which are used to control functions such as the RTC, Status, Alarm, Frequency output etc. There are also five bytes of EEPROM which contain the clock compensation settings and stored user data. The RTC and Alarm register data is stored in BCD format, while other data is stored in binary format. The register map shows the address definitions for the I2C interface. The command byte and R/W bit are used for the 3-wire interface. Register Definition Address D7 D6 D5 D4 D3 D2 D1 D0 Register Name Range Data Default Bit R/W Command Byte 00H CH 10 SEC SEC Seconds 00~59 80H W R 10000000 10000001 01H 0 10 MIN MIN Minutes 00~59 00H W R 10000010 10000011 02H 12/ 24 0 0 HR HR HOUR Hours 01~12 00~23 12H W R 10000100 10000101 03H 0 0 10 DATE DATE Date 01~31 01H W R 10000110 10000111 04H 0 0 0 10M MONTH Month 01~12 01H W R 10001000 10001001 05H 0 0 0 0 Day 01~07 01H W R 10001010 10001011 Year 00~99 00H W R 10001100 10001101 06H AP 10 0 DAY 10 YEAR YEAR 07H WP 0 0 0 0 0 0 0 ST ¾ 80H W R 10001110 10001111 08H ARE 0 0 EWE EB AI BE 0 ST ¾ 00H W R 10010000 10010001 09H IME AE LPM OEOBM FO3 FO2 FO1 FO0 INT ¾ 00H W R 10010010 10010011 0AH SECEN AL. 10SEC AL. SEC Seconds Alarm 00~59 00H W R 10010100 10010101 0BH MINEN AL. 10MIN AL. MIN Minutes Alarm 00~59 00H W R 10010110 10010111 0CH HREN 0 AL. 10HR AL. HOUR Hours Alarm 01~12 00~23 00H W R 10011000 10011001 0DH DTEN 0 AL. 10DT AL. DATE Date Alarm 01~31 00H W R 10011010 10011011 0EH MOEN 0 0 AL. 10M AL. MONTH Month Alarm 01~12 00H W R 10011100 10011101 0FH DAYEN 0 0 0 Day Alarm 01~07 00H W R 10011110 10011111 DT ¾ ¾ W R 10100000 10100001 0 AL. DAY EEPROM Data 10H DTS DT6 DT5 DT4 DT3 DT2 DT1 DT0 11H EEPROM User Data USR ¾ ¾ W R 10100010 10100011 12H EEPROM User Data USR ¾ ¾ W R 10100100 10100101 13H EEPROM User Data USR ¾ ¾ W R 10100110 10100111 14H EEPROM User Data USR ¾ ¾ W R 10101000 10101001 Rev. 1.40 11 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Real Time Clock Register The RTC register stores the Year, Day, Month, Date, Hours, Minutes and, Second data in BCD format. 12/24 Hour Mode Bit D7 of the hour register is defined as the 12-hour or 24-hours mode select bit. If the bit is ²1², the RTC uses a 24-hour format. If ²0², the RTC uses a 12-hour format. The default value is ²0². AM/PM Mode There are two function for the D5 bit in the hour register which is determined by the D7 bit. In the 12-hour mode the bit is used for AM/PM selection. When D5 is ²1², it will be PM, otherwise it will be AM. In the 24-hour mode, the bit is used to set the second 10-hour bit(20~23 hours). Leap Years Leap years add an extra day for February 29 and are defined as those years that are divisible by 4. The device will provide automatic correction for leap years until year 2099. Clock HALT Bit - CH This bit enables/disables the oscillator. The CH bit is set high to disable the oscillator and cleared to zero is enable it. The default value is define as ²1². Write Protect Bit - WP The WP bit is set high to prevent data writes and cleared to zero to allow data to be written. The default value is define as ²1². Battery Enable Bit - BE When the device enters the battery backup mode, the BE bit is set to ²1². This bit can be cleared to ²0² either manually by the user or automatically reset by the ARE pin. Only a ²0² an be written to this bit, not a ²1². Alarm Interrupt Bit - AI When the RTC register values match the alarm register values, the AI bit will be set to ²1². This bit can be reset to ²0² either manually by the user or automatically reset by the ARE pin. Only a ²0² an be written to this bit, not a ²1². The AI bit will be set by an alarm occurring during a read operation ad will remain set until after the read operation is complete. Auto Reset Enable Bit - ARE This bit enables/disables the automatic reset of the BE and AI status bits only. When ARE is set to ²1², BE and AI will be reset to ²0² after reading these registers. When ARE is cleared to ²0², the user must manually reset the BE and AI bits. EEPROM Write Enable Bit - EWE When EWE is cleared to ²0², the EEPROM is read only, and the user can not write data to the EEPROM. When EWE is set to ²1², the user can write data to the EEPROM. Before writing data to the EEPROM, this bit must be set to ²1². Rev. 1.40 12 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock EEPROM Busy Status Bit - EB This bit is set to ²1² when a write operation to the EEPROM has not completed. When this bit is set to ²1², reading data from the EEPROM or writing data to the EEPROM is invalid. After an EEPROM write has finished, this bit will be cleared to ²0² and the user can read data from the EEPROM or write data to the EEPROM. Output Enable On Battery Mode Bit - OEOBM This bit enables/disables the IRQ/FOUT pin in the battery mode. When the OEOBM bit is set to ²1², the IRQ/FOUT pin is disabled in the battery mode and the frequency output and alarm function are disabled. When the OEOBM bit is cleared to ²0², the IRQ/FOUT pin is enabled in the battery mode. Low Power Mode Bit - LPM This bit enables/disables the Low Power Mode. When the LPM bit is cleared to ²0², the device will be in the normal mode and will use the VBAT supply when VDD < VBAT and VDD < VCOMP. When the LPM bit is set to ²1², the device is in the Low Power Mode and uses the VBAT supply when VDD < VBAT. Frequency Output Bits - FO3~FO0 These bits enable/disable the frequency output function and selects the output frequency at the FOUT pin. The frequency selection table is shown below. It overrides the alarm mode. The 1, 1/2, 1/4, 1/8, 1/16, 1/32 frequency outputs are compensated. FOUT(Hz) FO3 FO2 FO1 FO0 ¾ 0 0 0 0 32768 0 0 0 1 4096 0 0 1 0 1024 0 0 1 1 64 0 1 0 0 32 0 1 0 1 16 0 1 1 0 8 0 1 1 1 4 1 0 0 0 2 1 0 0 1 1 1 0 1 0 1/2 1 0 1 1 1/4 1 1 0 0 1/8 1 1 0 1 1/16 1 1 1 0 1/32 1 1 1 1 Rev. 1.40 13 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Alarm Enable Bit - AE This bit enables/disables the alarm function. When the AE bit is set to ²1², the alarm function is enabled. When the AE bit is cleared to ²0², the alarm function is disabled. Digital Trimming Setting Bits - DTS This bit sets the digital trimming resolution and adjustment time. The user must detect the status of the EB bit before reading data or writing data. If the EB bit is ²0², it is valid to read data or write data. If the EB bit is ²1², it is invalid to read data or write data. Adjustment time DTS=²0² DTS=²1² Every 10 seconds Every 30 seconds Minimum resolution 3.052ppm 1.017ppm Correction range -192.276ppm to +192.276ppm -64.071ppm to + 64.071ppm Digital Trimming Bits - DT6~DT0 This digital trimming bit, DT6, is the sign bit. A ²0² indicates positive calibration and a ²1² indicates negative calibration. DT5~DT0 are the calibration values and the adjustable range is -63 ~ +63. If DTS is cleared to ²0², the correction range is -192.276ppm to +192.276ppm and if DTS is set to ²1², the correction range is -64.071ppm to +64.071ppm. The user must detect the status of EB bit before reading data or writing data. If the EB bit is ²0², it is valid to read data or write data. If the EB bit is ²1², it is invalid to read data or write data. DT6 DT5 DT4 DT3 DT2 DT1 DT0 Value 0 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 Correction Value (ppm) DTS=²0² DTS=²1² +63 +192.276 +64.071 +62 +189.224 +63.054 1 +61 +186.172 +62.037 0 +6 +183.120 +61.020 : : : : : : 0 0 0 0 0 1 1 +3 +9.156 +3.051 0 0 0 0 0 1 0 +2 +6.104 +2.034 0 0 0 0 0 0 1 +1 +3.052 +1.017 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 -1 -3.052 -1.07 1 0 0 0 0 1 0 -2 -6.104 -2.034 1 0 0 0 0 1 1 -3 -9.156 -3.051 : : : : : : 1 1 1 1 1 0 0 -60 -183.120 -61.020 1 1 1 1 1 0 1 -61 -186.172 -62.037 1 1 1 1 1 1 0 -62 -189.224 -63.054 1 1 1 1 1 1 1 -63 -192.276 -64.071 Rev. 1.40 14 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Interrupt Mode Enable Bit - IME This bit enables/disables the interrupt mode of the alarm function. When the IME bit is set to ²1², the interrupt mode is enabled and when the IME bit is cleared to ²0², the interrupt mode is disabled and the alarm operates in single mode. Alarm Register The addresses of alarm registers are 0Bh to 10h. The data is stored in the BCD format. The MSB of each alarm register is an enable bit. (enable=²1²). These enable bits specify which alarm registers are used to make the comparison between the alarm registers and the RTC registers. There is no alarm byte for year. When a compare match condition exists, the AI bit is set to ²1², and the IRQ pin is activated. To clear an alarm, the AI bit must be cleared to ²0². If the ARE bit is set to ²1², the AI bit will automatically be cleared when the status register is read. There are two alarm operation modes: Single mode and Interrupt Mode. Single mode: set the AE bit to ²1², the IME bit to ²0², and disable the frequency output. When the RTC register values match the alarm registers values, the AI bit will be set to ²1² and the alarm condition activates the IRQ pin. The IRQ pin will remain low until the AI bit is cleared to ²0². Interrupt mode: set the AE bit to ²1², the IME bit to ²1², and disable the frequency output. When the RTC registers values match the alarm registers values, the IRQ pin will be pulled low for 250ms and the AI bit will be set to ²1². This mode allows for a repetitive or recurring alarm function. When the alarm is set, the device will continue to activate an alarm for each match of the alarm and the present time. For example, if only the seconds are set, it will activate an alarm every minute, if only the minutes are set, it will activate an alarm every hour. EEPROM User Data The HT1382 provides 4 bytes EEPROM for user. The EEPROM will continue to operate in battery backup mode. However, it should be noted that the I2C/3-wire interface is disabled in battery backup mode. User must detect the status of EB bit before reading data or writing data. If the EB bit is ²0², it is valid to read data or write data. If the EB bit is ²1², it is invalid to read data or write data. Rev. 1.40 15 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock I2C Serial Interface The HT1382 includes an I2C serial interface. The I2C bus is used for bidirectional, two-line communication between multiple I2C devices. The two lines of the interface are the serial data line (SDA) and the serial clock line (SCL).Both lines are connected to the positive supply via a pull-up resistor externally. When the bus is free, both lines will be high. The output stages of the devices connected to the bus must have open-drain or open-collector output types to implement the wired-AND function necessary for connection. Data transfer is initiated only when the bus is not busy. Data Validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. SDA SCL Data line stable; Change of data data valid allowed START and STOP Conditions A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START(Sr) is generated instead of a STOP condition. In this respect, a START(S) and repeated START(Sr) conditions are functionally identical. SDA SDA SCL SCL S P START condition STOP condition Byte Format Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. P SDA Sr SCL Rev. 1.40 S or Sr 1 2 7 8 9 ACK 16 1 2 3-8 9 ACK P or Sr May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Acknowledge Each bytes of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level placed on the bus by the receiver. The master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge (ACK) after the reception of each byte. The acknowledging device must first pull down the SDA line during the acknowledge clock pulse so that it remains LOW during the HIGH period of this clock pulse. A master receiver must signal an end of data to the slave by generating a not-acknowledge (NACK) bit on the last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line HIGH during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition. Data Output By Transmitter not acknowledge Data Output By Receiver acknowledge SCL from Master 1 2 7 8 9 S START condition clk pulse for acknowledgement Device Addressing The slave address byte is the first byte received following the START condition from the master device. The first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be performed. When this R/W bit is ²1², then a read operation is selected. A ²0² selects a write operation. The device address bits are ²1101000². When an address byte is sent, the device compares the first seven bits after the START condition. If they match, the device outputs an acknowledge on the SDA line. LSB MSB 1 1 0 1 0 0 0 R/W The first byte after the START. Write Operation · Byte Write Operation A byte write operation requires a START condition, a slave address with R/ bit, a valid Register Address, the required Data and a STOP condition. After each of the three byte transfers, the device responds with an ACK. · Page Write Operation Following a START condition and slave address, a R/ bit is placed on the bus which indicates to the addressed device that a Register Address will follow which is to be written to the address pointer. The data to be written to the memory follows next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. After reaching memory location 0Fh, the pointer will be reset to 00h. Slave Address Register Address(An) Data(n) P S 1 1 0 1 0 0 0 0 Write ACK ACK ACK Byte Write Sequence Rev. 1.40 17 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Slave Address Register Address(An) Data(n+1) Data(n) Data(n+x) P S 1 1 0 1 0 0 0 0 Write ACK ACK ACK ACK ACK ACK Page Write Sequence Read Operation In this mode, the master reads the device data after setting the slave address. Following the R/W bit (=²0²) and the acknowledge bit, the register address (An) is written to the address W pointer. Next the START condition and slave address are repeated followed by the R/W bit (=²1²). The data which was addressed is then transmitted. The address pointer is only incremented on reception of an acknowledge clock. The device will then place the data at address An+1 on the bus. The master reads and acknowledges the new byte and the address pointer is incremented to ²An+2². After reaching the memory location 0Fh, the pointer will be reset to 00h. This cycle of reading consecutive addresses will continue until the master sends a STOP condition. Slave Address Register Address(An) P S 1 1 0 1 0 0 0 0 Write ACK ACK Slave Address Data(n) Data(n+1) Data(n+x) P S 1 1 0 1 0 0 0 1 Read ACK ACK ACK ACK ACK Read Sequence 3-wire Serial Interface The device also support a 3-wire serial interface. The CE pin is used to identify the transmitted data. The transmission is controlled by the active HIGH signal CE. Each data transfer is a byte, with the LSB sent first. The first byte transmitted is the Command Byte. Command Byte For each data transfer, a Command Byte is initiated to specify which register is accessed. This is to determine whether a read or write cycle is operational and whether a single byte or burst mode transfer is to occur. R/W Signal The LSB of the Command Byte determines whether the data in the register is to be read or be written to. If it is ²0² then this means that it is a write cycle. If it is ²1² then this means that it is a read cycle. Burst Mode When the Command Byte is 10111110 or 10111111, the device is configured in the burst mode. In this mode, the address of registers from 00h to 0Fh can be written or read in series, starting with bit 0 of register address 0. Rev. 1.40 18 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Data Input and Data Out In writing a data byte, R/W is cleared to ²0² in the Command Byte and is then followed by the corresponding data register address on the rising edge of the next eight SCLK. Additional SCLK cycles are ignored. Data inputs are entered starting with bit 0. In reading data from the register, the R/W is set to ²1² in the Command Byte. The data bits are output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted on the first falling edge after the last bit of the read command byte is written. Additional SCLK cycles re-transmits the data bytes as long as CE remains at high level. Data outputs are read starting with bit 0. · Single Byte Transfer S C L K C E 0 I/O R /W 1 2 3 4 5 A 0 A 1 A 2 A 3 A 4 6 0 7 0 1 3 4 5 6 7 1 C o m m a n d B y te · 2 D a ta I/O Burst Mode Transfer S C L K C E 0 I/O R /W 1 2 1 3 1 4 1 1 5 1 C o m m a n d B y te Rev. 1.40 19 6 0 7 0 7 0 7 1 D a ta B y te 0 D a ta B y te 1 5 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Application Circuits I2C Serial Interface V C 1 V 0 .1 m F R 2 D D V D D V D D B A T V B A T 4 .7 k W S C L V M C U In te r fa c e R 3 D D X 1 4 .7 k W H T 1 3 8 2 S D A V R 1 3 2 7 6 8 H z X 2 D D 4 .7 k W V S S IR Q /F O U T 3-wire Serial Interface V 0 .1 m F C 1 V D D V D D B A T V B A T C E S C L K M C U In te r fa c e I/O V R 1 X 1 H T 1 3 8 2 X 2 D D 4 .7 k W IR Q /F O U T Rev. 1.40 3 2 7 6 8 H z 20 V S S May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Package Information 8-pin DIP (300mil) Outline Dimensions A 8 5 B 1 4 H C D I G E F Symbol A Min. Nom. Max. 0.355 ¾ 0.375 B 0.240 ¾ 0.260 C 0.125 ¾ 0.135 D 0.125 ¾ 0.145 E 0.016 ¾ 0.020 F 0.050 ¾ 0.070 G ¾ 0.100 ¾ H 0.295 ¾ 0.315 I ¾ 0.375 ¾ Symbol A Rev. 1.40 Dimensions in inch Dimensions in mm Min. Nom. Max. 9.02 ¾ 9.53 B 6.10 ¾ 6.60 C 3.18 ¾ 3.43 D 3.18 ¾ 3.68 E 0.41 ¾ 0.51 F 1.27 ¾ 1.78 G ¾ 2.54 ¾ H 7.49 ¾ 8.00 I ¾ 9.53 ¾ 21 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock 8-pin SOP (150mil) Outline Dimensions A 5 8 1 B 4 C C ' G H D E a F MS-012 Symbol Nom. Max. A 0.228 ¾ 0.244 B 0.150 ¾ 0.157 C 0.012 ¾ 0.020 C¢ 0.188 ¾ 0.197 D ¾ ¾ 0.069 E ¾ 0.050 ¾ F 0.004 ¾ 0.010 G 0.016 ¾ 0.050 H 0.007 ¾ 0.010 a 0° ¾ 8° Symbol Rev. 1.40 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 5.79 ¾ 6.20 B 3.81 ¾ 3.99 C 0.30 ¾ 0.51 C¢ 4.78 ¾ 5.00 D ¾ ¾ 1.75 E ¾ 1.27 ¾ F 0.10 ¾ 0.25 G 0.41 ¾ 1.27 H 0.18 ¾ 0.25 a 0° ¾ 8° 22 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock 8-pin TSSOP Outline Dimensions 8 5 E 1 1 4 E D A L A 2 e R 0 .1 0 A 1 B C L 1 y q (4 C O R N E R S ) Symbol Min. Nom. Max. A 0.041 ¾ 0.047 A1 0.002 ¾ 0.006 A2 0.031 ¾ 0.041 B ¾ 0.010 ¾ C 0.004 ¾ 0.006 D 0.114 ¾ 0.122 E 0.244 ¾ 0.260 E1 0.169 ¾ 0.177 e ¾ 0.026 ¾ L 0.020 ¾ 0.028 L1 0.035 ¾ 0.043 y ¾ ¾ 0.004 q 0° ¾ 8° Symbol Rev. 1.40 Dimensions in inch Dimensions in mm Min. Nom. Max. A 1.05 ¾ 1.20 A1 0.05 ¾ 0.15 A2 0.80 ¾ 1.05 B ¾ 0.25 ¾ C 0.11 ¾ 0.15 D 2.90 ¾ 3.10 E 6.20 ¾ 6.60 E1 4.30 ¾ 4.50 e ¾ 0.65 ¾ L 0.50 ¾ 0.70 L1 0.90 ¾ 1.10 y ¾ ¾ 0.10 q 0° ¾ 8° 23 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock 8-pin MSOP Outline Dimensions 8 5 1 E 1 4 E D A L A 2 e A 1 B R 0 .1 0 C q y (4 C O R N E R S ) MO-187 Symbol Min. Nom. Max. A ¾ ¾ 0.043 A1 0.000 ¾ 0.006 A2 0.030 ¾ 0.037 B 0.009 ¾ 0.013 C 0.003 ¾ 0.009 D ¾ 0.012 ¾ ¾ E ¾ 0.193 E1 ¾ 0.118 ¾ e ¾ 0.026 ¾ L 0.016 ¾ 0.031 L1 ¾ 0.037 ¾ y ¾ ¾ 0.004 q 0° ¾ 8° Symbol Rev. 1.40 Dimensions in inch Dimensions in mm Min. Nom. Max. A ¾ ¾ 1.10 A1 0.00 ¾ 0.15 A2 0.75 ¾ 0.95 B 0.22 ¾ 0.33 C 0.08 ¾ 0.23 D ¾ 3.00 ¾ E ¾ 4.90 ¾ E1 ¾ 3.00 ¾ e ¾ 0.65 ¾ L 0.40 ¾ 0.80 L1 ¾ 0.95 ¾ y ¾ ¾ 0.10 q 0° ¾ 8° 24 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock 10-pin MSOP Outline Dimensions 1 0 6 E 1 1 5 E D L A 2 A e R B 0 .1 0 C q A 1 L 1 (4 C O R N E R S ) Symbol Nom. Max. A ¾ ¾ 0.043 A1 0.000 ¾ 0.006 A2 0.030 0.033 0.037 B 0.007 ¾ 0.011 C ¾ ¾ 0.010 D ¾ 0.012 ¾ E ¾ 0.193 ¾ E1 ¾ 0.118 ¾ e ¾ 0.020 ¾ L 0.016 0.024 0.031 L1 ¾ 0.037 ¾ q 0° ¾ 8° Symbol Rev. 1.40 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A ¾ ¾ 1.10 A1 0.00 ¾ 0.15 A2 0.75 0.85 0.95 B 0.17 ¾ 0.27 C ¾ ¾ 0.25 D ¾ 3.00 ¾ E ¾ 4.90 ¾ E1 ¾ 3.00 ¾ e ¾ 0.50 ¾ L 0.40 0.60 0.80 L1 ¾ 0.95 ¾ q 0° ¾ 8° 25 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Reel Dimensions D T 2 A C B T 1 SOP 8N Symbol Description Dimensions in mm A Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness 13.0 +0.5/-0.2 2.0±0.5 12.8 +0.3/-0.2 18.2±0.2 TSSOP 8L Symbol Description Dimensions in mm A Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.40 13.0 +0.5/-0.2 2.0±0.5 12.8 +0.3/-0.2 18.2±0.2 26 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Carrier Tape Dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . SOP 8N Symbol Description Dimensions in mm 12.0 +0.3/-0.1 W Carrier Tape Width P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 5.5±0.1 D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.4±0.1 B0 Cavity Width 5.2±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness C Cover Tape Width Rev. 1.40 1.55±0.1 1.50 +0.25/-0.00 0.30±0.05 9.3±0.1 27 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock TSSOP 8L Symbol Description Dimensions in mm 12.0 +0.3/-0.1 W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter 1.5 +0.1/-0.0 D1 Cavity Hole Diameter 1.5 +0.1/-0.0 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 7.0±0.1 B0 Cavity Width 3.6±0.1 K0 Cavity Depth 1.6±0.1 t Carrier Tape Thickness C Cover Tape Width Rev. 1.40 8.0±0.1 1.75±0.10 5.5±0.5 0.300±0.013 9.3±0.1 28 May 27, 2011 HT1382 I2C/3-Wire Real Time Clock Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.40 29 May 27, 2011