20 μA Maximum, Rail-to-Rail I/O, Zero Input Crossover Distortion Amplifiers AD8505/AD8506/AD8508 FEATURES V– 2 AD8505 5 The AD8505/AD8506/AD8508 are specified for both the industrial temperature range of −40°C to +85°C and the extended industrial temperature range of −40°C to +125°C. The AD8505 single amplifier is available in a tiny 5-lead SOT-23 and a 6-ball WLCSP packages. The AD8506 dual amplifier is available in 8-lead MSOP and 8-ball WLCSP packages. The AD8508 quad amplifier is available in 14-lead TSSOP and 14-ball WLCSP packages. The AD8505/AD8506/AD8508 are members of a growing series of zero crossover distortion op amps offered by Analog Devices, Inc., including the ADA4505-1/ADA4505-2/ADA4505-4, that operate from a single 1.8 V to 5 V supply or from dual ±0.9 V to ±2.5 V power supplies. NC B1 B2 +IN –IN C1 C2 AD8505 4 –IN Figure 1. 5-Lead SOT-23 (RJ-5) Figure 2. 6-Ball WLCSP (CB-6-7) BALL A1 CORNER –IN A 2 +IN A 3 AD8506 TOP VIEW (Not to Scale) V– 4 8 V+ 7 OUT B 6 –IN B 5 +IN B OUT B V+ OUT A A1 A2 A3 –IN B –IN A B1 B3 +IN B V– +IN A C1 C2 C3 AD8506 06900-002 OUT A 1 Figure 3. 8-Lead MSOP (RM-8) TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 4. 8-Ball WLCSP (CB-8-2) BALL A1 CORNER OUTD OUTA A1 A2 A3 –IND V– +INA B1 –INA B2 +IND B3 +INB OUT A 1 14 OUT D –IN A 2 13 –IN D +INC V+ +IN A 3 12 +IN D D1 D2 D3 V+ 4 –INC OUTC OUTB +IN B 5 E1 E2 E3 –IN B 6 9 –IN C OUT B 7 8 OUT C AD8508 C1 TOP VIEW 11 V– (Not to Scale) 10 +IN C Figure 5. 14-Lead TSSOP (RU-14) 06900-045 This combination of features makes the AD8505/AD8506/AD8508 amplifiers ideal choices for battery-powered applications because they minimize errors due to power supply voltage variations over the lifetime of the battery and maintain high CMRR even for a railto-rail input op amp. Remote battery-powered sensors, handheld instrumentation, consumer equipment, hazard detection (for example, smoke, fire, and gas), and patient monitors can benefit from the features of the AD8505/AD8506/AD8508 amplifiers. V– TOP VIEW (BALL SIDE DOWN) Not to Scale NC = NO CONNECT GENERAL DESCRIPTION The AD8505/AD8506/AD8508 are single, dual, and quad micropower amplifiers featuring rail-to-rail input/output swings while operating from a single 1.8 V to 5 V power supply or from dual ±0.9 V to ±2.5 V power supplies. Using a new circuit technology, these amplifiers offer zero input crossover distortion (excellent PSRR and CMRR performance) and low bias current while operating with a supply current of less than 20 μA per amplifier. This amplifier family offers the lowest noise in its power class. A2 V+ TOP VIEW (Not to Scale) +IN 3 V+ A1 06900-100 OUT 1 OUT 06900-001 Pressure and position sensors Remote security Bio sensors IR thermometers Battery-powered consumer equipment Hazard detectors BALL A1 INDICATOR C3 –INB AD8508 TOP VIEW (BALL SIDE DOWN) Not to Scale 06900-104 APPLICATIONS PIN CONFIGURATIONS 06900-051 PSRR: 100 dB minimum CMRR: 105 dB typical Very low supply current: 20 μA per amplifier maximum 1.8 V to 5 V single supply or ±0.9 V to ±2.5 V dual supply Rail-to-rail input/output Low noise: 45 nV/√Hz at 1 kHz 2.5 mV offset voltage maximum Very low input bias current: 1 pA typical Figure 6. 14-Ball WLCSP (CB-14-1) Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. AD8505/AD8506/AD8508 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Pin Configurations ........................................................................... 1 Applications Information .............................................................. 15 Revision History ............................................................................... 2 Pulse Oximeter Current Source ............................................... 15 Specifications..................................................................................... 3 Electrical Characteristics—1.8 V Operation ............................ 3 Four-Pole, Low-Pass Butterworth Filter for Glucose Monitor ........................................................................................ 16 Electrical Characteristics—5 V Operation................................ 4 Outline Dimensions ....................................................................... 17 Absolute Maximum Ratings............................................................ 5 Ordering Guide .......................................................................... 20 Thermal Resistance ...................................................................... 5 REVISION HISTORY 5/10—Rev. D to Rev. E Added AD8505, 6-Ball WLCSP Package ......................... Universal Changes to Large-Signal Voltage Gain Parameter (Table 1) ....... 4 Changes to Large-Signal Voltage Gain Parameter (Table 2) ....... 5 Changes to Table 4 ............................................................................ 6 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 21 10/09—Rev. C to Rev. D Added AD8505, 5-Lead SOT-23 Package ....................... Universal Changes to General Description, Added Figure 1 ....................... 1 Moved Electrical Characteristics—1.8 V Operation Section, Changes to Supply Current per Amplifier Parameter, Table 1 ..... 3 Moved Electrical Characteristics—5 V Operation Section, Changes to Supply Current per Amplifier Parameter, Table 2 ..... 4 Changes to Thermal Resistance Section and Table 4................... 5 Changes to Figure 20 and Figure 23 ............................................... 8 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 17 3/09—Rev. B to Rev. C Added AD8508, 14-Ball WLCSP Package....................... Universal Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 18 10/08—Rev. A to Rev. B Added WLCSP Package ..................................................... Universal Added Figure 2; Renumbered Sequentially .................................. 1 Added Input Resistance Parameter ................................................ 3 Changes to Input Capacitance Differential Mode Parameter Symbol and Input Capacitance Common Mode Parameter Symbol ................................................................................................ 3 Added Input Resistance Parameter ................................................ 4 Changes to Input Capacitance Differential Mode Parameter Symbol and Input Capacitance Common Mode Parameter Symbol ................................................................................................ 4 Changes to Table 4.............................................................................5 Changes to Figure 46...................................................................... 16 Updated Outline Dimensions ....................................................... 17 Added Figure 49 ............................................................................. 17 Changes to Ordering Guide .......................................................... 18 7/08—Rev. 0 to Rev. A Added AD8508 ................................................................... Universal Added TSSOP Package ...................................................... Universal Changes to Features Section and General Description Section ..1 Added Figure 2; Renumbered Sequentially ...................................1 Changed Electrical Characteristics Heading to Electrical Characteristics—5 V Operation ......................................................3 Changes to Table 1.............................................................................3 Added Electrical Characteristics—1.8 V Operation Heading .....4 Changes to Table 2.............................................................................4 Changes to Table 3, Thermal Resistance Section, and Table 4 ....5 Added TA = 25°C Condition to Typical Performance Characteristics Section .....................................................................6 Changes to Figure 3, Figure 4, Figure 6, and Figure 7 ..................6 Added Figure 11 and Figure 14 .......................................................7 Changes to Figure 17 Through Figure 20.......................................8 Changes to Figure 21 Through Figure 26.......................................9 Changes to Figure 27, Figure 28, Figure 30, and Figure 31....... 10 Changes to Figure 34, Figure 37, and Figure 38 ......................... 11 Added Figure 39 and Figure 40 .................................................... 12 Added Theory of Operation Section, Figure 41, and Figure 42 .......................................................................................... 13 Added Figure 43 and Figure 44 .................................................... 14 Added Applications Information Section and Figure 45 .......... 15 Added Figure 46 ............................................................................. 16 Updated Outline Dimensions ....................................................... 17 Added Figure 48 ............................................................................. 17 Changes to Ordering Guide .......................................................... 17 11/07—Revision 0: Initial Version Rev. E | Page 2 of 20 AD8505/AD8506/AD8508 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—1.8 V OPERATION VSY = 1.8 V, VCM = VSY/2, TA = 25°C, RL = 100 kΩ to GND, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Symbol Conditions VOS 0 V ≤ VCM ≤ 1.8 V −40°C ≤ TA ≤ +125°C Min IB Typ Max Unit 0.5 2.5 3.5 10 100 600 5 50 100 1.8 115 mV mV pA pA pA pA pA pA V dB dB dB dB 2.5 220 3 4.2 dB μV/°C GΩ pF pF 1 −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio CMRR Large-Signal Voltage Gain AVO Offset Voltage Drift Input Resistance Input Capacitance, Differential Mode Input Capacitance, Common Mode OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low ΔVOS/ΔT RIN CINDM CINCM VOH VOL Short-Circuit Limit POWER SUPPLY Power Supply Rejection Ratio ISC Supply Current per Amplifier AD8506/AD8508 ISY PSRR 0 85 85 80 95 100 95 RL = 100 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 10 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 100 kΩ to VSY −40°C ≤ TA ≤ +125°C RL = 10 kΩ to VSY −40°C ≤ TA ≤ +125°C VOUT = VSY or GND 1.78 1.78 1.65 1.65 VSY = 1.8 V to 5 V −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C 100 100 95 1.79 1.75 2 12 5 5 25 25 ±4.5 110 V V V V mV mV mV mV mA dB dB dB VOUT = VSY/2 −40°C ≤ TA ≤ +125°C VOUT = VSY/2 −40°C ≤ TA ≤ +125°C 16.5 SR GBP ΦM RL = 100 kΩ, CL = 10 pF, G = 1 RL = 1 MΩ, CL = 20 pF, G = 1 RL = 1 MΩ, CL = 20 pF, G = 1 13 95 60 mV/μs kHz Degrees en p-p en in f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 2.8 45 15 μV p-p nV/√Hz fA/√Hz AD8505 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density 0.5 −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C 0 V ≤ VCM ≤ 1.8 V −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C 0.05 V ≤ VOUT ≤ 1.75 V, RL = 100 kΩ to VCM −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C Rev. E | Page 3 of 20 16.5 20 25 24 27.5 μA μA μA μA AD8505/AD8506/AD8508 ELECTRICAL CHARACTERISTICS—5 V OPERATION VSY = 5 V, VCM = VSY/2, TA = 25°C, RL = 100 kΩ to GND, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Symbol Conditions VOS 0 V ≤ VCM ≤ 5 V −40°C ≤ TA ≤ +125°C Min IB Typ Max Unit 0.5 2.5 3.5 10 100 600 5 50 130 5 120 mV mV pA pA pA pA pA pA V dB dB dB dB 2 220 3 4.2 dB μV/°C GΩ pF pF 1 −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio CMRR Large-Signal Voltage Gain AVO Offset Voltage Drift Input Resistance Input Capacitance, Differential Mode Input Capacitance, Common Mode OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low ΔVOS/ΔT RIN CINDM CINCM VOH VOL Short-Circuit Limit POWER SUPPLY Power Supply Rejection Ratio ISC Supply Current per Amplifier AD8506/AD8508 ISY AD8505 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density PSRR 0.5 −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C 0 V ≤ VCM ≤ 5 V −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C 0.05 V ≤ VOUT ≤ 4.95 V, RL = 100 kΩ to VCM −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C 0 90 90 85 105 105 100 RL = 100 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 10 kΩ to GND −40°C ≤ TA ≤ +125°C RL = 100 kΩ to VSY −40°C ≤ TA ≤ +125°C RL = 10 kΩ to VSY −40°C ≤ TA ≤ +125°C VOUT = VSY or GND 4.98 4.98 4.9 4.9 VSY = 1.8 V to 5 V −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C 100 100 95 4.99 4.95 2 10 5 5 25 30 ±45 110 V V V V mV mV mV mV mA dB dB dB VOUT = VSY/2 −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C 15 SR GBP ΦM RL = 100 kΩ, CL = 10 pF, G = 1 RL = 1 MΩ, CL = 20 pF, G = 1 RL = 1 MΩ, CL = 20 pF, G = 1 13 95 60 mV/μs kHz Degrees en p-p en in f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 2.8 45 15 μV p-p nV/√Hz fA/√Hz Rev. E | Page 4 of 20 20 25 25.5 μA μA μA AD8505/AD8506/AD8508 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Supply Voltage Input Voltage Input Current1 Differential Input Voltage2 Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages with its exposed paddle soldered to a pad, if applicable. Table 4 shows simulated thermal values for a 4-layer (2S2P) JEDEC standard thermal test board, unless otherwise specified. Rating 5.5 V ±VSY ± 0.1 V ±10 mA ±VSY Indefinite −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C Table 4. 1 Input pins have clamp diodes to the supply pins. The input current should be limited to 10 mA or less whenever the input signal exceeds the power supply rail by 0.5 V. 2 The differential input voltage is limited to 5 V or the supply voltage, whichever is less. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Type 5-Lead SOT-23 (RJ-5) 6-Ball WLCSP (CB-6-7) 8-Lead MSOP (RM-8) 8-Ball WLCSP (CB-8-2) 14-Lead TSSOP (RU-14) 14-Ball WLCSP (CB-14-1) ESD CAUTION Rev. E | Page 5 of 20 θJA 190 105 142 82 112 64 θJC 92 N/A 45 N/A 35 N/A Unit °C/W °C/W °C/W °C/W °C/W °C/W AD8505/AD8506/AD8508 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 250 250 VSY = 1.8V VCM = VSY/2 VSY = 5V VCM = VSY/2 200 NUMBER OF AMPLIFIERS 150 100 150 100 –3 –2 –1 0 1 2 3 4 VOS (mV) 0 –4 06900-003 0 –4 –3 1 2 3 4 12 VSY = 5V –40°C ≤ TA ≤ +125°C VSY = 1.8V –40°C ≤ TA ≤ +125°C 14 10 12 NUMBER OF AMPLIFIERS 10 8 6 4 8 6 4 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 TCVOS (µV/°C) 0 06900-004 0 0 1 1000 1000 500 500 VOS (µV) 1500 0 –1000 –1000 –1500 –1500 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VCM (V) 06900-005 –500 0.4 6 7 8 9 10 11 12 13 Figure 9. Input Offset Voltage vs. Input Common-Mode Voltage VSY = 5V 0 –500 0.2 5 2000 VSY = 1.8V 0 4 Figure 11. Input Offset Voltage Drift Distribution 1500 –2000 3 TCVOS (µV/°C) Figure 8. Input Offset Voltage Drift Distribution 2000 2 06900-007 NUMBER OF AMPLIFIERS 0 Figure 10. Input Offset Voltage Distribution 16 VOS (µV) –1 VOS (mV) Figure 7. Input Offset Voltage Distribution 0 –2 06900-006 50 50 –2000 0 1 2 3 4 5 VCM (V) Figure 12. Input Offset Voltage vs. Input Common-Mode Voltage Rev. E | Page 6 of 20 06900-008 NUMBER OF AMPLIFIERS 200 AD8505/AD8506/AD8508 TA = 25°C, unless otherwise noted. –115 –120 VSY = 1.8V VSY = 5V –125 –120 VOS (µV) VOS (µV) –130 –125 –130 –135 –140 –135 0.6 0.8 1.0 VCM (V) 1.2 1.4 1.6 1.8 –150 500 450 450 IB (pA) 500 400 350 300 300 250 250 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VCM (V) 200 5 VSY = 5V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCM (V) Figure 14. Input Bias Current vs. Input Common-Mode Voltage at 125°C Figure 17. Input Bias Current vs. Input Common-Mode Voltage at 125°C 1000 1000 VSY = 1.8V VCM = VSY/2 VSY = 5V VCM = VSY/2 100 100 10 IB (pA) IB (pA) 10 1 1 0.1 0.1 35 45 55 65 75 85 95 TEMPERATURE (°C) 105 115 125 06900-018 0.01 25 4 400 350 06900-009 IB (pA) 550 0.2 3 600 VSY = 1.8V 0 2 Figure 16. Input Offset Voltage vs. Input Common-Mode Voltage 550 200 1 VCM (V) Figure 13. Input Offset Voltage vs. Input Common-Mode Voltage 600 0 06900-038 0.4 06900-012 0.2 0.01 25 Figure 15. Input Bias Current vs. Temperature 35 45 55 65 75 85 95 TEMPERATURE (°C) 105 Figure 18. Input Bias Current vs. Temperature Rev. E | Page 7 of 20 115 125 06900-019 0 06900-037 –140 –145 AD8505/AD8506/AD8508 TA = 25°C, unless otherwise noted. 10k OUTPUT VOLTAGE TO SUPPLY RAIL (mV) 1k 100 VOL VDD – VOH 10 1 0.1 0.001 0.01 0.1 LOAD CURRENT (mA) 1 10 1k 1 0.1 0.01 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 100 Figure 22. Output Voltage to Supply Rail vs. Load Current 14 12 VDD – VOH @ RL = 10kΩ 10 8 VOL @ RL = 10kΩ 6 4 VDD – VOH @ RL = 100kΩ 2 0 –40 VOL @ RL = 100kΩ –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) VOL @ RL = 10kΩ 6 4 VDD – VOH @ RL = 100kΩ 2 VOL @ RL = 100kΩ –25 –10 5 20 35 50 65 80 95 110 125 Figure 23. Output Voltage to Supply Rail vs. Temperature 90 VCM = VSY/2 80 TOTAL SUPPLY CURRENT (µA) 80 8 TEMPERATURE (°C) AD8508 AD8506 AD8505 VCM = VSY/2 VDD – VOH @ RL = 10kΩ 10 0 –40 Figure 20. Output Voltage to Supply Rail vs. Temperature 90 VSY = 5V 12 06900-014 OUTPUT VOLTAGE TO SUPPLY RAIL (mV) VSY = 1.8V 06900-011 70 60 50 40 30 20 10 70 60 50 40 AD8508, AD8508, AD8506, AD8606, AD8505, AD8505, 1.8V 5V 1.8V 5V 1.8V 5V 30 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 06900-052 10 SUPPLY VOLTAGE (V) 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 21. Total Supply Current vs. Supply Voltage Figure 24. Total Supply Current vs. Temperature Rev. E | Page 8 of 20 06900-053 OUTPUT VOLTAGE TO SUPPLY RAIL (mV) VOL 10 14 TOTAL SUPPLY CURRENT (µA) VDD – VOH 100 Figure 19. Output Voltage to Supply Rail vs. Load Current 0 VSY = 5V 06900-013 VSY = 1.8V 06900-010 OUTPUT VOLTAGE TO SUPPLY RAIL (mV) 10k AD8505/AD8506/AD8508 TA = 25°C, unless otherwise noted. 120 100 100 80 80 80 80 60 60 60 60 20 0 0 –20 –20 GAIN, CL = 0pF PHASE, CL = 0pF GAIN, CL = 50pF PHASE, CL = 50pF GAIN, CL = 100pF PHASE, CL = 100pF –40 –60 –80 –100 –120 100 1k –40 –60 10k FREQUENCY (Hz) 100k 40 20 0 0 –20 –60 –100 –80 –100 100 1k 40 CLOSED-LOOP GAIN (dB) G = –1 –10 –20 20 10k FREQUENCY (Hz) 0 VSY = 5V G = –100 –40 10k FREQUENCY (Hz) 100k 1M G = –1 –20 –40 1k G = –10 –10 –30 –50 100 –50 100 1k 10k FREQUENCY (Hz) 100k 1M Figure 29. Closed-Loop Gain vs. Frequency Figure 26. Closed-Loop Gain vs. Frequency 10k 10k VSY = 5V VSY = 1.8V 1k 1k G = 100 G = 100 G = 10 100 100 G = 10 G=1 G=1 ZOUT (Ω) 10 10 1 1 0.1 10 0.1 100 1k 10k FREQUENCY (Hz) 100k 1M 0.01 10 100 1k 10k FREQUENCY (Hz) Figure 30. ZOUT vs. Frequency Figure 27. ZOUT vs. Frequency Rev. E | Page 9 of 20 100k 1M 06900-031 ZOUT (Ω) –100 1M 100k 10 –30 06900-017 CLOSED-LOOP GAIN (dB) –80 30 G = –10 10 0 –60 50 30 20 –40 Figure 28. Open-Loop Gain and Phase vs. Frequency VSY = 1.8V G = –100 –20 GAIN, CL = 0pF PHASE, CL = 0pF GAIN, CL = 50pF PHASE, CL = 50pF GAIN, CL = 100pF PHASE, CL = 100pF –40 06900-020 40 40 GAIN Figure 25. Open-Loop Gain and Phase vs. Frequency 50 100 20 –80 –120 1M PHASE 120 PHASE (Degrees) 20 VSY = 5V 06900-025 40 GAIN 06900-022 40 PHASE (Degrees) VSY = 1.8V PHASE 06900-028 OPEN-LOOP GAIN (dB) 100 OPEN-LOOP GAIN (dB) 120 120 AD8505/AD8506/AD8508 TA = 25°C, unless otherwise noted. 100 90 80 80 CMRR (dB) 90 70 70 60 60 50 50 100 1k 10k FREQUENCY (Hz) 100k 1M 40 10 Figure 31. CMRR vs. Frequency 1k 10k FREQUENCY (Hz) VSY = 1.8V 90 80 80 70 70 60 60 PSRR (dB) 90 50 40 PSRR+ 20 VSY = 5V 50 40 PSRR+ 20 10 10 1k 10k 100k 1M FREQUENCY (Hz) 06900-023 100 0 10 100 100k 1M 80 80 VSY = 1.8V RL = 100kΩ VSY = 5V RL = 100kΩ 70 60 OVERSHOOT (%) 60 50 40 30 –OVERSHOOT 50 40 30 –OVERSHOOT 20 20 +OVERSHOOT +OVERSHOOT 10 10 100 LOAD CAPACITANCE (pF) 600 0 10 06900-027 OVERSHOOT (%) 10k Figure 35. PSRR vs. Frequency Figure 32. PSRR vs. Frequency 0 10 1k FREQUENCY (Hz) 06900-026 PSRR– PSRR– 70 1M 30 30 0 10 100k Figure 34. CMRR vs. Frequency 100 100 PSRR (dB) 100 100 LOAD CAPACITANCE (pF) Figure 36. Small-Signal Overshoot vs. Load Capacitance Figure 33. Small-Signal Overshoot vs. Load Capacitance Rev. E | Page 10 of 20 600 06900-030 40 10 VSY = 5V 06900-032 VSY = 1.8V 06900-029 CMRR (dB) 100 AD8505/AD8506/AD8508 TA = 25°C, unless otherwise noted. VSY = 1.8V RL = 100kΩ CL = 200pF G=1 TIME (100µs/DIV) 06900-035 06900-033 VOLTAGE (1V/DIV) VOLTAGE (500mV/DIV) VSY = 5V RL = 100kΩ CL = 200pF G=1 TIME (100µs/DIV) Figure 37. Large-Signal Transient Response Figure 40. Large-Signal Transient Response VSY = 1.8V RL = 100kΩ CL = 200pF G=1 TIME (100µs/DIV) Figure 38. Small-Signal Transient Response Figure 41. Small-Signal Transient Response 1k TIME (4s/DIV) 06900-034 VOLTAGE NOISE DENSITY (nV/√Hz) INPUT VOLTAGE NOISE (0.5µV/DIV) VSY = 1.8V AND 5V 2.78µV p-p VSY = 1.8V AND 5V 100 10 1 1 10 100 FREQUENCY (Hz) 1k Figure 42. Voltage Noise Density vs. Frequency Figure 39. Input Voltage Noise 0.1 Hz to 10 Hz Rev. E | Page 11 of 20 10k 06900-047 TIME (100µs/DIV) 06900-046 06900-036 VOLTAGE (5mV/DIV) VOLTAGE (5mV/DIV) VSY = 5V RL = 100kΩ CL = 200pF G=1 AD8505/AD8506/AD8508 TA = 25°C, unless otherwise noted. –40 –60 –70 –80 –90 –100 10kΩ –60 –70 –80 –90 –100 –110 1k 10k FREQUENCY (Hz) 100k Figure 43. Channel Separation vs. Frequency –120 100 1k 10k FREQUENCY (Hz) Figure 44. Channel Separation vs. Frequency Rev. E | Page 12 of 20 100k 06900-048 –110 –120 100 VSY = 5V VIN = 4V p-p 100kΩ –50 CHANNEL SEPARATION (dB) 10kΩ 06900-049 CHANNEL SEPARATION (dB) –50 –40 VSY = 1.8V VIN = 1.5V p-p 100kΩ AD8505/AD8506/AD8508 THEORY OF OPERATION VDD The AD8505/AD8506/AD8508 are unity-gain, stable, CMOS, railto-rail input/output operational amplifiers designed to optimize performance in current consumption, PSRR, CMRR, and zero crossover distortion, all embedded in a small package. The typical offset voltage is 500 μV, with a low peak-to-peak voltage noise of 2.8 μV from 0.1 Hz to 10 Hz and a voltage noise density of 45 nV/√Hz at 1 kHz. VBIAS VIN+ The AD8505/AD8506/AD8508 amplifiers are designed to solve two key problems in low voltage battery-powered applications: the battery voltage decrease over time and the rail-to-rail input stage distortion. The second problem with battery-powered applications is the distortion caused by the standard rail-to-rail input stage. Using a CMOS non-rail-to-rail input stage (that is, a single differential pair) limits the input voltage to approximately one VGS (gatesource voltage) away from one of the supply lines. Because VGS for normal operation is commonly over 1 V, a single differential pair input stage op amp greatly restricts the allowable input voltage range when using a low supply voltage. This limitation restricts the number of applications where the non-rail-to-rail input op amp was originally intended to be used. To solve this problem, a dual differential pair input stage is usually implemented (see Figure 45); however, this technique has its own drawbacks. One differential pair amplifies the input signal when the commonmode voltage is on the high end, whereas the other pair amplifies the input signal when the common-mode voltage is on the low end. This method also requires control circuitry to operate the two differential pairs appropriately. Unfortunately, this topology leads to a very noticeable and undesirable problem: if the signal level moves through the range where one input stage turns off and the other one turns on, noticeable distortion occurs (see Figure 46). Q1 Q2 Q4 VIN– IB 06900-039 IB VSS Figure 45. A Typical Dual Differential Pair Input Stage Op Amp (Dual PMOS Q1 and Q2 Transistors Form the Lower End of the Input Voltage Range, Whereas Dual NMOS Q3 and Q4 Compose the Upper End) 300 VSY = 5V TA = 25°C 250 200 150 100 50 VOS (µV) 0 –50 –100 –150 –200 –250 –300 0 0.5 1.0 1.5 2.0 2.5 3.0 VCM (V) 3.5 4.0 4.5 5.0 06900-040 In battery-powered applications, the supply voltage available to the IC is the voltage of the battery. Unfortunately, the voltage of a battery decreases as it discharges itself through the load. This voltage drop over the lifetime of the battery causes an error in the output of the op amps. Some applications requiring precision measurements during the entire lifetime of the battery use voltage regulators to power up the op amps as a solution. If a design uses standard battery cells, the op amps experience a supply voltage change from roughly 3.2 V to 1.8 V during the lifetime of the battery. This means that for a PSRR of 70 dB minimum in a typical op amp, the input-referred offset error is approximately 440 μV. If the same application uses the AD8505/AD8506/ AD8508 amplifiers with a 100 dB minimum PSRR, the error is only 14 μV. It is possible to calibrate out this error or to use an external voltage regulator to power the op amp, but these solutions can increase system cost and complexity. The AD8505/AD8506/ AD8508 amplifiers solve the impasse with no additional cost or error-nullifying circuitry. Q3 Figure 46. Typical Input Offset Voltage vs. Common-Mode Voltage Response in a Dual Differential Pair Input Stage Op Amp (Powered by 5 V Supply; Results of Approximately 100 Units per Graph Are Displayed) This distortion forces the designer to devise impractical ways to avoid the crossover distortion areas, therefore narrowing the common-mode dynamic range of the operational amplifier. The AD8505/AD8506/AD8508 amplifiers solve this crossover distortion problem by using an on-chip charge pump to power the input differential pair. The charge pump creates a supply voltage higher than the voltage of the battery, allowing the input stage to handle a wide range of input signal voltages without using a second differential pair. With this solution, the input voltage can vary from one supply extreme to the other with no distortion, thereby restoring the full common-mode dynamic range of the op amp. Rev. E | Page 13 of 20 AD8505/AD8506/AD8508 The charge pump has been carefully designed so that switching noise components at any frequency, both within and beyond the amplifier bandwidth, are much lower than the thermal noise floor. Therefore, the spurious-free dynamic range (SFDR) is limited only by the input signal and the thermal or flicker noise. There is no intermodulation between the input signal and the switching noise. Figure 48, the input offset voltage vs. input common-mode voltage response, shows the typical response of 12 devices. Figure 48 is expanded to make it easier to compare with Figure 46, the typical input offset voltage vs. common-mode voltage response in a dual differential pair input stage op amp. 300 250 Figure 47 displays a typical front-end section of an operational amplifier with an on-chip charge pump. 150 VPP = POSITIVE PUMPED VOLTAGE = VDD + 1.8V VPP 100 VDD VOS (µV) 50 VBIAS Q1 Q2 –IN CASCODE STAGE AND RAIL-TO-RAIL OUTPUT STAGE 0 –50 –100 –150 OUT –200 VSS Figure 47. Typical Front-End Section of an Op Amp with Embedded Charge Pump 0 0.5 1.0 1.5 2.0 2.5 3.0 VCM (V) 3.5 4.0 4.5 5.0 06900-042 –250 –300 06900-041 +IN VSY = 5V, TA = 25°C 200 Figure 48. Input Offset Voltage vs. Input Common-Mode Voltage Response (Powered by a 5 V Supply; Results of 12 Units Are Displayed) This solution improves the CMRR performance tremendously. For instance, if the input varies from rail to rail on a 2.5 V supply rail, using a part with a CMRR of 70 dB minimum, an input-referred error of 790 μV is introduced. Another part with a CMRR of 52 dB minimum generates a 6.3 mV error. The AD8505/AD8506/AD8508 CMRR of 90 dB minimum causes only a 79 μV error. As with the PSRR error, there are complex ways to minimize this error, but the AD8505/AD8506/AD8508 amplifiers solve this problem without incurring unnecessary circuitry complexity or increased cost. Rev. E | Page 14 of 20 AD8505/AD8506/AD8508 APPLICATIONS INFORMATION A pulse oximeter is a noninvasive medical device used for continuously measuring the percentage of hemoglobin (Hb) saturated with oxygen and the pulse rate of a patient. Hemoglobin that is carrying oxygen (oxyhemoglobin) absorbs light in the infrared (IR) region of the spectrum; hemoglobin that is not carrying oxygen (deoxyhemoglobin) absorbs visible red (R) light. In pulse oximetry, a clip containing two LEDs (sometimes more, depending on the complexity of the measurement algorithm) and the light sensor (photodiode) is placed on the finger or earlobe of the patient. One LED emits red light (600 nm to 700 nm) and the other emits light in the near IR (800 nm to 900 nm) region. The clip is connected by a cable to a processor unit. The LEDs are rapidly and sequentially excited by two current sources (one for each LED), whose dc levels depend on the LED being driven, based on manufacturer requirements, and the detector is synchronized to capture the light from each LED as it is transmitted through the tissue. drift of the total design need to be improved, then a more accurate and low temperature coefficient drift voltage reference and current source resistor should be utilized. C3 and C4 are used to improve stabilization of U1; R3 and R7 are used to provide some current limit into the U1 inverting pin; and R2 and R6 are used to slow down the rise time of the N-MOSFET when it turns on. These elements may not be needed, or some bench adjustments may be required. +5V +5V C1 0.1µF U1 1/2 8 R2 V 22Ω OUT1 V+ 7 Q1 IRLMS2002 V– 4 U2 ADG733 +5V S1A 12 14 D1 5 S1B 13 6 S2A 2 15 D2 S2B 1 C3 22pF R3 1kΩ R1 20Ω 0.1% 1/4W MIN 16 VDD AD8506 62.5mA An example design of a dc current source driving the red and infrared LEDs is shown in Figure 49. These dc current sources allow 62.5 mA and 101 mA to flow through the red and infrared LEDs, respectively. First, to prolong battery life, the LEDs are driven only when needed. One-third of the ADG733 SPDT analog switch is used to disconnect or connect the 1.25 V voltage reference from or to each current circuit. When driving the LEDs, the ADR1581 1.25 V voltage reference is buffered by half of the AD8506; the presence of this voltage on the noninverting input forces the output of the op amp (due to the negative feedback) to maintain a level that causes its inverting input to track the noninverting pin. Therefore, the 1.25 V appears in parallel with the 20 Ω R1 or 12.4 Ω R5 current source resistor, creating the flow of 62.5 mA or 101 mA current through the red or infrared LED as the output of the op amp turns on the Q1 or Q2 N-MOSFET IRLMS2002. The maximum total quiescent currents for the AD8506 (that is, half of the AD8506), ADR1581, and ADG733 are 25 μA, 70 μA, and 1 μA, respectively, resulting in a total of 96 μA current consumption (480 μW power consumption) per circuit, which is good for a system powered by a battery. If the accuracy and temperature C2 0.1µF CONNECT TO RED LED R4 53.6kΩ VREF = 1.25V U3 ADR1581 S3A 5 4 D3 S3B 3 RED CURRENT SOURCE 8 9 A2 10 A1 11 A0 6 EN GND VSS CONNECT TO INFRARED LED 101mA U1 1/2 7 +5V AD8506 R6 22Ω VOUT2 Q2 IRLMS2002 8 1 V+ V– 4 3 2 I_BIT2 I_BIT1 I_BIT0 I_ENA C4 22pF R7 1kΩ R5 INFRARED CURRENT 12.4Ω SOURCE 0.1% 1/2W MIN 06900-043 PULSE OXIMETER CURRENT SOURCE Figure 49. Pulse Oximeter Red and Infrared Current Sources Using the AD8506 as a Buffer to the Voltage Reference Device Rev. E | Page 15 of 20 AD8505/AD8506/AD8508 the I-to-V converter requires low input bias current. The AD8505/AD8506/AD8508 are excellent choices because these amplifiers provide 1 pA typical and 10 pA maximum of input bias current at ambient temperature. FOUR-POLE, LOW-PASS BUTTERWORTH FILTER FOR GLUCOSE MONITOR There are several methods of glucose monitoring: spectroscopic absorption of infrared light in the 2 μm to 2.5 μm range, reflectance spectrophotometry, and the amperometric type using electrochemical strips with glucose oxidase enzymes. The amperometric type generally uses three electrodes: a reference electrode, a control electrode, and a working electrode. Although this is a well established and widely used technique, signal-to-noise ratio and repeatability can be improved using the AD8505/ AD8506/AD8508 amplifiers with their low peak-to-peak voltage noise of 2.8 μV from 0.1 Hz to 10 Hz and voltage noise density of 45 nV/√Hz at 1 kHz. A low-pass filter with a cutoff frequency of 80 Hz to 100 Hz is desirable in a glucose meter device to remove extraneous noise; this can be a simple two-pole or four-pole Butterworth filter. Low power op amps with bandwidths of 50 kHz to 500 kHz should be adequate. The AD8505/AD8506/AD8508 amplifiers with their 95 kHz GBP and 15 μA typical current consumption meet these requirements. A circuit design of a four-pole Butterworth filter (preceded by a one-pole, low-pass filter) is shown in Figure 50. With a 3.3 V battery, the total power consumption of this design is 297 μW typical at ambient temperature. Another consideration is operation from a 3.3 V battery. Glucose signal currents are usually less than 3 μA full scale; therefore, C1 1000pF R1 5MΩ +3.3V WORKING CONTROL +3.3V 3 8 V+ 1 V– 2 4 U1 1/2 R3 22.6kΩ 5 C3 0.047µF 8 V+ 7 V– AD8506 U1 1/2 AD8506 6 4 +3.3V R4 22.6kΩ R5 22.6kΩ AD8506 3 C5 0.047µF 8 V+ 1 V– C2 0.1µF U2 1/2 2 VOUT 4 C4 0.1µF DUPLICATE OF CIRCUIT ABOVE 06900-044 REFERENCE R2 22.6kΩ Figure 50. A Four-Pole Butterworth Filter That Can Be Used in a Glucose Meter Rev. E | Page 16 of 20 AD8505/AD8506/AD8508 OUTLINE DIMENSIONS 3.00 2.90 2.80 5 1.70 1.60 1.50 1 4 2 3.00 2.80 2.60 3 0.95 BSC 1.90 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.20 MAX 0.08 MIN 10° 5° 0° SEATING PLANE 0.50 MAX 0.35 MIN 0.55 0.45 0.35 0.20 BSC 121608-A 1.30 1.15 0.90 COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 51. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 0.945 0.905 0.865 0.645 0.600 0.555 0.415 0.400 0.385 BALL A1 IDENTIFIER SEATING PLANE 0.287 0.267 0.247 1.425 1.385 1.345 2 1 A 0.80 BSC B 0.40 BSC C 0.230 0.200 0.170 0.05 NOM COPLANARITY 0.40 BSC Figure 52. 6-Ball Wafer Level Chip Scale Package [WLCSP] (CB-6-7) Dimensions shown in millimeters Rev. E | Page 17 of 20 BOTTOM VIEW (BALL SIDE UP) 081709-A TOP VIEW (BALL SIDE DOWN) AD8505/AD8506/AD8508 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 0.80 0.55 0.40 0.23 0.09 6° 0° 100709-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 53. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 0.650 0.595 0.540 1.460 1.420 SQ 1.380 SEATING PLANE 3 2 1 0.340 0.320 0.300 BALL 1 IDENTIFIER A B 0.50 BALL PITCH 0.380 0.355 0.330 COPLANARITY 0.075 C BOTTOM VIEW 0.270 0.240 0.210 Figure 54. 8-Ball Wafer Level Chip Scale Package [WLCSP] (CB-8-2) Dimensions shown in millimeters Rev. E | Page 18 of 20 (BALL SIDE UP) 011008-B TOP VIEW AD8505/AD8506/AD8508 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 1.20 MAX 0.20 0.09 SEATING PLANE 0.30 0.19 0.75 0.60 0.45 8° 0° 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 55. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 0.650 0.595 0.540 1.50 1.46 1.42 0.25 BSC 0.25 BSC 3 SEATING PLANE 2 0.25 BSC 0.25 BSC 1 A BALL 1 IDENTIFIER 0.50 BSC B 3.00 2.96 2.92 0.340 0.320 0.300 2.00 BSC 0.50 BSC C 0.50 BSC D E 0.380 0.355 0.330 0.10 MAX COPLANARITY 0.270 0.240 0.210 Figure 56. 14-Ball Wafer Level Chip Scale Package [WLCSP] (CB-14-1) Dimensions shown in millimeters Rev. E | Page 19 of 20 BOTTOM VIEW (BALL SIDE UP) 1.00 BSC 061208-A TOP VIEW (BALL SIDE DOWN) 0.50 BSC AD8505/AD8506/AD8508 ORDERING GUIDE Model1 AD8505ARJZ-R2 AD8505ARJZ-R7 AD8505ARJZ-RL AD8505ACBZ-R7 AD8505ACBZ-RL AD8506ACBZ-REEL AD8506ACBZ-REEL7 AD8506ARMZ AD8506ARMZ-R7 AD8506ARMZ-REEL AD8508ARUZ AD8508ARUZ-REEL AD8508ACBZ-REEL AD8508ACBZ-REEL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 5-Lead Small Outline Transistor Package [SOT-23] 5-Lead Small Outline Transistor Package [SOT-23] 5-Lead Small Outline Transistor Package [SOT-23] 6-Ball Wafer Level Chip Scale Package [WLCSP] 6-Ball Wafer Level Chip Scale Package [WLCSP] 8-Ball Wafer Level Chip Scale Package [WLCSP] 8-Ball Wafer Level Chip Scale Package [WLCSP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 14-Ball Wafer Level Chip Scale Package [WLCSP] 14-Ball Wafer Level Chip Scale Package [WLCSP] Z = RoHS Compliant Part. ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06900-0-5/10(E) Rev. E | Page 20 of 20 Package Option RJ-5 RJ-5 RJ-5 CB-6-7 CB-6-7 CB-8-2 CB-8-2 RM-8 RM-8 RM-8 RU-14 RU-14 CB-14-1 CB-14-1 Branding A2E A2E A2E A2H A2H A1X A1X A1X A1X A1X A27 A27