TI ADS5413-11IPHP Single 11-bit, 65-msps high if sampling Datasheet

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D Single-Ended or Differential Clock
D 1-GHz −3-dB Input Bandwidth
D 48-Pin TQFP Package With PowerPad
FEATURES
D 11-Bit Resolution
D 65-MSPS Maximum Sample Rate
D 2-Vpp Differential Input Range
D 3.3-V Single Supply Operation
D 1.8-V to 3.3-V Output Supply
D 400-mW Total Power Dissipation
D Two’s Complement Output Format
D On-Chip S/H and Duty Cycle Adjust Circuit
D Internal or External Reference
D 63.3-dBFS SNR and 72.9-dBc SFDR at
(7 mm x 7 mm body size)
APPLICATIONS
D Cellular Base Transceiver Station Receive
Channel
− High IF Sampling Applications
− CDMA: IS-95, UMTS, CDMA1X
− TDMA: GSM, IS-136, EDGE/UWC-136
− Wireless Local Loop
65 MSPS and 220-MHz Input
D Power-Down Mode
− Wideband Baseband Receivers
DESCRIPTION
The ADS5413−11 is a low power, 11-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from
a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and
low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit
allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous
sampling. The device can also be clocked with single ended or differential clock, without change in performance. The
internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the
application.
The device is specified over full temperature range (−40°C to +85°C).
FUNCTIONAL BLOCK DIAGRAM
AVDD
PWD
Gain
Stage
S/H
VINP
Gain
Stage
Σ
Σ
A/D
REF SEL
CML
VREFB
Flash
Σ
A/D
7 Stages
VINN
VREFT
Gain
Stage
OVDD
D/A
A/D
D/A
A/D
D/A
2.25 V
Internal
Reference
1.25 V Generator
1.8 V
2
VBG
2
2
2
Digital Error Correction
CLK
DCA
CLKC
DCA
D[0:10]
AGND
OGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
CommsADC is a trademark of Texas Instruments.
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Copyright  2004, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5413−11
HTQFP-48(2)
PowerPAD
PHP
−40°C to 85°C
A5413−11
ADS5413−11IPHP
Tray, 250
(1) For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2) Thermal pad size: 3,5 mm × 3,5 mm
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
AVDD measured with respect to AGND
Supply voltage range
−0.3 V to 3.9 V
OVDD measure with respect to OGND
−0.3 V to 3.9 V
Digital input, measured with respect to AGND
−0.3 V to AVDD + 0.3 V
Reference inputs Vrefb or Vreft, measured with respect to AGND
−0.3 V to AVDD + 0.3 V
Analog inputs Vinp or Vinn, measured with respect to AGND
−0.3 V to AVDD + 0.3 V
Maximum storage temperature
150°C
Soldering reflow temperature
235°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
NOM
MAX
UNIT
ENVIRONMENTAL
Operating free-air temperature, TA
−40
85
°C
3.6
V
3.6
V
SUPPLIES
Analog supply voltage, V(AVDD)
Output driver supply voltage, V(OVDD)
3
3.3
1.6
ANALOG INPUTS
CML(2)
Input common-mode voltage
Differential input voltage range
V
2
VPP
CLOCK INPUTS, CLK AND CLKC
Sample rate, fS = 1/tc
5
Differential input swing (see Figure 16)
1
Differential input common-mode voltage
Clock pulse width high, tw(H) (see Figure 15, with DCA off)
1.65
6.92
65
MHz
6
VPP
V
ns
Clock pulse width low, tw(L) (see Figure 15, with DCA off)
6.92
ns
(1) Recommended by design and characterization but not tested at final production unless specified under the electrical characteristics section.
(2) See V(CML) in the internal reference generator section.
2
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, clock frequency = 65 MSPS, 50% clock duty cycle (AVDD = OVDD = 3.3 V), duty cylce adjust off,
internal reference, AIN = −1 dBFS, 1.2-VPP square differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PERFORMANCE
Power Supply
Total analog supply current with internal reference and
DCA on
I(AVDD) Analog supply current with external reference and DCA on
113
AIN = 0 dBFS, fIN = 2 MHz
mA
96
Analog supply current with internal reference and DCA off
107
I(OVDD) Digital output driver supply current
PD
Total power dissipation
AIN = 0 dBFS, fIN = 2 MHz
AIN = 0 dBFS, fIN = 2 MHz
PD
Power down dissipation
DC Accuracy
PWDN = high
8
No missing codes
mA
400
480
mW
30
75
mW
Assured
DNL
Differential nonlinearity
Sinewave input, fIN = 2 MHz
−0.75
±0.3
0.75
LSB
INL
Integral nonlinearity
Sinewave input, fIN = 2 MHz
−1
±0.5
1
LSB
EO
EG
Offset error
Sinewave input, fIN = 2 MHz
3
Gain error
Sinewave input, fIN = 2 MHz
0.3
mV
%FS
Internal Reference Generator
VREFB Reference bottom
VREFT Reference top
1.1
1.25
1.4
V
2.1
2.25
2.4
V
VREFT − VREFB
VREFT − VREFB variation (6σ)
V(CML) Common-mode output voltage
Digital Inputs (PWD, DCA, REF SEL)
IIH
IIL
High-level input current
VIH
VIL
High-level input voltage
Low-level input current
VI = 2.4 V
VI = 0.3 V
1.06
V
0.06
V
1.8
V
−60
60
µA
−60
60
µA
2
V
Low-level input voltage
0.8
V
Digital Outputs
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = 50 µA
IOL = −50 µA
2.4
fIN = 14 MHz
fIN = 39 MHz
61.5
V
0.8
V
AC PERFORMANCE
SNR
Signal-to-noise ratio
Signal-to-noise and distortion
65.9
fIN = 70 MHz
fIN = 150 MHz
65.7
fIN = 190 MHz
fIN = 220 MHz
63.9
fIN = 14 MHz
fIN = 39 MHz
SINAD
65.7
64.3
dBFS
63.3
61
65.3
65.3
fIN = 70 MHz
fIN = 150 MHz
65.5
fIN = 190 MHz
fIN = 220 MHz
62.3
63.2
dBFS
62.4
3
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ELECTRICAL CHARACTERISTICS (CONTINUED)
over operating free-air temperature range, clock frequency = 65 MSPS, 50% clock duty cycle (AVDD = OVDD = 3.3 V), duty cylce adjust off,
internal reference, AIN = −1 dBFS, 1.2-VPP square differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
70
77.7
MAX
UNIT
AC PERFORMANCE (Continued)
fIN = 14 MHz
fIN = 39 MHz
SFDR
HD2
HD3
Spurious free dynamic range
Second order harmonic
Third order harmonic
Analog input bandwidth
75.8
fIN = 70 MHz
fIN = 150 MHz
84.5
fIN = 190 MHz
fIN = 220 MHz
68.3
dBc
70.5
72.9
fIN = 14 MHz
fIN = 39 MHz
95
fIN = 70 MHz
fIN = 150 MHz
89
fIN = 190 MHz
fIN = 220 MHz
84.5
fIN = 14 MHz
fIN = 39 MHz
77.6
fIN = 70 MHz
fIN = 150 MHz
85.5
fIN = 190 MHz
fIN = 220 MHz
68.3
94
dBc
79
72
75.4
dBc
70.5
77.6
−3 dB BW respect to −3 dBFS input at low
frequency
1
GHz
TIMING CHARACTERISTICS
25°C, CL = 10 pF
MIN
Aperture delay
td(A)
td(Pipe)
td1
td2
td1
td2
td1
td2
td1
4
2
Aperture jitter
0.4
Latency
6
Propagation delay from clock input to beginning of data stable(1)
Propagation delay from clock input to end of data stable(1)
DCS off, OVDD = 1.8 V
Propagation delay from clock input to beginning of data stable(1)
Propagation delay from clock input to end of data stable(1)
DCS off, OVDD = 3.3 V
Propagation delay from clock input to beginning of data stable(1)
Propagation delay from clock input to end of data stable(1)
DCS on, OVDD = 1.8 V
Propagation delay from clock input to beginning of data stable(1)
Propagation delay from clock input to end of data stable(1)
DCS on, OVDD = 3.3 V
td2
(1) Data stable if VO < 10% OVDD or VO > 90% OVDD
TYP
MAX
UNIT
ns
ps
Cycles
8
20.3
ns
7
20.3
ns
10
22.3
ns
9
22.3
ns
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TIMING DIAGRAM
Sample N
VINP
td(A)
tw(H)
td(Pipe)
tw(L)
CLK
tc
D[0:10]
Data N−7
td2(O)
Data N−6
Data N−5
Data N−4
Data N−3
Data N−2
Data N−1
Data N
Data N+1
Data N+2
td1(O)
Figure 1. ADS5413−11 Timing Diagram
PIN ASSIGNMENTS
OVDD
NC
AVDD
OGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
AGND
REF SEL
PHP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
AVDD
1
36
NC
AGND
VINP
2
3
35
34
D0 (LSB)
D1
VINN
AGND
4
5
33
32
D2
D3
31
D4
30
29
D5
D6
CML
6
AVDD
VREFB
7
8
VREFT
AVDD
9
10
28
27
D7
D8
AGND
NC
11
12
26
25
D9
D10 (MSB)
THERMAL PAD
(Connect to GND Plane)
OVDD
DCA
AGND
OGND
CLK
CLKC
AVDD
PWD
NC
NC
DECOUPLING
VBG
13 14 15 16 17 18 19 20 21 22 23 24
5
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AVDD
1, 7, 10, 18,
40, 44, 45, 47
I
Analog power supply
AGND
2, 5, 11, 21,
41, 42, 43, 46
I
Analog ground
CLK
19
I
Clock input
CLKC
20
I
Complementary clock input
CML
6
O
Common-mode output voltage
25−35
O
Digital outputs, D10 is most significant data bit, D0 is least significant data bit.
D10−D0
DCA
24
I
Duty cycle adjust control. High = enable, low = disable, NC = enable
DECOUPLING
15
O
Decoupling pin. Add 0.1 µF to GND
NC
12, 14, 17, 36,
37
Internally not connected
OGND
22, 39
I
Digital driver ground
OVDD
23, 38
I
Digital driver power supply
PWD
16
I
Power down. High = powered down, low = powered up, NC = powered up
REF SEL
48
I
Reference select. High = external reference, low = internal reference, NC = internal reference
VBG
13
O
Bandgap voltage output
VINN
4
I
Complementary analog input
VINP
3
I
Analog input
VREFB
8
I/O
Reference bottom
VREFT
9
I/O
Reference top
6
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TYPICAL CHARACTERISTICS†
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
fS = 65 MSPS
fIN = 2 MHz
SNR = 66 dBFS
SINAD = 65 dBFS
SFDR = 72.8 dBc
THD = 72 dBc
Amplitude − dBFS
−20
−40
−60
−80
−100
0
fS = 65 MSPS
fIN = 14 MHz
SNR = 65.7 dBFS
SINAD = 65.3 dBFS
SFDR = 77.7 dBc
THD = 76.2 dBc
−20
Amplitude − dBFS
0
−40
−60
−80
−100
−120
−120
−140
−140
0
5
10
15
20
25
0
30
5
Figure 3
30
SPECTRAL PERFORMANCE
0
fS = 65 MSPS
fIN = 70 MHz
SNR = 65.7 dBFS
SINAD = 65.5 dBFS
SFDR = 84.5 dBc
THD = 79.6 dBc
−20
−60
−80
−100
−120
−40
−60
−80
−100
−120
−140
−140
0
5
10
15
20
25
30
0
5
20
f − Frequency − MHz
Figure 5
25
30
SPECTRAL PERFORMANCE
0
fS = 65 MSPS
fIN = 190 MHz
SNR = 63.9 dBFS
SINAD = 62.3 dBFS
SFDR = 68.3 dBc
THD = 67.6 dBc
−20
Amplitude − dBFS
−40
15
Figure 4
fS = 65 MSPS
fIN = 150 MHz
SNR = 64.3 dBFS
SINAD = 63.2 dBFS
SFDR = 70.5 dBc
THD = 69.7 dBc
−20
10
f − Frequency − MHz
SPECTRAL PERFORMANCE
0
Amplitude − dBFS
25
Figure 2
Amplitude − dBFS
Amplitude − dBFS
−40
20
f − Frequency − MHz
fS = 65 MSPS
fIN = 39 MHz
SNR = 65.9 dBFS
SINAD = 65.3 dBFS
SFDR = 75.8 dBc
THD = 74 dBc
−20
15
f − Frequency − MHz
SPECTRAL PERFORMANCE
0
10
−60
−80
−100
−120
−40
−60
−80
−100
−120
−140
−140
0
5
10
15
20
25
30
0
5
10
15
20
f − Frequency − MHz
f − Frequency − MHz
Figure 6
Figure 7
25
30
† 50% duty cycle. AVDD = 3.3 V, OVDD = 3.3 V, 25°C, DCA off, internal reference, Ain = –1 dBFS, CLK 2.8-VPP sine wave single ended, unless
otherwise noted
7
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TYPICAL CHARACTERISTICS†
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fS = 65 MSPS
fIN = 220 MHz
SNR = 63.3 dBFS
SINAD = 62.4 dBFS
SFDR = 72.9 dBc
THD = 69.4 dBc
−40
fS = 40 MSPS
fIN = 70.5 MHz
SNR = 65.9 dBFS
SINAD = 65 dBFS
SFDR = 73.1 dBc
THD = 72.3 dBc
−20
Amplitude − dBFS
Amplitude − dBFS
−20
−60
−80
−100
−40
−60
−80
−100
−120
−120
−140
−140
0
5
10
15
20
25
0
30
5
10
f − Frequency − MHz
f − Frequency − MHz
Figure 8
Figure 9
AC PERFORMANCE
vs
REFERENCE VOLTAGES
AC Performance − dB
72
100
fS = 65 MSPS
fIN = 80 MHz
80
SFDR (dBc)
70
68
66
SNR (dBFS)
64
62
60
0.3
SNR (dBFS)
60
40
SFDR (dBc)
20
SNR (dBc)
0
−20
0.5
20
AC PERFORMANCE
vs
INPUT AMPLITUDE
AC Performance − dB
74
15
0.7
0.9
1.1
1.3
1.5
1.7
−40
−80
fS = 65 MSPS
fIN = 69 MHz
−70
−60
−50
−40
−30
−20
VrefT − VrefB − Reference Voltage Difference − V
PIN − Input Amplitude − dBFS
Figure 10
Figure 11
−10
0
AC PERFORMANCE
vs
INPUT AMPLITUDE
90
AC Performance − dB
SNR (dBFS)
60
SFDR (dBc)
30
SNR (dBc)
0
fS = 65 MSPS
fIN = 220 MHz
−30
−80
−70
−60
−50
−40
−30
−20
−10
0
PIN − Input Amplitude − dBFS
Figure 12
† 50% duty cycle. AVDD = 3.3 V, OVDD = 3.3 V, 25°C, DCA off, internal reference, Ain = –1 dBFS, CLK 2.8-VPP sine wave single ended, unless
otherwise noted
8
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TYPICAL CHARACTERISTICS†
62
100
61
63
64
59
63
90
fS − Sampling Frequency − MHz
60
64
80
58
59
60
61
62
63
65
57
60
61
62
56
58
64
62
63
65
70
64
65
66
60
50
66
65
40
66
65
64
30
65
20
64
20
0
62
63
65
10
64
60
80
61
60 59
140
61
59
60
57
58
120
100
63
62
61
62
40
63
160
180
200
220
fIN − Input Frequency − MHz
55
56
57
58
59
60
61
62
63
64
65
66
Figure 13. SNR− dBFS
100
69
73
80
65
69
71
73
77
60 75
79
63
65
67
67
69 71
70
61
63
67
90
fS − Sampling Frequency − MHz
59
81
65 69
65
79
77
75
69
73
83
73
81
79
77 81
30
73
71
73
69
71
69
20
69
71
75
73
69
40
55
60
60
80
100
120
fIN − Input Frequency − MHz
65
70
140
71
75
77
73
71
67
69
10
20
71
75
77
50
40
69
71
75
160
75
73
75
71
67
73
180
200
220
80
Figure 14. SFDR − dBc
† 50% duty cycle. AVDD = 3.3 V, OVDD = 3.3 V, 25°C, DCA off, internal reference, Ain = –1 dBFS, CLK 2.8-VPP sine wave single ended, unless
otherwise noted
9
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TYPICAL CHARACTERISTICS†
AC PERFORMANCE
vs
CLOCK AMPLITUDE
AC PERFORMANCE
vs
DUTY CYCLE
90
fS = 65 MSPS
fIN = 14.4 MHz
SFDR (DCA On)
80
AC Performance − dB
AC Performance − dB
85
75
SFDR (DCA Off)
70
SNR (DCA On)
65
60
SNR (DCA Off)
55
50
25
30
35
40
45
50
55
60
74
72
70
68
66
64
62
60
58
56
54
52
50
fS = 65 MSPS
fIN = 190 MHz
SNR Diff 3.3V
SNR SE 3.3V
SNR
Diff
1.8V
SNR SE 1.8V
SE = Single Ended
Diff = Differential Ended
1.8V = OVDD is 1.8 V
3.3V = OVDD is 3.3 V
1
2
3
Figure 15
74
65
64
DCA On
BP Filter
63
62
DCA On
No Filter
DCA Off
No Filter
25
50
75
100
125
150
SFDR
70
68
66
SNR
64
62
60
58
59
0
fS = 65 MSPS
fIN = 220 MHz
72
AC Performance − dB
SNR − Signal-to-Noise Ratio − dBFS
DCA Off
BP Filter
OVDD = 1.8 V
DCA Off
BP Filter
fS = 65 MSPS
7
AC PERFORMANCE
vs
ANALOG SUPPLY VOLTAGE
76
67
60
6
Figure 16
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
61
5
‡ Measured from CLK to CLKC
CLK 1.15-VPP square-wave differential
66
4
Clock Amplitude − VPP‡
Duty Cycle − %
NOTE:
SFDR Diff 3.3V
SFDR SE 3.3V
0
65
SFDR Diff 1.8V
SFDR SE 1.8V
175
200
225
56
3.0
3.2
3.4
fIN − Input Frequency − MHz
AVDD − Analog Supply Voltage − V
Figure 17
Figure 18
3.6
AC PERFORMANCE
vs
OUTPUT SUPPLY VOLTAGE
74
AC Performance − dB
72
SFDR
70
68
66
SNR
64
62
60
58
1.8
fS = 65 MSPS
fIN = 220 MHz
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
OVDD − Output Supply Voltage − V
Figure 19
† 50% duty cycle. AVDD = 3.3 V, OVDD = 3.3 V, 25°C, DCA off, internal reference, Ain = –1 dBFS, CLK 2.8-VPP sine wave single ended, unless
otherwise noted
10
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TYPICAL CHARACTERISTICS†
INTEGRAL NONLINEARITY
fS = 65 MSPS
fIN = 15.5 MHz
0.4
INL − Integral Nonlinearity − LSB
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY
0.5
0.3
0.2
0.1
0.0
−0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
500
1000
1500
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−0.0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
2000
fS = 65 MSPS
fIN = 15.5 MHz
0
Code
Code
Figure 21
fS = 65 MSPS
fIN = 220 MHz
2000
INPUT BANDWIDTH
SFDR
0
72
THD
70
68
66
SNR
64
−5
−10
−15
62
60
−40
1500
5
Output Power − dB‡
AC Performance − dB
74
1000
Figure 20
AC PERFORMANCE
vs
FREE-AIR TEMPERATURE
76
500
SINAD
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
100
−20
10
100
1k
10k
f − Frequency − MHz
‡ dB with respect to −3 dBFS
Figure 22
Figure 23
† 50% duty cycle. AVDD = 3.3 V, OVDD = 3.3 V, 25°C, DCA off, internal reference, Ain = –1 dBFS, CLK 2.8-VPP sine wave single ended, unless
otherwise noted
11
www.ti.com
SLWS156 − MARCH 2004
EQUIVALENT CIRCUITS
R2
φ2
R1
BAND
GAP
VREFT
R1
CML
120 Ω
R2
VREFB
φ1
φ1′
2 pF
VINP
AVDD
VINN
450 Ω
φ1
2 pF
φ1′
CML
CML
550 Ω
φ2
AGND
Figure 24. References
Figure 25. Analog Input Stage
AVDD
AVDD
To
Timing
Circuits
R1
5 kΩ
OVDD
R1
5 kΩ
AVDD
20 Ω
CLK
CLKC
AGND
R2
5 kΩ
R2
5 kΩ
D0−D10
AGND
OGND
AGND
Figure 26. Clock Inputs
12
Figure 27. Digital Outputs
www.ti.com
SLWS156 − MARCH 2004
APPLICATION INFORMATION
CONVERTER OPERATION
of an RF transformer. Since the input signal must be
biased around the common-mode voltage of the internal
circuitry, the common-mode (CML) reference from the
ADS5413−11 is connected to the center-tap of the
secondary. To ensure a steady low noise CML reference,
the best performance is obtained when the CML output is
connected to ground with a 0.1-µF and 0.01-µF low
inductance capacitor.
The ADS5413−11 is a 11-bit pipeline ADC. Its low power
(400 mW) at 65 MSPS and high sampling rate is achieved
using a state-of-the-art switched capacitor pipeline
architecture built on an advanced low-voltage CMOS
process. The ADS5413−11 analog core operates from a
3.3 V supply consuming most of the power. For additional
interfacing flexibility, the digital output supply (OVDD) can
be set from 1.6 V to 3.6 V. The ADC core consists of 10
pipeline stages and one flash ADC. Each of the stages
produces 1.5 bits per stage. Both the rising and the falling
clock edges are utilized to propagate the sample through
the pipeline every half clock, for a total of six clock cycles.
R0
Z0 = 50 Ω
1:1
VINP
50 Ω
R
ADS5413−11
50 Ω
VINN
VCM
AC Signal
Source
T1-1T
ANALOG INPUTS
The analog input for the ADS5413−11 consists of a
differential track-and-hold amplifier implemented using a
switched capacitor technique, shown in Figure 25. This
differential input topology, along with closely matched
capacitors, produces a high level of ac-performance up to
high sampling and input frequencies.
0.01 µF
Figure 28. Driving the ADS5413−11 Analog Input
With Impedance Matched Transmission Line
If it is necessary to buffer or apply a gain to the incoming
analog signal, it is possible to combine a single-ended
amplifier with an RF transformer as shown in Figure 29.
Texas Instruments offers a wide selection of operational
amplifiers, as the THS3001/2, the OPA847, or the OPA695
that can be selected depending on the application. RIN and
CIN can be placed to isolate the source from the switching
inputs of the ADC and to implement a low-pass RC filter to
limit the input noise in the ADC. Although not needed, it is
recommended to lay out the circuit with placement for
those three components, which allows fine tune of the
prototype if necessary. Nevertheless, any mismatch
between the differential lines of the input produces a
degradation in performance at high input frequencies,
mainly characterized by an increase in the even
harmonics. In this case, special care should be taken
keeping as much electrical symmetry as possible between
both inputs. This includes shorting RIN and leaving CIN
unpopulated.
The ADS5413−11 requires each of the analog inputs
(VINP and VINM) to be externally biased around the
common mode level of the internal circuitry (CML, pin 6).
For a full-scale differential input, each of the differential
lines of the input signal (pins 3 and 4) swings symmetrically
between CML+(Vreft+Vrefb)/2 and CML−(Vreft+Vrefb)/2.
The maximum swing is determined by the difference
between the two reference voltages, the top reference
(REFT), and the bottom reference (REFB). The total
differential full-scale input swing is 2(Vreft − Vrefb). See
the reference circuit section for possible adjustments of
the input full scale.
Although the inputs can be driven in single-ended
configuration, the ADS5413−11 obtains optimum
performance when the analog inputs are driven
differentially. The circuit in Figure 28 shows one possible
configuration. The single-ended signal is fed to the primary
5V
−5 V
+
VIN
RS
OPA690
−
R1
R2
0.1 µF
0.1 mF
1:n
RIN
RT R
IN
CIN
AIN+
ADS5413−11
AIN− CML
0.1 mF
Figure 29. Converting a Single-Ended Input Signal Into a Differential Signal Using an RF Transformer
13
www.ti.com
SLWS156 − MARCH 2004
Another possibility is the use of differential input/output
amplifiers that can simplify the driver circuit for applications
requiring input dc coupling. Flexible in their configurations
(see Figure 30), such amplifiers can be used for single ended
to differential conversion, for signal amplification, and for
filtering prior to the ADC.
CF
RS
VS
Rg
RT
Rg
VREFT
0.1 µF
0.1 µF
1 µF
Rf
VREFB
5V
3.3 V
10 µF
1 µF
Figure 10 shows the variation on SNR and SFDR for a
sampling rate of 65 MHz and a single-tone input of 80 MHz
at −1 dBFS for different VREFT−VREFB voltage settings.
0.1 µF
0.1 µF
+ −
VOCM
+
−
IN
IN
ADS5413−11
11 Bit/65 MSPS
CML
THS4503
−5 V
1 µF
VBG
0.1 µF
10 µF 0.1 µF
1 µF
0.1 µF
Rf
Figure 31. Internal Reference Usage
CF
Figure 30. Using the THS4503 With the
ADS5413−11
REFERENCE CIRCUIT
The ADS5413−11 has its own internal reference
generation saving external circuitry in the design. For
optimum performance, it is best to connect both VREFB
and VREFT to ground with a 1-µF and a 0.1-µF decoupling
capacitor in parallel and a 0.1-µF capacitor between both
pins (see Figure 31). The series inductance with these
capacitors should be minimized as much as possible. For
that we recommend to follow the layout of the EVM. In
particular, the 0.1-µF capacitors should be placed on the
same side of the printed circuit board as the ADS5413−11,
and as close as possible to the pins 8, 9, and 11. The
band-gap voltage output is not a voltage source to be used
external to the ADS5413−11. However, it should be
decoupled to ground with a 1-µF and a 0.01-µF capacitor
in parallel.
For even more design flexibility, the internal reference can
be disabled using the pin 48. By default, this pin is
internally connected with a 70-kΩ pulldown resistor to
ground, which enables the internal reference circuit. Tying
this pin to AVDD powers down the internal reference
generator, allowing the user to provide external voltages
for VREFT (pin 9) and VREFB (pin 8). In addition to the
power consumption reduction (typically 56 mW) which is
now transferred to the external circuitry, it also allows for
a precise setting of the input range. To further remove any
variation with external factors, such as temperature or
supply voltage, the user has direct access to the internal
resistor divider, without any intermediate buffering. The
equivalent circuit for the reference input pins is shown in
Figure 24. The core of the ADC is designed for a 1 V
difference between the reference pins. Nevertheless, the
user can use these pins to set a different input range.
14
CLOCK INPUTS
The ADS5413−11 clock input can be driven with either a
differential clock signal or a single ended clock input with
little or no difference in performance between the
single-ended and differential-input configurations (see
Figure 16). The common mode of the clock inputs is set
internally to AVDD/2 using 5-kΩ resistors (see Figure 26).
When driven with a single-ended clock input, it is best to
connect the CLKC input to ground with a 0.01-µF capacitor
(see Figure 32), while CLK is ac-coupled with 0.01 µF to
the clock source.
Square Wave or
Sine Wave
1 Vp-p to 3 Vp-p
CLK
0.01 µF
ADS5413−11
CLKC
0.01 µF
Figure 32. AC-Coupled Single-Ended Clock Input
The ADS5413−11 clock input can also be driven
differentially. In this case, it is best to connect both clock
inputs to the differential input clock signal with 0.01-µF
capacitors (see Figure 33). The differential input swing can
vary between 1 V and 6 V with little or no performance
degradation (see Figure 16).
CLK
Differential Square Wave or
Sine Wave
1 Vp-p to 6 Vp-p
0.01 µF
ADS5413−11
CLKC
0.01 µF
Figure 33. AC-Coupled Differential Clock Input
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SLWS156 − MARCH 2004
The ADS5413−11 can be driven either with a sine wave or
a square wave. The internal ADC core uses both edges of
the clock for the conversion process. This means that
ideally, a 50% duty cycle should be provided.
Nevertheless, the ADC includes an on-board duty cycle
adjuster (DCA) that adjusts the incoming clock duty cycle
which may not be 50%, to a 50% duty cycle for the internal
use. By default, this circuit is enabled internally (with a
pull-up resistor of 70 kΩ), which relaxes the design
specifications of the external clock. Nevertheless, there
are some situations where the user may prefer to disable
the DCA. For asynchronous clocking, i.e., when the
sampling period is purposely not constant, this circuit
should be disabled. Another situation is the case of high
input frequency sampling. For high input frequencies, a
low jitter clock should be provided. On that sense, we
recommend to band-pass filter the source which,
consequently, provides a sinusoidal clock with 50% duty
cycle. The use of the DCA on that case would not be
beneficial and adds noise to the internal clock, increasing
the jitter and degrading the performance. Figure 17 shows
the performance versus input frequency for the different
clocking schemes. Finally, adding the DCA introduces
delay between the input clock and the output data and
what is more important, slightly bigger variation of this
delay versus external conditions, such as temperature. To
disable the DCA, user should connect it to ground.
POWER DOWN
When power down (pin 16) is tied to AVDD, the device
reduces its power consumption to a typical value of
23 mW. Connecting this pin to AGND or leaving it not
connected (an internal 70-kΩ pulldown resistor is
provided) enables the device operation.
DIGITAL OUTPUTS
The ADS5413−11 output format is 2s complement. The
voltage level of the outputs can be adjusted by setting the
OVDD voltage between 1.6 V and 3.6 V, allowing for direct
interface to several digital families. For better
performance, customers should select the smaller output
swing required in the application. To improve the
performance, mainly on the higher output voltage swing
configurations, the addition of a series resistor at the
outputs, limiting peak currents, is recommended. The
maximum value of this resistor is limited by the maximum
data rate of the application. Values between 0 Ω and
200 Ω are usual. Also, limiting the length of the external
traces is a good practice.
All the data sheet plots have been obtained in the worst
case situation, where OVDD is 3.3 V. The external series
resistors were 150 Ω and the load was a 74AVC16244
buffer, as the one used in the evaluation board. In this
configuration, the rising edge of the ADC output is 5 ns,
which allows for a window to capture the data of 10.4 ns
(without including other factors).
15
www.ti.com
SLWS156 − MARCH 2004
DEFINITION OF SPECIFICATIONS
Maximum Conversion Rate
Analog Bandwidth
The clock rate at which parametric testing is performed.
The analog bandwidth is the analog input frequency at
which the spectral power of the fundamental frequency (as
determined by the FFT analysis) is reduced by 3 dB in
respect to the value measured at low input frequencies.
Power Supply Rejection Ratio
Aperture Delay
The delay between the 50% point of the rising edge of the
CLK command and the instant at which the analog input
is sampled.
Aperture Uncertainity (Jitter)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full
scale) to rms value of the sum of all other spectral
components, including harmonics but excluding dc.
The sample-to-sample variation in aperture delay.
Signal-to-Noise Ratio (Without Harmonics)
Differential Nonlinearity
The average deviation of any single LSB transition at the
digital output from an ideal 1 LSB step at the analog input.
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the the sum of all other spectral
components, excluding the first five harmonics and dc.
Integral Nonlinearity
Spurious-Free Dynamic Range
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic and it is
reported in dBc.
Clock Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
CLK pulse should be left in logic 1 state to achieve rated
performance; pulse width low is the minimum time CLK
pulse should be left in low state. At a given clock rate, these
specifications define acceptable clock duty cycles.
16
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product
reported in dBc.
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
ADS5413-11IPHP
ACTIVE
HTQFP
PHP
Pins Package Eco Plan (2)
Qty
48
250
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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