LMS12 LMS12 DEVICES INCORPORATED 12-bit Cascadable Multiplier-Summer 12-bit Cascadable Multiplier-Summer DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 12 x 12-bit Multiplier with Pipelined 26-bit Output Summer The LMS12 is a high-speed 12 x 12-bit combinatorial multiplier integrated with a 26-bit adder in a single 84-pin package. It is an ideal building block for the implementation of very highspeed FIR filters for video, RADAR, and other similar applications. The LMS12 implements the general form (A•B) + C. As a result, it is also useful in implementing polynomial approximations to transcendental functions. ❑ Summer has 26-bit Input Port Fully Independent from Multiplier Inputs ❑ Cascadable to Form Video Rate FIR Filter with 3-bit Headroom ❑ A, B, and C Input Registers Separately Enabled for Maximum Flexibility ❑ 28 MHz Data Rate for FIR Filtering Applications ARCHITECTURE ❑ High Speed, Low Power CMOS Technology A block diagram of the LMS12 is shown below. Its major features are discussed individually in the following paragraphs. ❑ 84-pin PLCC, J-Lead MULTIPLIER The A11-0 and B11-0 inputs to the LMS12 are captured at the rising edge of the clock in the 12-bit A and B input registers, respectively. These registers are independently enabled by the LMS12 BLOCK DIAGRAM A 11-0 B 11-0 12 12 A REGISTER ENA B REGISTER ENB CLK 24 PRODUCT REGISTER 26 26 FTS 2 24 S REGISTER C 25-0 C REGISTER SIGN EXTENDED S 25-0 26 ENA and ENB inputs. The registered input data are then applied to a 12 x 12-bit multiplier array, which produces a 24-bit result. Both the inputs and outputs of the multiplier are in two’s complement format. The multiplication result forms the input to the 24-bit product register. SUMMER The C 25-0 inputs to the LMS12 form a 26-bit two’s complement number which is captured in the C register at the rising edge of the clock. The C register is enabled by assertion of the ENC input. The summer is a 26-bit adder which operates on the C register data and the sign extended contents of the product register to produce a 26-bit sum. This sum is applied to the 26-bit S register. OUTPUT The FTS input is the feedthrough control for the S register. When FTS is asserted, the summer result is applied directly to the S output port. When FTS is deasserted, data from the S register is output on the S port, effecting a one-cycle delay of the summer result. The S output port can be forced to a high-impedance state by driving the OE control line high. FTS would be asserted for conventional FIR filter applications, however the insertion of zero-coefficient filter taps may be accomplished by negating FTS. Negating FTS also allows application of the same filter transfer function to two interleaved datastreams with successive input and output sample points occurring on alternate clock cycles. 26 OE ENC Multiplier-Summers 1 08/16/2000–LDS.S12-J LMS12 DEVICES INCORPORATED FIGURE 1. 12-bit Cascadable Multiplier-Summer FLOW DIAGRAM FOR 5-TAP FIR FILTER x(n) h4 h2 h3 Z –1 h0 h1 Z –1 Z –1 Z –1 y(n) x(n) A4 A3 A2 A1 A0 h4 h3 h2 h1 h0 Z –1 Z –1 Z –1 Z –1 Z –1 APPLICATIONS The LMS12 is designed specifically for high-speed FIR filtering applications requiring a throughput rate of one output sample per clock period. By cascading LMS12 units, the transpose form of the FIR transfer function is implemented directly, with each of the LMS12 units supplying one of the filter weights, and the cascaded summers accumulating the results. The signal flow graph for a 5-tap FIR filter and the equivalent implementation using LMS12’s is shown in Figure 1. The operation of the 5-tap FIR filter implementation of Figure 1 is depicted in Table 1. The filter weights h4 - h0 are assumed to be latched in the B input registers of the LMS12 units. The x(n) data is applied in parallel to the A input registers of all devices. For descriptive purposes in the table, the A register contents and sum output data of each device is labelled y(n) according to the index of the weight applied by that device; i.e., S0 is produced by the rightmost device, which has h0 as its filter weight and A0 as its input register contents. Each column represents one clock cycle, with the data passing a particular point in the system illustrated across each row. Multiplier-Summers 2 08/16/2000–LDS.S12-J LMS12 DEVICES INCORPORATED TABLE 1. 12-bit Cascadable Multiplier-Summer TIMING EXAMPLE FOR 5-TAP NONDECIMATING FIR FILTER CLK Cycle 1 2 3 4 X(n) Xn Xn+1 Xn+2 Xn+3 Xn+4 Xn+5 Xn+6 Xn+7 Xn+8 A4 Register Sum 4 Xn Xn+1 h4Xn Xn+2 h4Xn+1 Xn+3 h4Xn+2 Xn+4 h4Xn+3 Xn+5 h4Xn+4 Xn+6 h4Xn+5 Xn+7 h4Xn+6 A3 Register Sum 3 Xn Xn+1 h3Xn + h4Xn–1 Xn+2 h3Xn+1 + h4Xn Xn+3 h3Xn+2 + h4Xn+1 Xn+4 h3Xn+3 + h4Xn+2 Xn+5 h3Xn+4 + h4Xn+3 Xn+6 h3Xn+5 + h4Xn+4 Xn+7 h3Xn+6 + h4Xn+5 A2 Register Sum 2 Xn Xn+1 h2Xn + h3Xn–1 + h4Xn–2 Xn+2 h2Xn+1 + h3Xn + h4Xn–1 Xn+3 h2Xn+2 + h3Xn+1 + h4Xn Xn+4 h2Xn+3 + h3Xn+2 + h4Xn+1 Xn+5 h2Xn+4 + h3Xn+3 + h4Xn+2 Xn+6 h2Xn+5 + h3Xn+4 + h4Xn+3 Xn+7 h2Xn+6 + h3Xn+5 + h4Xn+4 A1 Register Sum 1 Xn Xn+1 h1Xn + h2Xn–1 + h3Xn–2 + h4Xn–3 Xn+2 h1Xn+1 + h2Xn + h3Xn–1 + h4Xn–2 Xn+3 h1Xn+2 + h2Xn+1 + h3Xn + h4Xn–1 Xn+4 h1Xn+3 + h2Xn+2 + h3Xn+1 + h4Xn Xn+5 h1Xn+4 + h2Xn+3 + h3Xn+2 + h4Xn+1 Xn+6 h1Xn+5 + h2Xn+4 + h3Xn+3 + h4Xn+2 Xn+7 h1Xn+6 + h2Xn+5 + h3Xn+4 + h4Xn+3 A0 Register Sum 0 Xn Xn+1 h0Xn + h1Xn–1 + h2Xn–2 + h3Xn–3 + h4Xn–4 Xn+2 h0Xn+1 + h1Xn + h2Xn–1 + h3Xn–2 + h4Xn–3 Xn+3 h0Xn+2 + h1Xn+1 + h2Xn + h3Xn–1 + h4Xn–2 Xn+4 h0Xn+3 + h1Xn+2 + h2Xn+1 + h3Xn + h4Xn–1 Xn+5 h0Xn+4 + h1Xn+3 + h2Xn+2 + h3Xn+1 + h4Xn Xn+6 h0Xn+5 + h1Xn+4 + h2Xn+3 + h3Xn+2 + h4Xn+1 Xn+7 h0Xn+6 + h1Xn+5 + h2Xn+4 + h3Xn+3 + h4Xn+2 FIGURE 2A. 5 6 7 8 9 INPUT FORMATS AIN BIN Fractional Two’s Complement 11 10 9 –20 2–1 2–2 2 1 0 2–9 2–10 2–11 11 10 9 –20 2–1 2–2 (Sign) 2 1 0 2–9 2–10 2–11 (Sign) Integer Two’s Complement 11 10 9 –211 210 29 2 1 0 22 21 20 11 10 9 –211 210 29 (Sign) FIGURE 2B. 2 1 0 22 21 20 (Sign) OUTPUT FORMATS Fractional Two’s Complement 25 24 –23 22 23 22 21 21 20 2–1 14 13 12 2–8 2–9 2–10 11 10 9 2–11 2–12 2–13 2 1 0 2–20 2–21 2–22 (Sign) Integer Two’s Complement 25 24 –225 224 23 22 21 223 222 221 14 13 12 214 213 212 11 10 9 211 210 29 2 1 0 22 21 20 (Sign) Multiplier-Summers 3 08/16/2000–LDS.S12-J LMS12 DEVICES INCORPORATED 12-bit Cascadable Multiplier-Summer MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 VOL Output Low Voltage VCC = Min., IOL = 4.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max Unit V 0.5 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±20 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 25 mA ICC2 VCC Current, Quiescent (Note 7) 1.0 mA 15 Multiplier-Summers 4 08/16/2000–LDS.S12-J LMS12 DEVICES INCORPORATED 12-bit Cascadable Multiplier-Summer SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) Symbol LMS12– 12345678901234567890123 12345678901234567890123 12345678901234567890123 * * 65 50 40 12345678901234567890123 12345678901234567890123 12345678901234567890123 Min Max Min Max Min Max 12345678901234567890123 12345678901234567890123 40 35 30 12345678901234567890123 12345678901234567890123 12345678901234567890123 12345678901234567890123 15 15 12 12345678901234567890123 12345678901234567890123 12345678901234567890123 15 12 12 12345678901234567890123 12345678901234567890123 12345678901234567890123 15 10 7 12345678901234567890123 12345678901234567890123 12345678901234567890123 15 12 12 12345678901234567890123 12345678901234567890123 12345678901234567890123 5 5 5 12345678901234567890123 12345678901234567890123 12345678901234567890123 12345678901234567890123 5 5 5 12345678901234567890123 12345678901234567890123 12345678901234567890123 5 5 5 12345678901234567890123 12345678901234567890123 12345678901234567890123 50 40 35 12345678901234567890123 12345678901234567890123 12345678901234567890123 25 25 25 12345678901234567890123 12345678901234567890123 12345678901234567890123 12345678901234567890123 25 25 25 12345678901234567890123 12345678901234567890123 12345678901234567890123 22 22 22 12345678901234567890123 Parameter tCP Clock Period tPW Clock Pulse Width tSAB A, B, Data Setup Time tSC C Data Setup Time tSEN ENA, ENB, ENC Setup Time tHAB A, B, Data Hold Time tHC C Data Hold Time tHEN ENA, ENB, ENC Hold Time tD Clock to S–FT = 1 Clock to S–FT = 0 tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) 35 Min Max 25 8 10 7 10 2 2 2 30 20 20 20 SWITCHING WAVEFORMS INPUTS A, B, C tSAB tSC tHAB tHC tSEN tHEN ENA ENB, ENC tPW CLOCK tPW S OUTPUTS tD OE tDIS tENA HIGH IMPEDANCE R OUTPUTS 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE 123456789012345678901234 Multiplier-Summers 5 08/16/2000–LDS.S12-J LMS12 DEVICES INCORPORATED 12-bit Cascadable Multiplier-Summer SWITCHING CHARACTERISTICS MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) Symbol LMS12– 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 * 65 50* 40* 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 Min Max Min Max Min Max 1234567890123456789012345678901212 1234567890123456789012345678901212 40 35 30 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 15 15 12 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 15 15 12 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 15 15 12 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 15 15 12 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 5 5 5 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 5 5 5 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 5 5 5 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 50 45 35 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 25 25 25 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 25 25 25 1234567890123456789012345678901212 1234567890123456789012345678901212 1234567890123456789012345678901212 22 22 22 1234567890123456789012345678901212 Parameter tCP Clock Period tPW Clock Pulse Width tSAB A, B, Data Setup Time tSC C Data Setup Time tSEN ENA, ENB, ENC Setup Time tHAB A, B, Data Hold Time tHC C Data Hold Time tHEN ENA, ENB, ENC Hold Time tD Clock to S–FT = 1 Clock to S–FT = 0 tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) SWITCHING WAVEFORMS INPUTS A, B, C tSAB tSC tHAB tHC tSEN tHEN ENA ENB, ENC tPW CLOCK tPW S OUTPUTS tD OE tDIS tENA HIGH IMPEDANCE R OUTPUTS 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE 123456789012345678901234 Multiplier-Summers 6 08/16/2000–LDS.S12-J LMS12 DEVICES INCORPORATED 12-bit Cascadable Multiplier-Summer NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a min- 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency Multiplier-Summers 7 08/16/2000–LDS.S12-J LMS12 DEVICES INCORPORATED 12-bit Cascadable Multiplier-Summer ORDERING INFORMATION B1 B0 ENA A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ENC C0 C1 C2 C3 C4 84-pin 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 72 15 71 16 70 17 69 18 68 19 67 20 66 Top View 21 22 23 65 64 63 24 62 25 61 26 60 27 59 28 58 29 57 30 56 31 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 GND C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 C25 B2 B3 B4 CLK B5 B6 B7 B8 B9 B10 B11 ENB S25 S24 S23 S22 S21 S20 OE FTS VCC Plastic J-Lead Chip Carrier (J3) Speed 0°C to +70°C — COMMERCIAL SCREENING 40 ns 35 ns LMS12JC40 LMS12JC35 Multiplier-Summers 8 08/16/2000–LDS.S12-J LMS12 DEVICES INCORPORATED 12-bit Cascadable Multiplier-Summer ORDERING INFORMATION 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 84-pin 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1 2 3 4 5 6 7 8 9 10 11 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 A 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 A8 A2 ENC C1 A9 A6 C2 GND B1 ENA A11 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 B 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 A10 A7 A3 A1 C3 C4 C0 C6 B0 B4 B2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 A5 A4 A0 C5 C7 CLK B3 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 D 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C8 C9 B5 B6 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 E 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Top View 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C13 C11 C12 B10 B9 B8 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Through Package F 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C14 C15 C10 B11 ENB B7 (i.e., Component Side Pinout) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 G 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C18 C17 C16 S25 S24 S23 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 H 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C20 C19 S22 S21 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 J 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 S10 S9 S5 C23 C21 S20 FTS 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 K 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 S6 S3 S0 C24 C22 OE S19 S18 S15 S12 S13 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 L 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 S8 S7 S4 S2 S1 C25 VCC S17 S16 S14 S11 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Discontinued Package 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Ceramic Pin Grid Array (G3) Speed 0°C to +70°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Multiplier-Summers 9 08/16/2000–LDS.S12-J