MPS HR1001CGS Enhanced llc controller with adaptive dead-time control, capacitive mode protection and enhanced surge protection Datasheet

HR1001C
Enhanced LLC Controller with
Adaptive Dead-Time Control,
Capacitive Mode Protection and
Enhanced Surge Protection
DESCRIPTION
The HR1001C is an enhanced LLC controller
that provides adaptive dead-time adjustment
(ADTA) and capacitive mode protection (CMP)
features, as well as functional improvements on
surge performance.
ADTA inserts a dead time between the two
complimentary gate outputs automatically. This
is ensured by keeping the outputs off while
sensing the dV/dt current of the half-bridge
switching node. ADTA features easier design,
lower EMI, and higher efficiency.
The HR1001C incorporates anti-capacitive
mode protection, which prevents potentially
destructive capacitive mode switching if the
output is shorted or has a severe overload.
This feature protects the MOSFET during
abnormal conditions, making the converter
robust.
The HR1001C has a programmable oscillator
that sets both the maximum and minimum
switching frequencies. It starts up at a
programmed maximum switching frequency
and decays until the control loop takes over to
prevent excessive inrush current.
The HR1001C enters a controlled burst mode
at light load to minimize power consumption
and tighten the output regulation.
Full protection features include two-level overcurrent protection (OCP) with external latch
shutdown, auto-recovery, brown-in and brownout, capacitive mode protection (CMP), and
over-temperature protection (OTP), improving
converter design safety with minimal extra
components.
HR1001C Rev.1.0
2/6/2017
FEATURES












Over-Current Protection (OCP) with
Programmable Delay for Enhanced Surge
Performance
Adaptive Dead-Time Adjustment (ADTA)
Capacitive Mode Protection (CMP)
50% Duty Cycle, Variable Frequency
Control for Resonant Half-Bridge Converter
600V High-Side Gate Driver with Integrated
Bootstrap Diode with a High-Accuracy
Oscillator of High dV/dt Immunity
Operates up to 600kHz
Two-Level Over-Current Protection (OCP):
Frequency Shift and Latched Shutdown with
Programmable Duration Time
Latched Disable Input for Easy Protection
Remote On/Off Control and Brown-Out
Protection through BO
Programmable Burst Mode Operation at
Light Load
Non-Linear Soft Start for Monotonic Output
Voltage Rise
Available in a SOIC-16 Package
APPLICATIONS






LCD and PDP TVs
Desktop PCs and Servers
Telecom SMPS
AC/DC Adapter, Open-Frame SMPS
Video Game Consoles
Electronic Lighting Ballasts
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology”
are registered trademarks of Monolithic Power Systems, Inc.
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
1
HR1001C – ENHANCED LLC CONTROLLER
Typical Application
BO
SS
16
1
TIMER
15
2
CT
14
3
CT
FSET
4 HR1001C 13
Rfmax BURST
12
5
CS
Rfmin
11
6
BO
10
7
LATCH
9
8
Rss
Css
BST
Vdc
Cbst
HG
S1
Lr
SW
NC
VCC
CHBVS
D1
S2
Output
Lm
LG
GND
VCC
HBVS
Cr
D2
Rf
Cf
Rs
Cs
TL431
HR1001C Rev.1.0
2/6/2017
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2
HR1001C – ENHANCED LLC CONTROLLER
ORDERING INFORMATION
Part Number*
HR1001CGS
Package
SOIC-16
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. HR1001CGS–Z)
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
HR1001C: Part number
LLLLLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
SS
1
16
BST
TIMER
2
15
HG
CT
3
14
SW
FSET
4
13
NC
BURST
5
12
VCC
CS
6
11
LG
BO
7
10
GND
LATCH
8
9
HBVS
HR1001C
SOIC-16
HR1001C Rev.1.0
2/6/2017
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3
HR1001C – ENHANCED LLC CONTROLLER
ABSOLUTE MAXIMUM RATINGS
(1)
BST voltage ................................. -0.3V to 618V
SW voltage ..................................... -3V to 600V
Max voltage slew rate of SW................... 50V/ns
Supply voltage (VCC) ...................... Self-limited
Sink current of HBVS .............................. ±65mA
Voltage on HBVS ..................... -0.3V to self-limit
Source current of FSET ..............................2mA
Voltage rating LG .......................... -0.3V to VCC
Voltage on CS .................................... -3V to 6V
Other analog inputs and outputs ...... -0.3V to 6V
Continuous power dissipation (TA = +25°C) (2)
PIC ............................................................ 1.56W
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Storage temperature ................ -65°C to +150°C
ESD immunity: BST, HG, SW passes HBM
2.5kV, other pins can pass HBM 4kV.
THERMAL RESISTANCE (4) ΘJA
ΘJC
SOIC-16 ................................ 80 ....... 35 ... °C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
RECOMMENDED OPERATING CONDITIONS
(3)
Supply voltage (VCC) ................... 13V to 15.5V
Analog inputs and outputs ............... -0.3V to 6V
Operating junction temp (TJ) ... -40°C to + 125°C
HR1001C Rev.1.0
2/6/2017
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4
HR1001C – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS
VCC = 13V, CHG = CLG = 1nF, CT = 470pF, RFSET = 12kΩ, TJ = -40°C ~ 125°C, min and max values
guaranteed by characterization, typical value tested under 25°C, unless otherwise specified.
Parameter
Symbol Condition
Min
Typ
Max
Units
15.5
11.7
8.9
V
V
V
V
IC Supply Voltage (VCC)
VCC operating range
VCC high threshold, IC switch on
VCC low threshold, IC switch off
Hysteresis
IC Supply Current (VCC)
VCCH
VCCL
VCC-hys
Start-up current
Istart-up
Iq
Quiescent current
Iq-f
Operating current
ICC-nor
8.9
10.3
7.5
Before the device turns on,
VCC = VCCH - 0.2V
250
320
μA
Device on, VBurst < 1.23V,
RFSET = 12kΩ, FMIN = 60kHz
1.2
1.5
mA
1.42
1.8
mA
3
5
mA
350
420
μA
VBST = 600V, TJ = 25°C
VSW = 582V, TJ = 25°C
14
14
µA
µA
VCS = 0 to VCS-OCP
2
µA
Device on, VBurst < 1.23V,
RFSET = 3.57kΩ,
FBURST = 200kHz
Device on, VBurst = VFSET
VCC < 8.2V or VLATCH > 1.85V
or VCS > 1.5V or VTIMER > 3.5V
Residual consumption
IFault
or VBO < 1.81V or VBO > 5.5V
or OTP
High-Side Floating Gate Driver Supply (BST and SW)
BST leakage current
SW leakage current
Current Sensing (CS)
Input bias current
ILK-BST
ILK-SW
ICS
11
8.2
2.8
240
Frequency shift threshold
VCS-OCR
0.71
0.78
0.85
V
OCP threshold
VCS-OCP
1.41
1.5
1.59
V
VCSPR
50
85
131
mV
VCSNR
-131
-85
-50
mV
2.30
2.40
V
Current polarity comparator
reference when HG turns off
Current polarity comparator
reference when LG turns off
Line Voltage Sensing (BO)
Start-up threshold voltage
VBO-On
Turn-off threshold voltage
VBO-Off
1.72
1.81
Clamp level
Latch Function (LATCH)
VBO-Clamp
5.1
5.5
Input bias current (VLATCH = 0 to Vth)
ILATCH
LATCH threshold
VLATCH
HR1001C Rev.1.0
2/6/2017
1.72
1.85
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V
5.9
V
1
µA
1.95
V
5
HR1001C – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 13V, CHG = CLG = 1nF, CT = 470pF, RFSET = 12kΩ, TJ = -40°C ~ 125°C, min and max values
guaranteed by characterization, typical value tested under 25°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units
48
47
50
50
52
53
600
%
%
kHz
V
V
2.05
290
V
ns
µs
ns
µs
Oscillator
Output duty cycle
D
Oscillation frequency
CT peak value
CT valley value
fosc
VCFp
VCFv
Voltage reference at FSET
VREF
tDMIN
tDMAX
tD-float
tCMP
Dead time
Timer for CMP
Half-Bridge Voltage Sense (HBVS)
TJ = 25°C
TJ = -40 ~ 125°C
CT ≤ 150pF, RFSET ≤ 2kΩ
3.8
0.9
CHBVS = 5pF typically
1.87
180
HBVS floating
250
VHBVS-
Voltage clamp
dvmin/dt
Td
Discharge resistance
Threshold for OCP latch
Standby Function (BURST)
RSS
VSS-OCP
Disable threshold
Hysteresis
VBurst
VBurst-hys
450
7.6
Clamp
Minimum voltage change rate that
can be detected
Turn-on delay
Soft-Start Function (SS)
2
235
1
350
52
CHBVS = 5pF, typically
180
Slope finish to turn-on delay
VCS > VCS-OCR
VCS > VCS-OCP
V
100
V/µs
ns
130
1.73
1.82
Ω
V
1.17
1.23
30
1.28
100
V
mV
80
130
180
µA
1.64
Delayed Shutdown (TIMER)
Charge current
ITIMER
VTIMER = 1V, VCS = 0.85V,
TJ = 25°C
Threshold for forced operation at
maximum frequency
VTIMER-fmax
1.80
2
2.10
V
Shutdown threshold
VTIMER-SD
3.2
3.5
3.7
V
Restart threshold
VTIMER-R
0.21
0.28
0.35
V
Low-Side Gate Driver (LG, Referenced to GND)
Peak source current (5)
ILG-source-pk
0.75
A
Peak sink current (5)
ILG-sink-pk
0.87
A
Sourcing resistor
Sinking resistor
Fall time
Rise time
RLG-source LG_R @ Isrc = 0.01A
RLG-sink LG_R @ Isnk = 0.01A
tLG-f
tLG-r
4
2
30
30
Ω
Ω
ns
ns
UVLO saturation
HR1001C Rev.1.0
2/6/2017
VCC = 0 to VCCH, Isink = 2mA
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1
V
6
HR1001C – ENHANCED LLC CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VCC = 13V, CHG = CLG = 1nF, CT = 470pF, RFSET = 12kΩ, TJ = -40°C ~ 125°C, min and max values
guaranteed by characterization, typical value tested under 25°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units
High-Side Gate Driver (HG, Referenced to SW)
Peak source current (5)
Peak sink current (5)
Sourcing resistor
Sinking resistor
Fall time
Rise time
Thermal Shutdown
Thermal shutdown threshold (5)
Thermal shutdown recovery
threshold (5)
IHG-source-pk
IHG-sink-pk
RHG-source
RHG-sink
tHG-f
tHG-r
HG_R @ Isrc = 0.01A
HG_R @ Isnk = 0.01A
0.74
0.87
4
2
30
A
A
Ω
Ω
ns
30
ns
150
°C
120
°C
NOTE:
5) Guaranteed by design.
HR1001C Rev.1.0
2/6/2017
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7
HR1001C – ENHANCED LLC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are generated using the evaluation board built with the design example
on page 22. VAC = 120V, VOUT = 24V, IOUT = 4.16A, TA = 25°C, unless otherwise noted.
HR1001C Rev.1.0
2/6/2017
www.MonolithicPower.com
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8
HR1001C – ENHANCED LLC CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are generated using the evaluation board built with the design example
on page 22. VAC = 120V, VOUT = 24V, IOUT = 4.16A, TA = 25°C, unless otherwise noted.
HR1001C Rev.1.0
2/6/2017
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9
HR1001C – ENHANCED LLC CONTROLLER
PIN FUNCTIONS
Pin #
Name
1
SS
2
TIMER
3
CT
4
FSET
5
BURST
Description
Soft start. Connect an external capacitor from SS to GND and a resistor to FSET to set the
maximum oscillator frequency and the time constant for the frequency shift during start-up.
An internal switch discharges the capacitor when the chip turns off (VCC < UVLO, BO <
VBO-Off or > VBO-Clamp, LATCH > VLATCH, CS > VCS-OCP, TIMER > VTIMER-fmax, thermal
shutdown) to guarantee a soft start.
Period between over-current and shutdown. Connect a capacitor and a resistor from
TIMER to GND to set both the maximum duration from an over-current condition before the
IC stops switching and the delay before the IC resumes switching. Whenever the voltage
on CS exceeds VCS-OCR, an internal current source (ITIMER) charges the capacitor. An
external resistor discharges this capacitor slowly. If the voltage on TIMER reaches VTIMERfmax, the soft-start capacitor discharges completely, raising its switching frequency to its
maximum value. ITIMER remains on. When the voltage exceeds VTIMER-SD, the IC stops
switching, the internal current source turns off, and the voltage decays. The IC enters soft
start when the voltage drops below VTIMER-R. This converter works intermittently with very
low average input power under short-circuit conditions.
Time set. An internal current source programmed by an external network connected to
FSET charges and discharges a capacitor connected to GND. This determines the
converter’s switching frequency.
Switching frequency set. FEST provides a precise 2V reference. A resistor connected
from FSET to GND defines a current that sets the minimum oscillator frequency. Connect
the phototransistor of an optocoupler to FSET through a resistor to close the feedback loop
that modulates the oscillator frequency, which regulates the converter’s output voltage. The
value of this resistor sets the maximum operating frequency. An R-C series connected from
FSET to GND sets the frequency shift at start-up to prevent excessive inrush energy.
Burst mode operation threshold. BURST senses the voltage related to the feedback
control, which is compared to an internal reference (VBurst). When the voltage on BURST is
lower than this reference, the IC enters an idle state and reduces its quiescent current.
When the feedback drives BURST above VBurst + 30mV (VBurst-hys), the chip resumes
switching. There is no soft start. This function enables burst mode operation when the load
falls below a programmed level determined by connecting an appropriate resistor to the
optocoupler to FSET (see the Block Diagram on page 12). Connect BURST to FSET if
burst mode is not used.
Current sense of the half-bridge. CS uses a sense resistor or a capacitive divider to
sense the primary current. CS has the following functions:
 Over-current regulation: If the voltage exceeds VCS-OCR, the soft-start capacitor on SS
discharges internally. The frequency increases, limiting the power throughout. During an
output short circuit, this normally results in a nearly constant peak primary current.
TIMER limits the duration of this condition.
6
CS
 Over-current protection (OCP): If the current continues to build despite the frequency
increase, when VCS > VCS-OCP, SS is discharged continuously, and OCP is not triggered
immediately until VSS < VSS-OCP. If the condition for VCS > VCS-OCP remains once VSS
drops below VSS-OCP, OCP is triggered in latch mode. This requires cycling the IC supply
voltage to restart. The latch is removed once the VCC voltage drops below the UVLO
threshold. This prevents OCP from mistriggering in surge tests or other transient tests.
 Capacitive mode protection (CMP): Once LG turns off, CS is compared to the VCSNR
CMP threshold. If VCS > VCSNR, the HG gate is blocked from turning on until the slope is
detected or the CMP timer is complete. Once HG turns off, CS is compared to the VCSPR
CMP threshold. If VCS < VCSPR, the low-side gate is blocked from turning on until the
slope is detected or the CMP timer is completed. If a capacitive mode status is
detected, SS is not discharged immediately; there is a 1µs delay. After the blanking
delay, SS is discharged if the fault condition in capacitive mode remains. This prevents
the influence of CS noise. Connect CS to GND if the CMP function is not used.
HR1001C Rev.1.0
2/6/2017
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10
HR1001C – ENHANCED LLC CONTROLLER
PIN FUNCTIONS (continued)
Pin #
Name
7
BO
8
LATCH
9
HBVS
10
GND
11
LG
12
VCC
13
NC
14
SW
15
HG
16
BST
HR1001C Rev.1.0
2/6/2017
Description
Input voltage sense and brown-in/brown-out protection. If the voltage on BO is over
VBO-On, the IC enables the gate driver. If the voltage on BO is below VBO-Off, the IC is
disabled.
IC latch off. When the voltage on LATCH exceeds VLATCH, the IC shuts down and lowers
its bias current almost to its pre-start-up level. LATCH is reset when the voltage on VCC is
discharged below its UVLO threshold. Connect LATCH to GND if the function is not used.
Half-bridge dV/dt sense. To detect the dV/dt of the half-bridge, a high-voltage capacitor is
connected between SW and HBVS. The dV/dt current through HVBS is used to adjust the
dead-time adaptively between the high-side gate and the low-side gate.
Ground. GND is the current return for both the low-side gate driver and the IC bias.
Connect all external ground connections with a trace to GND—one for signals and a
second for pulsed current return.
Low-side gate driver output. The driver is capable of a 0.8A source/sink peak current to
drive the lower MOSFET of the half-bridge. LG is pulled to GND during UVLO.
Supply voltage. VCC supplies both the IC bias and the low-side gate driver. Use a small
bypass capacitor (e.g.: 0.1µF) to achieve a clean bias voltage for the IC signal.
High-voltage spacer. No internal connection. NC isolates the high-voltage pin (SW) and
eases compliance with safety regulations (creepage-distance) on the PCB.
High-side switch source. SW is the current return for the high-side gate drive current. SW
requires careful layout to avoid large spikes below ground.
High-side floating gate driver output. HG is capable of a 0.8A source/sink peak current
to drive the upper MOSFET of the half-bridge. Connect an internal resistor to SW to ensure
that HG does not float during UVLO.
Bias for floating voltage supply of high-side gate driver. Connect a bootstrap capacitor
between BST and SW. This capacitor is charged by an internal bootstrap diode driven inphase with the low-side gate driver.
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11
HR1001C – ENHANCED LLC CONTROLLER
block diagram
VCC
VBUS
VCC
BST
Internal
circuit
HSG
DRIVER
LEVEL
SHIFTER
HG
CBOOT
Lr
SW
DRIVING
LOGIC
BURST
VDD
STANDBY
OTP
1.26V/
1.23V
LG
LSG
DRIVER
Dtmin/
Dtada/
DTmax
2V
RESONANT
TANK CIRCUIT
Cr
GND
ADTA
Ifmin
HBVS
FSET
Right
Slope detected
/52µs Timer out
1.73V
SS
OCP
Control
Logic
OCR
CMP
wrong
Current
Polarity
CS
1.5V
0.78V
Disable
LATCH
Q
S
R
Boost _OK
VCC
1.85V
UVLO
2.3V/1.81V
CT
VCLK
TIMER
BO
Figure 1: Functional Block Diagram
HR1001C Rev.1.0
2/6/2017
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12
HR1001C – ENHANCED LLC CONTROLLER
APPLICATION INFORMATION
Oscillator
Figure 2 shows the oscillator block diagram. A
modulated current charges and discharges the
CT capacitor repeatedly between its peak valley
thresholds, which determines the oscillator
frequency.
VREF
Is-1
Fset
Rss
Iset
Iset
Rfmax
Rfmin
Css
VCFv
GND
CT
VCFp
+
-
R
+
-
S
CT
Is-2
Q
2Iset
HR1001C
Figure 2: Oscillator Block Diagram
FSET sets the CT charging current, Iset (IS-1).
When CT passes its peak threshold (VCFp), the
flip-flop is set, and a discharge current source
twice the charge current is enabled. The
difference between these two currents forces
the charge and discharge of CT to be equal.
When the voltage on the CT capacitor falls
below its valley threshold (VCFv), the flip-flop is
reset and turns off IS-2. This starts a new
switching cycle. Figure 3 shows the detailed
waveform of the oscillator.
HG
SW
TD
t
Under normal operation, the phototransistor
adjusts the current flow through Rfmax to
modulate the frequency for output voltage
regulation. When the phototransistor is
saturated, the current through Rfmax is at its
maximum, which sets the frequency at its
maximum.
An R-C in series connected between FSET and
GND shifts the frequency at start-up. Please
see the Soft-Start Operation section on page 14
for details.
Set the minimum and maximum frequencies
with Equation (1) and Equation (2):
1
3  CT  Rfmin
(1)
1
3  CT  (Rfmin || Rfmax )
(2)
fmin 
fmax 
Rfmin 
1
3  CT  fmin
(3)
t
Rfmax 
t
t
Figure 3: CT Waveform and Gate Signal
HR1001C Rev.1.0
2/6/2017
Rfmin from FSET to GND contributes to the
maximum resistance of the external R-C
network when the phototransistor does not
conduct. This sets the FSET minimum source
current, which defines the minimum switching
frequency.
Typically, the CT capacitance is between 0.1nF
and 1nF. Calculate the values of Rfmin and Rfmax
with Equation (3) and Equation (4):
CT
LG
An R-C network connected to FSET externally
determines the normal switching frequency and
the soft-start switching frequency.
Rfmin
fmax
1
fmin
(4)
It is recommended to use a CT capacitor
(≤330pF) for best overall temperature
performance.
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13
HR1001C – ENHANCED LLC CONTROLLER
Soft-Start Operation (SS)
For the resonant half-bridge converter, the
power delivered is inversely proportional to its
switching frequency. To ensure that the
converter starts or restarts with safe currents,
the soft start forces a high initial switching
frequency until the value is controlled by the
closed loop.
Soft start is achieved by using an external R-C
series circuit (see Figure 4).
Fset
4
RSS
Rfmin
SS
HR1001C
1
CSS
Figure 4: Soft-Start Block
When start-up begins, the SS voltage is 0V, so
the soft-start resistor (RSS) is in parallel to Rfmin.
Rfmin and RSS determine the initial frequency,
which can be calculated with Equation (5):
fstart 
1
3  CT  (Rfmin ||RSS )
(5)
During start-up, CSS charges until its voltage
reaches the reference (VREF), and the current
through RSS decays to zero. This period takes
about 5x(RSSxCSS). During this period, the
switching frequency change follows an
exponential curve. Initially, the CSS charge
reduces the frequency relatively quickly, but the
rate decreases gradually.
Select an initial frequency (fstart) at least four
times fmin. When selecting CSS, there is a tradeoff between the desired soft-start operation and
the over-current protection (OCP) speed. See
the Over-Current Protection section on page 17
for details.
Adaptive Dead-Time Adjustment (ADTA)
When operating in inductive mode, the soft
switching of the power MOSFETs results in
high efficiency of the resonant converter. A
fixed dead time may result in hard switching in
light load, especially if the magnetizing
inductance (Lm) is too large. A dead time that is
too long may lead to ZVS loss. The current may
change polarity during the dead time, resulting
in capacitive mode switching. The adaptive
dead-time control adjusts the dead time
automatically by detecting the dV/dt of the halfbridge switching node (SW).
The HR1001C incorporates an intelligent
adaptive dead-time adjustment (ADTA) logic
circuit, which detects SW’s dV/dt and inserts a
proper dead time automatically. For the external
circuit, connect a capacitor (CHBVS, typically 5pF)
between SW and HBVS to sense dV/dt. Figure
5 shows the simplified block diagram of ADTA.
Figure 6 shows the operation waveform of
ADTA.
Vbus
BST
HSG Driver
HG
CBOOT
HG
Lr
SW
VDD
LG
LG
LSG Driver
After the soft-start period, the switching
frequency is dominated by the feedback loop to
regulate the output voltage. With the soft start,
the current of the resonant tank increases
during the start-up gradually.
Select the soft-start R-C network with Equation
(6) and Equation (7):
RSS 
CSS 
HR1001C Rev.1.0
2/6/2017
Rfmin
fstart
1
fmin
3  10-3
RSS
CHBVS
GND
Cr
HG
LG
ADTA
Logic
CLK
id
HBVS
D1
CLKN
Figure 5: Block Diagram of ADTA
(6)
(7)
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14
HR1001C – ENHANCED LLC CONTROLLER
Dead time adaptively
adjusted
Then design CHBVS with Equation (10):
LG
HG
HG
CHBVS 
im
ir
700uA Coss
Im
2
(10)
Where Coss is the output capacitance when
drain-source voltage on the MOSFET is almost
zero volts (refer to the Coss characteristics curve
in the MOSFET’s datasheet).
VSW
VHBVS
In a typical design, Lm = 870µH, VIN = 450Vdc,
and fmax = 140kHz. CHBVS is calculated at 4.5pF,
indicating that 5pF is suitable for most
MOSFETs.
TDmin
Current of C HBVS
id
CLK
Figure 6: Operation Waveform of ADTA
When HG switches off, SW voltage swings from
high to low due to the resonant tank current (ir).
Accordingly, this negative dV/dt pulls current
from HBVS via CHBVS. If the dV/dt current is
higher than the internal comparison current, the
voltage on HBVS (VHBVS) is pulled down and
clamped at zero. When SW stops slewing and
differential current stops, VHBVS starts to ramp
up. LG turns on after a delay (minimum dead
time). Dead time is the duration between the
moment HG turns off and the moment LG turns
on.
When LG switches off, the SW voltage swings
from low to high, and a positive dV/dt current is
detected via CHBVS. The dead time between LG
turning off and HG turning on is maintained
automatically by sensing the dV/dt current.
To avoid damaging HBVS, CHBVS should be
selected carefully. Keep the dV/dt current below
65mA using Equation (8):
id  CHBVS
dv
 65mA
dt
Figure 7 illustrates a possible dead time by
ADTA logic. Note that there are three kinds of
dead time: minimum dead time (tDmin), maximum
dead time (tDmax), and adjusted dead time (tDadj),
which is between tDmin and tDmax. ADTA logic
sets tDmin = 235ns. When the SW transition time
is smaller than tDmin, the logic does not let the
gate turn on, which prevents a shoot-through
between the low-side and high-side MOSFETs.
A maximum dead time (tDmax = 1µs) forces the
gate to turn on, preventing duty cycle losses or
soft switching.
ADTA adjusts the dead time automatically and
ensures zero-voltage switching (ZVS), which
enables more flexibility in the MOSFET and Lm
selection. ADTA also prevents hard switching if
the design does not carefully account for light
load or no load. At light load, the switching
frequency goes high, and the magnetizing
current goes low, risking hard switching that
can lead to a thermal or reliability issue.
DTmin
DTmax
t
VCLK
t
(8)
If CHBVS is designed too low to sense the dV/dt,
the minimum voltage change rate (dVmin/dt)
must be accounted for to design a proper CHBVS
value.
Vgate
LG
HG
First, calculate the peak magnetizing current (Im)
with Equation (9):
Vin
(9)
Im 
8  Lm  fmax
LG
HG
t
VSW
t
VDT
t
t1 t2 t3
HR1001C Rev.1.0
2/6/2017
DTmin
Vosc
t4 t5 t6
t7
t8
Figure 7: Dead Time in ADTA
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15
HR1001C – ENHANCED LLC CONTROLLER
If HBVS is not connected, the internal circuit
cannot detect the differential current from HBVS,
so the dead time remains fixed at 350ns.
Figure 8 shows the dead-time waveform when
HG turns off, and Figure 9 shows the dead-time
waveforms when LG turns off. ADTA logic
inserts the dead time automatically according to
the transition shape of SW.
If VHBVS is pulled down too low by the negative
current of CHBVS, the dead time from HG turning
off to LG turning on may be too long. To clamp
HBVS at zero and ensure an optimum dead
time, connect a Schottky diode (D1) (such as
BAT54) on HBVS to GND.
VSW
VLG
VHG
VHBVS
Capacitive Mode Protection (CMP)
When the resonant HB converter output is in an
overload or short circuit, it may cause the
converter to run into a capacitive region. In
capacitive mode, the voltage applied to the
resonant tank causes the current of the
resonant tank to lag. Under this condition, the
body diode of one of the MOSFETs is
conducting. The other MOSFET should not be
turned on to prevent device failure. The
functional block diagram of capacitive mode
protection (CMP) is shown in Figure 10.
Figure 11 shows the operating current principle
of CMP. CSPOS and CSNEG stand for the
current polarity, which is generated by
comparing the voltage on CS with the internal
VCSNR and VCSPR voltage reference.
At t0, LG turns off. CSNEG is high, which
means the current is in the correct direction and
is operating in inductive mode.
At t1, HG turns off. CSPOS is high, which
means the current is in the correct direction and
is operating in inductive mode.
Figure 8: Dead Time at High-to-Low Transition
VSW
VLG
VHBVS
VHG
At t2, LG turns off for the second time. CSNEG
is low, indicating the current is in the wrong
direction (the low-side MOSFET body diode is
conducting), and the converter is operating in
capacitive mode.
SW does not swing high until the current
returns to the correct polarity. DT stays high
and VOSC is stopped, preventing the other
MOSFET from turning on. This prevents
capacitive switching.
At t3, the current returns to the correct polarity,
and the other MOSFET turns on after the dV/dt
current is detected.
Between t2 to t5, the correct current polarity
cannot be detected, or there is so little current
that SW cannot be pulled up or down.
Figure 9: Dead Time at Low-to-High Transition
HR1001C Rev.1.0
2/6/2017
Eventually, the timer (tCMP) for CMP expires,
and the other MOSFET is forced to switch on
(see Figure 11).
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16
HR1001C – ENHANCED LLC CONTROLLER
Vbus
BST
HSG
DRIVER
2V
CBOOT
HG
HG
FSET
Lr
SW
Iset
VDD
Discharge:
OCR
SS
CMP
LG
LG
Restart
LSG
DRIVER
SET
Q
D
Q
V
3.5
Timer
V
G
VS
W
D
85mV
CLK
CMP
2.0
Protection
G
CS
SET
Q
TIMER
VL
CLR
detected
130uA
VH
-85mV
CLK
Capacitive
Cr
GND
Q
CLR
ir
Latch off
Control
Logic
0.3
Q
S
QN
R
1.5
UVLO
V
OCP
V
Protection
OCR
0.8
Timer
V
HR1001C
Figure 12: Capacitive Mode Protection Waveform
Figure 10: Block Diagram of CMP and OCP
DTmin
DTmin
Timer out
Vosc
DTmax
t
VCLK
Vgate
t
LG
HG
LG
VSW
HG
HG
t
Slope Missing
t
Vcs
t
CSNEG
t
CSPOS
Figure 12 shows CMP behavior when the
output is shorted. The current polarity goes in
the wrong direction when LG switches off. The
CMP logic detects this capacitive mode
immediately and prevents HG from turning on.
This prevents destructive capacitive switching.
Once the current (ir) returns to the correct
polarity, SW ramps up, the dV/dt current is
detected, and HG turns on at the ZVS condition.
Over-Current Protection (OCP)
The HR1001C provides two levels of overcurrent protection (see Figure 13).
t
tOC
Vss
tOP
tSTOP
tSS
VCC
t
VCCH
VCCL
DT
SS
t
t0
t1
t2
t3 t4
t5
t
VSS
VSS-OCP
t6
t
Figure 11: Operating Principle of CMP
ICr
t
VCS-OCP
When capacitive mode operation is detected,
the VSS control signal goes high, turning on an
internal transistor to discharge CSS after a 1µs
blanking delay. This causes the frequency to
increase to a very high level quickly to limit the
output power. The VSS control is reset, and soft
start is activated when the first gate driver is
switched off after CMP. The switching
frequency decreases smoothly until the control
loop takes over.
HR1001C Rev.1.0
2/6/2017
VCS-OCR
VCS
TIMER
t
VTIMER-SD
VTIMER-fmax
VTIMER-R
t
Vout
Normal
operation
Over load
Shutdown
Soft-start
OCP(Latch-off mode)
Pmin
t
Soft-start
Figure 13: OCP Timing Sequence
The first level of protection occurs when the
voltage on CS (VCS) exceeds VCS-OCR. Once this
occurs, two actions take place. First, the
internal transistor connected between SS and
GND turns on for at least 10µs, which
discharges CSS. This creates a sharp increase
in the oscillator frequency, reducing the energy
transferred to the output. Second, an internal
current source (ITIMER) turns on to charge CTIMER,
ramping
the
TIMER
voltage.
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17
HR1001C – ENHANCED LLC CONTROLLER
If VCS drops below VCS-OCR before the voltage on
TIMER (VTIMER) reaches VTIMER-fmax, both the
discharge of CSS and the charge of CTIMER are
stopped. The converter resumes normal
operation.
VSS
tOC is the time for VTIMER to rise from 0V to
VTIMER-fmax. tOC is also a delay time for overcurrent regulation. There is no simple
relationship between tOC and CTIMER. Select
CTIMER based on experimental results. Based on
experiments, CTIMER may increase the operating
time by 100ms.
If VCS is still larger than VCS-OCR after VTIMER rises
to VTIMER-fmax, CSS is discharged completely.
Simultaneously, ITIMER continues to charge
CTIMER until VTIMER reaches VTIMER-SD and then
turns off all gate drivers.
Calculate the time VTIMER takes to rise from
VTIMER-fmax to VTIMER-SD with Equation (11):
tOP  104  CTIMER
(11)
The IC maintains the condition until VTIMER
decreases to VTIMER-R, and then the IC restarts.
Calculate this time period with Equation (12):
t OFF =RTIMER  CTIMER  ln
3.5
 2.5RTIMER  CTIMER (12)
0.3
The second level of over-current protection is
triggered when VCS rises to VCS-OCP. Typically,
this condition occurs when VCS continues to rise
during a short circuit. Once VCS reaches VCS-OCP,
the HR1001C does not stop switching
immediately, and CSS is discharged by an
internal transistor continuously. If VCS remains
above VCS-OCP until VSS drops below VSS-OCP, the
IC shuts down in latch-off mode (see Figure 14).
While VSS is dropping, the converter resumes
normal operation if VCS decreases below VCSOCR. This is a particular characteristic of the
HR1001C
and
prevents
instantaneous
interference on CS to trigger any protection
when the converter suffers a surge or other
transient waves. Once the latch is triggered, it is
not reset until VCC drops below UVLO.
VCS
VLG
Figure 14: SCP Waveform
OCP limits the energy transferred from the
primary side to the secondary side during an
overload or short-circuit condition. Excessive
power consumption due to high continuous
currents can damage the secondary-side
windings and rectifiers. TIMER provides
additional protection to reduce the average
power consumption. When OCP is triggered
(except in a VCS > VCS-OCP condition), the
converter enters a hiccup-like protection mode
that operates intermittently.
Current Sensing
There are two current sensing methods:
lossless current sensing and current sensing
with a sense resistor.
Generally, a lossless current sensing solution is
used in high-power applications (see Figure 15).
Lr
CS
R1
C1
Rs
Cs
Cr
Figure 15: Current Sensing with a Lossless
Network
Design a lossless current sensing network with
Equation (13) and Equation (14):
Cs 
HR1001C Rev.1.0
2/6/2017
Cr
100
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(13)
18
HR1001C – ENHANCED LLC CONTROLLER
Choose Rs with Equation (14):
Rs<
C
0.8
 (1  r )
ICrpk
CS
(14)
Where ICrpk is the peak current of the resonant
tank at a low input voltage and full load.
Calculate ICrpk with Equation (15):
ICrpk  (
NVO 2 IO 2
) (
)
4Lm fs
2N
(15)
Where N is the turns ratio of the transformer, lo
is the output current, Vo is the output voltage, fS
is the switching frequency, and Lm is the
magnetizing inductance.
For capacitive mode detection in no load or
tiny-load conditions, Rs should fulfill the
condition in Equation (16):
C
85mV
RS 
(1  r )
Im
CS
(16)
In some conditions, especially where a large
Lm is used, it can be difficult to fulfill both
Equation (14) and Equation (16). The IC
operates without a CMP function at light load if
it does not have the restriction of Equation (16).
The R1 and C1 network is used to attenuate
switching noise on CS. The time constant
should be in the range of 100ns.
An alternate solution uses a sense resistor in
series with the resonant tank (see Figure 16).
This method is simple but causes unnecessary
power loss on the sense resistor.
Input Voltage Sensing (BI/BO)
The HR1001C stops switching when the input
voltage drops below a specified value and
restarts when the input voltage returns to
normal. This function guarantees that the
resonant half-bridge converter always operates
within the specified input voltage range. The IC
senses the voltage on BO (VBO) through the tap
of a resistor divider connected to the rectified
AC voltage or the PFC output.
Figure 17 shows the line-sensing internal block
diagram.
Shutdown
VBO-Clamp
RH
BO 7
RL
VinOK
VBO-On/
VBO-Off
HR1001C
Figure 17: Input Voltage Sensing Block
If VBO is higher than VBO-On, the IC provides the
gate driver outputs. The IC does not stop the
gate driver until VBO drops below VBO-Off.
For a minimum operation input voltage of the
half-bridge (VIN-min), select a value for RH that is
large enough to reduce power consumption at
no load. Then calculate RL with Equation (18):
RL  RH 
1.81
VIN-min  1.81
(18)
For additional protection, the IC shuts down
when VBO exceeds the internal clamp voltage
(VBO-Clamp). When VBO is between VBO-On and VBOClamp, the IC operates normally.
CS
R1
Cr
C1
Rs
Figure 16: Current Sensing with a Sense
Resistor
Design the sense resistor using Equation (17):
RS 
HR1001C Rev.1.0
2/6/2017
0.8
ICrpk
Burst Mode Operation
At light load or in the absence of a load, the
maximum frequency limits the resonant halfbridge switching frequency. To control the
output voltage and limit power consumption, the
HR1001C enables compatible converters to
operate in burst mode. This reduce the average
switching frequency greatly, thus reducing the
average residual magnetizing current and
associated losses.
(17)
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19
HR1001C – ENHANCED LLC CONTROLLER
Operating in burst mode requires setting
BURST. If the voltage on BURST (VBURST)
drops below the internal threshold (VBurst), the
HR1001C shuts down the HG and LG gate
drive outputs, leaving only the 2V reference
voltage on FSET and SS to retain the previous
state and minimize the power consumption.
When VBURST exceeds VBurst over 30mV (VBursthys), the HR1001C resumes normal operation.
Based on the burst mode operating principle,
BURST must be connected to the feedback
loop. Figure 18 shows a typical circuit
connecting BURST to the feedback signal for
narrow input voltage range applications.
Fset
4
Rfmin
Rfmax
Burst
HR1001C
5
Figure 18: Burst Mode Operation Set-Up
In addition to setting the oscillator maximum
frequency at start-up, Rfmax and determines the
maximum burst mode frequency. After
confirming fmax, calculate Rfmax with Equation
(19):
Rfmax 
3 Rfmin

8 fmax
1
fmin
(19)
Here, fmax corresponds to a load point (PBurst),
where the peak current flow through the
transformer is too low to cause audible noise.
So far, this section has been based on a narrow
input voltage range. As a property of the
resonant circuit, the input voltage determines
the switching frequency. This means PBurst has
a large variance over the wide input voltage
range. To stabilize PBurst over the input range,
use the circuit in Figure 19 to insert the input
voltage signal into the feedback loop.
HR1001C Rev.1.0
2/6/2017
Vin
FSET
Rss
Rfmin
Css
Rfmax
BURST
HR1001C
BO
RH
RL
RB1
Cburst
RB2
Figure 19: Burst Mode Operation Set-Up for a
Wide Input Voltage Range
RB1 and RB2 in Figure 19 correct against the
wide input voltage range. Select both resistors
based on experimental results. The total
resistance of RB1 and RB2 should be much
larger than RH to minimize the effect on VBO.
During burst mode operation, when the load is
lower than PBurst, the switching frequency is
clamped at the maximum frequency. The output
voltage must rise over the setting value, which
increases the current flowing through the
optocoupler. Therefore, the voltage on Rfmax
rises due to the increased phototransistor
current. Then VBURST drops below VBurst,
triggering the gate signal off state. Until the
output voltage falls below the setting value, the
current flow through the optocoupler decreases,
causing VBURST to rise. When VBURST exceeds
VBurst over 30mV, the IC restarts to generate the
gate signal. The IC operates in this mode under
no load or light load to decrease average power
consumption.
Latch Operation
The HR1001C provides a simple latch-off
function through LATCH. Applying an external
voltage over VLATCH causes the IC to enter a
latched shutdown. After the IC is latched, its
consumption drops, as shown by the residual
current in the Electrical Characteristics table on
page 5. Resetting the IC requires dropping the
VCC voltage below the UVLO threshold (see
the latch internal block diagram in Figure 20).
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20
HR1001C – ENHANCED LLC CONTROLLER
Low-Side Gate Driver
LG provides the gate driver signal for the lowside MOSFET. The maximum absolute rating
table shows the maximum voltage on LG is 16V.
Under some conditions, a large voltage spike
occurs on LG due to oscillations from the long
gate driver wire, the MOSFET parasitic
capacitance, and the small gate driver resistor.
This voltage spike is dangerous to LG, so a 15V
Zener diode close to LG and GND is
recommended (see Figure 22).
HR1001C
LATCH 8
+
S
VLATCH
Q
Disable
UVLO
R
Figure 20: Latch Function Block
High-Side Gate Driver
The external BST capacitor provides energy to
the high-side gate driver. An integrated
bootstrap diode charges this capacitor through
VCC. This diode simplifies the external driving
circuit for the high-side switch, allowing the BST
capacitor to charge when the low-side MOSFET
is on (see the high-side gate driver internal
block diagram in Figure 21).
To provide enough gate driver energy
(considering the BST capacitor charge time),
use a 100nF to 470nF capacitor for the BST
capacitor.
SW
Vs
Cgd
Low-Side
Driver
Cds
Rg
11 LG
Cgs
15V
HR1001C
10
GND
Figure 22: Low-Side Gate Driver
VCC
12
16 BST
High-Side
Driver
Level
Shifter
15
CBST
HG
14 SW
HR1001C
Figure 21: High-Side Gate Driver
HR1001C Rev.1.0
2/6/2017
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21
HR1001C – ENHANCED LLC CONTROLLER
Design Example
A 100W LED driver is designed with the
specifications below (see Table 1).
Table 1: Design Example
Input AC Voltage
Output Voltage
Output Current
90-305VAC
24V
4.16A
Figure 23 shows the detailed application
schematic. The typical performance and circuit
waveforms are shown in the Typical
Performance Characteristics section. The
HR1001C has passed 4kV surge test for 30s
duration on the EV44010-S + HR1001 - S - 00A
evaluation board built with the design example.
PFC Stage
LLC Stage
Figure 23: Design Example for a 24V/4.16A Output
HR1001C Rev.1.0
2/6/2017
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22
HR1001C – ENHANCED LLC CONTROLLER
CONTROL FLOW CHARTS
START
VCC capacitor is charged
by external circuit
N
VCC>11V
& BO>2.3V?
Y
Soft Start
Slope
detected?
Y
N
Fixed
DT=350ns
ADTA
Normal operation, IFset
controls fs
Latched
Shutdown
CMP
Monitor CS
Vcs>85mV or
Vcs<-85mV
Monitor LATCH
N
N
LATCH>1.85V
Y
1. Latch off the
switching pulse
2. Soft-start
capacitor is fully
discharged
Polarity is
wrong?
TIMER>2V
1. Discharge softstart capacitor
(10µs), increasing
switching frequency
2. TIMER capacitor is
charged (10µs) by an
internal 130µA
current source
Y
Monitor current polarity
at the moment of gate
driver turning off
Y
Burst
Mode
Monitor Thermal
Monitor BO
Monitor VCC
Monitor Burst
CS>0.8V
N
Y
VCC<8.2V
1. Discharge SS cap
after 1µs delay.
2. VCLK is held.
3. Both HSG and LSG
are turned off
Y
Y
CMP timer
out?
Y
1. Stop
discharging
soft-start
capacitor
2. Stop
charging TIMER
capacitor
3. Continue
normal
operation
CS>1.5V
Y
N
BO>5.5V or
BO<1.81V
N
VCC<8.2V
Y
Y
Burst<1.23V
Y
1. Stop the
switching pulse
2. Soft-start
capacitor is fully
discharged
1. Stop the
switching pulse
2. Soft start
capacitor is fully
discharged
1. Stop the
switching pulse
2. Soft-start
capacitor is fully
discharged
1. Switching
frequency is
pushed to
maximum
2. Soft-start
capacitor is fully
discharged
3. TIMER
capacitor is
charged by an
internal 130µA
current source
Stop the
switching pulse
Burst>1.26V
<120ºC
Y
N
2.3V<BO<5.5V
Y
N
VCC>11V
Y
N
N
Y
Resume the
switching pulse
Y
N
SS<1.73V
Y(Latch)
N
1. Stop the
switching pulse
2. Soft start
capacitor is fully
discharged
3. Stop charging
TIMER capacitor
Y
Turn on the
other gate
driver
N
N
>150ºC
N
Y
N
CMP timer à 52µs
No slope
detected?
UVLO
CS>0.8V
Enable CMP
N
Brown-Out
Monitor TIMER
Y
N
OTP
OCP
N
TIMER>3.5V
N
Y
1. Stop the
switching pulse
2. TIMER
capacitor is
discharged by
external resistor
VCC<8.2V
Y
TIMER<0.3V
N
Y
Figure 24: Control Flow Chart
HR1001C Rev.1.0
2/6/2017
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© 2017 MPS. All Rights Reserved.
23
HR1001C – ENHANCED LLC CONTROLLER
TYPICAL APPLICATION CIRCUIT
PFC Pre-Regulator
MP44010/
MP44014
Resonant Half-Bridge
HR1001C
Figure 25: Application Circuit
HR1001C Rev.1.0
2/6/2017
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24
HR1001C – ENHANCED LLC CONTROLLER
SYSTEM TIMING
Unplug from
main input
Over temperature
VCC
VCCH
VCCL
LG/HG
Soft Start
VSS-OCP
VLATCH
LATCH
CS
VCS-OCP
VCS-OCR
TIMER
VTIMER-SD
VTIMER-fmax
VTIMER-R
BO
VBO-On
VBO-Off
Burst
VBurst
UVLO Brown- Normal
OCP
In Soft
Latch
OCP Latch
Shutdown
Start
HR1001C Rev.1.0
2/6/2017
OCP
BrownOut
OTP
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Burst
Mode
25
HR1001C – ENHANCED LLC CONTROLLER
PACKAGE INFORMATION
SOIC-16
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
HR1001C Rev.1.0
2/6/2017
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© 2017 MPS. All Rights Reserved.
26