ATMEL ATMEGA644/V 8-bit microcontroller with 16/32/64k bytes in-system programmable flash Datasheet

Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
•
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
– 16/32/64K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512B/1K/2K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 1/2/4K Bytes Internal SRAM
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
Differential mode with selectable gain at 1x, 10x or 200x
– Byte-oriented Two-wire Serial Interface
– One/Two Programmable Serial USART (ATmega644, ATmega164/324)
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
Operating Voltages
– 1.8 - 5.5V for ATmega164/324/644V
– 2.7 - 5.5V for ATmega164/324/644
Speed Grades
– ATmega164/324/644V: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V
– ATmega164/324/644: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1 MHz, 3V, 25°C for ATmega644
– Active: 240 µA @ 1.8V, 1MHz
– Power-down Mode: 0.1 µA @ 1.8V
8-bit
Microcontroller
with 16/32/64K
Bytes In-System
Programmable
Flash
ATmega164/V
ATmega324/V
ATmega644/V
Advance
Information
Summary
2593AS–AVR–06/05
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
Pin Configurations
Figure 1. Pinout ATmega164/324
PDIP
(PCINT8/XCK0/T0) PB0
(PCINT9/CLKO/T1) PB1
(PCINT10/INT2/AIN0) PB2
(PCINT11/OC0A/AIN1) PB3
(PCINT12/OC0B/SS) PB4
(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6
(PCINT15/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
(PCINT27/TXD1/INT1) PD3
(PCINT28/XCK1/OC1B) PD4
(PCINT29/OC1A) PD5
(PCINT30/OC2B/ICP) PD6
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
PC3 (TMS/PCINT19)
PC2 (TCK/PCINT18)
PC1 (SDA/PCINT17)
PC0 (SCL/PCINT16)
PD7 (OC2A/PCINT31)
PB4 (SS/OC0B/PCINT12)
PB3 (AIN1/OC0A/PCINT11)
PB2 (AIN0/INT2/PCINT10)
PB1 (T1/CLKO/PCINT9)
PB0 (XCK0/T0/PCINT8)
GND
VCC
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
TQFP/QFN/MLF
(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6
(PCINT15/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0) PD0
(PCINT25/TXD0) PD1
(PCINT/RXD1/26/INT0) PD2
(PCINT/TXD1/27/INT1)
(PCINT28/XCK1/OC1B)
(PCINT29/OC1A)
(PCINT30/OC2B/ICP)
(PCINT31/OC2A)
PD3
PD4
PD5
PD6
PD7
VCC
GND
(PCINT16/SCL) PC0
(PCINT17/SDA) PC1
(PCINT18/TCK) PC2
(PCINT19/TMS) PC3
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
2
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
Figure 2. Pinout ATmega644
PDIP
(PCINT8/XCK0/T0) PB0
(PCINT9/CLKO/T1) PB1
(PCINT10/INT2/AIN0) PB2
(PCINT11/OC0A/AIN1) PB3
(PCINT12/OC0B/SS) PB4
(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6
(PCINT15/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0) PD0
(PCINT25/TXD0) PD1
(PCINT26/INT0) PD2
(PCINT27/INT1) PD3
(PCINT28/OC1B) PD4
(PCINT29/OC1A) PD5
(PCINT30/OC2B/ICP) PD6
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
PC3 (TMS/PCINT19)
PC2 (TCK/PCINT18)
PC1 (SDA/PCINT17)
PC0 (SCL/PCINT16)
PD7 (OC2A/PCINT31)
PB4 (SS/OC0B/PCINT12)
PB3 (AIN1/OC0A/PCINT11)
PB2 (AIN0/INT2/PCINT10)
PB1 (T1/CLKO/PCINT9)
PB0 (XCK0/T0/PCINT8)
GND
VCC
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
TQFP/QFN/MLF
(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6
(PCINT15/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0) PD0
(PCINT25/TXD0) PD1
(PCINT26/INT0) PD2
(PCINT27/INT1)
(PCINT28/OC1B)
(PCINT29/OC1A)
(PCINT30/OC2B/ICP)
(PCINT31/OC2A)
PD3
PD4
PD5
PD6
PD7
VCC
GND
(PCINT16/SCL) PC0
(PCINT17/SDA) PC1
(PCINT18/TCK) PC2
(PCINT19/TMS) PC3
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
Note:
The large center pad underneath the QFN/MLF package should be soldered to the board
to ensure good mechanical stability.
3
2593AS–AVR–06/05
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
Overview
The ATmega164/324/644 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATmega164/324/644 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 3. Block Diagram
PA7..0
PB7..0
VCC
Power
Supervision
POR / BOD &
RESET
RESET
GND
PORT A (8)
PORT B (8)
Watchdog
Timer
Watchdog
Oscillator
Analog
Comparator
A/D
Converter
USART 0
XTAL1
Oscillator
Circuits /
Clock
Generation
EEPROM
Internal
Bandgap reference
SPI
XTAL2
16bit T/C 1
CPU
JTAG
TWI
NOTE:
The USART 1 is only
available for ATmega164/324
4
8bit T/C 0
FLASH
SRAM
8bit T/C 2
PORT C (8)
PORT D (8)
PC7..0
PD7..0
USART 1
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega164/324/644 provides the following features: 16/32/64K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM,
1/2/4K bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and
PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with
optional differential input stage with programmable gain, programmable Watchdog
Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test
interface, also used for accessing the On-chip Debug system and programming and six
software selectable power saving modes. The Idle mode stops the CPU while allowing
the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the
asynchronous timer continues to run, allowing the user to maintain a timer base while
the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and
all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running
while the rest of the device is sleeping. This allows very fast start-up combined with low
power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Program mable Flash on a monolithic ch ip, the Atmel
ATmega164/324/644 is a powerful microcontroller that provides a highly flexible and
cost effective solution to many embedded control applications.
The ATmega164/324/644 AVR is supported with a full suite of program and system
development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Comparison Between
ATmega164,
ATmega324 and
ATmega644
Table 1. Differences between ATmega164 and ATmega644
Device
Flash
EEPROM
RAM
ATmega164
16 Kbyte
512 Bytes
1 Kbyte
ATmega324
32 Kbyte
1 Kbyte
2 Kbyte
ATmega644
64 Kbyte
2 Kbyte
4 Kbyte
5
2593AS–AVR–06/05
Pin Descriptions
VCC
Digital supply voltage.
GND
Ground.
Port A (PA7..PA0)
Port A serves as analog inputs to the Analog-to-digital Converter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port A output buffers have symmetrical drive characteristics
with both high sink and source capability. As inputs, Port A pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port A pins are
tri-stated when a reset condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega164/324/644
as listed on page 71.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega164/324/644
as listed on page 73.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of the
ATmega164/324/644 as listed on page 76.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega164/324/644
as listed on page 78.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table
20 on page 44. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting Oscillator amplifier.
AVCC
AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. It should
be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should
be connected to VCC through a low-pass filter.
6
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
AREF
This is the analog reference pin for the Analog-to-digital Converter.
7
2593AS–AVR–06/05
Register Summary
Address
(0xFF)
8
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Name
-
-
-
-
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
(0xFE)
Reserved
-
-
-
-
-
-
-
-
(0xFD)
Reserved
-
-
-
-
-
-
-
-
(0xFC)
Reserved
-
-
-
-
-
-
-
-
(0xFB)
Reserved
-
-
-
-
-
-
-
(0xFA)
Reserved
-
-
-
-
-
-
-
(0xF9)
Reserved
-
-
-
-
-
-
-
(0xF8)
Reserved
-
-
-
-
-
-
-
-
(0xF7)
Reserved
-
-
-
-
-
-
-
-
(0xF6)
Reserved
-
-
-
-
-
-
-
-
(0xF5)
Reserved
-
-
-
-
-
-
-
(0xF4)
Reserved
-
-
-
-
-
-
-
-
(0xF3)
Reserved
-
-
-
-
-
-
-
-
(0xF2)
Reserved
-
-
-
-
-
-
-
-
(0xF1)
Reserved
-
-
-
-
-
-
-
(0xF0)
Reserved
-
-
-
-
-
-
-
(0xEF)
Reserved
-
-
-
-
-
-
-
(0xEE)
Reserved
-
-
-
-
-
-
-
-
(0xED)
Reserved
-
-
-
-
-
-
-
-
(0xEC)
Reserved
-
-
-
-
-
-
-
-
(0xEB)
Reserved
-
-
-
-
-
-
-
(0xEA)
Reserved
-
-
-
-
-
-
-
-
(0xE9)
Reserved
-
-
-
-
-
-
-
-
(0xE8)
Reserved
-
-
-
-
-
-
-
-
(0xE7)
Reserved
-
-
-
-
-
-
-
(0xE6)
Reserved
-
-
-
-
-
-
-
-
(0xE5)
Reserved
-
-
-
-
-
-
-
-
(0xE4)
Reserved
-
-
-
-
-
-
-
-
(0xE3)
Reserved
-
-
-
-
-
-
-
(0xE2)
Reserved
-
-
-
-
-
-
-
(0xE1)
Reserved
-
-
-
-
-
-
-
(0xE0)
Reserved
-
-
-
-
-
-
-
(0xDF)
Reserved
-
-
-
-
-
-
-
-
(0xDE)
Reserved
-
-
-
-
-
-
-
-
(0xDD)
Reserved
-
-
-
-
-
-
-
-
(0xDC)
Reserved
-
-
-
-
-
-
-
(0xDB)
Reserved
-
-
-
-
-
-
-
-
(0xDA)
Reserved
-
-
-
-
-
-
-
-
(0xD9)
Reserved
-
-
-
-
-
-
-
-
(0xD8)
Reserved
-
-
-
-
-
-
-
-
(0xD7)
Reserved
-
-
-
-
-
-
-
-
(0xD6)
Reserved
-
-
-
-
-
-
-
-
(0xD5)
Reserved
-
-
-
-
-
-
-
-
(0xD4)
Reserved
-
-
-
-
-
-
-
-
(0xD3)
Reserved
-
-
-
-
-
-
-
-
(0xD2)
Reserved
-
-
-
-
-
-
-
-
(0xD1)
Reserved
-
-
-
-
-
-
-
-
(0xD0)
Reserved
-
-
-
-
-
-
-
-
(0xCF)
Reserved
-
-
-
-
-
-
-
-
(0xCE)
UDR1
(0xCD)
UBRR1H
-
-
-
UBRR1L
(0xCB)
Reserved
-
-
(0xCA)
UCSR1C
UMSEL11
UMSEL10
(0xC9)
UCSR1B
RXCIE1
TXCIE1
(0xC8)
UCSR1A
RXC1
TXC1
UDRE1
-
-
-
(0xC7)
Reserved
UDR0
(0xC5)
UBRR0H
(0xC4)
UBRR0L
-
-
USART1 I/O Data Register
(0xCC)
(0xC6)
-
-
176
USART1 Baud Rate Register High Byte
180
USART1 Baud Rate Register Low Byte
180
-
-
-
-
-
UPM11
UPM10
USBS1
UCSZ11
UCSZ10
UCPOL1
UDRIE1
RXEN1
TXEN1
UCSZ12
RXB81
TXB81
178
FE1
DOR1
UPE1
U2X1
MPCM1
177
-
-
-
-
-
USART0 I/O Data Register
-
-
Page
-
-
179
176
USART0 Baud Rate Register High Byte
180
USART0 Baud Rate Register Low Byte
180
(0xC3)
Reserved
-
-
-
-
-
-
-
-
(0xC2)
UCSR0C
UMSEL01
UMSEL00
UPM01
UPM00
USBS0
UCSZ01
UCSZ00
UCPOL0
(0xC1)
UCSR0B
RXCIE0
TXCIE0
UDRIE0
RXEN0
TXEN0
UCSZ02
RXB80
TXB80
178
(0xC0)
UCSR0A
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
177
179
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
Address
(0xBF)
Name
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Page
(0xBE)
Reserved
-
-
-
-
-
-
-
(0xBD)
TWAM
TWAM6
TWAM5
TWAM4
TWAM3
TWAM2
TWAM1
TWAM0
-
(0xBC)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
-
TWIE
(0xBB)
TWDR
(0xBA)
TWAR
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
223
(0xB9)
TWSR
TWS7
TWS6
TWS5
TWS4
TWS3
-
TWPS1
TWPS0
221
2-wire Serial Interface Data Register
223
220
222
(0xB8)
TWBR
(0xB7)
Reserved
-
-
-
2-wire Serial Interface Bit Rate Register
-
-
-
-
-
220
(0xB6)
ASSR
-
EXCLK
AS2
TCN2UB
OCR2AUB
OCR2BUB
TCR2AUB
TCR2BUB
(0xB5)
Reserved
-
-
-
-
-
-
-
-
(0xB4)
OCR2B
Timer/Counter2 Output Compare Register B
(0xB3)
OCR2A
Timer/Counter2 Output Compare Register A
144
(0xB2)
TCNT2
Timer/Counter2 (8 Bit)
144
(0xB1)
TCCR2B
FOC2A
FOC2B
-
-
WGM22
CS22
CS21
CS20
143
(0xB0)
TCCR2A
COM2A1
COM2A0
COM2B1
COM2B0
-
-
WGM21
WGM20
140
(0xAF)
Reserved
-
-
-
-
-
-
-
-
145
144
(0xAE)
Reserved
-
-
-
-
-
-
-
-
(0xAD)
Reserved
-
-
-
-
-
-
-
-
(0xAC)
Reserved
-
-
-
-
-
-
-
-
(0xAB)
Reserved
-
-
-
-
-
-
-
-
(0xAA)
Reserved
-
-
-
-
-
-
-
-
(0xA9)
Reserved
-
-
-
-
-
-
-
-
(0xA8)
Reserved
-
-
-
-
-
-
-
-
(0xA7)
Reserved
-
-
-
-
-
-
-
-
(0xA6)
Reserved
-
-
-
-
-
-
-
-
(0xA5)
Reserved
-
-
-
-
-
-
-
-
(0xA4)
Reserved
-
-
-
-
-
-
-
-
(0xA3)
Reserved
-
-
-
-
-
-
-
-
(0xA2)
Reserved
-
-
-
-
-
-
-
-
(0xA1)
Reserved
-
-
-
-
-
-
-
-
(0xA0)
Reserved
-
-
-
-
-
-
-
-
(0x9F)
Reserved
-
-
-
-
-
-
-
-
(0x9E)
Reserved
-
-
-
-
-
-
-
-
(0x9D)
Reserved
-
-
-
-
-
-
-
-
(0x9C)
Reserved
-
-
-
-
-
-
-
-
(0x9B)
Reserved
-
-
-
-
-
-
-
-
(0x9A)
Reserved
-
-
-
-
-
-
-
-
(0x99)
Reserved
-
-
-
-
-
-
-
-
(0x98)
Reserved
-
-
-
-
-
-
-
-
(0x97)
Reserved
-
-
-
-
-
-
-
-
(0x96)
Reserved
-
-
-
-
-
-
-
-
(0x95)
Reserved
-
-
-
-
-
-
-
-
(0x94)
Reserved
-
-
-
-
-
-
-
-
(0x93)
Reserved
-
-
-
-
-
-
-
-
(0x92)
Reserved
-
-
-
-
-
-
-
-
(0x91)
Reserved
-
-
-
-
-
-
-
-
(0x90)
Reserved
-
-
-
-
-
-
-
-
(0x8F)
Reserved
-
-
-
-
-
-
-
-
(0x8E)
Reserved
-
-
-
-
-
-
-
-
(0x8D)
Reserved
-
-
-
-
-
-
-
-
(0x8C)
Reserved
-
-
-
-
-
-
-
-
(0x8B)
OCR1BH
Timer/Counter1 - Output Compare Register B High Byte
(0x8A)
OCR1BL
Timer/Counter1 - Output Compare Register B Low Byte
126
(0x89)
OCR1AH
Timer/Counter1 - Output Compare Register A High Byte
126
(0x88)
OCR1AL
Timer/Counter1 - Output Compare Register A Low Byte
126
(0x87)
ICR1H
Timer/Counter1 - Input Capture Register High Byte
126
(0x86)
ICR1L
Timer/Counter1 - Input Capture Register Low Byte
126
(0x85)
TCNT1H
Timer/Counter1 - Counter Register High Byte
126
126
(0x84)
TCNT1L
(0x83)
Reserved
-
-
-
Timer/Counter1 - Counter Register Low Byte
(0x82)
TCCR1C
FOC1A
FOC1B
-
-
-
-
-
-
125
(0x81)
TCCR1B
ICNC1
ICES1
-
WGM13
WGM12
CS12
CS11
CS10
124
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
-
-
WGM11
WGM10
122
(0x7F)
DIDR1
-
-
-
-
-
-
AIN1D
AIN0D
226
(0x7E)
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
244
-
-
126
-
-
-
9
2593AS–AVR–06/05
Address
(0x7D)
Name
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Page
(0x7C)
ADMUX
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
240
(0x7B)
ADCSRB
-
ACME
-
-
-
ADTS2
ADTS1
ADTS0
224
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
(0x79)
ADCH
ADC Data Register High byte
242
243
(0x78)
ADCL
(0x77)
Reserved
-
-
-
-
-
-
-
-
(0x76)
Reserved
-
-
-
-
-
-
-
-
(0x75)
Reserved
-
-
-
-
-
-
-
-
(0x74)
Reserved
-
-
-
-
-
-
-
-
(0x73)
PCMSK3
PCINT31
PCINT30
PCINT29
PCINT28
PCINT27
PCINT26
PCINT25
PCINT24
(0x72)
Reserved
-
-
-
-
-
-
-
-
(0x71)
Reserved
-
-
-
-
-
-
-
-
(0x70)
TIMSK2
-
-
-
-
-
OCIE2B
OCIE2A
TOIE2
147
(0x6F)
TIMSK1
-
-
ICIE1
-
-
OCIE1B
OCIE1A
TOIE1
127
(0x6E)
TIMSK0
-
-
-
-
-
OCIE0B
OCIE0A
TOIE0
99
(0x6D)
PCMSK2
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
62
(0x6C)
PCMSK1
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
62
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
63
(0x6A)
Reserved
-
-
-
-
-
-
-
-
(0x69)
EICRA
-
-
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
59
(0x68)
PCICR
-
-
-
-
PCIE3
PCIE2
PCIE1
PCIE0
61
(0x67)
Reserved
-
-
-
-
-
-
-
-
(0x66)
OSCCAL
(0x65)
Reserved
(0x64)
PRR0
(0x63)
Reserved
(0x62)
Reserved
(0x61)
CLKPR
(0x60)
WDTCSR
ADC Data Register Low byte
243
Oscillator Calibration Register
62
32
-
-
-
-
-
-
-
-
PRTWI
PRTIM2
PRTIM0
PRUSART1
PRTIM1
PRSPI
PRUSART0
PRADC
-
-
-
-
-
-
-
-
40
-
-
-
-
-
-
-
-
CLKPCE
-
-
-
CLKPS3
CLKPS2
CLKPS1
CLKPS0
35
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
52
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
9
0x3E (0x5E)
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
10
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
10
0x3C (0x5C)
Reserved
-
-
-
-
-
-
-
-
0x3B (0x5B)
RAMPZ
-
-
-
-
-
-
-
RAMPZ0
0x3A (0x5A)
Reserved
-
-
-
-
-
-
-
-
0x39 (0x59)
Reserved
-
-
-
-
-
-
-
-
0x38 (0x58)
Reserved
-
-
-
-
-
-
-
-
0x37 (0x57)
SPMCSR
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
0x36 (0x56)
Reserved
-
-
-
-
-
-
-
-
0x35 (0x55)
MCUCR
JTD
-
-
PUD
-
-
IVSEL
IVCE
71/255
0x34 (0x54)
MCUSR
-
-
-
JTRF
WDRF
BORF
EXTRF
PORF
47/255
37
0x33 (0x53)
SMCR
-
-
-
-
SM2
SM1
SM0
SE
0x32 (0x52)
Reserved
-
-
-
-
-
-
-
-
0x31 (0x51)
OCDR
0x30 (0x50)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
-
-
-
-
-
-
-
-
On-Chip Debug Register
13
265
251
242
0x2F (0x4F)
Reserved
0x2E (0x4E)
SPDR0
0x2D (0x4D)
SPSR0
SPIF0
WCOL0
-
-
-
-
-
SPI2X0
157
0x2C (0x4C)
SPCR0
SPIE0
SPE0
DORD0
MSTR0
CPOL0
CPHA0
SPR01
SPR00
157
0x2B (0x4B)
GPIOR2
General Purpose I/O Register 2
0x2A (0x4A)
GPIOR1
General Purpose I/O Register 1
0x29 (0x49)
Reserved
0x28 (0x48)
OCR0B
Timer/Counter0 Output Compare Register B
99
0x27 (0x47)
OCR0A
Timer/Counter0 Output Compare Register A
99
0x26 (0x46)
TCNT0
Timer/Counter0 (8 Bit)
0x25 (0x45)
TCCR0B
FOC0A
FOC0B
-
-
WGM02
CS02
CS01
0x24 (0x44)
TCCR0A
COM0A1
COM0A0
COM0B1
COM0B0
-
-
WGM01
WGM00
99
0x23 (0x43)
GTCCR
TSM
-
-
-
-
-
PSR2
PSR54310
149
0x22 (0x42)
EEARH
-
-
-
0x21 (0x41)
EEARL
0x20 (0x40)
EEDR
0x1F (0x3F)
EECR
SPI 0 Data Register
-
-
-
-
157
25
25
-
-
-
-
-
99
CS00
EEPROM Address Register High Byte
20
EEPROM Address Register Low Byte
20
EEPROM Data Register
-
-
EEPM1
EEPM0
EERIE
98
20
EEMWE
EEWE
EERE
20
0x1E (0x3E)
GPIOR0
0x1D (0x3D)
EIMSK
-
-
-
-
-
INT2
INT1
INT0
60
0x1C (0x3C)
EIFR
-
-
-
-
-
INTF2
INTF1
INTF0
60
10
General Purpose I/O Register 0
25
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x1B (0x3B)
Address
PCIFR
Name
-
-
-
-
PCIF3
PCIF2
PCIF1
PCIF0
61
0x1A (0x3A)
Reserved
-
-
-
-
-
-
-
-
0x19 (0x39)
Reserved
-
-
-
-
-
-
-
-
0x18 (0x38)
Reserved
-
-
-
-
-
-
-
-
0x17 (0x37)
TIFR2
-
-
-
-
-
OCF2b
OCF2A
TOV2
148
0x16 (0x36)
TIFR1
-
-
ICF1
-
-
OCF1B
OCF1A
TOV1
127
0x15 (0x35)
TIFR0
-
-
-
-
-
OCF0B
OCF0A
TOV0
100
0x14 (0x34)
Reserved
-
-
-
-
-
-
-
-
0x13 (0x33)
Reserved
-
-
-
-
-
-
-
-
0x12 (0x32)
Reserved
-
-
-
-
-
-
-
-
0x11 (0x31)
Reserved
-
-
-
-
-
-
-
-
0x10 (0x30)
Reserved
-
-
-
-
-
-
-
-
0x0F (0x2F)
Reserved
-
-
-
-
-
-
-
-
0x0E (0x2E)
Reserved
-
-
-
-
-
-
-
-
0x0D (0x2D)
Reserved
-
-
-
-
-
-
-
-
0x0C (0x2C)
Reserved
-
-
-
-
-
-
-
-
0x0B (0x2B)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
83
0x0A (0x2A)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
83
0x09 (0x29)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
83
0x08 (0x28)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
82
0x07 (0x27)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
82
0x06 (0x26)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
82
0x05 (0x25)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
82
0x04 (0x24)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
82
0x03 (0x23)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
82
0x02 (0x22)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
82
0x01 (0x21)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
82
0x00 (0x20)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
82
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega164/324/644 is a
complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the
IN and OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions
can be used.
11
2593AS–AVR–06/05
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
MUL
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
Z,C
2
MULS
Rd, Rr
Multiply Signed
R1:R0 ← Rd x Rr
Z,C
2
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0 ← Rd x Rr
Z,C
2
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0 ← (Rd x Rr) <<
1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
2
Z,C
2
Z,C
2
2
FMULS
Rd, Rr
Fractional Multiply Signed
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
BRANCH INSTRUCTIONS
RJMP
k
IJMP
Relative Jump
PC ← PC + k + 1
None
Indirect Jump to (Z)
PC ← Z
None
2
JMP
k
Direct Jump
PC ← k
None
3
RCALL
k
Relative Subroutine Call
PC ← PC + k + 1
None
4
Indirect Call to (Z)
PC ← Z
None
4
Direct Subroutine Call
PC ← k
None
5
RET
Subroutine Return
PC ← STACK
None
5
RETI
Interrupt Return
PC ← STACK
I
5
ICALL
CALL
k
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1/2/3
1
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
12
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
1
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
None
1
None
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
Rd ← K
None
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
ELPM
ELPM
Rd, Z
ELPM
Rd, Z+
SPM
Extended Load Program Memory
R0 ← (RAMPZ:Z)
None
3
Extended Load Program Memory
Rd ← (Z)
None
3
Extended Load Program Memory
Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1
None
3
Store Program Memory
(Z) ← R1:R0
None
-
13
2593AS–AVR–06/05
Mnemonics
Operands
Description
Operation
Flags
#Clocks
IN
Rd, P
In Port
Rd ← P
None
OUT
P, Rr
Out Port
P ← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
1
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
1
N/A
14
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
Ordering Information
ATmega164
Speed (MHz)(3)
Power Supply
Package(1)
Ordering Code
(2)
10
20
Notes:
Operational Range
1.8 - 5.5V
ATmega164V-10AU
ATmega164V-10PU(2)
ATmega164V-10MU(2)
44A
40P6
44M1
Industrial
(-40oC to 85oC)
2.7 - 5.5V
ATmega164-20AU(2)
ATmega164-20PU(2)
ATmega164-20MU(2)
44A
40P6
44M1
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see “Maximum speed vs. VCC” on page 310.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
15
2593AS–AVR–06/05
ATmega324
Speed (MHz)(3)
Power Supply
Package(1)
Ordering Code
(2)
10
20
Notes:
Operational Range
1.8 - 5.5V
ATmega324V-10AU
ATmega324V-10PU(2)
ATmega324V-10MU(2)
44A
40P6
44M1
Industrial
(-40oC to 85oC)
2.7 - 5.5V
ATmega324-20AU(2)
ATmega324-20PU(2)
ATmega324-20MU(2)
44A
40P6
44M1
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see “Maximum speed vs. VCC” on page 310.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
16
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
ATmega644
Speed (MHz)(3)
Power Supply
Package(1)
Ordering Code
(2)
10
20
Notes:
Operational Range
1.8 - 5.5V
ATmega644V-10AU
ATmega644V-10PU(2)
ATmega644V-10MU(2)
44A
40P6
44M1
Industrial
(-40oC to 85oC)
2.7 - 5.5V
ATmega644-20AU(2)
ATmega644-20PU(2)
ATmega644-20MU(2)
44A
40P6
44M1
Industrial
(-40oC to 85oC)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see “Maximum speed vs. VCC” on page 310.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
17
2593AS–AVR–06/05
Packaging Information
44A
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
18
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
40P6
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.826
A1
0.381
–
–
D
52.070
–
52.578
E
15.240
–
15.875
E1
13.462
–
13.970
B
0.356
–
0.559
B1
1.041
–
1.651
L
3.048
–
3.556
C
0.203
–
0.381
eB
15.494
–
17.526
SYMBOL
eB
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
e
NOTE
Note 2
Note 2
2.540 TYP
09/28/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
40P6
REV.
B
19
2593AS–AVR–06/05
44M1
D
Marked Pin# 1 ID
E
SEATING PLANE
A1
TOP VIEW
A3
A
K
L
Pin #1 Corner
D2
1
2
3
Option A
SIDE VIEW
Pin #1
Triangle
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
Option B
Pin #1
Chamfer
(C 0.30)
SYMBOL
MIN
A
0.80
0.90
1.00
A1
–
0.02
0.05
A3
b
K
Option C
b
e
BOTTOM VIEW
D2
5.00
0.23
0.30
5.20
5.40
7.00 BSC
5.00
e
Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.
NOTE
7.00 BSC
E
E2
MAX
0.25 REF
0.18
D
Pin #1
Notch
(0.20 R)
NOM
5.20
5.40
0.50 BSC
L
0.59
0.64
0.69
K
0.20
0.26
0.41
3/18/05
R
20
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm,
5.20 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
44M1
REV.
F
ATmega164/324/644
2593AS–AVR–06/05
ATmega164/324/644
Errata
ATmega164 Rev. A
Not sampled.
ATmega324 Rev. A
Not sampled.
ATmega644 Rev. A
• EEPROM read from application code does not work in Lock Bit Mode 3.
1. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM
read does not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
21
2593AS–AVR–06/05
Datasheet Revision
History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.
Rev. 2593A-06/05
1.Initial revision.
22
ATmega164/324/644
2593AS–AVR–06/05
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not
intended, authorized, or warranted for use as components in applications intended to support or sustain life.
© Atmel Corporation 2005. All rights reserved. Atmel ®, logo and combinations thereof, Everywhere You Are ®, AVR ®, AVR Studio ®, and others
are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
Printed on recycled paper.
2593AS–AVR–06/05
Similar pages