LINER LT4220 Dual supply hot swap controller Datasheet

LT4220
Dual Supply
Hot Swap Controller
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FEATURES
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DESCRIPTIO
Hot SwapTM Controller for Positive
and Negative Supplies
Supply Tracking Mode
±2.7V to ±16.5V Operation
Analog Current Limit with Foldback
Allows Safe Board Insertion and Removal
from a Live Backplane
Open-Collector Power Good Comparators
Automatic Retry or Latchoff After a Current Fault
Dual Undervoltage Lockout Comparator Inputs
Current Fault Indication
The LT®4220 16-pin dual voltage Hot Swap controller
allows a board to be safely inserted and removed from a
live backplane. The device operates with any combination
of 2.7V to 16.5V and –2.7V to –16.5V supplies. Using two
external N-channel pass transistors, the board supply
voltages can be ramped up at an adjustable rate. A selectable tracking mode allows dual supply tracking control for
ramping the positive and negative supplies together.
The LT4220 features foldback current limit and latches off
both gates if either supply remains in current limit longer
than an adjustable time period. The IC can be configured
for automatic restart after a delay set by the same timer.
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APPLICATIO S
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A power good signal indicates when the output voltages
monitored by the two FB comparators are within tolerance,
and the gate drive signals are at their full on voltage.
Live Board Insertion
RAID Systems
–5.2V ECL Supplies
Industrial Controls
Split Supply Systems
The LT4220 is available in a 16-lead narrow SSOP
package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
±12V 10A Hot Swap Controller
RS +
0.005Ω
VIN+
12V
VCC
R13
10Ω
C4
100nF
Z1*
R5
10Ω
CONNECTOR 1
CONNECTOR 2
7
R15
20k
R1
36.5k
R2
4.99k
R4
4.99k
C7
10nF
C6
1µF
C8
10nF
TRACK
12
16
VCC
15
SENSE +
ON+
11 FAULT
8
TIMER
9
CL1
14
GATE+
10
PWRGD
13 R16, 20k
+
FB
R10
4.99k
FB
6
ON –
VEE
1
Z2*
+
C1
10nF
GND
SENSEK SENSE –
2
3
C5
1µF
VIN–
R6
1k
12V
VOUT+
R9
36.5k
D1
IN4001
12V
VIN +
12V
VOUT +
LT4220
R3
36.5k
–12V
VEE
Q1
SUB85N03-04
R14
10Ω
* 1SMA13AT3 TRANSIENT
VOLTAGE SUPPRESSOR
GATE –
C3
100nF
RS –
0.005Ω
– 5
R12
4.99k
–12V
VIN –
R11
36.5k
C2
4 R8 10nF
1k
R7
10Ω
Q2
SUB85N03-04
D2
IN4001
–12V
VOUT –
TIME (10ms/DIV)
+
CL2
–12V
VOUT –
4220 TA01
4220f
1
LT4220
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VCC to GND ............................................................. 22V
VEE to GND ........................................................... –22V
TRACK, TIMER .............................. – 0.3V to VCC + 0.3V
ON+, FB + ................................. VEE – 0.3V to VCC + 0.3V
ON –, FB – .................................. VEE – 0.3V to VCC + 0.3V
GATE+ ................................................ –0.3V to VCC + 8V
GATE – .............................. –16.5V with VEE = –22V to 0V
SENSE + ............................................. –0.3V to VCC + 5V
SENSE –, SENSEK ....................... VEE – 0.3V to VEE + 3V
PWRGD, FAULT ................................. –0.3V to VCC + 5V
Operating Temperature Range
LT4220C ........................................... 0°C ≤ TA ≤ 70°C
LT4220I ....................................... –40°C ≤ TA ≤ 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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(Notes 1, 2)
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
TOP VIEW
VEE
1
16 VCC
SENSEK
2
15 SENSE+
SENSE –
3
14 GATE+
–
4
13 FB
FB –
5
12 ON+
–
6
11 FAULT
TRACK
7
10 PWRGD
TIMER
8
9
GATE
ON
ORDER PART
NUMBER
LT4220CGN
LT4220IGN
+
GN PART MARKING
GND
4220
4220I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, unless otherwise noted.
SYMBOL
PARAMETER
VCC
VCC Operating Range
●
ICC
VCC Supply Current
●
VEE
VEE Operating Range
●
IEE
VEE Supply Current
VPLKO
VCC Undervoltage Lockout
VMLKO
VEE Undervoltage Lockout
VON+H
ON+ ON Threshold
VON+HYS
ON+ Hysteresis
∆VON + H
ON+ ON Threshold Line Regulation
VCC = 2.7V, VEE = –2.7V to VCC = 16.5V, VEE = –16.5V
∆VON – H
ON – ON Threshold Line Regulation
VCC = 2.7V, VEE = –2.7V to VCC = 16.5V, VEE = –16.5V
VON – HYS
ON – Hysteresis
●
VON – H
ON – ON Voltage Threshold
ON– Falling
●
ION+
ON+ Input Current
VON+ = 2V
●
ION –
ON – Input Current
VON– = GND
●
VFB + H
FB+
FB + Rising
●
VFB + HYS
FB+ Hysteresis
Gate = 5V
●
VFB – H
FB – PWRGD Voltage Threshold
FB – Falling
VFB – HYS
FB – Hysteresis
Gate = 3V
PWRGD Voltage Threshold
CONDITIONS
ON+ Rising
MIN
TYP
2.7
2.7
–2.7
MAX
UNITS
16.5
V
4
mA
–16.5
V
–1.6
–2.4
mA
●
2.35
2.45
2.55
V
●
–2.4
–2.45
–2.5
V
●
1.22
1.24
1.26
V
●
25
50
70
●
0.02
0.15
mV/V
●
0.05
1
mV/V
25
50
70
mV
–1.22
–1.24
–1.26
V
0.01
±1
µA
0.01
±1
µA
1.22
1.24
1.26
25
50
70
●
–1.22
–1.24
–1.26
●
25
50
70
mV
V
mV
V
mV
4220f
2
LT4220
DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
●
0.09
±1
µA
●
0.08
±1
µA
VCC = 2.7V, VEE = –2.7V to VCC = 16.5V, VEE = –16.5V ●
0.015
0.15
mV/V
IINFB+
FB + Input Current
FB + = 3V
IINFB–
FB – Input Current
FB – = –3V
∆VFB+H
FB + PWRGD Threshold Line Regulation
∆VFB–H
FB – PWRGD Threshold Line Regulation
VCC = 2.7V, VEE = –2.7V to VCC = 16.5V, VEE = –16.5V ●
VSENSE+
SENSE+ Trip Voltage (VCC – VSENSE+)
VFB+ = 0V, GATE+ – 0.5V
VFB+ = 1V, GATE+ – 0.5V
VSENSE–
UNITS
0.05
0.5
mV/V
●
6
36
15
48
22
60
mV
mV
SENSE– Trip Voltage (VSENSEK – VSENSE–) VFB – = 0V, GATE– – 0.5V
VFB – = –1V, GATE– – 0.5V
●
–10
–43
–15
–52
–22
–61
mV
mV
IGATEUP+
GATE+ Pull-Up Current
Charge Pump On, VGATE+ = 7V
●
–9
–13
–17
µA
IGATEUP –
GATE– Pull-Up Current
VGATE– = –3V
●
–6
–10
–14
µA
IGATEDN+
GATE+ Pull-Down Current
Any Fault Condition, VGATE+ = 1V
●
20
40
60
mA
IGATEDN –
GATE– Pull-Down Current
Any Fault Condition, VGATE– = VEE + 4V
●
30
70
130
mA
∆VGATE+
External N-Channel GATE+
Drive
VGATE+ – VCC, VCC = 2.7V, VEE = –2.7V
VCC = 5V to 16.5V, VEE = –5V to –16.5V
●
3.5
5
4
6.5
6
8
V
V
∆VGATE–
External N-Channel GATE– Drive
VGATE– – VEE, VCC = 2.7V, VEE = –2.7V
VCC = 5V to 16.5V, VEE = –5V to –16.5V
●
3.5
7.5
5.2
8.5
6
9
V
V
VTIMERH
TIMER High Threshold, Sets FAULT
●
1.22
1.24
1.26
V
VTIMERL
TIMER Low Threshold, Allows Restart
●
0.4
0.5
0.6
V
ITIMERUP
TIMER Pull-Up Current
TIMER = 0V
●
–40
–65
–85
µA
ITIMERDN
TIMER Pull-Down Current
TIMER = 1V
●
2
3.3
4.5
µA
ITIMER(R)
TIMER Current Ratio
ITIMERDN/ITIMERUP
5
7
%
VOL
PWRGD Output Low Voltage
IO = 2mA
IO = 5mA
●
0.3
0.5
V
V
IOH
PWRGD Leakage Current
VPWRGD = 16.5V
●
2
µA
VFOL
FAULT Output Low Voltage
IO = 2mA
IO = 5mA
●
0.3
0.5
V
V
IFPH
FAULT Leakage Current
VFAULT = 16.5V
●
0.06
2
µA
VTRKTHR
TRACK Input Threshold
0.8
1.1
V
ITRK
TRACK Input Current
TRACK = 16.5V
●
0.05
2
µA
VTRKFB+
TRACK Mode FB+ Threshold
IGATE+ = 0µA, TRACK = VCC (Note 3)
●
40
70
mV
VTRKFB–
TRACK Mode FB– Threshold
IGATE– = 0µA, TRACK = VCC (Note 3)
●
40
80
mV
●
0.1
0.3
4220f
3
LT4220
AC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
tPHLON+
ON+ Low to GATE+ Low
5k Pull-Up to GATE+, 1nF Load Capacitor
●
0.6
0.8
1.2
µs
tPLHON+
ON+ High to GATE+ High
5k Pull-Up to GATE+, 1nF Load Capacitor
●
0.6
1.5
3
µs
tPHLFB +
FB + Low to PWRGD Low
5k Pull-Up to PWRGD
●
0.5
0.8
1.2
µs
tPLHFB +
FB + High to PWRGD High
5k Pull-Up to PWRGD
●
0.6
1.25
3
µs
tPHLON–
ON– Low to GATE–
5k Pull-Up to GATE–, 1nF Load Capacitor
●
0.6
1
1.5
µs
tPLHON–
ON – High to GATE– High
5k Pull-Up to GATE–, 1nF Load Capacitor
●
1
2.1
3.5
µs
tPHLFB –
FB – Low to PWRGD Low
5k Pull-Up to PWRGD
●
0.6
1
1.5
µs
tPLHFB –
FB – High to PWRGD High
5k Pull-Up to PWRGD
●
0.8
1.25
2
µs
tSENSE+
SENSE+ to GATE+ Low
1nF On GATE+, 100mV Step, 5k Pull-Up
●
1
4
6
µs
tSENSE–
SENSE– to GATE– Low
1nF On GATE–, 100mV Step, 5k Pull-Up
●
1
4
6
µs
Low
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
UNITS
pins are negative. All voltages referenced to ground (GND) unless
specified.
Note 3: The absolute voltage difference between FB+ and FB– required to
force either the GATE+ or GATE– current to 0µA.
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TYPICAL PERFOR A CE CHARACTERISTICS
50
TA = 25°C
VCC-SENSE+ VOLTAGE (mV)
SUPPLY CURRENT (mA)
ICC
3
2
IEE
1
0
0
5
10
15
SUPPLY VOLTAGE (V)
20
4220 G01
40
60
VCC = 5V
VEE = –5V
ON+ = 2V
ON – = –2V
TA = 25°C
SENSEK-SENSE– VOLTAGE (mV)
4
Negative Circuit Breaker Sense
Voltage vs FB– Voltage
Positive Circuit Breaker Sense
Voltage vs FB+ Voltage
Supply Current vs Supply Voltage
30
20
10
0
–1.5
–1.0
–0.5
0
0.5
FB+ VOLTAGE (V)
1.0
1.5
4220 G02
VCC = 5V
VEE = –5V
ON+ = 2V
ON – = –2V
TA = 25°C
50
40
30
20
10
0
–1.5
–1.0
–0.5
0
0.5
FB– VOLTAGE (V)
1.0
1.5
4220 G03
4220f
4
LT4220
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TYPICAL PERFOR A CE CHARACTERISTICS
Drive vs VCC
10
TA = 25°C
7
GATE– DRIVE (VGATE– – VEE) (V)
GATE+ DRIVE (VGATE+ – VCC) (V)
8
VEE = –5V
6
VEE = –2.7V
5
4
0
3
6
GATE + Pull-Up Current vs
GATE+ Voltage
GATE – Drive vs VEE
9
12
15
14
9
VCC = 5V
8
7
VCC = 2.7V
6
5
4
18
16
TA = 25°C
GATE+ PULL-UP CURRENT (µA)
GATE +
3
6
9
VEE (V)
12
15
30
GATE – Pull-Down Current vs
GATE – Voltage
VCC = 5V
VEE = –5V
ON+ = 0V
FB+ = 2V
TA = 25°C
4
2
6
8
10
8
6
VCC = 5V
VEE = –5V
SENSE+ = VCC
SENSE– = VEE
TA = 25°C
2
0
14
12
10
4
4
2
0
8
6
4220 G07
75
FAULT
400
PWRGD
300
200
20
10
0
3
5
6
2
4
7
1
GATE– VOLTAGE (VGATE– – VEE) (V)
8
4220 G09
ON +, ON – and FB +, FB –
Hysteresis vs Temperature
45.0
TA = 25°C
44.5
70
65
60
55
44.0
43.5
43.0
42.5
42.0
41.5
100
0
30
0
10
HYSTERESIS VOLTAGE (mV)
TIMER PULL-UP CURRENT (µA)
600
500
40
TIMER Pull-Up Current vs VCC
VCC = 5V
VEE = –5V
TA = 25°C
700
50
4220 G08
900
800
VCC = 5V
VEE = –5V
ON– = 0V
FB– = –2V
TA = 25°C
60
GATE– VOLTAGE (VGATE– – VEE) (V)
PWRGD and FAULT VOL vs
Sink Current
7
4220 G06
GATE– PULL-DOWN CURRENT (mA)
GATE– PULL-UP CURRENT (µA)
GATE+ PULL-DOWN CURRENT (mA)
40
2
4
1
3
5
6
GATE+ VOLTAGE (VGATE+ – VCC) (V)
0
70
GATE+ VOLTAGE (V)
VOL (mV)
18
12
50
VCC = 5V
VEE = –5V
VSENSE+ = VCC
VSENSE– = VEE
TA = 25°C
4
GATE – Pull-Up Current vs
GATE – Voltage
60
0
6
4220 G05
GATE + Pull-Down Current vs
GATE+ Voltage
0
8
0
0
4220 G04
10
10
2
VCC (V)
20
12
0
2
4
6
8
SINK CURRENT (mA)
10
50
0
3
6
9
12
15
18
VCC (V)
4220 G10
4220 G11
41.0
–40
–20
40
20
60
0
TEMPERATURE (°C)
80
4220 G12
4220f
5
LT4220
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TYPICAL PERFOR A CE CHARACTERISTICS
FB– and ON– Threshold Voltage vs
Temperature
TIMER Pull-Up Current vs
Temperature
–1.241
70
1.240
–1.240
69
1.239
1.238
1.237
1.236
1.235
–40
TIMER PULL-UP CURRENT (µA)
1.241
THRESHOLD VOLTAGE (V)
THRESHOLD VOLTAGE (V)
FB+ and ON+ Threshold Voltage vs
Temperature
–1.239
–1.238
–1.237
–1.236
–20
40
20
60
0
TEMPERATURE (°C)
80
–1.235
–40
–20
40
20
60
0
TEMPERATURE (°C)
4220 G13
80
4220 G14
68
67
66
65
64
–40
–20
40
20
60
0
TEMPERATURE (°C)
80
4220 G15
GATE +, GATE – Pull-Up Current vs
Temperature
GATE+, GATE– PULL-UP CURRENT (µA)
15
14
GATE+
13
12
GATE–
11
10
–40
–20
40
20
60
0
TEMPERATURE (°C)
80
4220 G16
4220f
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LT4220
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PI FU CTIO S
VEE (Pin 1): Negative Supply. The negative supply input
ranges from –2.7V to –16.5V for normal operation. IEE is
typically –1.6mA. An internal undervoltage lockout circuit
disables the device for inputs greater than –2.45V. A 10Ω,
1µF RC bypass network from VIN– to the VEE pin decouples
transients from the device.
SENSEK (Pin 2): Negative Supply Current Limit Kelvin
Sense Pin. Connect to VIN–.
SENSE – (Pin 3): Negative Supply Current Limit Sense Pin.
A sense resistor is placed in the supply path between
SENSEK and SENSE–. The current limit circuit will regulate
the voltage across the sense resistor to
–50mV (SENSEK – SENSE–) when the FB– voltage is less
than –0.7V. If VFB– goes above –0.7V, the voltage across
the sense resistor decreases linearly and stops at –15mV
when VFB– is 0V. If current limit is not used, connect to
SENSEK.
GATE– (Pin 4): Gate Drive for the External Negative Supply
N-Channel FET. An internal 10µA current source drives the
pin. An external capacitor connected from the GATE– pin
to VOUT– will control the rising slope of the VOUT– signal.
The voltage is clamped to 9V above VEE.
When the current limit is reached, the GATE– pin voltage
will be adjusted to maintain a constant voltage across the
RS– resistor while the timer capacitor starts to charge. If
the TIMER pin voltage exceeds 1.24V, the fault latch will be
set and both GATE– and GATE+ pins will be pulled low.
The GATE– pin is pulled to VEE whenever the ON+ pin is
below 1.24V, the ON– pin is above –1.24V, or either supply
is in the undervoltage lockout voltage range, or the fault
latch is set by the TIMER pin rising above 1.24V.
FB– (Pin 5): Negative Power Good Comparator Input. This
pin monitors the negative output voltage (VOUT–) with an
external resistive divider. When the voltage on FB– is
below –1.24V and the initial GATE– drive voltage has
reached a maximum (indicated by setting the internal
GATE– good latch) and the FB+ release conditions are met,
the PWRGD pin is released. PWRGD is pulled low when the
FB– pin is above –1.185V. Note the PWRGD pin is wireORed with the FB+ pin conditions.
FB– also controls the negative supply current limit sense
amplifier input offset to provide foldback current limit. The
FB– pin linearly reduces the negative supply sense amplifier offset from –52mV to –15mV for FB– in the range
–0.75V < FB– < 0V. To disable VEE PWRGD and foldback
current limit, the FB– pin should be set to a voltage in the
range: –1.3V > FB – > VEE + 0.5V but should never be more
negative then –5.8V for normal operation.
ON– (Pin 6): The Negative Supply Good Comparator Input.
This pin monitors the negative input voltage (VEE) with an
external resistive divider for undervoltage lockout. When
the voltage at the ON– pin is below the VON–H high-to-low
threshold (–1.24V), the negative supply is considered
good. If the ON– pin rises above –1.185V, both GATE– and
GATE+ are pulled low. If ON– is not used, the ON– pin
should be set to –1.3V > ON– > VEE + 0.5V.
TRACK (Pin 7): Supply Tracking Mode Control. If the TRACK
pin is pulled high, the internal supply tracking circuit will
be enabled during start-up. The TRACK circuit monitors
the FB+ and the FB– pins to keep their magnitude within a
small voltage range by controlling the GATE+ and GATE–
charge currents. The tracking is disabled when either FB
comparator indicates the output is good. Tracking is reenabled if ON+ is pulled below 1.185V, ON– is pulled above
–1.185V or either supply is below the internal undervoltage
lockout. Typically, the TRACK pin is tied to GND or to VCC.
If left floating, tracking is enabled.
TIMER (Pin 8): Fault Time Out Control. An external timing
capacitor at this pin programs the maximum time the part
is allowed to remain in current limit before issuing a fault
and turning off the external FETs. Additionally, for
autorestart, this pin controls the time before an autorestart
is initiated.
When the part goes into current limit, a 65µA pull-up
current source starts to charge the timing capacitor. When
the voltage reaches VTIMERH (1.24V), the internal fault
latch is set, FAULT pulls low and both GATE pins are pulled
low; the pull-up current will be turned off and the capacitor
is discharged by a 3.3µA pull-down current. When the
TIMER pin falls below 0.5V, the part is allowed to restart
if the ON+ pin is pulsed below 1.185V, thereby resetting
internal fault latch—typically done by connecting the
4220f
7
LT4220
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PI FU CTIO S
FAULT pin to the ON+ pin, otherwise the part remains
latched off.
To disable the timeout circuit breaker, connect the TIMER
pin to GND.
GND (Pin 9): Supply Ground Pin.
PWRGD (Pin 10): Open-Collector Output to GND. PWRGD
goes to high impedance after the initial GATE– and final
GATE+ pins have reached their maximum voltage and after
the FB+ pin goes above 1.24V low-to-high threshold and
after the FB– pin falls below –1.24V high-to-low threshold.
An external pull-up resistor can pull the pin to a voltage
higher or lower than VCC. If not used, PWRGD can be left
floating or tied to GND.
FAULT (Pin 11): Open-Collector Output to GND. The
FAULT pin is pulled low whenever the TIMER pin rises
above VTIMERH (1.24V) threshold, thereby setting the
internal fault latch. It goes to high impedance whenever the
internal fault latch is reset. The fault latch is reset with
either internal undervoltage lockout conditions, or by the
ON comparators if the TIMER pin is also below 0.5V. If not
used, the FAULT pin can be left floating or tied to GND.
ON+ (Pin 12): Positive Supply Good Comparator Input. It
monitors the positive input voltage (VCC) with an external
resistive divider for undervoltage lockout. When the voltage on ON+ is above the VON+H high-to-low threshold
(1.24V) the positive supply is considered good. If ON+
drops below 1.185V, both GATE– and GATE+ are pulled
low.
released. PWRGD is pulled low when the FB+ pin is below
1.185V. The PWRGD pin is wire-ORed with the FB– pin
conditions.
FB+ also controls the positive current limit sense amplifier
input offset to provide foldback current limit. The FB+ pin
linearly reduces the positive sense amplifier offset from
48mV to 15mV for FB+ in the range 0.85V > FB+ > 0V. If
PWRGD and foldback current limit are not used, the FB+
pin should be set to a voltage in the range of 1.3V < FB+ <
VCC + 0.3V.
GATE+ (Pin 14): High Side Gate Drive for the External
Positive Supply N-Channel FET. An internal charge pump
guarantees at least 3.5V above VCC, for supply voltages at
±2.7V increasing to a minimum of 5V above VCC for supply
voltages greater than ±5V. A 10µA pull-up current source
drives the pin. An external capacitor connected from the
GATE+ pin to GND will control the rising slope of the GATE+
signal. The voltage is clamped to 7V above VCC.
When the current limit is reached, the GATE+ pin voltage
will be adjusted to maintain a constant voltage across the
RS+ resistor while the timer capacitor starts to charge. If
the TIMER pin voltage exceeds 1.24V, the GATE+ pin will
be pulled low.
The GATE+ pin is pulled to GND whenever the ON+ pin is
below 1.24V, the ON– pin is above –1.24V, either supply is
in the undervoltage lockout voltage range, or the TIMER
pin rises above 1.24V.
If ON+ is pulled low after a current limit fault and when the
TIMER pin is below 0.5V, the fault latch is reset allowing
the part to turn back on. Typically the FAULT pin is tied
back to the ON+ pin for autorestart. If not used, the ON+ pin
should be set to a voltage in the range of 1.3V < ON+ < VCC
+ 0.3V. The ON+ pin requires a bypass capacitor connected
to ground.
SENSE+ (Pin 15): Positive Supply Current Limit Sense Pin.
A sense resistor must be placed in the supply path between VCC and SENSE+. The current limit circuit will
regulate the voltage across the sense resistor to 50mV
(VCC – SENSE+) when the FB+ voltage is greater than
0.85V. If VFB+ goes below 0.85V, the voltage across the
sense resistor decreases linearly and stops at 15mV when
VFB+ is 0V.
FB+ (Pin 13): Positive Power Good Comparator Input. This
pin monitors the positive output voltage (VOUT+) with an
external resistor divider. When the voltage on FB+ is above
the VFB+H low-to-high threshold (1.24V) and the GATE+
drive voltage has reached a maximum, the PWRGD is
VCC (Pin 16): Positive Supply. The positive supply input
ranges from 2.7V to 16.5V for normal operation. ICC is
typically 2.7mA. An internal undervoltage lockout circuit
disables the chip for inputs less than 2.45V. Place a 0.1µF
bypass capacitor next to the VCC pin.
4220f
8
LT4220
W
BLOCK DIAGRA
VCC
CURRENT LIMIT
FROM SENSE AMPS
TIMER AND LOGIC
+
ILIM
FAULT
S Q
R
R Q
–
1.24V
60µA
FAULT
LATCH
8 TIMER
3µA
11 FAULT
+
–
0.5V
1.24V
+
ON+
ON
–
12
PUMP
10µA
ON–
+
6
–1.24V
1.24V
FB
–
GATE ON
–
UVLO
VCC AND
VEE GOOD
FB +
15 SENSE+
+–
53mV
+
+
+
–
13
FB –
14 GATE +
+
VCC
TRACK
10 PWRGD
–
S Q
P GATE
GOOD
EN
R Q
+
5
–1.24V
VCC
ON
GATE GOOD
LATCHES
10µA
4 GATE –
+
–
–
N GATE
GOOD
S Q
+–
R Q
2 SENSEK
52mV
TOFF
S Q
3 SENSE–
R Q
WEAK DIODES
TRACK OFF
LATCH
1 VEE
9 GND
16 VCC
TRACK
7
4220 BD
SUBSTRATE
VCC
4220f
9
LT4220
W
UW
TI I G DIAGRA S
ON +
0V
1V
FB +
1V
100mV
tPLHON+
GATE+
0V
tPHLON+
PWRGD
10V
0.5V
4220 F01
1V
100mV
tPLHFB+
tPHLFB+
2.5V
2.5V
0V
Figure 1. ON+-to-GATE+ Timing
4220 F02
Figure 2. FB+-to-PWRGD Timing
0V
ON–
1V
0V
0V
–1V
FB–
–1V
tPLHON–
tPHLON–
VEE + 3.5V
GATE–
4220 F03
Figure 3. ON–-to-GATE– Timing
tPHLFB–
2.5V
2.5V
0V
4220 F04
Figure 4. FB–-to-PWRGD Timing
100mV
VCC – SENSE+
0V
tPLHFB–
PWRGD
VEE + 1.2V
VEE
–1V
–1V
0V
VEE – SENSE –
50mV
–50mV
–100mV
tSENSE+
tSENSE –
10V
GATE+
GATE–
0V
4220 F05
–2V
4220 F06
Figure 5. SENSE+-to-GATE+ Timing
VEE
Figure 6. SENSE–-to-GATE– Timing
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APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
circuit board bypass capacitors can draw large peak
currents from the backplane power bus as they charge up.
The LT4220 is designed to turn on a board’s ±V dual
supplies in a controlled manner, allowing the circuit board
to be safely inserted or removed from a live backplane. The
part provides supply tracking as well as undervoltage and
overcurrent protection. Power good and fault output signals indicate, respectively, if both power output voltages
are ready or if an overcurrent time-out fault has occurred.
The dual power supply on the circuit board is controlled
with two external N-channel pass transistors Q1 and Q2 in
the ±V dual power supply path. The sense resistors RS+
and RS– provide current detection while capacitor C1 and
C2 control the VOUT+ and VOUT – slew rate. Optionally, the
TRACK pin can be tied to VCC enabling the dual output
voltages to ramp up together by tracking the voltages at
the FB+ and FB– pins. Resistors R6 and R8 provide current
control loop compensation while R5 and R7 prevent high
frequency oscillations in Q1 and Q2. C3 and R8 on Q2
prevent fast dV/dt transients from turning Q2 on during
4220f
10
LT4220
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APPLICATIO S I FOR ATIO
live insertion. Resistive dividers R1, R2 and R3, R4 provide undervoltage sensing. Resistor dividers R9, R10 and
R11, R12 provide a power good signal and control output
voltage tracking when TRACK is enabled.
Initial Power-Up Sequence
After the power pins first make contact, transistors Q1 and
Q2 remain off. If the voltage at the ON+ and ON– pins
exceed the turn-on threshold voltage, the internal voltage
on the VCC and VEE power pins exceed the undervoltage
lockout threshold, and the timer pin voltage is less than
1.24V, the gate drive to transistors Q1 and Q2 will be
turned on. The voltage on the GATE+ and GATE– pins will
be regulated to control the inrush current if the voltage
across RS+ or RS– exceeds the sense amplifier current
limit threshold. If supply tracking is enabled, each gate will
also be regulated to keep the magnitudes at the FB+ and
FB– pins within 50mV of each other.
Internal Supply Diodes
The LT4220 contains two internal diodes which clamp VEE
and VCC with respect to GND in the event either supply pin
is floating. VEE is clamped one diode above GND and VCC
is clamped one diode below GND. The current through
these diodes are designed to handle 10mA internal device
current and should not be used for high load current
conditions.
VCC
STAGGERED
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
VIN+
RS+
VOUT+
Z1*
R1
R2
GND
C7
ESD
CONTROL
R4
R13
10Ω
C4
100nF
7
CONNECT FOR
TRACK
AUTO RESTART
12
ON+
11 FAULT
8
TIMER
C6
1µF
9
GND
R5
10Ω
16
VCC
15
SENSE +
– 5
R11
D2
IN4001
GATE –
C2
4 R8 10nF
1k
C3
100nF
R7
10Ω
+
CL2
RS–
Q2
GND MUST CONNECT FIRST
D1
IN4001
R12
ON –
VEE SENSEK SENSE –
1
2
3
R14
10Ω
CL1
R10
C5
1µF
Z2*
C1
10nF
LT4220
FB
R3
VEE
R6
1k
+
14
GATE+
10
R9
PWRGD
R16, 20k
+ 13
FB
C8
6
VIN–
Q1
*TRANSIENT VOLTAGE SUPPRESSOR
VOUT–
4220 F07
Figure 7. Hot Swap Controller on Daughter Board with Tracking Disabled
4220f
11
LT4220
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APPLICATIO S I FOR ATIO
Whenever the output voltages reach their final value as
sensed by R9, R10 and R11, R12 and both gate signals are
fully on, the PWRGD pin will go high impedance.
A typical timing sequence is shown in Figure 8 with
tracking enabled. The sequence is as follows:
1) The power pins make contact and the undervoltage
lockout thresholds are exceeded.
2) The ON comparator thresholds are exceeded and the
GATE pins start ramping up. VOUT+ follows GATE+ by
the N-channel FET threshold voltage.
3) GATE+ is limited by the tracking circuit because VOUT–
lags behind VOUT+. When VOUT– starts ramping, GATE–
holds at approximately the threshold voltage of the
N-channel FET due to C2 slew rate control.
4) When the magnitude of VOUT– catches up with VOUT+,
GATE+ resumes ramping. The slowest VOUT will limit
the faster VOUT slew rate.
5) GATE+ internal gate good signal threshold is reached.
6) GATE – internal gate good signal threshold is reached,
enabling the FB output comparators. If both FB com12
VCC
VEE
3 4
5
6
+UVLO
parators indicate the output is good, the PWRGD pin
output goes high impedance and is pulled up by an
external pullup resistor.
Power Supply Ramping
For large capacitive loads, the inrush current will be limited
by the VOUT+ and VOUT– slew rate or by the fold-back
current limit. For a desired inrush current that is less than
the fold-back current limit, the feedback networks R6, C1
and R8, C2 can be used to control the VOUT slew rate. For
the desired inrush current and typical gate pull-up current,
the feedback network capacitors C1 and C2 can be calculated as:
C1 = (10µA • CL1)/IINRUSH+ and
(1)
C2 = (10µA • CL2)/IINRUSH–
(2)
where CL1 and CL2 are the positive and negative output
load capacitance. If the supply-tracking mode is enabled
(TRACK = High), during startup, the output with the
slowest slew rate will also limit the slew rate of the
opposite output (Note: Supply-tracking is also controlled
by the resistive dividers on the FB pins. See Supply
Tracking). Additionally, C1 and C2 should be greater than
5nF to prevent large overshoot in the output voltage for
transient loads with small capacitive loads.
Capacitor C3 and resistor R8 prevent Q2 from momentarily turning on when the power pins first make contact.
Without C3, capacitor C2 and CGD(Q2) would hold the gate
of Q2 near ground before the LT4220 could power up and
pull the gate low. The minimum required value of C3 can
be calculated by:
–UVLO
ON+
ON–
GATE+
 VEE − VTH

C3 = 
(C GD(Q2) + C 2) • 1.2
 VTH



VOUT+
GATE–
VOUT–
PWRGD
4220 F08
Figure 8. Typical Timing Sequence
(3)
where VTH is the MOSFET’s minimum gate threshold and
VEEMAX is the maximum negative supply input voltage. If
C2 is not used, the minimum value for C3 should be 10nF
to ensure stability. C2 and C3 must be the same type to
ensure tracking over temperature.
4220f
12
LT4220
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APPLICATIO S I FOR ATIO
Current Limit/Electronic Circuit Breaker
The LT4220 features foldback current limit with an electronic circuit breaker that protects against short-circuits
or excessive supply currents. The current limit is set by
placing sense resistors between VCC (Pin 16) and SENSE+
(Pin 15) and between SENSEK (Pin 2) and SENSE– (Pin 3).
An adjustable timer will trip an electronic circuit breaker if
the part remains in current limit for too long.
To prevent excessive power dissipation in the pass transistors and to prevent voltage spikes on the input supply
during overcurrent conditions at the output, the current
folds back as a function of the output voltage, which is
sensed at the feedback pins FB+ and FB– . When the voltage
at the FB+ (or FB–) pin is 0V, the sense amplifier offset is
15mV (–15mV), and limits the current to ILIMIT = 15mV/
RS+ (–15mV/RS–). As the output voltage increases, the
sense amplifier offset increases until the FB+ (or FB–)
voltage reaches 0.85V (–0.75V), At which point the current limit reaches a maximum of ILIMIT = 48mV/RS+
(– 52mV/RS–).
Timer Function and Autorestart
The TIMER pin (Pin 8) provides a method for setting the
maximum time the LT4220 is allowed to operate in current
limit. When the current limit circuitry is not active, the
TIMER pin is pulled to GND by a 3.3µA current sink.
Whenever the current limit circuit becomes active, by
either a positive or negative sense amplifier operating in
current limit, a 65µA pull-up current source is connected
to the TIMER pin and the voltage rises with a slope equal
to dV/dt = 65µA/CTIMER. The desired current limit time (t)
can be set with a capacitor value of:
CTIMER = t • 65µA/1.24V
(4)
If the current limit circuit turns off, the TIMER pin will be
discharged to GND at a rate of:
dV/dt = 3.3µA/CTIMER
(5)
Whenever the TIMER pin ramps up and reaches the 1.24V
threshold, the internal fault latch is set and the FAULT pin
(Pin 11) is pulled low. GATE+ is pulled down to ground,
GATE– is pulled down to VEE, and the TIMER pin starts
ramping back to GND by the 3.3µA current sink. After the
fault latch is set, the LT4220 can be restarted by pulling the
ON+ pin low after the TIMER pin falls below 0.5V. The
LT4220 can also be restarted by cycling either supply
beyond its UVLO. Otherwise the part remains latched off.
For autorestart, the FAULT pin can be tied to the ON+ pin.
The autorestart will occur after the TIMER pin falls below
0.5V.
Undervoltage Detection
The ON+ and ON– pins can be used to detect an undervoltage
condition at the power supply inputs. The ON+ and ON–
pins are connected to analog comparators with 50mV of
hysteresis. If the ON+ pin falls below its threshold voltage
or the ON– pin rises above its threshold voltage, the GATE
pins are pulled low and held low until the ON+ and ON– pins
exceed their turn-on thresholds (1.24V and –1.24V). External capacitance at the ON pins may be required to filter
supply ringing from crossing the ON comparator threshold.
Additionally there is an internal undervoltage lockout on
both supplies of approximately VCC < 2.45V and VEE >
–2.45V. If either supply is in UVLO, both GATE pins will be
pulled low and all internal latches will be reset.
ON– Protection
If the ON– pin is driven directly and not connected to the
negative supply through a resistor divider, a 10k resistor
must be connected between the driver and the ON– pin.
Power Good Detection
The LT4220 includes two comparators for monitoring the
output voltages. The FB+ and the FB– pins are compared
against 1.24V and –1.24V internal references respectively.
The comparators exhibit 50mV of hysteresis. The comparator outputs are wire-ORed to the open collector PWRGD
pin that is enabled once both GATE+ and GATE– pins have
reached their maximum gate drive voltage as indicated by
the internal gate good latches. The PWRGD pin goes high
impedance when both FB+ and FB– inputs exceed VFB+H
and VFB –H thresholds, GATE+ is fully on and Gate– initially
has been fully on.
4220f
13
LT4220
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APPLICATIO S I FOR ATIO
Supply Tracking
ON+, ON– Bypass Capacitors
If the TRACK pin (Pin 7) is high the supply power-up
tracking mode is enabled. This feature forces both supplies to reach their final value at the same time, during
power-up and for faults that drive the output supplies to
zero. During this mode the GATE pins are controlled to
keep the differential magnitude of the FB pins to within
50mV. The FB pins are scaled versions of the output
voltages. Therefore, control of the FB pins, via the GATE
pins, will control the output voltages at the same scale.
Bypass capacitors are required from ON+ to ground and
ON– to ground. A typical time constant is:
|∆VFB(TRK)| = |VFB+ – VFB–|
(6)
Supply tracking will continue until: either FB pin reaches
the associated PWRGD threshold. If any fault condition
occurs that turns the GATE pins off, supply tracking will be
reenabled. The GATE off conditions include: (1) either ON
pin detects undervoltage, (2) internal undervoltage lockout, (3) the fault latch is set by a current limit time-out.
VEE Bypassing
The VEE supply pin should be filtered with an RC network
to reduce high dV/dt slew rates from disturbing internal
circuits. Typical RC bypassing sufficient to prevent circuit
misbehavior is R14 = 10Ω and C5 = 1µF. The GATE–,
SENSEK and SENSE– pins have been designed such that
they can be pulled below or above VEE for short periods of
time while the VEE pin is reaching its steady state voltage.
If desired, a higher R14 • C5 time constant may be used to
prevent short circuit transients from tripping the VEE
undervoltage lockout circuit at –2.45V. R14 should be
sufficient to decouple C5 from causing transients on VIN–
during live insertion.
Under the condition of a short circuit on VOUT–, parasitic
inductance and resistance in the VIN– path will cause VIN–
to collapse toward 0V causing the VEE pin voltage to also
discharge toward 0V before the external FET can be turned
off (typically 7µs to 10µs). To prevent a UVLO condition
from occurring, the R14 • C5 time constant should be
sufficient to hold the VEE pin voltage out of the VEE UVLO
voltage range. If the VEE pin reaches its UVLO voltage,
GATE+ will also be pulled low. For the case where C3 is
large, causing an even slower N-channel FET turnoff,
higher RC bypassing may be necessary to prevent tripping
the VEE UVLO.
14
TC (ON+) = (R1||R2)C7 = 44µs
TC (ON–) = (R3||R4)C8 = 44µs
Supply Ringing
Normal circuit design practice calls for capacitive bypassing of the input supply to active devices. The opposite is
true for Hot Swap circuits that are connected into a
backplane, where capacitive loading would cause transients during an abrupt connection to the backplane. With
little or no capacitive decoupling on the powered side of
the N-channel FETs, connection transients or load transients will typically cause ringing on the supply leads due
to parasitic inductance. It is recommended to use a
snubber circuit comprising of a series 10Ω and 0.1µF
capacitor to dampen transient ringing. The supply
decoupling circuit on the VEE pin also provides a snubber
for VIN–.
Additionally, if the supply voltage overshoot can exceed
the ±22V maximum rating on the part, a transient voltage
suppressor is recommended. Voltage transients can occur during load short-circuit conditions, where parasitic
inductance in the supply leads can build up energy before
the external N-channel FET can be turned off. This is
especially true for the negative side FET where a large C3
value slows the turn off of the N-channel FET. Subsequent
overshoot when the FET is finally turned off can be as
much as 2× the supply voltage even with the snubber
circuit. Additional protection using a transient suppressor
may be needed to prevent exceeding the maximum supply
voltage rating.
Supply Reversal Protection
A variety of conditions on VOUT+ and VOUT – may result in
supply reversal. To protect devices connected to VOUT+
and VOUT – protection diodes should be used. 1N4001
diodes can be used for most aplications. Connection of
these diodes (D1, D2) are shown in the front page Typical
Application.
4220f
LT4220
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.053 – .068
(1.351 – 1.727)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0502
4220f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT4220
U
TYPICAL APPLICATIO
RS+
STAGGERED
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
Q1
SUB85N03-04 POWER GOOD
VCC
VOUT +
Z1*
R13
10Ω
C4
100nF
7
CONNECT FOR
AUTO RESTART
R1
TRACK
12
R2
C7
C6
1µF
R5
10Ω
16
VCC
15
SENSE +
ON+
11 FAULT
8
TIMER
RPG
5.1k
C1
10nF
R6
1k
14
GATE+
10
PWRGD
13
FB+
R10
LT4220
9
GND
R4
FB
ON –
VEE SENSEK SENSE –
1
2
3
R3
GND
R14
10Ω
–
5
ESD
CONTROL
R11
+
GATE–
C2
4 R8 10nF
1k
C3
100nF
C5
1µF
CL1
R12
C8
6
+
R9
CL2
R7
10Ω
RS–
VEE
Z2*
VOUT –
Q2
SUB85N03-04
4220 F09
GND MUST CONNECT FIRST
*TRANSIENT VOLTAGE SUPPRESSOR
Figure 9. Hot Swap Controller on Mainboard with Tracking
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC 1421
Dual Hot Swap Controller
Two Circuit Breakers for Supplies from 3V to 12V and Supports –12V
LTC1422
Single Hot Swap Controller in SO-8
Operates from 3V to 12V
LTC1645
Dual Hot Swap Controller
Operates from 1.2V to 12V, Allows Supply Sequencing
LTC1647
Dual Hot Swap Controller
Operates from 2.7V to 16.5V, Separate ON Pins
LTC4211
Single Hot Swap Controller with Multifunction
Current Control
2.5V to 16.5V, Active Inrush Limiting, Fast Comparator
LTC4230
Triple Hot Swap Controller with Multifunction
Current Control
1.7V to 16.5V, Active Inrush Limiting, Fast Comparator
®
4220f
16 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
LT/TP 0403 2K • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2003