TI1 AMC1311QDWVQ1 High-impedance, 2-v input, reinforced isolated amplifier Datasheet

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AMC1311-Q1, AMC1311B-Q1
SBAS897 – MARCH 2018
AMC1311x-Q1 High-Impedance, 2-V Input, Reinforced Isolated Amplifiers
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C6
2-V, High-Impedance Input Voltage Range
Optimized for Isolated Voltage Measurement
Low Offset Error and Drift:
– AMC1311B-Q1: ±1.5 mV (max), ±15 µV/°C
(max)
– AMC1311-Q1: ±9.9 mV (max), ±20 µV/°C (typ)
Fixed Gain: 1
Very Low Gain Error and Drift:
– AMC1311B-Q1: ±0.3% (max), ±45 ppm/°C
(max)
– AMC1311-Q1: ±1% (max), ±30 ppm/°C (typ)
Low Nonlinearity and Drift: 0.01%, 1 ppm/°C (typ)
3.3-V Operation on High-Side (AMC1311B-Q1)
Missing High-Side Supply Indication
Safety-Related Certifications:
– 7000-VPK Reinforced Isolation per DIN V VDE
V 0884-11 (VDE V 0884-11): 2017-01
– 5000-VRMS Isolation for 1 Minute per UL1577
– CAN/CSA No. 5A-Component Acceptance
Service Notice
Isolated Voltage Sensing In:
– Traction Inverters
– Onboard Chargers
– DC/DC Converters
3 Description
The AMC1311-Q1 is a precision, isolated amplifier
with an output separated from the input circuitry by an
isolation barrier that is highly resistant to magnetic
interference. This barrier is certified to provide
reinforced galvanic isolation of up to 7 kVPEAK
according to VDE V 0884-11 and UL1577. Used in
conjunction with isolated power supplies, this isolated
amplifier separates parts of the system that operate
on different common-mode voltage levels and
protects lower-voltage parts from damage.
The high-impedance input of the AMC1311-Q1 is
optimized for connection to high-voltage resistive
dividers or other voltage signal sources with high
output resistance. The excellent performance of the
device supports accurate, low temperature drift
voltage or temperature sensing and control in closedloop systems. The integrated missing high-side
supply voltage detection feature simplifies systemlevel design and diagnostics.
The AMC1311-Q1 is offered with two performance
grade options: AMC1311-Q1 and AMC1311B-Q1.
Device Information(1)
PART NUMBER
AMC1311x-Q1
PACKAGE
SOIC (8)
BODY SIZE (NOM)
5.85 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
HV+
Gate
Driver
R1
AMC1311B-Q1
R2
RF
Power Supply
VIN
CF
Gate
Driver
R3
3.0 V to 5.5 V
SHTDN
VDD1
GND1
HV-
Reinforced Isolation
VDD1
Detection
VOUTP
ADC121S101-Q1
12-Bit ADC
VOUTN
VDD2
3.0 V to 5.5 V
GND2
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
AMC1311-Q1, AMC1311B-Q1
SBAS897 – MARCH 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
ADVANCE INFORMATION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 21
1
1
1
2
3
3
4
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
9.3 Do's and Don'ts ...................................................... 24
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ...................................... 10
Insulation Characteristics Curves ........................ 11
Typical Characteristics .......................................... 12
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2018
*
Initial release.
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5 Device Comparison Table
PARAMETER
AMC1311B-Q1
High-side supply voltage, VDD1
Specified ambient temperature, TA
Input offset voltage, VOS
AMC1311-Q1
3.0 V to 5.5 V
4.5 V to 5.5 V
–40°C to +125°C
–40°C to +125°C
4.5 V ≤ VDD1 ≤ 5.5 V
±1.5 mV
±9.9 mV
3.0 V ≤ VDD1 ≤ 5.5 V
±2.5 mV
Not applicable
±3 µV/°C (typ), ±15 µV/°C (max)
±20 µV/°C (typ)
±0.3%
±1%
±5 ppm/°C (typ), ±45 ppm/°C (max)
±30 ppm/°C (typ)
75 kV/µs (min)
15 kV/µs (min)
Input offset drift, TCVOS
Gain error, EG
Gain error drift, TCEG
Common-mode transient immunity, CMTI
6 Pin Configuration and Functions
VDD1
1
8
VDD2
VIN
2
7
VOUTP
SHTDN
3
6
VOUTN
GND1
4
5
GND2
ADVANCE INFORMATION
DWV Package
8-Pin SOIC
Top View
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
VDD1
—
2
VIN
I
Analog input
3
SHTDN
I
Shutdown input, active high, with internal pullup resistor (typical value: 100 kΩ)
4
GND1
—
High-side analog ground
5
GND2
—
Low-side analog ground
6
VOUTN
O
Inverting analog output
7
VOUTP
O
Noninverting analog output
8
VDD2
—
Low-side power supply, 3.0 V to 5.5 V, relative to GND2.
See the Power Supply Recommendations section for power-supply decoupling recommendations.
High-side power supply, 3.0 V to 5.5 V for the AMC1311B-Q1 (4.5 V to 5.5 V for the AMC1311-Q1),
relative to GND1. See the Power Supply Recommendations section for power-supply decoupling
recommendations.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN
MAX
VDD1 to GND1
–0.3
6.5
VDD2 to GND2
–0.3
6.5
GND1 – 6
VDD1 + 0.5
SHTDN
GND1 – 0.5
VDD1 + 0.5
Output voltage
VOUTP, VOUTN
GND2 – 0.5
VDD2 + 0.5
V
Input current
Continuous, any pin except power-supply pins
–10
10
mA
Power-supply voltage
Input voltage
Temperature
(1)
VIN
Junction, TJ
Storage, Tstg
UNIT
V
V
150
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
ADVANCE INFORMATION
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD1 to GND1, AMC1311-Q1
4.5
5
5.5
VDD1 to GND1, AMC1311B-Q1
3.0
5
5.5
VDD2 to GND2
3.0
3.3
5.5
V
POWER SUPPLY
High-side power supply
Low-side power supply
V
ANALOG INPUT
Absolute input voltage
VIN to GND1
–2
VDD1
V
VFSR
Specified linear input full-scale voltage
VIN to GND1
–0.1
2
V
VClipping
Input voltage before clipping output
VIN to GND1
2.516
V
DIGITAL INPUT
Input voltage
SHTDN
GND1
VDD1
V
–40
125
°C
TEMPERATURE RANGE
TA
4
Specified ambient temperature
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7.4 Thermal Information
AMC1311x-Q1
THERMAL METRIC (1)
DWV (SOIC)
UNIT
8 PINS
RθJA
84.6
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
28.3
°C/W
RθJB
Junction-to-board thermal resistance
41.1
°C/W
ψJT
Junction-to-top characterization parameter
4.9
°C/W
ψJB
Junction-to-board characterization parameter
39.1
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
Junction-to-ambient thermal resistance
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
TEST CONDITIONS
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (high-side supply)
PD2
Maximum power dissipation (low-side supply)
VALUE
VDD1 = VDD2 = 5.5 V
97.9
VDD1 = VDD2 = 3.6 V, AMC1311B-Q1 only
56.16
VDD1 = 5.5 V
53.35
VDD1 = 3.6 V, AMC1311B-Q1 only
30.24
VDD2 = 5.5 V
44.55
VDD2 = 3.6 V
25.92
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UNIT
mW
ADVANCE INFORMATION
PARAMETER
mW
mW
5
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SBAS897 – MARCH 2018
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7.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance (1)
Shortest pin-to-pin distance through air
≥9
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
≥9
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double insulation
(2 × 0.0105 mm)
≥ 0.021
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 600
V
Material group
According to IEC 60664-1
Overvoltage category
per IEC 60664-1
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01
ADVANCE INFORMATION
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
I
Rated mains voltage ≤ 300 VRMS
(2)
At ac voltage (bipolar)
2121
VPK
Maximum-rated isolation
working voltage
At ac voltage (sine wave)
1500
VRMS
At dc voltage
2121
VDC
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM, t = 60 s (qualification test)
7000
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
8400
VIOSM
Maximum surge isolation
voltage (3)
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
Apparent charge (4)
qpd
Barrier capacitance,
input to output (5)
CIO
Insulation resistance,
input to output (5)
RIO
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s
≤5
Method b1, at routine test (100% production) and preconditioning (type test),
Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
≤5
VIO = 0.5 VPP at 1 MHz
~1
VPK
VPK
pC
pF
12
VIO = 500 V at TA = 25°C
> 10
VIO = 500 V at 100°C ≤ TA ≤ 125°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
55/125/21
Ω
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
5000
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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7.7 Safety-Related Certifications
VDE
UL
Certified according to DIN V VDE V 0884-11 (VDE V 0884-11):
2017-01, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output (I/O) circuitry.
A failure of the I/O may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power (1)
TS
Maximum safety temperature
(1)
TEST CONDITIONS
MIN
TYP
MAX
RθJA = 84.6°C/W, TJ = 150°C, TA = 25°C,
VDD1 = VDD2 = 5.5 V, see Figure 2
268
RθJA = 84.6°C/W, TJ = 150°C, TA = 25°C,
VDD1 = VDD2 = 3.6 V, AMC1311B-Q1 only, see
Figure 2
410
RθJA = 84.6°C/W, TJ = 150°C, TA = 25°C, see Figure 3
UNIT
mA
1477
mW
150
°C
Input, output, or the sum of input and output power must not exceed this value.
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
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7
ADVANCE INFORMATION
PARAMETER
AMC1311-Q1, AMC1311B-Q1
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7.9 Electrical Characteristics
minimum and maximum specifications of the AMC1311-Q1 apply from TA = –40°C to +125°C, VDD1 = 4.5 V to 5.5 V,
VDD2 = 3.0 V to 5.5 V, VIN = –0.1 V to 2 V, and SHTDN = GND1 = 0 V; minimum and maximum specifications of the
AMC1311B-Q1 apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, VIN = –0.1 V to 2 V, and
SHTDN = GND1 = 0 V; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
AMC1311-Q1, initial, at TA = 25°C,
VIN = GND1
–9.9
±0.4
9.9
AMC1311B-Q1, initial, at TA = 25°C,
VIN = GND1, 4.5 V ≤ VDD1 ≤ 5.5 V
–1.5
±0.4
1.5
AMC1311B-Q1, initial, at TA = 25°C,
VIN = GND1, 3.0 V ≤ VDD1 ≤ 5.5 V (2)
–2.5
–1.1
2.5
UNIT
ANALOG INPUT
Input offset voltage (1)
VOS
ADVANCE INFORMATION
TCVOS
Input offset drift (1)
CIN
Input capacitance (3)
RIN
Input resistance (3)
IIB
Input bias current
TCIIB
Input bias current drift
AMC1311-Q1
AMC1311B-Q1
±20
–15
fIN = 275 kHz
VIN = GND1
–15
±3
15
mV
µV/°C
7
pF
1
GΩ
3.5
15
±10
nA
pA/°C
ANALOG OUTPUT
Nominal gain
EG
Gain error (1)
TCEG
Gain error drift (1)
1
AMC1311-Q1, initial, at TA = 25°C
AMC1311B-Q1, initial, at TA = 25°C
0.4%
1%
–0.3% ±0.05%
–1%
0.3%
AMC1311-Q1
AMC1311B-Q1
Nonlinearity (1)
±30
–45
±5
45
–0.04% ±0.01%
0.04%
Nonlinearity drift
THD
SNR
1
Total harmonic distortion
VIN = 2 V, fIN = 10 kHz, BW = 100 kHz
Output noise
VIN = GND1, BW = 100 kHz
Signal-to-noise ratio
PSRR
Power-supply rejection ratio (4)
VCMout
Common-mode output voltage
VFAILSAFE
Failsafe differential output
voltage
BW
Output bandwidth
ROUT
Output resistance
VIN = 2 V, fIN = 1 kHz, BW = 10 kHz
79
(1)
(2)
(3)
(4)
8
Common-mode transient
immunity
dB
220
μVRMS
82.6
70.9
PSRR vs VDD1, at dc
–65
PSRR vs VDD1, 100-mV and 10-kHz ripple
–65
PSRR vs VDD2, at dc
–85
dB
dB
–70
1.39
VOUTP – VOUTN, SHTDN = high,
or VDD1 ≤ VDD1UV, or VDD1 missing
1.44
1.49
V
–2.6
–2.5
V
AMC1311-Q1
100
220
AMC1311B-Q1
220
275
On VOUTP or VOUTN
< 0.2
Output short-circuit current
CMTI
ppm/°C
–87
VIN = 2 V, fIN = 10 kHz, BW = 100 kHz
PSRR vs VDD2, 100-mV and 10-kHz ripple
ppm/°C
±13
|GND1 – GND2| = 1 kV, AMC1311-Q1
15
30
|GND1 – GND2| = 1 kV, AMC1311B-Q1
75
140
kHz
Ω
mA
kV/µs
The typical value includes one sigma statistical variation.
The typical value is at VDD1 = 3.3 V.
See the Analog Input section for more details.
This parameter is output referred.
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Electrical Characteristics (continued)
minimum and maximum specifications of the AMC1311-Q1 apply from TA = –40°C to +125°C, VDD1 = 4.5 V to 5.5 V,
VDD2 = 3.0 V to 5.5 V, VIN = –0.1 V to 2 V, and SHTDN = GND1 = 0 V; minimum and maximum specifications of the
AMC1311B-Q1 apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, VIN = –0.1 V to 2 V, and
SHTDN = GND1 = 0 V; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT (SHTDN Pin: CMOS Logic Family, CMOS With Schmitt-Trigger)
GND1 ≤ VSHTDN ≤ VDD1
IIN
Input current
CIN
Input capacitance
–70
1
VIH
High-level input voltage
0.7 × VDD1
VDD1 + 0.3
V
VIL
Low-level input voltage
–0.3
0.3 × VDD1
V
2.53
2.7
V
6
8.4
4.5 V ≤ VDD1 ≤ 5.5 V, SHTDN = low
7.1
9.7
SHTDN = high
1.3
3.0 V ≤ VDD2 ≤ 3.6 V
5.3
7.2
4.5 V ≤ VDD2 ≤ 5.5 V
5.9
8.1
5
µA
pF
POWER SUPPLY
VDD1 undervoltage detection
threshold voltage
VDD1 falling
AMC1311B-Q1 only, 3.0 V ≤ VDD1 ≤ 3.6 V,
SHTDN = low
IDD1
IDD2
High-side supply current
Low-side supply current
1.75
µA
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mA
ADVANCE INFORMATION
VDD1UV
mA
9
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7.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tr
Rise time of VOUTP, VOUTN
See Figure 1
1.3
tf
Fall time of VOUTP, VOUTN
See Figure 1
1.3
VIN to VOUTN, VOUTP signal
delay
(50% – 10%)
AMC1311-Q1, unfiltered output, see Figure 1
1.5
2.5
AMC1311B-Q1, unfiltered output, see Figure 1
1.0
1.5
VIN to VOUTN, VOUTP signal
delay
(50% – 50%)
AMC1311-Q1, unfiltered output, see Figure 1
2.1
3.1
AMC1311B-Q1, unfiltered output, see Figure 1
1.6
2.1
VIN to VOUTN, VOUTP signal
delay
(50% – 90%)
AMC1311-Q1, unfiltered output, see Figure 1
3.0
4.0
AMC1311B-Q1, unfiltered output, see Figure 1
2.5
3.0
UNIT
µs
µs
µs
µs
µs
tAS
Analog settling time
VDD1 step to 3.0 V with VDD2 ≥ 3.0 V,
to VOUTP, VOUTN valid, 0.1% settling
50
100
µs
tEN
Device enable time
SHTDN high to low
50
100
µs
tSHTDN
Shutdown time
SHTDN low to high
3
10
µs
ADVANCE INFORMATION
2V
VIN
50%
0V
50% - 50%
50% - 90%
50% - 10%
VOUTP
50%
10%
VCMout
VOUTN
tr
tf
Figure 1. Rise, Fall, and Delay Time Waveforms
10
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7.11
SBAS897 – MARCH 2018
Insulation Characteristics Curves
1600
500
AVDD = DVDD = 3.6 V, AMC1311B-Q1
AVDD = DVDD = 5.5 V
1400
400
300
PS (mW)
IS (mA)
1200
200
1000
800
600
400
100
200
0
0
50
100
TA (°C)
150
200
0
Figure 2. Thermal Derating Curve for Safety-Limiting
Current per VDE
100
TA (qC)
200
D002
Safety Margin Zone: 1800 VRMS , 254 Years
Operating Zone: 1500 VRMS , 135 Years
TDDB Line (<1 PPM Fail Rate)
1E+10
1E+9
150
Figure 3. Thermal Derating Curve for Safety-Limiting
Power per VDE
1E+11
Time to Fail (sec)
50
D001
ADVANCE INFORMATION
0
87.5%
1E+8
1E+7
1E+6
1E+5
1E+4
1E+3
20%
1E+2
9000
9500
8500
8000
7500
7000
6500
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
500
1000
1E+1
Stress Voltage (V RMS)
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1500 VRMS, operating lifetime = 135 years
Figure 4. Reinforced Isolation Capacitor Lifetime Projection
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7.12 Typical Characteristics
70
60
60
50
50
D003
VOS (mV)
ADVANCE INFORMATION
Figure 5. Input Offset Voltage Histogram
Figure 6. Input Offset Voltage Histogram
10
vs VDD1
vs VDD2
2
8
6
1
4
0.5
2
VOS (mV)
1.5
0
-0.5
0
-2
-1
-4
-1.5
-6
-2
-8
-10
-40
-2.5
3
3.25
3.5
3.75
4
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
Device 1
Device 2
Device 3
-25
-10
5
20 35 50 65
Temperature (°C)
D005
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B-Q1 only
80
95
D019
Figure 8. Input Offset Voltage vs Temperature
1.5
2.5
Device 1
Device 2
Device 3
2
1
1.5
1
VOS (mV)
0.5
0
-0.5
0.5
0
-0.5
-1
-1.5
Device 1
Device 2
Device 3
-1
-1.5
-40
110 125
AMC1311-Q1
Figure 7. Input Offset Voltage vs Supply Voltage
VOS (mV)
2.6
VDD1 = 3.3 V, AMC1311B-Q1
2.5
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
-2
110 125
-2.5
-40
-25
D006
VDD1 = 5 V, AMC1311B-Q1
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D007
VDD1 = 3.3 V, AMC1311B-Q1
Figure 9. Input Offset Voltage vs Temperature
12
2.2
1.8
1
0.6
0
0.2
-0.2
1.4
D004
VOS (mV)
VDD1 = 5 V, AMC1311B-Q1
VOS (mV)
-0.6
-2.6
1.6
1.4
1
1.2
0.8
0.6
0.4
0
0.2
-0.2
-0.4
0
-0.6
0
-1
10
-0.8
10
-1.2
20
-1.4
20
-1
30
-1.4
30
40
-1.8
40
-2.2
Devices (%)
70
-1.6
Devices (%)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
Figure 10. Input Offset Voltage vs Temperature
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Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
80
14
70
12
10
50
CIN (pF)
Devices (%)
60
40
30
8
6
20
4
10
2
0
100
15
13
9
11
7
5
3
1
-1
-3
-5
-7
-9
-11
-13
-15
0
1000
fIN (kHz)
D008
TCVOS (PV/qC)
10000
D009
AMC1311B-Q1
15
12
12
9
9
6
6
3
3
0
-3
-6
ADVANCE INFORMATION
Figure 12. Input Capacitance vs Input Signal Frequency
IIB (nA)
IIB (nA)
Figure 11. Input Offset Drift Histogram
15
0
-3
-6
-9
-9
-12
-12
-15
-40
-15
3
3.25
3.5
3.75
4
4.25 4.5
VDD1 (V)
4.75
5
5.25
5.5
-25
-10
5
20 35 50 65
Temperature (°C)
D010
80
95
110 125
D011
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B-Q1 only
Figure 14. Input Bias Current vs Temperature
Figure 13. Input Bias Current
vs High-Side Supply Voltage
60
1
0.8
50
0.4
EG (%)
Devices (%)
0.6
40
30
20
0.2
0
-0.2
-0.4
AMC1311-Q1 vs VDD1
AMC1311-Q1 vs VDD2
AMC1311B-Q1 vs VDD1
AMC1311B-Q1 vs VDD2
-0.6
10
-0.8
EG (%)
AMC1311B-Q1
-1
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
0
3
3.25
D013
3.5
3.75
4
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
D014
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B-Q1 only
Figure 15. Gain Error Histogram
Figure 16. Gain Error vs Supply Voltage
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Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
1
0.3
Device 1
Device 2
Device 3
0.8
0.2
0.6
0.1
0.2
EG (%)
EG (%)
0.4
0
-0.2
0
-0.1
-0.4
-0.6
Device 1
Device 2
Device 3
-0.8
-1
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
-0.2
-0.3
-40
110 125
-25
-10
5
D015
80
95
110 125
D016
AMC1311B-Q1
AMC1311-Q1
Figure 18. Gain Error vs Temperature
Figure 17. Gain Error vs Temperature
40
5
35
0
30
-5
Normalized Gain (dB)
ADVANCE INFORMATION
Devices (%)
20 35 50 65
Temperature (°C)
25
20
15
10
-10
-15
-20
-25
-30
5
AMC1311B-Q1
AMC1311-Q1
-35
-40
45
40
35
30
25
20
15
5
10
-5
-10
-15
-20
-25
-30
-35
-40
-45
0
1
10
D017
TCEG (ppm/qC)
100
1000
fIN (kHz)
D043
D004
AMC1311B-Q1
Figure 19. Gain Error Drift Histogram
Figure 20. Normalized Gain vs Input Frequency
50
5
0
4.5
4
3.5
-100
VOUTx (V)
Output Phase
-50
-150
-200
-250
-400
0.01
2.5
2
1
AMC1311B-Q1
AMC1311-Q1
0.1
0.5
1
10
100
fIN (kHz)
1000
0
-0.1
0.3
D044
Figure 21. Output Phase vs Input Frequency
14
3
1.5
-300
-350
VOUTP
VOUTN
0.7
1.1
1.5
VIN (V)
1.9
2.3
2.7
D018
Figure 22. Output Voltage vs Input Voltage
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Typical Characteristics (continued)
0.04
0.04
0.03
0.03
0.02
0.02
Nonlinearity (%)
Nonlinearity (%)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
0.01
0
-0.01
0.01
0
-0.01
-0.02
-0.02
-0.03
-0.03
-0.04
-0.2
vs VDD1
vs VDD2
-0.04
0
0.2
0.4
0.6
0.8
1
VIN (V)
1.2
1.4
1.6
1.8
3
2
3.25
3.5
3.75
4
D020
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
D021
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B-Q1 only
Figure 24. Nonlinearity vs Supply Voltage
ADVANCE INFORMATION
Figure 23. Nonlinearity vs Input Voltage
-70
0.04
0.03
vs VDD1
vs VDD2
-75
-80
0.01
THD (dB)
Nonlinearity (%)
0.02
0
-0.01
-85
-90
-0.02
Device 1
Device 2
Device 3
-0.03
-0.04
-40
-95
-100
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
3
110 125
3.25
3.5
3.75
D022
4
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
D023
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B-Q1 only
Figure 25. Nonlinearity vs Temperature
Figure 26. Total Harmonic Distortion vs Supply Voltage
-70
1000
Noise Density (PV/—Hz)
-75
THD (dB)
-80
-85
-90
10
1
Device 1
Device 2
Device 3
-95
-100
-40
100
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
0.1
0.1
D024
Figure 27. Total Harmonic Distortion vs Temperature
1
10
Frequency (kHz)
100
1000
D025
Figure 28. Input-Referred Noise Density vs Frequency
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Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
80
72.5
70
65
75
SNR (dB)
62.5
SNR (dB)
vs VDD1
vs VDD2
77.5
67.5
60
57.5
55
52.5
50
72.5
70
67.5
65
47.5
62.5
45
42.5
60
0
0.2
0.4
0.6
0.8
1
1.2
VIN (V)
1.4
1.6
1.8
2
3
3.25
3.5
3.75
D026
4
4.25 4.5
VDDx (V)
4.75
5
5.25
5.5
D027
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B-Q1 only
Figure 29. Signal-to-Noise Ratio vs Input Voltage
Figure 30. Signal-to-Noise Ratio vs Supply Voltage
ADVANCE INFORMATION
80
0
77.5
-20
-40
72.5
PSRR (dB)
SNR (dB)
75
70
67.5
-60
-80
65
Device 1
Device 2
Device 3
62.5
60
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
-100
VDD1
VDD2
-120
0.1
110 125
1
10
100
Ripple Frequency (kHz)
D028
1000
D029
100-mV ripple
1.49
1.49
1.48
1.48
1.47
1.47
1.46
1.46
1.45
1.45
1.44
1.43
1.44
1.43
1.42
1.42
1.41
1.41
1.4
1.4
1.39
3
3.25
3.5
3.75
4
4.25 4.5
VDD2 (V)
4.75
5
5.25
5.5
1.39
-40
-25
D031
Figure 33. Output Common-Mode Voltage
vs Low-Side Supply Voltage
16
Figure 32. Power-Supply Rejection Ratio
vs Ripple Frequency
VCMout (V)
VCMout (V)
Figure 31. Signal-to-Noise Ratio vs Temperature
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D032
Figure 34. Output Common-Mode Voltage vs Temperature
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Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
300
300
AMC1311B-Q1
AMC1311-Q1
280
280
270
270
260
260
240
250
240
230
230
220
220
210
210
200
3.25
3.5
3.75
4
4.25 4.5
VDD2 (V)
4.75
5
5.25
200
-40
5.5
Figure 35. Output Bandwidth vs Low-Side Supply Voltage
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D034
Figure 36. Output Bandwidth vs Temperature
8.5
8.5
8
8
7.5
7.5
7
7
6.5
IDDx (mA)
IDDx (mA)
-25
D033
ADVANCE INFORMATION
250
3
AMC1311B-Q1
AMC1311-Q1
290
BW (kHz)
BW (kHz)
290
6
5.5
5
6.5
6
5.5
5
4.5
4.5
IDD1 vs VDD1
IDD2 vs VDD2
4
3.5
-40
3.5
3
3.25
3.5
3.75
4
4.25 4.5
VDDx (V)
4.75
5
5.25
IDD1
IDD2
4
5.5
-25
-10
5
D035
20 35 50 65
Temperature (°C)
80
95
110 125
D036
3.0 V ≤ VDD1 < 4.5 V for the AMC1311B-Q1 only
Figure 38. Supply Current vs Temperature
4
3.5
3.5
3
3
2.5
2.5
tr/tf (Ps)
tr / tf (Ps)
Figure 37. Supply Current vs Supply Voltage
4
2
2
1.5
1.5
1
1
0.5
0.5
0
3
3.25
3.5
3.75
4
4.25 4.5
VDD2 (V)
4.75
5
5.25
5.5
0
-40
-25
D037
Figure 39. Output Rise and Fall Time vs
Low-Side Supply Voltage
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D038
Figure 40. Output Rise and Fall Time vs Temperature
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Typical Characteristics (continued)
3.8
3.8
3.4
3.4
3
3
Signal Delay (Ps)
Signal Delay (Ps)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
2.6
2.2
1.8
1.4
1
2.6
2.2
1.8
1.4
1
50% - 90%
50% - 50%
50% - 10%
0.6
50% - 90%
50% - 50%
50% - 10%
0.6
0.2
0.2
3
3.25
3.5
3.75
4
4.25 4.5
VDD2 (V)
4.75
5
5.25
5.5
3
3.25
3.5
3.75
D039
AMC1311-Q1
4.75
ADVANCE INFORMATION
3.8
3.8
3.4
3.4
Signal Delay (Ps)
2.2
1.8
1.4
1
0.6
-10
5
20 35 50 65
Temperature (°C)
5.5
50% - 90%
50% - 50%
50% - 10%
80
95
2.6
2.2
1.8
1.4
1
50% - 90%
50% - 50%
50% - 10%
-25
5.25
D040
3
2.6
0.2
-40
5
Figure 42. VIN to VOUTP, VOUTN Signal Delay
vs Low-Side Supply Voltage
3
Signal Delay (Ps)
4.25 4.5
VDD2 (V)
AMC1311B-Q1
Figure 41. VIN to VOUTP, VOUTN Signal Delay
vs Low-Side Supply Voltage
0.6
110 125
0.2
-40
-25
D041
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D042
AMC1311B-Q1
AMC1311-Q1
Figure 43. VIN to VOUTP, VOUTN Signal Delay vs
Temperature
18
4
Figure 44. VIN to VOUTP, VOUTN Signal Delay vs
Temperature
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8 Detailed Description
8.1 Overview
The AMC1311-Q1 is a precision, isolated amplifier with a high input-impedance and wide input-voltage range.
The input stage of the device drives a second-order, delta-sigma (ΔΣ) modulator. The modulator uses the internal
voltage reference and clock generator to convert the analog input signal to a digital bitstream. The drivers
(termed TX in the Functional Block Diagram section) transfer the output of the modulator across the isolation
barrier that separates the high-side and low-side voltage domains. The received bitstream and clock are
synchronized and processed by a fourth-order analog filter on the low-side and presented as a differential analog
output.
The SiO2-based, double-capacitive isolation barrier supports a high level of magnetic field immunity, as described
in ISO72x Digital Isolator Magnetic-Field Immunity. The digital modulation used in the AMC1311-Q1 and the
isolation barrier characteristics result in high reliability and common-mode transient immunity.
8.2 Functional Block Diagram
VDD1
Detection
Isolation
Barrier
Band-Gap
Reference
VIN
Data
û -Modulator
CLK
SHTDN
TX
Band-Gap
Reference
Retiming and
4th-Order
Active
Low-Pass
Filter
RX
RX
ADVANCE INFORMATION
VDD2
VDD1
TX
VOUTP
VOUTN
Oscillator
AMC1311-Q1
GND1
GND2
8.3 Feature Description
8.3.1 Analog Input
The input stage of the AMC1311-Q1 feeds a second-order, switched-capacitor, feed-forward ΔΣ modulator. The
modulator converts the analog signal into a bitstream that is transferred over the isolation barrier, as described in
the Isolation Channel Signal Transmission section. The high-impedance, and low bias-current input of the
AMC1311-Q1 makes the device suitable for isolated voltage sensing applications. Figure 45 depicts the
equivalent input structure of the AMC1311-Q1 with the relevant components.
VDD1
5k
VIN
2 pF
5 pF
1 *Ÿ
3.5 nA
GND1
Figure 45. Equivalent Analog Input Circuit
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Feature Description (continued)
There are two restrictions on the analog input signal, VIN. First, if the input voltage VIN exceeds the voltage of
6.5 V, the input current must be limited to 10 mA because the device input electrostatic discharge (ESD)
protection turns on. In addition, the linearity and noise performance of the device are ensured only when the
analog input voltage remains within the specified linear full-scale range (VFSR).
8.3.2 Isolation Channel Signal Transmission
The AMC1311-Q1 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream
across the SiO2-based isolation barrier. As shown in Figure 46, the transmitter modulates the bitstream at TX IN
with an internally-generated, high-frequency carrier across the isolation barrier to represent a digital one and
does not send a signal to represent the digital zero. The nominal frequency of the carrier used inside the
AMC1311-Q1 is 480 MHz.
The receiver demodulates the signal after advanced signal conditioning and produces the output. The AMC1311Q1 also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions caused by the high-frequency carrier and IO buffer switching.
Transmitter
Receiver
ADVANCE INFORMATION
OOK
Modulation
TX IN
TX Signal
Conditioning
SiO2-Based
Capacitive
Reinforced
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Oscillator
Figure 46. Block Diagram of an Isolation Channel
Figure 47 shows the concept of the OOK scheme.
TX IN
Carrier Signal Across
the Isolation Barrier
RX OUT
Figure 47. OOK-Based Modulation Scheme
20
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Feature Description (continued)
8.3.3 Fail-Safe Output
The AMC1311-Q1 offers a fail-safe output that simplifies diagnostics on system level. The fail-safe output is
active in three cases:
• When the high-side supply VDD1 of the AMC1311-Q1 device is missing
• When the high-side supply VDD1 falls under the VDD1UV undervoltage threshold level or
• When the SHTDN pin is pulled high
Figure 48 shows the fail-safe output of the AMC1311-Q1 that is a negative differential output voltage that does
not occur under normal device operation. As a reference value for the fail-safe detection on a system level, use
the VFAILSAFE voltage as specified in the Electrical Characteristics table.
3.5
VOUTP
VOUTN
3
VFSR
VOUTx (V)
VFAILSAFE
2
VCLIPPING
1.5
1
0.5
0
-0.1
0.5
1
1.5
2
VIN (V)
2.5
3
3.5
Figure 48. AMC1311-Q1 Output Behavior
8.4 Device Functional Modes
The AMC1311-Q1 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The very low input bias current, ac and dc errors, and temperature drift make the AMC1311-Q1 a highperformance solution for automotive applications where voltage measurement with high common-mode levels is
required.
9.2 Typical Application
Isolated amplifiers are widely used in automotive applications such as traction inverters, on-board chargers, and
dc/dc converters. The input structure of the AMC1311-Q1 is tailored for isolated voltage sensing using resistive
dividers to reduce the high common-mode voltage.
ADVANCE INFORMATION
Figure 49 depicts a typical use of the AMC1311-Q1 for dc bus voltage sensing in a traction inverter application.
Phase current measurement is accomplished through the shunt resistors, RSHUNT (in this case, two-pin shunts)
and the AMC1301-Q1 isolated amplifiers that are optimized for isolated current sensing. The high-impedance
input and the high common-mode transient immunity of the AMC1311-Q1 ensure reliable and accurate operation
even in high-noise environments.
+VBUS
Motor
ICROSS
R1
RSHUNT
L1
R2
RSHUNT
L3
RSHUNT
L2
RSENSE
3.3 V
AMC1301-Q1
VDD1
VINP
VOUTP
VINN
VOUTN
GND1
-VBUS
3.3 V
AMC1301-Q1
VDD1
3.3 V
AMC1301-Q1
VDD1
3.3 V
AMC1311B-Q1
VDD1
GND2
3.3 V
VOUTP
VINN
VOUTN
Analog
Filter
To ADC
GND2
VDD2
VINP
VOUTP
VINN
VOUTN
GND1
To ADC
VDD2
VINP
GND1
Analog
Filter
Analog
Filter
To ADC
GND2
VDD2
VIN
VOUTP
SHTDN
VOUTN
GND1
3.3 V
3.3 V
3.3 V
VDD2
Analog
Filter
To ADC
GND2
Figure 49. Using the AMC1311B-Q1 for DC Bus Voltage Sensing in Traction Inverters
22
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Typical Application (continued)
9.2.1 Design Requirements
Table 1 lists the parameters for this typical application.
Table 1. Design Requirements
PARAMETER
VALUE
High-side supply voltage
3.3 V or 5 V
Low-side supply voltage
3.3 V or 5 V
Voltage drop across the sensing resistor for a linear response
2 V (maximum)
Current through the resistive divider, ICROSS
0.1 mA (maximum)
Signal delay (50% VIN to 90% VOUTP, VOUTN)
3 µs (maximum)
9.2.2 Detailed Design Procedure
Consider the following two restrictions to choose the proper value of the shunt resistor RSENSE:
• The voltage drop on RSENSE caused by the nominal voltage range of the system must not exceed the
recommended input voltage range: VSENSE ≤ VFSR
• The voltage drop on RSENSE caused by the maximum allowed system overvoltage must not exceed the input
voltage that causes a clipping output: VSENSE ≤ VClipping
Table 2 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 600 V and 800 V
on the dc bus.
Table 2. Resistor Value Examples
PARAMETER
600-V DC BUS
800-V DC Bus
Resistive divider resistor R1
3.01 MΩ
4.22 MΩ
Resistive divider resistor R2
3.01 MΩ
4.22 MΩ
Sense resistor RSENSE
20 kΩ
21 kΩ
Resulting current through resistive divider ICROSS
99.3 µA
94.5 µA
Resulting voltage drop on sense resistor VSENSE
1.987 V
1.986 V
For systems using single-ended input ADCs, Figure 50 shows an example of a TLV313-Q1-based signal
conversion and filter circuit as used on the AMC1311EVM. Tailor the bandwidth of this filter stage to the
bandwidth requirement of the system and use NP0-type capacitors for best performance.
AMC1311-Q1
VDD1
VCMADC
VDD2
TLV313-Q1
VIN
VOUTP
+
SHTDN
VOUTN
±
To ADC
GND1
GND2
GND2
Figure 50. Connecting the AMC1311-Q1 Output to Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see 18Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data Acquisition
Block (DAQ) Optimized for Lowest Power, available for download at www.ti.com.
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ADVANCE INFORMATION
Use Ohm's Law to calculate the minimum total resistance of the resistive divider to limit the cross current to the
desired value (RTOTAL = VBUS / ICROSS) and the required sense resistor value to be connected to the AMC1311Q1 input: RSENSE = VFSR / ICROSS.
AMC1311-Q1, AMC1311B-Q1
SBAS897 – MARCH 2018
www.ti.com
9.2.3 Application Curve
In traction inverter applications, the power switches must be protected in case of an overvoltage condition. To
allow for fast system power-off, a low delay caused by the isolated amplifier is required. Figure 51 shows the
typical full-scale step response of the AMC1311-Q1. Consider the delay of the required window comparator and
the MCU to calculate the overall response time of the system.
VOUTN
VCMout
ADVANCE INFORMATION
VOUTP
Figure 51. Step Response of the AMC1311B-Q1
9.3 Do's and Don'ts
Do not leave the analog input VIN of the AMC1311-Q1 unconnected (floating) when the device is powered up on
the high-side. If the device input is left floating, the bias current may generate a negative input voltage that
exceeds the specified input voltage range and the output of the device is invalid.
24
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10 Power Supply Recommendations
In a typical traction inverter application, the high-side power supply (VDD1) for the AMC1311-Q1 is generated
from the low-side supply (VDD2) of the device by an isolated dc/dc converter circuit. A low-cost solution is based
on the push-pull driver SN6501-Q1 and a transformer that supports the desired isolation voltage ratings. TI
recommends using a low-ESR decoupling capacitor of 0.1 µF and an additional capacitor of minimum 1 µF for
both supplies of the AMC1311-Q1. Place these decoupling capacitors as close as possible to the AMC1311-Q1
power-supply pins to minimize supply current loops and electromagnetic emissions.
The AMC1311-Q1 does not require any specific power up sequencing. Consider the analog settling time tAS as
specified in the Switching Characteristics table after ramp up of the VDD1 high-side supply.
SHTDN
1 …F
0.1 …F
VDD1
GND1
VOUTP
VDD2
VOUTN
VDD2
0.1 …F
GND2
GND2
GND1
VDD2
TPS7B6950-Q1
OUT
VDD1
VDD2
SN6501-Q1
IN
0.1 …F
10 …F
1 …F
ADVANCE INFORMATION
VIN
Reinforced Isolation
AMC1311-Q1
VDD1
Detection
10 …F
20 V
D1
VCC
D2
GND2
0.1 …F
GND
GND1
20 V
10 …F
GND2
GND1
GND2
Figure 52. SN6501-Q1-Based, High-Side Power Supply
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AMC1311-Q1, AMC1311B-Q1
SBAS897 – MARCH 2018
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11 Layout
11.1 Layout Guidelines
For best performance, place the smaller 0.1-µF decoupling capacitors (C1 and C6) as close as possible to the
AMC1311-Q1 power-supply pins, followed by the additional C2 and C5 capacitors with a minimum value of 1 µF.
The resistors and capacitors used for the analog input (C3) and output filters (R5, R10, and C13) are placed next
to the decoupling capacitors. Use 1206-size, SMD-type, ceramic decoupling capacitors and route the traces to
the VIN and SHTDN pins underneath. Connect the supply voltage sources in a way that allows the supply
current to flow through the pads of the decoupling capacitors before powering the AMC1311-Q1.
Figure 53 shows this approach as implemented on the AMC1311EVM. Capacitors C5 and C6 decouple the highside supply VDD1 while capacitors C1 and C2 are used to support the low-side supply VDD2 of the AMC1311Q1.
11.2 Layout Example
ADVANCE INFORMATION
Figure 53. Recommended Layout of the AMC1311-Q1
26
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
For related documentation, see the following:
• Isolation Glossary
• ADC121S101x-Q1 Single-Channel, 0.5 to 1-Msps,12-Bit Analog-to-Digital Converter
• Semiconductor and IC Package Thermal Metrics
• ISO72x Digital Isolator Magnetic-Field Immunity
• AMC1301-Q1 Precision, ±250-mV Input, 3-μs Delay, Reinforced Isolated Amplifier
• TLV313-Q1 Low-Power, Rail-to-Rail In/Out, 750-µV Typical Offset, 1-MHz Operational Amplifier for CostSensitive Systems
• AMC1311EVM Users Guide
• 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
• 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power
• SN6501-Q1 Transformer Driver for Isolated Power Supplies
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
AMC1311-Q1
Click here
Click here
Click here
Click here
Click here
AMC1311B-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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27
ADVANCE INFORMATION
12.1.2 Related Documentation
AMC1311-Q1, AMC1311B-Q1
SBAS897 – MARCH 2018
www.ti.com
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
ADVANCE INFORMATION
28
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Product Folder Links: AMC1311-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jun-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AMC1311BQDWVQ1
PREVIEW
SOIC
DWV
8
64
TBD
Call TI
Call TI
-40 to 125
1311BQ1
AMC1311BQDWVRQ1
PREVIEW
SOIC
DWV
8
1000
TBD
Call TI
Call TI
-40 to 125
1311BQ1
AMC1311QDWVQ1
PREVIEW
SOIC
DWV
8
64
TBD
Call TI
Call TI
-40 to 125
1311Q1
AMC1311QDWVRQ1
PREVIEW
SOIC
DWV
8
1000
TBD
Call TI
Call TI
-40 to 125
1311Q1
PAMC1311BQDWVRQ1
ACTIVE
SOIC
DWV
8
1000
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jun-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AMC1311-Q1 :
• Catalog: AMC1311
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
SCALE 2.000
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.95
5.75
NOTE 3
4
5
0.51
0.31
0.25
C A
8X
A
7.6
7.4
NOTE 4
B
B
2.8 MAX
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0 -8
0.46
0.36
1.0
0.5
(2)
DETAIL A
TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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