ON MC100LVEL16DTG 3.3v ecl differential receiver Datasheet

MC100LVEL16
3.3V ECL Differential
Receiver
Description
The MC100LVEL16 is a differential receiver. The device is
functionally equivalent to the EL16 device, operating from a 3.3 V
supply. The LVEL16 exhibits a wider VIHCMR range than its EL16
counterpart. With output transition times and propagation delays
comparable to the EL16 the LVEL16 is ideally suited for interfacing
with high frequency sources at 3.3 V supplies.
Under open input conditions, the Q input will be pulled down to VEE
and the Q input will be biased to VCC/2. This condition will force the
Q output low.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
•
•
•
•
•
•
•
•
300 ps Propagation Delay
High Bandwidth Output Transitions
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −3.8 V
Internal Input Pulldown Resistors on D, Pullup and Pulldown
Resistors on D
Q Output will Default LOW with Inputs Open or at VEE
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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MARKING
DIAGRAMS*
8
8
KVL16
ALYW
G
1
SOIC−8
D SUFFIX
CASE 751
1
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
KV16
ALYWG
G
1
1
4BMG
G
DFN8
MN SUFFIX
CASE 506AA
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 7
1
Publication Order Number:
MC100LVEL16/D
MC100LVEL16
Table 1. PIN DESCRIPTION
NC
1
8
VCC
D
2
7
Q
D
3
6
Q
VBB
4
5
VEE
PIN
FUNCTION
D, D
Q, Q
VBB
VCC
VEE
NC
EP
ECL Data Inputs
ECL Data Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
Figure 1. Logic Diagram and Pinout Assignment
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
75 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time out of Drypack,
Pb−Free Packages (Note 1)
Flammability Rating
SOIC−8
TSSOP−8
DFN8
Oxygen Index: 28 to 34
Transistor Count
> 4 KV
> 400 V
> 2 kV
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
79
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Refer to Application Note AND8003/D for additional information.
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2
MC100LVEL16
Table 3. MAXIMUM RATINGS
Rating
Unit
VCC
Symbol
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
SO−8
SO−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SO−8
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
qJC
Thermal Resistance (Junction−to−Case)
35 to 40
°C/W
Pb
Pb−Free
(Note 2)
Condition 2
VI VCC
VI VEE
DFN8
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
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MC100LVEL16
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 3)
−40°C
Typ
Max
17
23
2215
2295
2420
1470
1605
1745
2135
2420
Input LOW Voltage (Single−Ended)
1490
VBB
Output Voltage Reference
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
Vpp < 500 mV
Vpp y 500 mV
Symbol
Min
25°C
Characteristic
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
VOL
Output LOW Voltage (Note 4)
VIH
Input HIGH Voltage (Single−Ended)
VIL
IIH
Input HIGH Current
IIL
Input LOW Current
Min
Typ
Max
17
23
Typ
Max
Unit
18
24
mA
2275
2345
2420
1490
1595
1680
2275
2345
2420
mV
1490
1595
1680
mV
2135
2420
2135
2420
mV
1825
1490
1825
1490
1825
mV
1.92
2.04
1.92
2.04
1.92
2.04
V
1.2
2.9
1.1
2.9
1.1
2.9
V
1.5
2.9
1.4
2.9
1.4
2.9
V
150
mA
150
D
D
85°C
0.5
−600
Min
150
0.5
−600
mA
mA
0.5
−600
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2 V.
5. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 6)
−40°C
Symbol
Min
Characteristic
25°C
Typ
Max
17
23
Min
85°C
Typ
Max
17
23
Min
Typ
Max
Unit
18
24
mA
−955
−880
mV
−1705
−1620
mV
−1165
−880
mV
−1475
−1810
−1475
mV
−1.38
−1.26
−1.38
−1.26
V
−0.4
−2.2
−0.4
−2.2
−0.4
V
−0.4
−1.9
−0.4
−1.9
−0.4
V
150
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7)
−1085
−1005
−880
−1025
−955
−880
−1025
VOL
Output LOW Voltage (Note 7)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
VIL
Input LOW Voltage (Single−Ended)
−1810
−1475
−1810
VBB
Output Voltage Reference
−1.38
−1.26
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
Vpp < 500 mV
Vpp y 500 mV
−2.1
−1.8
IIH
Input HIGH Current
IIL
Input LOW Current
150
D
D
0.5
−600
150
0.5
−600
0.5
−600
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
7. Outputs are terminated through a 50 W resistor to VCC − 2 V.
8. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
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MC100LVEL16
Table 6. AC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V or VCC= 0.0 V; VEE= −3.3 V (Note 9)
−40°C
Symbol
Min
Characteristic
fmax
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay to Output
tSKEW
Duty Cycle Skew (Differential) (Note 10)
tJITTER
Random Clock Jitter (RMS)
VPP
Input Swing (Note 11)
150
tr
tf
Output Rise/Fall Times Q
(20% − 80%)
120
Differential
Single−Ended
25°C
Typ
Max
Min
1.75
85°C
Typ
Max
Min
1.75
Typ
Max
1.75
Unit
GHz
ps
150
100
275
275
400
450
5
30
225
175
0.7
300
300
375
425
5
20
240
190
0.7
1000
150
320
120
220
315
315
390
440
5
20
0.7
220
1000
150
320
120
220
ps
ps
1000
mV
320
ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. VEE can vary ±0.3 V.
10. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
11. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
Zo = 50 W
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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MC100LVEL16
ORDERING INFORMATION
Package
Shipping†
MC100LVEL16DG
SO−8
(Pb−Free)
98 Units / Rail
MC100LVEL16DR2G
SO−8
(Pb−Free)
2500 Tape & Reel
MC100LVEL16DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100LVEL16DTR2G
TSSOP−8
(Pb−Free)
2500 Tape & Reel
MC100LVEL16MNR4G
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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6
MC100LVEL16
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
Y
M
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC100LVEL16
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
K REF
0.10 (0.004)
S
2X
L/2
8
1
PIN 1
IDENT
S
T U
S
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
5
0.25 (0.010)
B
−U−
L
0.15 (0.006) T U
M
M
4
A
−V−
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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8
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC100LVEL16
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE E
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
L1
PIN ONE
REFERENCE
0.10 C
2X
0.10 C
2X
ÇÇ
ÇÇ
0.10 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉ
ÉÉ
EXPOSED Cu
TOP VIEW
A
DETAIL B
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTION
0.08 C
(A3)
NOTE 4
A1
C
SIDE VIEW
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
8X
DETAIL A
D2
1
8X
1.30
L
8
4
5
8X
e/2
e
0.50
PACKAGE
OUTLINE
E2
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.30 REF
0.25
0.35
−−−
0.10
0.90
2.30
1
b
0.10 C A B
0.05 C
8X
0.30
NOTE 3
0.50
PITCH
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
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MC100LVEL16/D