Datasheet The 24bit Audio CODEC series Monaural Audio CODEC with Touch Panel Interface BU26154MUV General Description Key Specifications BU26154 is a low-power compact audio CODEC. BU26154 also incorporates touch panel interface and Cap-Less headphones amplifier, speaker amplifier which is most suitable for digital still cameras, electronic dictionaries. BU26154 has built-in voltage regulator for the stability of CODEC characteristic that is sensitive to the outside noise. Speaker amplifier that can change AB / D Class. Therefore, when the interference including the FM radio influences it, BU26154 can prevent interference by operating AB grade. As digital code processing, it is equipped with the high-pass filter as the noise cut use of the specific frequency band, Notch filter 2 and the Equalizer of 5 bands and P Bass+, Noise gate, and flexible sound quality effect processing is possible. HVDD Power Supply: SPVDD Power Supply: CPDD Power Supply: TVDD Power Supply: MIC-ADC SNR: DAC-SP SNR: DAC-HP SNR: ■ 2.7V to 3.6V 2.7V to 5.5V 2.7V to 3.6V 2.7V to 3.6V 92dB(Typ) 95dB (Typ) 93dB (Typ) W (Typ) x D (Typ) x H (Max) 6.00mm x 6.00mm x 1.00mm Package(s) VQFN040V6060 Features ■ ■ ■ ■ Various sound processing functions 2 P Bass+ Noise gate Fast release ALC 5-band Equalizer/Notch Filter High PSRR is attained by built-in regulator Speaker amplifier can be switched to AB class and D class. Touch panel interface. VQFN040V6060 Applications ■ ■ ■ ■ ■ Electronic Dictionary Digital Still Camera Digital Single-lens Reflex Camera Digital Mirror-less Camera Digital Video Camera, others Typical Application Circuit(s) VMID HVDD1 HGND2 REGOUT HGND1 HVDD REGOUT IOVDD Bias MBIASCAP LDO MICBIAS REGOUT CPU I/F CSB/SCL IO SDATA/SDA REGOUT REGOUT SCLK REGOUT IOVDD MIN1 ADC PGA MIN2 RESET SPVDD Class AB or Class D SPGND RESETB IO REGOUT IOVDD SPVDD SPOUT+ SP VOL SPOUTHPVDD HPL HP HPR CPVDD HPVDD CPP CPN SAI_LRCLK IO SAI_BCLK SAI_SDOUT SAI_SDIN REGOUT HP DAC REGOUT IOVDD HPVSS LDO MCLKI TVDD HPVDD CHARGE PUMP Serial Audio InterFac e DAC HPVSS HPVDD HPCOM ALC Filter Sound Effect REGOUT VOL CLOCK PLL TSTO TOUCH PANEL I/F HPVSS HPVSS IO CPGND XP XN YP YN TVDD TGND IRQB PLLC Figure 1. Block Diagram 〇Product structure : Silicon monolithic integrated circuit .www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 14 • 001 〇This product has no designed protection against radioactive rays 1/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Pin Configuration(s) IRQB SAI_SDOUT SAI_SDIN SAI_BCLK SAI_LRCLK SCLK/SAD SDATA/SDA CSB/SCL MCLKI TSTO Top view 30 29 28 27 26 25 24 23 22 21 18 REGOUT YN 34 17 HVDD TGND 35 16 NC TVDD 36 15 HGND1 HPCOM 37 14 HGND2 CPVDD 38 13 MIN2 CPP 39 12 MIN1 HPR 40 11 MBIASCAP 1 2 3 4 5 6 7 8 9 10 VMID 33 SPGND XN SPOUT- PLLC SPOUT+ 19 SPVDD 32 CPN XP HPVSS RESETB CPGND 20 HPVDD 31 HPL YP Figure 2. Pin Configuration(s) Pin Description(s) No Name I/O Power 17 HVDD P - 6 SPVDD P - 38 CPVDD P - 16 N.C - - 36 TVDD P - 15 HGND1 P - 14 HGND2 P - 9 SPGND P - 3 CPGND P - 35 TGND P - 18 REGOUT O HVDD www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 Function High voltage power supply pin A capacitor is connected between HVDD and HGND1. Speaker power supply pin A capacitor is connected between SPVDD and SPGND. Voltage power supply pin for charge pump A capacitor is connected between CPVDD and CPGND. A no connect pin. Voltage power supply for the touch panel Please connect a capacitor between TVDD and TGND. High voltage ground 1 It is used on the same voltage as HGND2, SPGND, CPGND, and TGND. High voltage ground 2 It is used on the same voltage as HGND1, SPGND, CPGND, and TGND. Ground pin for Speaker It is used on the same voltage as HGND1, HGND2, CPGND, and TGND. Ground pin for charge pump It is used on the same voltage as HGND1, HGND2, SPGND, and TGND. Ground pin for touch panel interface It is used on the same voltage as HGND1, HGND2, CPGND, and SPGND. Regulator output A capacitor is connected between REGOUT and HGND1. Please connect as close as possible to the chip. 2/86 Reset (Note1) No use (Note3) - - - - - - - - - - - - - - - - - - - - HGND2 - TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV 2 HPVDD O CPVDD 4 HPVSS O CPVDD 22 21 MCLKI TSTO I O HVDD HVDD 20 RESETB I HVDD 24 SDATA /SDA IO HVDD 25 SCLK /SAD I HVDD 23 CSB /SCL I HVDD 26 27 28 29 SAI_LRCLK SAI_BCLK SAI_SDIN SAI_SDOUT IO IO I O HVDD HVDD HVDD HVDD 30 IRQB O HVDD 10 VMID O REGOUT 11 MBIASCAP O HVDD 12 MIN1 I REGOUT 13 MIN2 I REGOUT 8 7 1 40 39 5 SPOUTSPOUT+ HPL HPR CPP CPN O O O O O O SPVDD SPVDD SPVDD SPVDD CPVDD CPVDD 19 PLLC O HVDD 31 32 33 34 37 YP XP XN YN HPCOM O O O O I TVDD TVDD TVDD TVDD - A positive side voltage output pin for the headphones driver. A capacitor is connected between HPVDD and CPGND. Please connect as close as possible to the chip. A negative side voltage output pin for the headphones driver. A capacitor is connected between HPVSS and CPGND. Please connect as close as possible to the chip. Master Clock pin Output pin for test-mode. Make it open. Reset pin "L" level: Reset enables. "H" level: Reset disable. 3 wire interface: data input output pin It is indicated as SDATA. 2 wire interface: data input output pin(Note 1) It is indicated as SDA. 3 wire interface: Serial clock input pin It is indicated as SCLK. 2 wire interface: Slave address select input pin. It is indicated as SAD. SAD pin = "L" level slave address is "0011010" SAD pin = "H" level slave address is "0011011" 3 wire interface: chip select input pin It is indicated as CSB. 2 wire interface: Serial clock input pin *1 It is indicated as SCL. SAI LR clock input/output pin SAI bit clock input/output pin SAI serial data input pin SAI serial data output pin An interrupt output terminal. When an interrupt occurs, chip outputs "L". Analog reference voltage pin A capacitor is connected between VMID and HGND2. Microphone bias voltage output pin A capacitor is connected between HGND2. Please connect as close as possible to the chip. Analog microphone input 1 Single-end and differential can be chosen. When differential is chosen, it connects with microphone + pin. Analog microphone input 2 Single-end and differential can be chosen. When differential is chosen, it connects with microphone - pin. speaker output - pin speaker output + pin Headphones output Lch terminal Headphones output Rch terminal Charge pump flying capacitor, positive side output pin Charge pump flying capacitor, negative side output pin PLL filter pin When clock of the MCLKI pin input is used, make it open. When clock of the SAI_BCLK pin input is used, it is necessary to connect resistors and a capacitor. YP pin for the touch panel interface XP pin for the touch panel interface XN pin for the touch panel interface YN pin for the touch panel interface Headphones amplifier common pin (Note 1) In case of 2 wire serial, if this pin is used with external pull-up resistor, it possibly gets noise from power. in the noisy environment. (Note 2) At the time of power down, in HPVDD and HPVSS, is short-circuited. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 3/86 CPGND (Note 2) CPGND (Note 2) (input) HGND1 HGND1 Open (input) - (input) - (input) HGND1 (input) - (input) (input) (input) HGND1 HGND1 HGND1 HGND1 Open HGND1 Open HGND2 - HGND2 Open Hi-Z Open Hi-Z Open SPGND SPGND CPGND CPGND Hi-Z Hi-Z Open Open Open Open Open Open HGND2 Open Hi-Z Hi-Z Hi-Z Hi-Z (input) Open Open Open Open - Therefore, tamper noise design is required TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Description of Block(s) 1μF 1μF 1μF CPVDD HVDD TVDD option 2.2kohm MBIASCAP 4.7μF 0.47μF 0.47μF MIN1 MIN2 SPOUT+ SPOUT- BU26154 option HPR VMID XN 2.2μF Touch Screen YP CPP CPN HPVSS 1μF CPU and DSP XP HPVDD 2.2μF CSB/SCL SDATA/SDA SCLK RESETB IRQB SAI_LRCLK SAI_BCLK SAI_SDOUT SAI_SDIN MCLKI option REGOUT 2.2μF SPVDD PLLC HPL 1μF 1μF YN HPCOM TSTO CPGND HGND2HGND1 TGND SPGND Open option Figure 3. BU26154 Application circuit www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 4/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Absolute Maximum Ratings (Ta = 25°C) (HGND1=HGND2=SPGND=CPGND=TGND=0V) Parameter Symbol Condition Rating Unit HVDD - -0.3 to 4.5 V SPVDD Supply Voltage SPVDD - -0.3 to 7.0 V CPVDD Supply Voltage CPVDD - -0.3 to 4.5 V VIN MCLKI, SAI_LRCLK, SAI_BCLK, SAI_SDIN, SDATA/SDA, SCLK. CSB/SCL pins MIN1, MIN2 pins -0.3 to HVDD+0.3 V -0.3 to REGOUT+0.3 V - -55 to +150 ℃ (Note 1) 0.80 W Ta=25°C (Note 2) 3.01 W HVDD Supply Voltage Input Voltage Storage Temperature Tstg Ta=25°C (Note 1) Power Dissipation Pd Output Current 1 IOSP SPOUT+, SPOUT- pins -560 to +560 mA Output Current 2 IOHP HPL, HPR pins -100 to +100 mA Output Current 3 IOCP HPVSS,HPVDD,CP,CN pin -500 to +500 mA Output Current 4 IOREGO REGOUT pin -30 to 0 mA IOO Except SPOUT+,SPOUT-, HPL,HPR, REGOUT,HPVDD,HPVSS pins -8 to +8 mA Output Current 5 Do not short the output pin to another output pin, power supply pin or GND pin.(Output pin includes an IO pin which is in output mode) (Note 1) 74.2mm×74.2mm×1.6tmm FR4 1Layer Glass epoxy base Surface Copper foil 0%）Mounting Above Ta=25℃,reduced by 8.0mW/℃. Thermal beer is on a base. (Note 2) 74.2mm×74.2mm×1.6tmm FR4. 4 Layer Glass epoxy base（2,3layer Copper foil 100%）Mounting Above Ta=25℃, reduced by 30.12mW/℃. Thermal beer is on a base. Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Recommended Operating Conditions (HGND1=HGND2=SPGND=CPGND=TGND=0V) Parameter Symbol Condition Rating Unit HVDD HVDD=CPVDD=TVDD 2.7 to 3.6 V SPVDD Supply Voltage SPVDD - 2.7 to 5.5 V CPVDD Supply Voltage CPVDD HVDD=CPVDD=TVDD 2.7 to 3.6 V TVDD HVDD=CPVDD=TVDD 2.7 to 3.6 V Top - -20 to +85 ℃ HVDD Supply Voltage TVDD Supply Voltage Operating Temperature (Note 1) The radiation-proof design is not carried out. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 5/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Electrical Characteristics DC Characteristics (HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃) Parameter Symbol Conditions Min Typ Max Unit Related Pin All Digital "H" Input Voltage1 VIH1 HGND1=0V HVDD *0.8 HVDD+0.3 V Input All Digital "L" Input Voltage 1 VIL1 HGND1=0V -0.3 HVDD *0.2 V Input All Digital "H" Input Voltage 2 VIH2 HGND1=0V HVDD-0.4 HVDD+0.3 V Input All Digital "L" Input Voltage 2 VIL2 HGND1=0V -0.3 0.4 V Input "H" output Voltage VOH IOH=-1mA HVDD *0.85 V Except SDA "L" output Voltage 1 VOL1 IOL=1mA HVDD *0.15 V Except SDA "L" output Voltage 2 VOL2 IOL=3mA 0.4 V SDA "H" Input Leakage All Digital IIH VIH= HVDD 10 µA Current Input "L" Input Leakage All Digital IIL VIL=HGND1 -10 µA Current Input "Z" output Leakage IOZH VOH=HVDD 10 µA SDA Current "Z" output Leakage IOZL VOL=HGND1 -10 µA SDA Current Playback(fs48kHz) no Load, Hp-amp Operating Current1 IDDO1 use 10 13 mA Sin1kHz-Full Scale output Playback(fs48kHz) no Load, D-class, Operating Current2 IDDO2 Sp-amp use 10.5 13.7 mA Sin1kHz-Full Scale output Playback(fs48kHz) no Load, AB-class, Operating Current3 IDDO3 Sp-amp use 12 15.6 mA Sin1kHz-Full Scale output Record(fs48kHz) Operating Current4 IDDO4 Sin1kHz-Full Scale 9.5 12.4 mA input Touch Panel Operating Current5 IDDO5 0.6 1 mA Interface Operate Touch Panel Interface Interrupt Operating Current6 IDDO6 220 320 uA (Note 3) Wait Ta = -40 to 55 ℃ Standby Current IDDS 25 ℃ 0.5 5 µA (Note 1) Touch Panel Interface Interrupt electric current at the time of the wait. Please refer to a touch panel interface clause for the movement setting condition. (Note 2) Standby current is total value for all power supply currents. (Note 3) Standby current's condition is power off state by RESETB=L www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 6/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV AC Characteristics Clock PLL not used (HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃) Min Max Unit Parameter Symbol MCLKI Frequency fC 4.096 49.152 MHz MCLKI Period tC 1/fC 1/fC ns MCLKI “H” Length tCH tC*0.4 - ns MCLKI “L” Length tCL tC*0.4 - ns PLL used (HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V,Ta=25℃) Min Max Unit Parameter Symbol MCLKI Frequency fC 6.75 54 MHz MCLKI Period tC 1/fC 1/fC ns MCLKI “H” Length tCH tC*0.4 - ns MCLKI “L” Length tCL tC*0.4 - ns When PLL is use, clock from SAI_BCLK pin other than MCLKI pin could be inputted. Please refer to SAI slave clause about the BCLK pin input frequency. tC, fC MCLKI tCH tCL Figure 4 Reset (HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃) Min Max. Unit Parameter Symbol RESETB pulse width tW_RST 5 - µs tW_RST RESETB Figure 5 When Reset pin is made low-level, internal LDO goes to power mode. 1ms is necessary until REGOUT pin becomes low-level. The recommended tW_RST is over 1ms. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 7/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV 2-Wire Serial Interface (HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃, CL=30pF) Standard Mode Fast Mode Unit Parameter Symbol Min Max Min Max SCL Frequency fSCL - 100 - 400 kHz SCL "L" Length tLOW 4.7 - 1.3 - µs SCL "H" Length tHIGH 4.0 - 0.6 - µs Hold Time under Repeat [Start] Condition tHD:STA 4.0 - 0.6 - µs Setup Time under Repeat [Start] Condition tSU:STA 4.0 - 0.6 - µs Data Hold Time tHD:DAT 0 3.45 0 0.9 µs Data Setup Time tSU:DAT 250 - 100 - ns Setup Time under [Stop] Condition tSU:STO 4.0 - 0.6 - µs tHD:STA SDA tLOW tSU:DAT SCL tHD:STA tHD:DAT tSU:STA tHIGH tSU:STO Figure 6 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 8/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV 3-Wire Serial Interface (HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, CL=30pF) Parameter Symbol Min Max Unit SCLK Low to Chip Select enable tSLCL 100 - ns Chip Select Enable to SCLK Low tCLSL 100 - ns Chip Select Enable to SCLK High tCLSH 100 - ns CLK High to Chip Select enable tSHCL 100 - ns SCLK High Pulse Width tSH 50 - ns SCLK Low Pulse Width tSL 50 - ns Input Data Setup time tIDS 30 - ns Input Data Hold time tIDH 30 - ns tCHS2 100 - ns tCH 100 - ns tODV - 40 ns tCHDTS - 40 ns SCLK last edge to Chip Select disable Chip Select High Pulse Width Output Data Valid Chip Select High to Data Transition Ta=25℃, Two kinds of timing are supported depending on the SCLK pin level at data transfer start. Read or Write is selected by LSB logic INDEX. Figure 7 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 9/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Serial Audio Interface (Slave) (HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, VDD=3.3V, CL=30pF) Parameter Symbol Min Max SAI_BCLK Period Ta=25℃, Unit tC_BCLK 32fs 128fs Hz SAI_BCLK "H" Length tHW_BCLK 73 - ns SAI_BCLK "L" Length tLW_BCLK 73 - ns SAI_LRCLK Hold Time tH_LRCLK 20 - ns SAI_LRCLK Setup Time tSU_LRCLK 20 - ns - 80 ns SAI_SDOUT Delay Time tD_SDO (Note 1) SAI_SDIN Setup Time tSU_SDI 20 - ns SAI_SDIN Hold Time tH_SDI 20 - ns (Note 1) tD_SDO is the delay time from previous SAI_BCLK transition and SAI_LRCLK transition. SAI_LRCLK tH_LRCLK tSU_LRCLK tC_BCLK SAI_BCLK tHW_BCLK tLW_BCLK SAI_SDOUT tD_SDO SAI Transmit Figure 8 SAI_LRCLK tH_LRCLK tSU_LRCLK tC_BCLK SAI_BCLK tSU_SDI tH_SDI tHW_BCLK tLW_BCLK SAI_SDIN SAI Receive Figure 9 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 10/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV SAI (Master) - Serial Audio Interface (Master) (HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, CL=30pF) Parameter Symbol Min Max SAI_BCLK Period Ta=25℃, Unit tC_BCLK 32fs 64fs Hz SAI_BCLK "H" Length tHW_BCLK 146 - ns SAI_BCLK "L" Length tLW_BCLK 146 - ns SAI_LRCLK Delay time tD_LRCLK - 20 ns SAI_SDOUT Delay Time tD_SDO - 20 ns SAI_SDIN Setup Time tSU_SDI 50 - ns SAI_SDIN Hold Time tH_SDI 0 - ns SAI_LRCLK tC_BCLK tD_LRCLK SAI_BCLK tHW_BCLK tLW_BCLK SAI_SDOUT tD_SDO SAI Transmit Figure 10 SAI_LRCLK tC_BCLK tD_LRCLK SAI_BCLK tSU_SDI tH_SDI tHW_BCLK tLW_BCLK SAI_SDIN SAI Receive Figure 11 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 11/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Power Supply Sequence Please power on/off the LSI with all kind of power at the same time. Each power supply should power up/down in 50ms. Also, keep all power supply in the ON state or the OFF state. Please avoid partial ON or partial OFF states. Please keep RESETB pin “L” level until all power supply become ON state. The CPU I/F become available when all power supply is powered on after tW_PURST and tW_REGU time exceeds. HVDD must be powered on first, but HVDD must be powered off last. About SPVDD, there is no limitation above. Parameter Symbol Min Typ Max Unit Power On Delay Time tVDD_ON 0 - 50 ms Power Off Delay Time tVDD_OFF 0 - 50 ms Reset Time after Power ON tw_PURST 1 - - μs Wait Time for Regulator Starting after Reset Release tw_REGU 1 - - ms PowerSupply*0.9 HVDD Power supply tVDD_ON PowerSupply*0.1 Other tVDD_OFF PowerSupply*0.9 Power tW_PURST tW_REGU supply PowerSupply*0.1 REGOUT RESETB CPU I/F STATUS not available VDD OFF PowerDown Wait Regulator available not available Operation VDD OFF Figure 12 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 12/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Analog Characteristics (HGND1= HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25°C) Parameter Symbol Condition Min Typ Max Unit Regulator Output REGOUT Output Level VREGOUT - 1.7 1.8 1.9 V - - 0.124 Vp-p 20 30 40 kΩ Mic Input (MIC Gain=18dB / Digital Volume=0.0dB / ALC=OFF) Full Scale Input Signal Level Input Resistance VMINFS1 MIN1,MIN2 RMIN1 MIN1,MIN2 Mic Input (MIC Gain=9.0dB / Digital Volume=0.0dB / ALC=OFF) Full Scale Input Signal Level Input Resistance VMINFS2 MIN1,MIN2 - - 0.454 Vp-p RMIN2 MIN1,MIN2 20 30 40 kΩ VREF - 0.9x REGOUT/2 1.0x REGOUT/2 1.1x REGOUT/2 V IMIC = -1mA, MICBCON=0 1.50x REGOUT/2 1.67x REGOUT/2 1.84x REGOUT/2 V IMIC = -1mA, MICBCON=1 2.00x REGOUT/2 2.22x REGOUT/2 2.45x REGOUT/2 V 2.50x REGOUT/2 2.78x REGOUT/2 3.06x REGOUT/2 V 3.00x REGOUT/2 - 3.33x REGOUT/2 - 3.67x REGOUT/2 2 V Analog Reference Level(VMID-pin) Analog Reference Voltage Microphone Bias(MBIASCAP -pin) Output Voltage where, VMIC<HVDD*0.85 VMIC IMIC = -1mA, MICBCON=2 IMIC = -1mA, MICBCON=3 Output Current www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 IMIC - 13/86 mA TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV (HGND1=HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V, Ta=25℃) Parameter Symbol Conditions Min Typ Max Unit Analog Inputs to ADC out (MIC Gain=18dB / Digital Volume=0.0dB / ALC=OFF) S/(N+D) SND1 S/N SNR1 -1dBFS/ A-weighted - 78 - A-weighted HVDD on 100mVp-p, 1kHz Power Supply Rejection Ratio PSRR1 noise, no signal input Analog Inputs to ADC out (MIC Gain=9.0dB / Digital Volume=0.0dB / ALC=OFF) - 89 - dB dB - 90 - dB S/(N+D) SND2 - 80 - dB S/N SNR2 A-weighted HVDD on 100mVp-p, 1kHz Power Supply Rejection Ratio PSRR2 noise, no signal input DAC to Headphone OUT(HPR/HPL, with 16Ω/50pF load) - 92 - dB - 90 - dB Total Harmonic Distortion -1dBFS/ A-weighted THD+N3 1kHz,input -12dBFS - 75 - dB SNR3 - 93 - dB - 90 - dB - 90 - dB VOF A-weighted HVDD on 100mVp-p,1kHz noise, no signal input CPVDD on 100mVp-p,1kHz noise, no signal input No signal input - ±1 - mV Charge Pump Oscillator Frequency CPOSC - - 500 - kHz HPVDD Port Output Voltage HPVDO - - 1.8 - V HPVSS Port Output Voltage HPVSO - - -1.8 - V Signal to Noise Ratio Power Supply Rejection Ratio Output Offset Voltage PSRR3 DAC to Speaker OUT D-class Mode (SPOUT+/-, with 8Ω/50pF load) Output Power Total Harmonic Distortion Signal to Noise Ratio Power Supply Rejection Ratio PWM frequency Efficiency Po4 THD=10%, SPVOL=6dB - 700 - mW THD+N4 Po=310mW - 66 - dB SNR4 - 95 - dB - 90 - dB - 60 - dB PWMF A-weighted, THD+N=1% HVDD on 100mVp-p,1kHz noise SPVDD on 100mVp-p,1kHz noise - - 370 - kHz EFF - - 90 - % PSRR4 DAC to Speaker OUT AB-class Mode (SPOUT+/-, with 8Ω/50pF load) Output Power Total Harmonic Distortion Signal to Noise Ratio Power Supply Rejection Ratio Po5 THD=10%, SPVOL=6dB - 700 - mW THD+N5 Po=310mW - 62 - dB SNR5 A-weighted, THD+N=1% HVDD on 100mVp-p,1kHz noise SPVDD on 100mVp-p,1kHz noise - 95 - dB - 90 - dB - 60 - dB - 5 - μV - 70 - dB PSRR5 Microphone Bias(MBIASCAP-pin) *1 Output Noise Voltage VMICN6 Power Supply Rejection Ratio PSRR6 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 22Hz to 22kHz, MICBCON=1 HVDD on 100mVp-p,1kHz noise Load=1mA MICBCON=1 14/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV (HGND1=HGND2=SPGND=CPGND=TGND=0V, HVDD=3.3V, SPVDD=3.3V, CPVDD=3.3V, TVDD=3.3V,Ta=25℃) Parameter Symbol Conditions Min Typ Max Unit Touch Panel Interface ADC Resolution N - - - 12 Bit Differential Non-Linearity Error DNL - -3 - 3 LSB Integral Non-Linearity Error INL - -4 - 4 LSB Offset Error OFTERR - - 1 - LSB Gain Error GAERR - - 0.5 - LSB Touch Panel Driver Switch SWONR - - 5 - Ω IRQR1 RSEL=0 40 50 70 kΩ IRQR2 RSEL=1 Interrupt Pull-up Resistance ADC Conversion Timing www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 70 90 120 kΩ Tw_ADC1 - - 35 μs Tw_ADC2 - - 43 μs 15/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Function Description Clock Control Main modules that make sound path of the LSI inside operate with 1024fs Audio Clock. Audio Clock can be selected whether divided clock of 256fs/512fs/1024fs from MCLKI or generated clock from Audio PLL. When PLL is used, PLL generates internal clock. The input clock into PLL can be selected from either MCLKI port or SAI_BCLK port by setting Clock Input / Output Control register. PLL generates 256fs clock of sampling frequency. The registers about Audio Clock setting: Sampling Rate Setting Register, FPLLM, FPLLNL, FPLLNH, FPLLD, FPLLFL, FPLLFH, FPLLFDL, FPLLFDH, Clock Input / Output Control register, Clock Input Select Register 1. 2. 3. 4. 5. 6. 7. 8. ・The sequence of PLL setting Stop PLL output by setting PLLOE bit to “0”. Disable PLL by setting PLLEN bit to “0”. Set PFLLM, FPPNL, FPLLNH, FPLLD, FPLLFL, FPLLFH, FPLLFDL, FPLLFDH. Set input port by PLLISEL bit. Set PLLEN bit to “1”. Wait for the PLL stabilizing time as the table “PLL Stabilizing Time”. Set PLLOE bit to “1”. Start recording or playback. PLL Stabilizing Time PLL stability time 10msec - Related Register Sampling Rate Setting Register PLLNL, PLLNH Register PLLML, PLLMH Register PLLDIV Register Clock Enable Register Clock Input / Output Control Register www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 16/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV When PLL is Used. The LSI support audio PLL function that can generate precise audio clock from wide range of clock frequency. Then, it can be realize audio function without external clock generator for audio. The LSI supports following cases. The LSI generates audio clock with input clock provided from MCLKI port or BCLKI port. ■case1: PLLISEL (0x0e/0x0f)=0x1, MST(0x64/0x65)="0" Audio clock is generated by the PLL BU26154 with MCLKI clock. SAI_LRCLK and SAI_BCLK are provided by the CPU. B26154 SAI_LRCLK SAI_BCLK SAI_SDIN SAI_SDOUT CPU CLOCK MCLKI Figure 13 ■case2: PLLISEL (0x0e/0x0f)=0x1, MST(0x64/0x65)="1" Audio clock is generated by the PLL in BU26154 from MCLKI clock. SAI_LRCLK and SAI_BCLK are provided from the LSI. Figure 14 ■case3: PLLISEL (0x0e/0x0f)=0x2, MST(0x64/0x65)="1" Audio clock is generated by PLL in BU26154 form SAI clock. Figure 15 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 17/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV When PLL is not Used. Audio clock is generated by the CPU and supplied to the LSI when PLL is not used. Then CPU and the LSI are synchronized. ■case 5: MST (0x64/0x65) ="0" Audio clock (256fs, 512fs, 1024fs) is generated by the CPU and supplied to MCLKI port of the LSI. LRCLK and BCLK are also provided from the CPU. Figure 16 ■case6: MST (0x64/0x65)="1" Audio clock (256fs, 512fs, 1024fs) is generated by the CPU and supplied to MCLKI port of the LSI. SAI_LRCLK and SAI_BCLK are provided from the LSI. Figure 17 Even when using the same sampling frequency, the setting condition is different depending on clock frequency. When changing MCLKI input frequency, PLLOE should be set to “0”, then PLLOE should be set to “1” back. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 18/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV SAI (Serial Audio System Interface) The LSI supports SAI formats. WSLI="0", DLYI="0", FMTI="0" SAI_ LRCLK Right Left 1 2 3 ……………16………… SAI_SDIN SAI_SDOUT MSB 2SB 3SB LSB Left 1 2 3 ……………16………… MSB 2SB 3SB LSB MSB 2SB 3SB SAI_BCLK Figure 18 WSLI="1", DLYI="0", FMTI="0" Left SAI_ LRCLK 1 2 3 ……………16………… SAI_SDIN SAI_SDOUT Left Right MSB 2SB 3SB LSB 1 2 3 ……………16………… MSB 2SB 3SB LSB MSB 2SB 3SB SAI_BCLK Figure 19 WSLI="0", DLYI="1", FMTI="0" SAI_ LRCLK Left 1 2 3 ……………16………… SAI_SDIN SAI_SDOUT MSB 2SB 3SB Left Right LSB 1 2 3 ……………16………… MSB 2SB 3SB LSB MSB 2SB 3SB SAI_BCLK Figure 20 WSLI="1", DLYI="1", FMTI="0" SAI_ LRCLK SAI_SDIN SAI_SDOUT Right Left 1 2 3 ……………16………… MSB 2SB 3SB LSB Left 1 2 3 ……………16………… MSB 2SB 3SB LSB MSB 2SB 3SB SAI_BCLK Figure 21 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 19/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV DLYI="0", FMTI="1" Flame synchronous transfer mode: R channel data is transferred right after L channel data. SAI_ LRCLK Left Left Right 1 2 3 ……………16 1 2 3 ……………16………… SAI_SDIN SAI_SDOUT MSB 2SB 3SB LSB MSB 2SB 3SB MSB 2SB 3SB LSB SAI_BCLK Figure 22 DLYI="1", FMTI="1" Flame synchronous transfer mode: R channel data is transferred right after L channel data. SAI_ LRCLK SAI_SDIN SAI_SDOUT Left 1 2 3 ……………16 1 2 3 MSB 2SB 3SB Right Left …………16………… LSB MSB 2SB 3SB LSB MSB 2SB 3SB SAI_BCLK Figure 23 - Related Register SAI Transmitter Control Register SAI Receiver Control Register www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 20/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV 2 wire serial interface This LSI has 2 wire serial interfaces. The LSI operates as a slave device. The address is fixed at “0011010”. - Format The followings are the protocol of the LSI. Write (MSB first) Start Condition (Set SDA level from “H” to “L” during SCL=“H”) Slave Address (0011010) +W (0) (8bit) Write Address (8bit) Write Data (8bit) … Stop Condition (Set SDA level from “L” to “H” during SCL=“H”) Read (MSB first) Start Condition Slave Address (0011010) +W (0) (8bit) Read Address (8bit) (Stop Condition) Start Condition Slave Address (0011010) +R (1) (8bit) Read Data (8bit) The following shows the wave form of the LSI. The yellow gridding shows that slave device drives the bus. The symbol in the wave form means as following table. Unit Description W/R 0: It is Read Write 1 A 0: ACK(Acknowledge) 1: NAK(Not Acknowledge) A[7-0] Address (8bit) D[7-0] Data(8bit) Write slave address reception SCL Start 0 0 SDA 1 0 2 1 3 1 Access address reception 4 5 6 7 0 1 0 W 8 0 1 8 0 1 2 3 4 3 4 5 6 7 A A7 A6 A5 A4 A3 A2 A1 A0 Write data reception Continued from the above 2 Write data reception 8 0 1 7 8 A D7 D6 D5 D4 D3 D2 D1 D0 A 6 7 A D7 D6 D5 D4 D3 D2 D1 D0 Internal write 8 0 1 2 3 4 5 6 7 A D7 D6 D5 D4 D3 D2 D1 D0 Internal write 3 4 5 6 Write data reception Write data reception 5 2 8 0 1 2 3 4 5 6 7 A D7 D6 D5 D4 D3 D2 D1 D0 Stop A Internal write Figure 24 In case there is no Stop or Start condition after internal register is written (Above figure: Internal Write), the slave device becomes continuous write mode and the next received 8 bits of data will be written into the internal register addressed by incremented by two to the current address. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 21/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Read slave address reception SCL Start SDA 0 0 1 0 2 1 3 1 4 0 Access address reception 5 1 6 0 7 8 0 W A A7 A6 A5 A4 A3 A2 A1 A0 A 1 slave address reception Continued fromthe above Start 0 0 1 0 2 3 4 1 1 0 5 1 2 3 4 5 6 7 8 S Read data transmission 6 0 7 R 8 0 1 2 3 4 5 Read data transmission 6 7 8 A D7 D6 D5 D4 D3 D2 D1 D0 A Internal read 0 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 A Internal read Figure 25 If the Master device returns ACK (acknowledge) after the 8 bit data transferred from the LSI becomes continuous read mode. The next received 8 bits of data will be read from the internal register addressed by incremented by two to the current address. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 22/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV State transition about sound control The following shows state transition about sound control. A change state is carried out by RECPLAY bit setup. Sound Stop STATE 0x0 Play STATE 0x2 Rec STATE 0x1 Rec and Play STATE 0x3 Monitor STATE 0x7 BU26154MUV is changed status by setting RECPLAY bit. Figure 26 (1) Sound Stop STATE (RECPLAY=0x0) Sound activity is stopped. (2) Rec STATE (RECPLAY =0x1) Recording is enabled through microphone. (3) Play STATE (RECPLAY =0x2) Playback is enabled from SAI. (4) Monitor STATE (RECPLAY =0x7) Monitoring recording via microphone is enabled. ALC function is only effective in recording path. Only 2ch sound effects are available in Notch filter mode. In the time of transition Rec STATE to Monitor STATE, please set off the register bits of EQ2EN-EQ3EN. (5) Rec and Play STATE (RECPLAY =0x3) Playback is enabled from SAI with recording via microphone. ALC function is only effective in recording path. Only 2ch sound effects are available in Notch filter mode. In the time of transition Rec STATE to Monitor STATE, please set off the register bits of EQ2EN-EQ3EN. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 23/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Signal Flow It uses signal flow Case1 or Case2 at the time of recording (analog microphone). Case1: Recording AMIC VOL DV MUTE ALC ADC HPF1 HPF2 REC LPF Filter REC ALCVOL Noise Gate REC DATT Digital Interface Filter Block Case2: Recording AMIC VOL DV MUTE ALC ADC HPF1 HPF2 Filter REC LPF REC ALCVOL Noise Gate REC DATT Digital Interface Filter Block Figure 27 Name Function Related Register AMICVOL Analog Microphone volume Mic input volume control HPF1 High path filter for record DC cut DSP Filter Function Enable HPF2 High pass Filter for Record Filter Notch filter is available RECLPF Low pass Filter for recording. DSP Filter Function Enable High Pass Filter2 Cut-off Control Sound Effect Mode DSP Filter Function Enable EQ Band N Gain Setting Programmable EQ Band N Coeffeicient-a0/1 Rec Programmable LPF Setting REC ALCVOL ALC Noise Gate RECDATT DVMUTE ALC use:ALC controls volume ALC not use: It’s available as Boost volume Auto Level Controller Function. ALC is processed to recording data The purpose is for reducing a floor noise Record Digital Attenuator. It’s available fader function for reducing a Pop-noise when changing volume. Record Digital Volume Mute Rec Programmable LPF Cutoff Coef Setting Volume setting 9dB to +35.25dB HPF Enable/Disable HPF Enable/Disable order setting Cut-off frequency setting Sound Effect mode setting Each filters Enable/Disable setting Each filters gain setting Each sound effects characteristics setting LPF Enable/Disable setting order setting Cut-off frequency setting refer to application note Record Digital Attenuator Control Digital Volume Control Function Enable Record Digital Attenuator Control Digital Volume Control Function Enable Mixer & Volume Control Mixer & Volume Control Digital Volume Control Function Enable Digital Volume Control Function Enable * Please refer to the Sound Effect Mode register for Filter Block. When Filter Block is connected with the reproduction route, nothing is processed in the recording route. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 24/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Signal flow at the time of the reproduction Playback To Speaker ampifier VOL SPVOL SPINSEL AVOL AVOL AVOL DAC SOFT CLIP PLAY DATT PLAY ALCVOL DV MUTE ALC PLAY LPF Filter HPF2 H-BASS Effect Vol LRM CON Digital Interface Filter Block To Headphone ampifier HPINSEL Figure 28 Name LRMCON Effect Vol P2Bass+ Function Mixer of the Lch/Rch data input from SAI. It is digital before the sound is processed Volume. Block for P2Bass + processing. Filter Notch filter is available PLAYLPF It is programmable LPF for the reproduction. PLAY ALCVOL ALC PLAYDATT DVMUTE SPVOL AVOL AVMUTE SPINSEL HPINSEL When ALC is used It functions as Volume that ALC controls. When ALC unused: It functions as Boost Volume. It is an auto level controller. ALC is processed to the reproduction data. Digital Attenuator of the reproduction route. Fader can be used for the noise reduction at the Volume setting change. Reproduction route (PLAYDATT) is compulsorily put into the state of Mute. The value of PLAYDATT need not be changed. The Analog Boost Volume of Speaker amplifier setting. The Analog Volume of reproduction route setting. Fader can be used for the Pop-noise reduction at the Volume setting change. Reproduction route (SPVOL) is compulsorily put into the state of Mute. The value of SPVOL need not be changed. It selects the input path to speaker amplifier. It selects the input path to headphone amplifier. Related Register Setting Mixer & Volume Control Mixer setting Playback Effect Volume Volume setting -71.5dB to 0dB (0.5dBstep) P2Bass+ Enable P2Bass+ Parameter* Sound Effect Mode DSP Filter Function Enable EQ Band N Gain Setting Programmable EQ Band N Coeffeicient-a0/1 Play Programmable LPF Setting Play Programmable LPF Cutoff Coef Setting of P2Bass+ Sound mode setting Enable/Disable of each filter Gain setting of each filter Characteristic setting of each filter and acoustic treatment Degree setting of LPF for Enable/Disable reproduction of LPF for reproduction Characteristic setting of LPF for reproduction Please refer to the application note for the ALC function. Playback Digital Attenuator Control Digital Volume Control Function Enable Mixer & Volume Control Digital Volume Control Function Enable Speaker Amplifier Input Control Analog volume control Amplifier Volume Fader Control Amplifier Volume Control Function Enable Amplifier Volume Control Function Enable Speaker Amplifier Input Control Headphone Amplifier Input Control Volume setting -71.5dB to 0dB (0.5dBstep) Fader ON/OFF setting (Synchronize with DVMUTE.) Setting at Fade time (Synchronize with DVMUTE.) MUTE ON/ Turning off setting Volume setting 0dB/6dB/12dB/18dB Volume setting -28dB to +18dB*At BTL Fader ON/OFF setting (Synchronize with AVMUTE.) Setting at Fade time (Synchronize with AVMUTE.) MUTE ON/OFF setting Selection of speaker amplifier playback path Selection of headphone amplifier playback path * Please refer to Sound Effect Mode Register for Filter Block. When Filter Block is connected with the recording route, nothing is processed in the reproduction route. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 25/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Filter (5bands-Programmable IIR Filter) A five bands equalizer features a second-order IIR type Band Pass Filter. Volume control of MUTE, -71.5dB to +12dB (0.5dB step) can be controlled at all paths. Each channels of the filter can be selected parallel connection or serial connection The followings are block diagrams at parallel connection and serial connection Coefficient(a0, a1) X 5ch gain X 5ch Input Band0-IIR Coefficient(a0, a1) X 5ch Band1-IIR gain X 5ch Input Output Band2-IIR Band0-IIR Band1-IIR Band2-IIR Band2-IIR Output Band3-IIR Band4-IIR Band4-IIR Parallel connection Figure 29 Serial connection Figure 30 The filter coefficient is programmable. From required center frequency and band width, Programmable Equalizer Coefficient-a0 Control Register and Programmable Notch Filter Coefficient-a1 Control Register value is decided. Followings are the setting formula. a0 = (1 - tanπfb/fs) / (1 + tanπfb/fs) a1 = - 2cos2πf0/fs / (1 + tanπfb/fs) f0: Band center frequency [Hz] fb: -3dB band width [Hz] fs: Sampling frequency [Hz] * Actual setting value is an integral number that the result of above formula multiplied by 214 then round up numbers of five and above and round down anything under five to a integer. DSP filtering function: ON / OFF DSP Filter Function Enable register can set ON or OFF of each filter function. Please change this register when RECPLAY bit is 0x0. If this register is changed on playback or recording, the noise may be generated. ALC Auto Level Control Please refer the application note “AutoLevelControlApplicationNote”. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 26/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV P2Bass+ (Perfect Pure Bass Plus) Please refer the application note. Soft clip limiter Soft clip function is reduced power comsumption. If ALC cannot be responded to input waveform, soft clip function is reduced input waveform. In case of input waveform is overed threshold level, soft clip reduce output waveform. OUT SCGAIN=2 SCGAIN=1 SCGAIN=1/2 SCGAIN=1/4 … SCGAIN=1/64 Soft Clip Gain (SCGAIN) 0x000000 Soft Clip Threshold (SCTHRH, SCHTRM, SCHTRL) 0xFFFFFF IN Figure 31 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 27/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Low Power Consumption Operation When PCM data is inputted into LSI consecutive "0" is detected, it will disable the output amplifier automatically and perform low power consumption mode operation by stopping the internal clock. When data except “0” are inputted, it will automatically return to original movement. When "0" is detected in both LCHRCH, this function is effective. When you use only LCH, please input "0" data into the RCH side. When you use only RCH, please input "0" data into the LCH side. This function is effective only at the time of the playback of the speaker amplifier. At the time of headphones amplifier playback and the recording, please set it to disable. In addition, set the enable function and "0" count level in Zero Detection Setting Register. Low power operation Normal operation Normal operation Figure 32 Change of the SP/HP playback When it changes of Speaker Amplifier and Headphone Amplifier, it prepares for COEFSEL bit because it does not perform the re-setting of filter coefficients. A side register is used when COEFSEL bit is "0". B side register is used when COEFSEL bit is "1". The target registers are as follows. Please be careful in setting addresses. MAP 2 0 0 0 0 0 0 0 0 A side register INDEX(R) 0x24/0x26/0x28 0x46 0x4c/0x4e 0x5c 0x66 0x70 0x3e 0x74 to 0x7c 0x80 to 0xa6 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 MAP 2 2 2 2 2 2 2 2 2 B side register INDEX(R) 0x2a/0x2c/0x2e 0x46 0x4c/0x4e 0x5c 0x66 0x70 0x73 0x74 to 0x7c 0x7e to 0xa4 28/86 Register P2BASS+ Parameter0/1/2 Play HPF2 Setting Play Programmable HPF2L/H Coef Sound Effect Mode DSP Filter Function Enable Playback Effect Volume Control Playback Digital Attenuator Control EQ Band0/1/2/3/4 Gain Setting Programmable Equalizer Band0/1/2/3/4 Coefficient-a0/a1 L/H TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Analog block VMID is used as analog circuit reference voltage for both recording path and playback path. Therefore, both case for recording and playback, VMID need to do power up. At the power up, the wait time in proportion to the capacitor value is needed to charge external capacitor connected with VMID pin. If recording and playback start before completion of charge, it may generate noise. The following is a sequence of recommendation. Refer to the Analog Reference Power Management Register for the function of VMIDCON. . VMID Power UP/DOWN Sequence (External capacitor 1uF) Power Down Power Up 1/2 Regout Level vmid ( 0V ) Power Down VMIDCON 0x0 Charge Time Record or Playback Power Down 0x0 0x1 0x2 Min 5ms Min 5ms Figure 33 Playback Path The LSI can be executed sound output from 4 paths bellow. The output can be selected by Speaker Amplifier Output Control Resister and Analog Reference Power Management Register. Digital Input (SAI) → DAC → D-class Speaker Amplifier Digital Input (SAI) → DAC → AB-class Speaker Amplifier Digital Input (SAI) → DAC → Headphone Amplifier Analog Microphone Input (MIN pin) → ADC → DAC → Headphone Amplifier <attention> No guaranty of record path sound quality during speaker amplifier active. Speaker amplifier The speaker amplifier of BU26154 can choose operation mode among one of D-class operation or the AB-class operation. It can prevent interference with FM radio influence by making AB-class operation. It performs the change of the enable / disable setting of the speaker amplifier and the AB-class/D-class operation in Speaker Amplifier Power Management Register. Headphones amplifier The headphones amplifier of BU26154 operates in a ground reference. Therefore the LSI can delete the condenser for the AC coupling to get outside. In addition, the LSI can suppress a POP noise when you want to suppress a POP noise by connecting the optional resistance of the chart below outside. Left Headpphone Amplifier BU26154 option HPL option HPR Right Headpphone Amplifier Figure 34 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 29/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV In addition, it is necessary to operate LDO for headphone amplifier when operating headphones amplifier. The power up of headphones amplifier and LDO for headphone set in Analog Reference Power Management Register. Please power up the headphones amplifier after 1mS waiting time for LDO for headphones. At the time of the power down, please power down HPVDD after the power down of the headphones amplifier. HPVDD Power UP/DOWN Sequence Power Up HP Power Down HPVDD Power Down Regout Level HPVDD ( 0V ) Power Down HPVDD Power up HP Power up and Playback HP Power Down HPVDD Power Down HPVDDEN HPLEN or HPREN Min 1ms Min 0ms Figure 35 About HPCOM pin HPCOM pin is a signal ground pin of the headphones amplifier. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 30/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Microphone amplifier The microphone input can support two modes, a single-end and differential. When using it in single-end input, it writes "0" in the MINDIF bit of the MIC Interface Control register. When using differential input, it writes "1". In the case of single-end input, it can input from MINP pin or MINN pin. Please set of the input pin in MIC Select Control Register. Microphone bias The Case of using Microphone bias, it shows a recommended connection diagram. By all means, please connect a condenser (2.2uF at the minimum) to MBIASCAP outside pin. On this occasion, the LSI can improve noise characteristics by connecting the option resistance on the chart below (the optional resistance is up to 50 Ω). MicBiasAmplifier BU26154 option MBIASCAP 2.2uF Figure 36 In addition, according to the capacity of the outside condenser, it is necessary to wait until microphone bias is stable. In waiting time of MICBIAS, please set the value of the MICTIME bit at the MIC Input Charging Time register. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 31/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV BU26154 Y-plate X-plate BU26154 Y -plate X- plate Touch Screen Controller SAR 12 bits ADC is integrated into this LSI and is available as 4 lines type touch screen controller. There is the function of the X-axis, the position sensing of the Y-axis, the pen pressure detection and the pen interrupt detection. It becomes independent to Codec and is controllable without minding timing. But the hard reset (reset signal input by RESETB pin) communizes it. Clock control When enabled clock is to be used for touch screen controller, set TCLKEN bit of Clock Enable Register to "1". The touch screen controller function uses a built-in oscillator. Therefore it is not necessary to perform clock control listing in item clock control when using only the touch screen controller. Position sensing This LSI is available for the position sensing of the touch screen. The twice measurement of the X-axis measurement, the Y-axis measurement is necessary for position sensing. XP XP YP YP refp refp ainp ainp ainn ainn refn YN refn YN XN XN At the time of the X-axis plate measurement At the time of the Y-axis plate measurement Figure 37 The Pen Pressure Detection BU26154 Y-plate X-plate BU26154 Y-plate X-plate The measurement of touch pressure is carried out to measure the resistance between X plate and Y plate. It is calculable by two methods, from the location information by location determination, and the measurement result in touch pressure measurement mode. In case of X-Position and Y-Position are known Touch pressure resistance = X-plate resistance*(X-position/4096)*[(4096/Z1)-1] - Y-plate resistance*[1-(Y-position/4096)] In case of X-Position is known Touch pressure resistance = X-plate resistance*(X-position/4096)*[(Z2/Z1)-1] XP XP YP YP refp refp ainp ainp ainn YN ainn refn YN XN refn XN At the time of Z1 point measurement At the time of Z2 point measurement Figure 38 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 32/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV The Pen Interrupt Detection BU26154 Y-plate X-plate Touch detect function outputs the X-plate and Y-plate contact from IRQB pin. Please refer to Description of Registers for valid or invalid setup of Touch Detection. When X-plate and Y-plate do not contact, H level is outputted from IRQB pin by internal pull-up resister (typical 10kohm). When X-plate and Y-plate contact, L level is outputted from IRQB pin by touch plate resistance (about hundreds ohm). Please refer to Description of Registers for IRQB output selection. Touch Detect schematic diagram is shown below. Typ.50koh m XP YP IRQB YN XN Interrupt detect circuit Figure 39 IRQB pin outputs "L" during RESETB "L"(RESET state) period. During this period, please mask interrupt. RESETB IRQB Valid Min: 1ms Interrupt timing Figure 40 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 33/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV About Touch Panel Interface at Interrupt Wait Touch panel interface can switch to low power consumption by stopping the operation of unnecessary circuits at interrupt wait. Setting of touch panel interface at interrupt wait 0x2d = 0x00, // Thermal detect circuit Disable 0x1d = 0x02, // MAPCON=2 0x05 = 0x22, // Level shifter for headphone OFF 0x13 = 0x00, // Reference current circuit for audio system OFF 0x1d = 0x00, // MAPCON=0 0x0d = 0x80, // Touch panel interface oscillation circuit Enable 0x1d = 0x01, // MAPCON=1 0x61 = 0x38, // Touch panel interface interrupt circuit Enable 0x1d = 0x00, // MAPCON=0 0x0d = 0x00, // Touch panel interface oscillation circuit Disable This state is interrupt wait mode. Please use a touch panel interface after interrupt, setting enable oscillation circuit. Please, set circuit from Disable to Enable in circuit when using of audio system function Setting at using of audio system function 0x2d = 0x01, // Thermal detect circuit Enable 0x1d = 0x02, // MAPCON=2 0x05 = 0x26, // Level shifter for headphone ON 0x13 = 0x01, // Reference current circuit for audio system ON 0x1d = 0x00, // MAPCON=0 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 34/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Operating Mode Normal operating mode It becomes Normal operating mode by setting Touch ADC Control registerTCHA2=0x1. Next AD conversion starts by reading register value of ADCR1 register (8Bit mode) or ADCR2 register (12Bit mode), at Normal operating mode. TCLKEN Bit Internal Clk I2C Operation Write Data reception INDEX=0x61,TCHEN="1" Slave address receptio Read Data reception INDEX=0x64 SCL SDA D2 D1 D0 ACK 1 0 R ACK D7 D6 D5 Internal ADC Start Sync ADC Status IDLE Data Hold AD Conversion1_1 ADCR1Register AD Conversion1_2 IDLE Data Hold AD Conversion2_1 Data Valid1_1 ADCR2 Register AD Conversion2_2 IDLE Data Valid2_1 Data Valid1_2 Data Valid2_2 Tw_ADC1 Tw_ADC1 Tw_ADC2 Tw_ADC2 12Bit Normal Mode I2C Timing TCLKEN Bit Internal Clk I2C Operation Write Data reception INDEX=0x61,TCHEN="1" Slave address receptio Read Data reception INDEX=0x62 SCL SDA D2 D1 D0 ACK 1 0 R ACK D7 D6 D5 Internal ADC Start Sync ADC Status IDLE Data Hold AD Conversion1 ADCR1Register IDLE Data Hold AD Conversion2 Data Valid1 IDLE Data Valid2 ADCR2 Register Tw_ADC1 Tw_ADC1 8Bit Normal Mode I2C Timing AD conversion starts by rising edge of CSB at using SPI. 12Bit timing mode chart is listed below. similar it. 8Bit mode start timing is TCLKEN Bit Internal Clk SPI Operation Write Data INDEX=0x61,TCHEN="1" Read Data INDEX = 0x64 SCLK CSB Internal ADC Start Sync ADC Status IDLE Data Hold AD Conversion1_1 ADCR1Register AD Conversion1_2 IDLE Data Hold AD Conversion2_1 Data Valid1_1 ADCR2 Register AD Conversion2_2 Idle Data Valid2_1 Data Valid1_2 Tw_ADC1 Data Valid2_2 Tw_ADC1 Tw_ADC2 Tw_ADC2 8Bit Normal Mode SPI Timing www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 35/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Auto Operation Mode When TCHA2 bit of Touch ADC Control register is set to "0", BU26154MUV is set to Auto Operation Mode. When is to set in Auto Mode Operation, BU 26154 MUV is Interrupt mode by reading to ADCR2 register in 12 bit mode and BU 26154 MUV is Interrupt mode by reading to ADCR1 register in 8 bit mode. TCLKEN Bit Internal Clk I2C Operation Write Data reception INDEX=0x61,TCHEN="1" Slave address receptio Read Data reception INDEX=0x64 SCL SDA D2 D1 D0 ACK 1 0 R ACK D7 D6 D5 Internal ADC Start Sync ADC Status IDLE Data Hold AD Conversion1_1 ADCR1Register AD Conversion1_2 IDLE Interrupt Mode Data Valid1_1 ADCR2 Register Data Valid1_2 Tw_ADC1 Tw_ADC2 12Bit Auto Mode I2C Timing TCLKEN Bit Internal Clk I2C Operation Write Data reception INDEX=0x61,TCHEN="1" Slave address receptio Read Data reception INDEX=0x62 SCL SDA D2 D1 D0 ACK 1 0 R ACK D7 D6 D5 Internal ADC Start Sync ADC Status IDLE Data Hold AD Conversion1_1 ADCR1Register IDLE Interrupt Mode Data Valid1_1 ADCR2 Register Tw_ADC1 8Bit Auto Mode I2C Timing TCLKEN Bit Internal Clk SPI Operation Write Data INDEX=0x61,TCHEN="1" Read Data INDEX = 0x64 SCLK CSB Internal ADC Start Sync ADC Status IDLE Data Hold AD Conversion1_1 ADCR1Register AD Conversion1_2 IDLE Interrupt Mode Data Valid1_1 ADCR2 Register Data Valid1_2 Tw_ADC1 Tw_ADC2 12Bit Auto Mode SPI Timing www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 36/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Register function explanation Register map Note: “-” indicates a reserved bit. They return “0” for read. Write “0” to the bit every time. If “1” is written to this bit, the operations cannot be guaranteed. Don’t write data to empty INDEX or register bit to guarantee normal operation. A function with (*)bit doesn’t need internal clock to change state. The following registers are accessible at the time of MAPCON=0x0 of the Register Map Control register (0x1c/0x1d). www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 37/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV INDEX R W 0x00 0x01 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x1c 0x1d 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x3a 0x3b 0x3e 0x3f 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x70 0x71 0x72 0x73 0x74 0x75 b07 (Initial) TCLKEN 0 HPREN 0 SPMDSEL 0 - b06 b05 b04 b03 b02 b01 b00 SR 0 0 0 0 MCLKOE PLLOE PLLEN MCLKEN 0 0 0 0 PLLISEL CLKSEL 0 0 0 0 0 SOFTRST 0 RECPLAY 0 0 0 MCTIME 0 0 0 0 0 0 MAPCON 0 0 VMIDCON HPVDDEN MICBEN 0 0 0 0 PGAATT PGAEN ADCREN ADCEN 0 0 00 DACREN DACLEN 0 0 AVREN COEFSEL SPEN AVLEN 0 0 1 0 0 TSDEN 1 ZCEN 0 MICBCON 0 0 AVVOL 0 1 0 1 0 PDATT 1 1 1 1 1 1 1 1 PLHPF2CUT HPF2CSEL PLHPF2OD PLHPF2EN 0 0 0 0 0 0 AVMUTE AVFADE 0 0 AVFCON 0 0 0 PHPF2C0L 0 0 0 0 0 0 0 0 PHPF2C0H 0 0 0 0 0 0 0 0 OSRSEL 0 0 MINVOL MINDIF 1 0 0 0 SEMODE[2:0] SEMODE[7] 0 0 0 0 PCMFO24 FMTO MSBO ISSCKO AFOO DLYO WSLO 1 1 0 0 0 0 0 0 PCMFI24 FMTI MSBI ISSCKI AFOI DLYI WSLI 1 1 0 0 0 0 0 0 BSWP MST 0 0 HPF2OD EQ4EN EQ3EN EQ2EN EQ1EN EQ0EN HPF2EN HPF1EN 0 0 0 0 0 0 0 1 DVMUTE DVFADE RALCEN PALCEN 0 0 0 0 DVFCON RMCON LMCON 0 0 0 0 0 0 0 0 RDVOL 1 1 1 1 1 1 1 1 Effect VOL 1 1 1 1 1 1 1 1 RALCVOL 0 1 0 0 0 0 0 EQGAIN0 1 1 1 0 0 1 1 1 HPLEN 0 - www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 - - 38/86 Register Name Note Sampling Rate Setting Clock Enable Clock Input/Output Control Software Reset Record/Playback Running Control Mic Input Charging Time Register MAP Control Analog Reference Power Management Analog Input Power Management DAC Power Management Speaker Amplifier Power Management Thermal Shutdown Control Zero Cross Cmparator Power Management MICBIAS Voltage Control Analog Volume Control Playback Digital Attenuator Control Play HPF2 Setting Amplifier Volume Control Function Enable Amplifier Volume Fader Control Play Programable HPF2 CoefL Play Programable HPF2 CoefH DAC Clock Setting note1 Mic Interface Control Sound Effect Mode SAI Transmitter Control SAI Receiver Control SAI Mode select DSP Filter Function Enable Digital Volume Control Function Enable Mixer & Volume Control Record Digital Attenuator Control Playback Effect Volume Control note1 Record ALC Volume Control EQ Band0 Gain Setting TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV INDEX R W 0x76 0x77 0x78 b07 (Initial) b06 b05 b04 1 1 1 0 1 1 1 0 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xb2 0xb3 1 - 0 1 1 1 1 - 1 - 0 - 0 - 1 1 0 1 HPF2CUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 EQ2A1L 0 0 0 EQ2A1H 0 0 0 EQ3A0L 0 0 0 0 EQ3A0H 0 0 0 0 EQ3A1L 0 0 0 0 EQ3A1H 0 0 0 0 EQ4A0L 0 0 0 0 EQ4A0H 0 0 0 0 EQ4A1L 0 0xc3 0 EQ2A0H 0 0xc2 1 EQ2A0L 0 0xc1 1 EQ1A1H 0 0xc0 1 EQ1A1L 0 0xbf 1 EQ1A0H 0 0xbe 1 EQ1A0L 0 0xbd 0 EQ0A1H 0 0xbc 1 EQ0A1L 0 0xbb 1 EQ0A0H 0 0xba 1 EQ0A0L 0 0xb9 0 EQGAIN4 0 0xb8 b00 EQGAIN3 0 0xb5 b01 EQGAIN2 1 0xb4 b02 EQGAIN1 0x79 0x7a b03 0 0 0 EQ4A1H 0 RSATEN 0 - 0 - 0 - 0 - 0 - 1 - 0 - www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 1 - RALCATK 0 0 0 0 RSATMINGAIN 0 - RALCDCY 0 1 RALCLVL 1 1 RALCMINGAIN 0 0 0 - 1 1 0 1 0 RALCZCTM 0 0 PALCATK 0 1 0 1 0 0 0 1 PALCDCY 39/86 Register Name EQ Band1 Gain Setting EQ Band2 Gain Setting EQ Band3 Gain Setting EQ Band4 Gain Setting High Pass Filter2 Cut-off Control Programable Equalizer Band0 Coefficient-a0 (L) Programable Equalizer Band0 Coefficient-a0 (H) Programable Equalizer Band0 Coefficient-a1 (L) Programable Equalizer Band0 Coefficient-a1 (H) Programable Equalizer Band1 Coefficient-a0 (L) Programable Equalizer Band1 Coefficient-a0 (H) Programable Equalizer Band1 Coefficient-a1 (L) Programable Equalizer Band1 Coefficient-a1 (H) Programable Equalizer Band2 Coefficient-a0 (L) Programable Equalizer Band2 Coefficient-a0 (H) Programable Equalizer Band2 Coefficient-a1 (L) Programable Equalizer Band2 Coefficient-a1 (H) Programable Equalizer Band3 Coefficient-a0 (L) Programable Equalizer Band3 Coefficient-a0 (H) Programable Equalizer Band3 Coefficient-a1 (L) Programable Equalizer Band3 Coefficient-a1 (H) Programable Equalizer Band4 Coefficient-a0 (L) Programable Equalizer Band4 Coefficient-a0 (H) Programable Equalizer Band4 Coefficient-a1 (L) Programable Equalizer Band4 Coefficient-a1 (H) Record ALC Attack Time Control Record ALC Decay Time Control Record ALC Target Level Control Record ALC Min Gain Control Record ALC Satulation Detect Control Record ALC Zero Cross Time Out Control Playback ALC Attack Time Control Playback ALC Decay Time Control Note note1 note1 note1 note1 note1 note1 note1 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV INDEX R W 0xc4 0xc5 0xc6 0xc8 0xc7 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xdc 0xe8 b07 (Initial) - b06 b05 b04 b03 - - 1 - 0 - 1 - 0 - 0 0 0 1 0 0 0 1 0 - 0 - 0 - 0 - 1 PALCVOL 0 RALCFREN 0 PALCFREN 0 - RALCFRTH 0xcf PALCFRTH 0xdd 0xe9 ZDTIME www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 b02 PALCLVL 0 40/86 0 0 - b01 b00 1 PALCMINGAIN 0 1 0 0 0 PALCZCTM 0 0 RALCFRSP 0 1 PALCFRSP 0 1 ZDEN 0 MIN2EN MIN1EN 0 1 Register Name Note Playback ALC Target Level Control Playback ALC Min Gain Control Playback ALC Volume Control Playback ALC ZeroCross TimeOut ALC Fast Release Setting Playback Limiter Fast Release Setting Zero Detection Setting MIC select Control note1 note1 note1 note1 note1 note1 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV The following registers are accessible at the time of MAPCON=0x1 of the Register Map Control register (0x1c/0x1d). INDEX R W 0x02 0x03 0x04 0x07 0x08 0x09 0x0c 0x0e 0x10 b06 b05 b04 b03 b02 b01 b00 - - - - 0 FPLLM 0 0 0 - 0 - 0 - 0 - 0 - 0 - 0 FPLLNH 0 0 0 0 FPLLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 - 0 - 0 - 0 0 0 0 0x05 0x06 0x0a b07 (Initial) - 0x1d 0x20 0x21 0x22 0x23 0x24 0x25 0x27 0x28 0x29 0x60 0x61 0x62 0x63 0 TCHSEN 0 0 0x64 0x65 0x82 0x83 0x84 0x85 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xda 0xdb 0xde 0xdf 0 0 0 0 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 FPLL F Setting(L) FPLL F Setting(H) FPLL F_D Setting(L) FPLLFDH 0 0x26 FPLL D Setting FPLLFDL 0x11 0x1c FPLL N Setting(H) FPLLFH 0x0f 0x13 FPLL N Setting(L) FPLLFL 0x0d 0 1 - FPLL F_D Setting(H) FPLLV 0 0 0 0 MAPCON 0 0 SCEN 0 SCTHRH 0 0 0 0 0 0 0 SCTHRM 0 0 0 0 0 0 0 SCTHRL 0 0 0 0 0 0 0 SCGAIN 0 0 1 TCHA2 TCHA1 TCHA0 TCHRSEL TCHMODE 1 1 1 1 0 0 ADCR1 0 0 0 0 0 0 0 ADCR2 0 0 0 HPRIN2EN HPRIN1EN HPLIN1EN 0 0 0 SPVOL SPIN2EN SPIN1EN 0 0 0 0 PLPFOD PLPFEN 0 0 PLPFC0L 0 0 0 0 0 0 0 PLPFC0H 0 0 0 0 0 0 0 RLPFOD RLPFEN 0 0 RLPFC0L 0 0 0 0 0 0 0 RLPFC0H 0 0 0 0 0 0 0 NGEN 0 NGMINGAIN 1 0 1 0 0 1 1 NGTH 0 1 0 0 1 0 NGTHHYS 0 1 0 NGSLOPE 0 0 1 0 1 0 0 NGGAINSTEP 1 0 NGENVAVE NGZTIM 0 0 1 0 0 0 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 Note FPLL M setting FPLLNL 0x0b 0x12 Register Name 41/86 FPLL V setting RegisterMAP Control Soft Clip Enable Soft Clip Threshold H Soft Clip Threshold M Soft Clip Threshold L Soft Clip Gain Touch ADC Control Touch ADC result1 Touch ADC result2 Headphone input Select Control SPAMP input Control Play Programable LPF Setting Play Programable LPF Coef (L) Play Programable LPF Coef (H) Rec Programable LPF Setting Rec Programable LPF Coef (L) Rec Programable LPF Coef (H) Noise Gate Setting Noise Gate Minimum Gain Noise Gate Threshold Noise Gate Threshold Hysteresis Noise Gate Slope Noise Gate Gain Step Noise Gate Time Setting note1 note1 note1 note1 note1 note1 note1 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV INDEX R W 0xea 0xeb 0xec 0xee 0xf0 0xf2 0xf4 b07 (Initial) b06 b05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b04 b03 b02 b01 b00 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NGFDOUT NGFDIN 0xed 0xef 0xf1 0xf3 0xf5 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 1 0 NGENVMONL[7:0] 0 0 NGENVMONL[15:8] 0 0 NGENVMONR[7:0] 0 0 NGENVMONR[15:8] 0 0 NGGAINMON 0 0 42/86 Register Name Note Noise Gate Fade Control Noise Gate Envelope Monitor Lch(L) Noise Gate Envelope Monitor Lch(H) Noise Gate Envelope Monitor Rch(L) Noise Gate Envelope Monitor Rch(H) Noise Gate Gain Monitor note1 note1 note1 note1 note1 note1 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV The following registers are accessible at the time of MAPCON=0x2 of the Register Map Control register (0x1c/0x1d). INDEX R W 0x00 0x01 0x04 0x05 0x12 0x13 0x1c 0x1d 0x24 0x25 0x26 0x27 0x28 b07 (Initial) 0 - 0x29 0 0x2a 0x2c 0x2e 0x2b 0x2d 0 - 0x2f 0x04 0x05 0x12 0x13 0x1c 0x1d 0x46 0x47 0x4c 0x4d 0x4e 0x4f 0x5c 0x5d 0x66 0x67 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0 - b06 b05 1 P2BLPF1A 0 0 P2BGAINBSA 0 0 P2BGAINEVA 0 0 P2BLPF1B 0 0 P2BGAINBSB 0 0 P2BGAINEVB 0 0 1 HPF2CSELB 0 0 0 SEMODE[7] 0 HPF2ODB 0 0 0 EQ4ENB 0 0 0 EQ3ENB 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 b04 b03 - - 0 0 0 0 0 0 0 0 0 0 0 - b02 b01 b00 Register Name EXMODE 1 HPLSEN 1 1 AREFI1EN 1 MAPCON 0 0 P2BHPF1A 0 0 0 P2BLPF2A 0 0 0 P2BGAINODA 0 0 0 P2BHPF1B 0 0 0 P2BLPF2B 0 0 0 P2BGAINODB 0 0 0 HPLSEN 1 1 AREFI1EN 1 MAPCON 0 0 0 ＰＬHPF2CUTB ＰＬHPF2ODB ＰＬHPF2ENB 0 0 0 0 0 PHPF2C0LB 0 0 0 0 0 PHPF2C0HB 0 0 0 0 0 SEMODE[2:0] 0 0 0 EQ2ENB EQ1ENB EQ0ENB HPF2ENB HPF1ENB 0 0 0 0 1 Effect VOLB 1 1 1 1 1 PDATTB 1 1 1 1 1 EQGAIN0B 0 0 1 1 1 EQGAIN1B 0 0 1 1 1 EQGAIN2B 0 0 1 1 1 EQGAIN3B 0 0 1 1 1 EQGAIN4B 0 0 1 1 1 EQ0A0LB 0 0 0 0 0 EQ0A0HB 0 0 0 0 0 EQ0A1LB 0 0 0 0 0 EQ0A1HB 0 0 0 0 0 EQ1A0LB 0 0 0 0 0 EQ1A0HB 0 0 0 0 0 EQ1A1LB 0 0 0 0 0 EQ1A1HB 0 0 0 0 0 EQ2A0LB 0 0 0 0 0 EQ2A0HB 0 0 0 0 0 EQ2A1LB 0 0 0 0 0 EQ2A1HB 0 0 0 0 0 EQ3A0LB 0 0 0 0 0 43/86 Note PLL External Components Setting Register Audio Analog Control2 Audio Analog Contrl1 RegisterMAP Control P2 Bass+ Parameter0A P2 Bass+ Parameter1A P2 Bass+ Parameter2A P2 Bass+ Parameter0B P2 Bass+ Parameter1B P2 Bass+ Parameter2B Audio Analog Control2 Audio Analog Contrl1 RegisterMAP Control Play HPF2B Play Programable HPF2 CoefL B Play Programable HPF2 CoefH B Sound Effect Mode B Filter Func Enable B Playback Effect Volume Control B Playback Digital Attenuator Control B EQ gain Band0 B EQ gain Band1 B EQ gain Band2 B EQ gain Band3 B EQ gain Band4 B EQ Band0 Coef0L B EQ Band0 Coef0H B EQ Band0 Coef1L B EQ Band0 Coef1H B EQ Band1 Coef0L B EQ Band1 Coef0H B EQ Band1 Coef1L B EQ Band1 Coef1H B EQ Band2 Coef0L B EQ Band2 Coef0H B EQ Band2 Coef1L B EQ Band2 Coef1H B EQ Band3 Coef0L B TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV INDEX R W 0x98 0x99 0x9a b07 (Initial) b06 b05 b04 0 0 0 0 0 0 0 0 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 b02 b01 b00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ3A0HB 0x9b 0x9c b03 EQ3A1LB EQ3A1HB 0 0 0 0 EQ4A0LB 0 0 0 0 EQ4A0HB 0 0 0 0 EQ4A1LB 0 0 0 0 EQ4A1HB 0 0 0 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 0 44/86 Register Name Note EQ Band3 Coef0H B EQ Band3 Coef1L B EQ Band3 Coef1H B EQ Band4 Coef0L B EQ Band4 Coef0H B EQ Band4 Coef1L B EQ Band4 Coef1H B TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Register details explanation Note: “-” indicates a reserved bit. They return “0” for read. Write “0” to the bit every time. If “1” is written to this bit, the operations cannot be guaranteed. Don’t write data to empty INDEX or register bit to guarantee normal operation. A function with (*)bit doesn’t need internal clock to change state. Sampling Rate Setting Register MAPCON 0x0 INDEX R W 0x00 0x01 b07 (Initial) - b06 b05 b04 b03 b02 - - - 0 0 b01 b00 0 0 SR This register sets the sampling rate of the recording/playback. Please perform the change of this register level in RECPLAY=0x0) at a recording/playback stop. SR [3:0] Setting 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Explanation 8kHz 11.025 kHz 12kHz 16kHz 22.05 kHz 24kHz 32kHz 44.1 kHz 48kHz Clock Enable Register MAPCON 0x0 INDEX R W 0x0c 0x0d b07 (Initial) TCLKEN 0 b06 b05 b04 b03 b02 b01 b00 - - - - PLLOE 0 PLLEN 0 MCLKEN 0 This register is a register to control the operation of the clock. MCLKEN This bit sets permission / stop of the input of the MCLKI terminal. The input logic of the MCLKI terminal becomes invalid at the time of the stop and clock is not transmitted to the LSI inside. Setting Explanation MCLKI terminal input stop 0 A clock stops at the input first grade of the terminal 1 MCLKI terminal input permission PLLEN This bit sets movement / stop of PLL. Setting Explanation 0 PLL stop 1 PLL movement After setting the PLL Setting register, please set PLLEN bit to "1". PLLOE This bit is to set the status of PLL output. Set this bit to “1” after PLL operation has stabilized. Also, this bit must be set to “1” if PLL is not used, otherwise internal clock cannot be provided. Setting Explanation 0 The PLL output is put under ban 1 PLL output permission TCLKEN This bit sets the clock for the touch panel interface circuit. TCLKEN Explanation 0 Disable clock for the touch panel interface. 1 Enable clock for the touch panel interface. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 45/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Clock Input / Output Control Register INDEX MAPCON 0x0 R W 0x0e 0x0f b07 (Initial) b06 b05 b04 - - - 0 b03 b02 b01 b00 0 CLKSEL 0 0 PLLISEL 0 This register is to select internal clock. It is to use or not use and to create MCLKI input or internal clock divided PLL. CLKSEL[2:0] Choose a clock to be use Setting Explanation Using PLL lets you output 256fs clock from PLL. 0x0 The PLL output is just used inside this LSI. Using PLL lets you output 512fs clock from PLL. 0x2 The clock that is divided by 1/2 the PLL output is used inside this LSI. Using PLL lets you output 1024fs clock from PLL 0x3 The clock that is divided by 1/4 the PLL output is used inside this LSI. Input 256fs clock to MCLKI terminal and PLL is not used. 0x4 MCLKI terminal input is just used in this LSI. Input 512fs clock to MCLKI terminal and PLL is not used. 0x6 The clock that is divided by ½ the MCLKI terminal input is used inside this LSI. Input 1024fs clock than MCLKI terminal and use it without using PLL. 0x7 The clock that is divided by 1/4 the MCLKI terminal input is used inside this LSI. PLLISEL[1:0] When this bit chooses to input clock into PLL and does not use PLL, please set register to 0x0. Setting Explanation 0x0 Prohibited from setting 0x1 Use MCLKI terminal input 0x2 Use BCLK terminal input Software Reset Register INDEX MAPCON 0x0 R W 0x10 0x11 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - - - SOFTRST 0 This register is for software reset. CPU interface and this register are reset by writing SOFTRST bit to “1”. And then, write “0” for releasing reset. Record/Playback Running Control Register INDEX MAPCON 0x0 R W 0x12 0x13 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - 0 RECPLAY 0 0 This register controls start / stop of the recording/playback operation of the LSI. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 46/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV RECPLAY [2:0] This bit controls start / stop of the recording/playback operation of the LSI and it is feasible by recording and reproduction at the same time and monitor recording data from the reproduction course, and please refer to "state transition item about the recording reproduction control" for the transition between recording/playback states again. Transition between other states is prohibited. Please move to the next movement once by all means after having let recording/playback movement make a stop (RECPLAY=0x0). TCLKEN Explanation Sound Stop STATE 0x0 Stop recording and playback. Rec STATE 0x1 Recording start. Microphone input is converted from analog to digital, and transferred through SAI. Play STATE 0x2 Playback start. SAI received data is converted from digital to analog and output from playback path. Rec and Play STATE. Simultaneously Recording and Playback start. Microphone input is converted from 0x3 analog to digital, and transferred through SAI and SAI received data is converted from digital to analog and output from playback path. Monitor STATE. Monitoring the recording sound start. Microphone input is converted from analog to 0x7 digital, and transferred through SAI and this data is converted from digital to analog and output from playback path. MIC Input Charging Time Register INDEX MAPCON 0x0 R W 0x14 0x15 b07 (Initial) b06 b05 b04 b03 - - 0 0 0 b02 b01 b00 0 0 MCTIME 0 This register is to select the wait time for microphone input load charge. The LSI work recording signal or playback signal are mute when from RECPLAY is changed from 0x0 until MCTIME. This time contains required time of initializing DSP that is 40/fs. It must be waited the setting time to start recording or playback. MCTIME is valid at playback. If it is necessary to start up earlier on playback, please set MCTIME to 0x00. It is minimum time. . MCTIME [5:0] Setting fs conversion Time (fs=48kHz) 0x00 40/fs 0.8ms 0x01 128/fs 2.7ms 0x02 256/fs 5.3ms 0x03 384/fs 8.0ms 0x04 - 0x3D (128/fs / step) : 0x3E 7936/fs 165.3ms 0x3F 8064/fs 168.0ms Note) the waiting time for microphone input load charge It is a recommended value of MIN1 coupling capacitor at the charge time. Charge waiting time Capacitor Charge waiting time (6 τ) capacity 0.1µF 16ms 0.22µF 36ms * Charge time is proportional to capacity of capacitor. Register MAP Control Register INDEX MAPCON ALL R W 0x1c 0x1d b07 (Initial) b06 b05 b04 b03 b02 b01 - - - - - - 0 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 47/86 b00 MAPCON 0 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV MAPCON This register controls register MAP. Setting 0x0 It is accessible to register MAP0 0x1 It is accessible to register MAP1 0x2 It is accessible to register MAP2 0x3 This is prohibited from setting Explanation Analog Reference Power Management Register INDEX MAPCON 0x0 R W 0x20 0x21 b07 (Initial) b06 b05 b04 b03 b02 b01 HPREN 0 HPLEN 0 - - HPVDDEN 0 MICBEN 0 0 b00 VMIDCON 0 This register controls headphones amplifier, LDO for the charge pump, the power-up / down of the hole Rch standard voltage generation circuit. VMIDCON [1:0] These bits control power up and down of the VMID generation circuit. Power up time can be reduced by using high speed mode. VMID generation circuit should be changed to normal mode after high speed mode. Setting Explanation 0x0 power down 0x1 high speed mode power up 0x2 normal mode power up MICBEN It controls Microphone bias circuit. Setting 0 Power down 1 Power up Explanation HPVDDEN It controls HPAMP LDO for the charge pump. Setting 0 Disables 1 Enables Explanation HPLEN It controls HPAMP. When using headphone, please set HPLEN/HPREN to "1". Setting Explanation 0 Disable(HPL) 1 Enable(HPL) HPREN It controls HPAMP. When using headphones , please set HPLEN/HPREN "1". Setting Explanation 0 Disable(HPR) 1 Enable(HPR) Analog Input Power Management Register MAPCON 0x0 INDEX R W 0x22 0x23 b07 (Initial) - b06 b05 b04 b03 b02 b01 b00 - PGAATT 0 - PGAEN 0 - ADCEN 0 - This register controls the power-up / down of analog circuit. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 48/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV ADCEN It controls power-up / down of the ADC. Setting Explanation 0 ADC power down 1 ADC power up PGAEN It controls the power-up / down of the microphone amplifier. Setting Explanation 0 Microphone amplifier power down 1 Microphone amplifier power up PGAATT It controls the gain of the microphone amplifier. Setting Explanation 0 Normal mode (0dB) 1 Attenuation mode (-9dB) DAC Power Management Register INDEX MAPCON 0x0 R W 0x24 0x25 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - DACREN 0 DACLEN 0 - This register controls power-up / down of the DAC. DACLEN It controls the power-up / down of the DAC left. Setting Explanation 0 power down 1 power up DACREN It controls the power-up / down of the DAC right. Setting Explanation 0 power down 1 power up Speaker Amplifier Power Management Register MAPCON 0x0 INDEX R W 0x26 0x27 b07 (Initial) SPMDSEL 0 b06 b05 b04 b03 b02 b01 b00 - - AVREN 0 COEFSEL 0 1 SPEN 0 AVLEN 0 This register controls speaker amplifier volume’s power-up / down. b02 is H fix. AVLEN It controls power-up / down of the Lch analog volume. AVLEN Explanation 0x0 Lch analog volume power down 0x1 Lch analog volume power up SPEN I control the power-up / down of the speaker amplifier. SPEN Explanation 0x0 Speaker amplifier power down 0x1 Speaker amplifier power up www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 49/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV COEFSEL In BU26154, an A side, a B side prepare filter setting at the time of the reproduction, a volume setting register. register value of the A side, in the case of "1", I use a register level of the B side when this bit is "0". COEFSEL Explanation 0x0 It uses the register A side. 0x1 It uses the register B side. The AVREN It controls power-up / down of the Rch analog volume. AVREN Explanation 0x0 Rch analog volume power down 0x1 Rch analog volume power up SPMDSEL It sets the speaker amplifier to D class or AB class. At the time of the change, set SPEN=0 before setting SPMDSEL. SPMDSEL Explanation 0x0 Set speaker amplifier to AB-class. 0x1 Set speaker amplifier to D-class. Thermal Shutdown Control Register MAPCON 0x00 INDEX R W 0x2c 0x2d b07 (initial) - b06 b05 b04 b03 b02 b01 b00 - - - - - - TSDEN 1 TSDEN It controls a thermal shut down function. Setting Explanation 0x0 disable 0x1 enable Zero Cross Comparator Power Management Register INDEX MAPCON 0x0 R W 0x2e 0x2f b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - - ZCEN 0 - b00 This register sets ON/OFF of the zero cross function of the digital volume. ZCEN This function is effective for EFFECT VOLUME and RDATT Setting Explanation 0 disable 1 enable MICBIAS Voltage Control Register INDEX MAPCON 0x0 R W 0x30 0x31 b07 (Initial) b06 b05 b04 b03 b02 b01 - - - - - - 0 MICBCON 0 This register sets the output voltage reading of the microphone bias. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 50/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV MICBCON [1:0] These bits are to set the MICBIAS. Set the MICBIAS voltage less than HVDD x 0.85. Setting The output voltage 0x0 REGOUT / 2 x 1.67V 0x1 REGOUT / 2 x 2.22V 0x2 REGOUT / 2 x 2.78V 0x3 REGOUT / 2 x 3.33V Analog Volume Control Register INDEX MAPCON 0x0 R W 0x3a 0x3b b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - 0 1 AVVOL 0 1 0 This register sets the Gain of the analog volume of Lch and Rch. The fader function of the AMP Volume Control Function Enable register is also available. AVOL[5:0] AVOL[5:0] Gain[dB] AVOL[5:0] Gain[dB] 0x3Fto0x1a - 0x09 -2.0 0x19 +18.0 0x08 -4.0 0x18 +17.0 0x07 -6.0 0x17 +16.0 0x06 -8.0 0x16 +15.0 0x05 -12.0 0x15 +14.0 0x04 -16.0 0x14 +13.0 0x03 -20.0 0x13 +12.0 0x02 -24.0 0x12 +11.0 0x01 -28.0 0x11 +10.0 0x00 MUTE 0x0f +8.0 0x0e +7.0 0x0d +6.0 0x0c +4.0 0x0b +2.0 0x0a 0.0 Playback Digital Attenuator Control Register INDEX MAPCON 0x0 R W 0x3e 0x3f b07 (Initial) b06 b05 b04 b03 b02 b01 b00 1 1 1 1 1 1 1 1 b03 b02 b01 b00 1 1 1 PDATT Playback Digital Attenuator Control Register B INDEX MAPCON 0x2 R W 0x72 0x73 b07 (Initial) b06 b05 b04 1 1 1 1 PDATTB 1 PDATT[7:0]/ PDATTB[7:0]/ This register sets the Gain of the digital volume in the case of COEFSEL=0, the register level of PDATT is effective. In the case of COEFSEL=1, the register level of PDATTB is effective. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 51/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV PDATT/ PDATTB PDATT [7:0] Gain (dB) PDATT [7:0] Gain (dB) PDATT [7:0] Gain (dB) 0x93 -54.0 0xB8 -35.5 0xDD -17.0 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F Gain (dB) This is prohibited from setting MUTE -71.5 -71.0 -70.5 -70.0 -69.5 -69.0 -68.5 -68.0 -67.5 -67.0 -66.5 -66.0 -65.5 -65.0 -64.5 -64.0 -63.5 -63.0 -62.5 -62.0 -61.5 -61.0 -60.5 -60.0 -59.5 -59.0 -58.5 -58.0 -57.5 -57.0 -56.5 -56.0 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 -53.5 -53.0 -52.5 -52.0 -51.5 -51.0 -50.5 -50.0 -49.5 -49.0 -48.5 -48.0 -47.5 -47.0 -46.5 -46.0 -45.5 -45.0 -44.5 -44.0 -43.5 -43.0 -42.5 -42.0 -41.5 -41.0 -40.5 -40.0 -39.5 -39.0 -38.5 -38.0 -37.5 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 -35.0 -34.5 -34.0 -33.5 -33.0 -32.5 -32.0 -31.5 -31.0 -30.5 -30.0 -29.5 -29.0 -28.5 -28.0 -27.5 -27.0 -26.5 -26.0 -25.5 -25.0 -24.5 -24.0 -23.5 -23.0 -22.5 -22.0 -21.5 -21.0 -20.5 -20.0 -19.5 -19.0 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0x90 -55.5 0xB5 -37.0 0xDA -18.5 0xFF -16.5 -16.0 -15.5 -15.0 -14.5 -14.0 -13.5 -13.0 -12.5 -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 (Prohibit setting) 0x91 0x92 -55.0 -54.5 0xB6 0xB7 -36.5 -36.0 0xDB 0xDC -18.0 -17.5 0x00 - to 0x6E Play HPF2 Setting Register INDEX MAPCON 0x0 R W 0x46 0x47 b07 (Initial) b06 b05 - - HPF2CSEL 0 b04 b03 b02 0 PLHPF2CUT 0 0 b01 b00 PLHPF2OD PLHPF2EN 0 0 Play HPF2 Setting Register B This register is a setting register of HPF for the reproduction. In the case of COEFSEL=0, PLHPF2EN, PLHPF2OD, PLHPF2CUT, the register level of HPF2CEL are effective. In the case of COEFSEL=1, PLHPF2ENB, PLHPF2ODB, PLHPF2CUTB, the value of the HPF2CELB register become effective. PLHPF2EN/ PLHPF2ENB This bit is enables HPF for the reproduction. PLHPF2EN/ Explanation PLHPF2ENB 0 Disable 1 Enable www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 52/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV PLHPF2OD/ PLHPF2ODB This bit sets the degree of HPF for the reproduction. PLHPF2OD/ Explanation PLHPF2ODB 0 The second order 1 The first order PLHPF2CUT/ PLHPF2CUTB This bit sets the cut-off frequency of HPF for reproduction. In the case of "0", HPF2CEL becomes effective for setting this bit. PLHPF2CUT/ Fs=8,16,32kHz PLHPF2CUTB 0x00 80Hz 0x01 100Hz 0x02 130Hz 0x03 160Hz 0x04 200Hz 0x05 260Hz 0x06 320Hz 0x07 400Hz HPF2CEL/ HPF2CELB I make HPF at the time of the reproduction programmable, or I make it parametric, or this bit sets it. HPF2CEL/ Explanation HPF2CELB 0 PLHPF2CUT is effective. 1 PHPF2COEFL/H is effective. Amplifier Volume Control Function Enable Register INDEX MAPCON 0x0 R W 0x48 0x49 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - - AVMUTE 0 AVFADE 0 This register controls the fading function of the analog volume. AVFADE It sets the fading function of the analog volume to ON/OFF. AVFADE Explanation Fading function OFF When a register set point of AVOL is just used for a real Volume 0 price and wants to do it and changes a value, setting of the analog volume is updated immediately. Fading function ON When a register set point of AVOL was updated, a gain of the 1 analog volume changes by a +/-1 step towards a register set point after the update in step time for AVFCON register setting. AVMUTE When this is set, mute becomes effective for the analog volume at the time of reproduction. It can control fading for the mute shift by this bit by the analog volume forcibly by AVFADE. AVMUTE Explanation 0 As for the analog volume, a register set point of AVOL is effective. At the time of re-start: The analog volume is set to MUTE. It comes back to the setting Volume in AVOL by canceling it 1 because it writes it. This register level of AVOL cannot be replaced by the setting of this bit. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 53/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Amplifier Volume Fader Control Register INDEX MAPCON 0x0 R W 0x4a 0x4b b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - 0 AVFCON 0 0 This register controls the amplifier volume fade function. AVFCON[2:0] These bits are to set the volume change step time of the amplifier volume fade function. The volume changes step by step with this setting period. Step time is in proportion to sampling frequency (fs) as following table. AVFCON[2:0] 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 fs conversion 1/fs 4/fs 16/fs 64/fs 256/fs 1024/fs 4096/fs 16384/fs time(fs=48kHz) 20.8µs 83.3µs 333µs 1.33ms 5.33ms 21.3ms 85.3ms 341.ms Play Programmable HPF2 CoefL Register Play Programmable HPF2 CoefH Register MAPCON 0x0 0x0 INDEX R 0x4c 0x4e W 0x4d 0x4f b07 (Initial) b06 b05 0 0 0 0 0 0 b04 b03 b02 b01 b00 0 0 0 0 b01 b00 0 0 0 0 PHPF2C0L 0 0 0 PHPF2C0H 0 0 0 Play Programmable HPF2 CoefL Register B Play Programmable HPF2 CoefH Register B MAPCON 0x2 0x2 INDEX R 0x4c 0x4e W 0x4d 0x4f b07 (Initial) b06 b05 0 0 0 0 0 0 b04 b03 b02 PHPF2C0LB 0 0 0 PHPF2C0HB 0 0 0 It is the register settings of the programmable high path filter cut-off frequency for the reproduction. HPF2CSEL bit becomes effective when the register value is equal to "1". If COEFSEL=0, then the register level of PHPF2C0L, PHPF2C0H is effective. If COEFSEL=1, then the register level of PHPF2C0LB, PHPF2C0HB is effective. PHPF2C0L [7:0]/ PHPF2C0LB [7:0] PHPF2C0H [7:0]/ PHPF2C0HB [7:0] This sets the cut-off frequency of the programmable high path filter for the reproduction. Please refer for the setting method. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 54/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV DAC Clock Setting Register INDEX MAPCON 0x0 R W 0x58 0x59 b07 (Initial) b06 b05 - - 0 b04 OSRSEL 0 b03 b02 b01 b00 - - - - This register sets the DAC clock movement to be used in this LSI. OSRSEL [1:0] This register decides sampling frequency. Setting Explanation 0x0 8k,11.025k,12kHz 0x1 16k,22.05k,24kHz 0x2 32k,44.1k,48kHz 0x3 This is prohibited from setting Mic Interface Control Register INDEX MAPCON 0x0 R W 0x5a 0x5b b07 (Initial) 1 b06 b05 b04 b03 b02 b01 b00 MINVOL 0 0 - - - MINDIF 0 - This register controls the microphone input interface. MINDIF It sets the MIC movement mode. Setting 0 Single-end mode 1 Differential mode Explanation MINVOL This bit sets the Analog MIC volume. MINVOL Gain 0x00 6dB 0x01 9dB 0x02 12dB 0x03 15dB 0x04 18dB 0x05 21dB 0x06 24dB 0x07 27dB Sound Effect Mode Register INDEX MAPCON 0x0 b05 b04 b03 b02 b01 b00 W b07 (Initial) b06 R 0x5c 0x5d SEMODE[7] - - - - 0 SEMODE[2:0] 0 0 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 SEMODEB[7] - - - - 0 SEMODEB[2:0] 0 0 0 Sound Effect Mode Register B MAPCON 0x2 INDEX R 0x5c W 0x5d 0 If COEFSEL=0, then the register level of SEMODE is effective. becomes effective. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 55/86 If COEFSEL=1, then the value of the SEMODEB register TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV SEMODE [7]/SEMODEB [7] You choose a course putting Filter Block, and please refer to the clause of "the signal flow" of "the function explanation" for Filter Block. SEMODE[7]/ Explanation SEMODEB [7] 0 Use Filter Block on Recording path. 1 Use Filter Block on Playback path. SEMODE [2:0]/ SEMODEB [2:0] This sets distribution of EQ/Notch Filter. SEMODE[2:0]/ Explanation SEMODEB[2:0] 0x0 Notch5 band / EQ0 band 0x1 Notch4 band / EQ1 band 0x2 Notch3 band / EQ2 band 0x3 Notch2 band / EQ3 band 0x4 Notch1 band / EQ4 band 0x5 Notch0 band / EQ5 band When "0x01" is set, Band0 to Band3 filters Notch, and Band4 becomes the EQ. SAI Transmitter Control Register INDEX MAPCON 0x0 R W 0x60 0x61 b07 (Initial) b06 PCMFO24 1 1 b05 b04 b03 b02 b01 b00 FMTO 0 MSBO 0 ISSCKO 0 AFOO 0 DLYO 0 WSLO 0 This register controls the SAI transmission format setting. The RECPLAY bit of the Record/Playback Running Control register, please change this register in recording stop state (0x0), and please use it by setting again same as the SAI reception side (SAI Receiver Control register). WSLO You appoint LRCLK polarity at the time of the transmission of this LSI, and please set this bit in "1" in (FMTO at the time of "1") in a transfer mode by all means in the frame same period. Setting Explanation Left channel transmission at SAI_LRCLK is “L” level; right 0 channel transmission at SAI_LRCLK is “H” level. Left channel transmission at SAI_LRCLK is “H” level; right 1 channel transmission at SAI_LRCLK is “L” level.l DLYO This bit appoints 1 clock delay existence / nothing of transmission data. Setting Explanation 0 Serial data delay existence 1 Serial data delay nothing AFOO You appoint in front of filling / attacking the enemy from behind of transmission data, and, in the case of a slave mode, this bit is ignored, and it is in previous final stage is fixed, and please set this bit in "0" in (FMTO at the time of "1") in a transfer mode by all means in the frame same period. Setting Explanation 0 Left-justify 1 Right-justify ISSCKO This bit sets BCLK terminal to 32fs/64fs. Setting 0 32fs 1 64fs Explanation MSBO This bit sets the MSB first /LSB first data transmission. Setting Explanation 0 MSB first 1 LSB first www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 56/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV FMTO This bit sets the transmission mode. Setting Explanation 0 LRCLK transfer mode 1 Frame synchronization transfer mode PCMFO24 This bit sets PCM format of the SAI transmission. Setting Explanation 0x2 16bit PCM 0x3 24bit PCM Other than the This is prohibited from setting above SAI Receiver Control Register INDEX MAPCON 0x0 R W 0x62 0x63 b07 (Initial) b06 PCMFI24 1 1 b05 b04 b03 b02 b01 b00 FMTI 0 MSBI 0 ISSCKI 0 AFOI 0 DLYI 0 WSLI 0 This register is a register controlling SAI reception format setting, and RECPLAY bit of the Record/Playback Running Control register, please change this register in recording stop state (0x0), and please use it by setting again same as the SAI transmission side (SAI Transmitter Control register). WSLI This bit selects LRCLK polarity of the LSI. This bit must be set to “1” when at Flame synchronous transfer mode (FMTI is “1”). Setting Explanation Left channel is received when SAI_LRCLK is “L” level, right 0 channel is received at SAI_LRCLK is “H” level. Left channel is received when SAI_LRCLK is “H” level, right 1 channel is received at SAI_LRCLK is “L” level. DLYI This bit specifies the existence for serial input data one clock delay of master device. Setting Explanation 0 Serial data delay existence 1 Serial data delay nothing AFOI This bit sets the receiving data to be Left-justify or Right-justify. This bit must be set to “0” when at Flame synchronous transfer mode (FMTI is “1”). Setting Explanation 0 Left-justify 1 Right-justify ISSCKI This bit sets the sampling frequency of SAI_BCLK pin. Setting Explanation 0 32fs 1 64fs MSBI This bit sets the SAI receiving data to be MSB-first or LSB-first. Setting Explanation 0 MSB first 1 LSB first FMTI This bit sets the receiving mode Setting Explanation 0 LRCLK transfer mode 1 Frame synchronization transfer mode www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 57/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV PCMFI24 This bit sets the SAI PCM receiving format. Setting Explanation 0x2 16bit PCM 0x3 24bit PCM Other than the This is prohibited from setting above SAI Mode select Register INDEX MAPCON 0x0 R W 0x64 0x65 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - BSWP 0 - - - MST 0 This register is a register setting a movement mode of SAI, and RECPLAY bit of the Record/Playback Running Control register, please change this register in recording stop state (0x0). MST It appoints whether this bit uses SAI with a master mode or a slave mode. Setting Explanation 0 Slave mode 1 Master mode BSWP As for this bit, it is done byte swap I2S data with PCM format by 16bitPCM without depending on the setting of the I2S Receiver Control/I2S Transmitter Control register at the time of setting when I set byte swap having I2S or not on the same side of transmission and reception data and there is byte swap and sets it. Setting Explanation There is no byte swap 0 (16bit data line up :15bit-8bit,7bit-0bit) (24bit data line up :23bit-16bit,15bit-8bit,7bit-0bit) There is byte swap 1 (16bit data line up :7bit-0bit,15bit-8bit) (24bit data line up :7bit-0bit,15bit-8bit 23bit-16bit) DSP Filter Function Enable Register INDEX MAPCON 0x0 R W 0x66 0x67 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 HPF2OD 0 EQ4EN 0 EQ3EN 0 EQ2EN 0 EQ1EN 0 EQ0EN 0 HPF2EN 0 HPF1EN 1 DSP Filter Function Enable Register INDEX MAPCON 0x0 R W 0x66 0x67 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 HPF2OD 0 EQ4EN 0 EQ3EN 0 EQ2EN 0 EQ1EN 0 EQ0EN 0 HPF2EN 0 HPF1EN 1 b05 b04 b03 b02 b01 b00 EQ3ENB 0 EQ2ENB 0 EQ1ENB 0 EQ0ENB 0 DSP Filter Function Enable Register B MAPCON 0x2 INDEX R 0x66 W 0x67 b07 b06 (Initial) HPF2ODB EQ4ENB 0 0 HPF2ENB HPF1ENB 0 1 This register sets the filter function of the digital code processing ON/OFF. If COEFSEL=0, then register level of HPF1/2EN, EQ0/1/2/3/4EN, HPF2OD is effective. HPF1/2ENB, EQ0/1/2/3/4ENB, HPF2ODB register becomes effective. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 58/86 If COEFSEL=1, then value of TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV HPF1EN/ HPF1ENB This bit is to set ON or OFF of a first-order high pass filter for DC cut. Do not change this bit during operation of the recording (0x13/0x14: RECPLAY=0x1, 0x3, or 0x7). If this bit is changed, the noise may be generated. When this IC being operated the playing (RECPLAY=0x2), this bit operating don't have effective. HPF1EN/ Explanation HPF1ENB 0 Primary high-pass filter OFF for the DC cut 1 Primary high-pass filter ON for the DC cut HPF2EN/ HPF2ENB This bit is to set ON or OFF of a second-order high pass filter for noise cut. Do not change this bit during operation of the recording (RECPLAY=0x1,0x3, or 0x7). If this bit is changed, the noise may be generated. The bit of HPF2EN is effective only when 0xA6/0xA7:RLPFEN is enable. HPF2EN/ Explanation HPF2ENB 0 Second high-pass filter OFF for noise reduction 1 Second high-pass filter ON for noise reduction EQ0EN/EQ0ENB This bit is to set ON or OFF of equalizer band 0. In case of changing this bit during recording and playback operation (RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then change the gain to 0dB. EQ0EN/ Explanation EQ0ENB 0 Equalizer band 0 OFF 1 Equalizer band 0 ON EQ1EN/EQ1ENB This bit is to set ON or OFF of equalizer band 1. In case of changing this bit during recording and playback operation (0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then change the gain to 0dB. EQ1EN/ Explanation EQ1ENB 0 Equalizer band 1 OFF 1 Equalizer band 1 ON EQ2EN/EQ2ENB This bit is to set ON or OFF of equalizer band 2. In case of changing this bit during recording and playback operation (0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then change the gain to 0dB. EQ2EN/ Explanation EQ2ENB 0 Equalizer band 2 OFF 1 Equalizer band 2 ON EQ3EN/EQ3ENB This bit is to set ON or OFF of equalizer band 3. In case of changing this bit during recording and playback operation (0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then change the gain to 0dB. EQ3EN/ Explanation EQ3ENB 0 Equalizer band 3 OFF 1 Equalizer band 3 ON EQ4EN/EQ4ENB This bit is to set ON or OFF of equalizer band 4. In case of changing this bit during recording and playback operation (0x13/0x14: RECPLAY=0x1, 0x2, 0x3, or 0x7), enables digital volume fade function (0x68/0x69: DVFADE=1) and then change the gain to 0dB. EQ4EN/ Explanation EQ4ENB 0 Equalizer band 4 OFF 1 Equalizer band 4 ON www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 59/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV HPF2OD/HPFODB This bit is to set number of high pass filter order (HPF2EN bit) for noise cut. In recording or playback operation(0x13/0x14: RECPLAY≠0）,do not change this bit. If this bit is changed, the noise may be generated. HPF2OD/ Explanation HPF2ODB 0 The second filter 1 Primary filter Digital Volume Control Function Enable Register INDEX MAPCON 0x0 R W 0x68 0x69 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - DVMUTE 0 DVFADE 0 - RALCEN 0 PALCEN 0 This register sets ON/OFF of digital, the Volume control function. PALCEN This bit is to set ON or OFF of the playing ALC. It must not be wrote during recording and playback operation (0x13/0x14: RECPLAY=0x1, 0x3, or 0x7). If this bit was set as the operation, this IC cannot guarantee correct operating. PALCEN Explanation 0 Reproduction ALC OFF 1 Reproduction ALCON RALCEN This bit is to set ON or OFF of the recording ALC. It must not be wrote during recording and playback operation (0x13/0x14: RECPLAY=0x2). If this bit was set as the operation, this IC cannot guarantee correct operating. RALCEN Explanation 0 Recording ALC OFF 1 Recording ALC ON DVFADE This bit is to set ON or OFF of the digital volume fade function. The fade function is effective for recording/playback digital volume and equalizer gain. DVFADE Explanation Fading Function OFF: The register setting value of RDATT, PDATT and EQGAIN0 to 3 0 is used actual volume value as it is. Therefore the value is effective immediate. Fading Function ON: The volume is changing to the register setting value of RDATT, 1 PDATT and EQGAIN0 to 3 with 1 step per DVFCON register step time. DVMUTE This bit is to set MUTE of the digital volume. This mute function is effective for the recording digital volume at recording and effective for playback digital volume at playback. The fade function by DVFADE is effective against the volume change by this bit. DVMUTE Explanation 0 Register value of RDVOL and PDATT is effective. Digital volume is set to MUTE. Register value of RDVOL and PDATT cannot be changed by this 1 bit, the volume is resumed by releasing this bit (DVMUTE=0) to the original setting value of RDVOL and PDVOL. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 60/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Mixer & Volume Control Register INDEX MAPCON 0x0 R W 0x6a 0x6b b07 (Initial) b06 0 0 b05 b04 b03 0 0 DVFCON b02 b01 RMCON 0 b00 LMCON 0 0 0 This register controls L/R mixer processing at the time of the SAI reception and a fading function of the digital Volume. LMCON[1:0] This bit sets the input channel of SAI reception data of the DAC (Lch). Setting Explanation 0x0 I use L 0x1 I use R 0x2 I use (L+R) 0x3 I use (L+R)/2 RMCON[1:0] This bit sets it about SAI reception data which channel you input into DAC (Rch). Setting Explanation 0x0 I use R 0x1 I use L 0x2 I use (L+R) 0x3 I use (L+R)/2 DVFCON[3:0] These bits are to set the volume change step time of the digital volume fade function. The volume changes step by step (0.5dB) with this setting period. Step time is in proportion to sampling frequency (fs) as following table. Setting fs conversion Time(fs=48kHz) 0x0 1/fs 20.8µs 0x1 2/fs 41.7µs 0x2 4/fs 83.3µs 0x3 8/fs 167µs 0x4 16/fs 333µs 0x5 32/fs 667µs 0x6 64/fs 1.33ms 0x7 128/fs 2.67ms 0x8 256/fs 5.33ms 0x9 512/fs 10.7ms 0xA 1024/fs 21.3ms 0xB 2048/fs 42.7ms 0xC 4096/fs 85.3ms 0xD 8192/fs 171ms 0xE 16384/fs 341ms Record Digital Attenuator Control Register INDEX MAPCON 0x0 R W 0x6c 0x6d b07 (Initial) b06 b05 b04 1 1 1 1 b03 b02 b01 b00 1 1 1 1 RDVOL This register sets digital Volume Gain of the recording course. MUTE could be set from -71.5dB to 0.0dB by 0.5dB step. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 61/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV RDATT[7:0] Setting Gain(dB) This is 0x00 prohibited 0x6E from setting 0x6F MUTE 0x70 -71.5 0x71 -71.0 0x72 -70.5 0x73 -70.0 0x74 -69.5 0x75 -69.0 0x76 -68.5 0x77 -68.0 0x78 -67.5 0x79 -67.0 0x7A -66.5 0x7B -66.0 0x7C -65.5 0x7D -65.0 0x7E -64.5 0x7F -64.0 0x80 -63.5 0x81 -63.0 0x82 -62.5 0x83 -62.0 0x84 -61.5 0x85 -61.0 0x86 -60.5 0x87 -60.0 0x88 -59.5 0x89 -59.0 0x8A -58.5 0x8B -58.0 0x8C -57.5 0x8D -57.0 0x8E -56.5 0x8F -56.0 0x90 -55.5 0x91 -55.0 0x92 -54.5 Setting Gain(dB) Setting Gain(dB) Setting Gain(dB) 0x93 -54.0 0xB8 -35.5 0xDD -17.0 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 -53.5 -53.0 -52.5 -52.0 -51.5 -51.0 -50.5 -50.0 -49.5 -49.0 -48.5 -48.0 -47.5 -47.0 -46.5 -46.0 -45.5 -45.0 -44.5 -44.0 -43.5 -43.0 -42.5 -42.0 -41.5 -41.0 -40.5 -40.0 -39.5 -39.0 -38.5 -38.0 -37.5 -37.0 -36.5 -36.0 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC -35.0 -34.5 -34.0 -33.5 -33.0 -32.5 -32.0 -31.5 -31.0 -30.5 -30.0 -29.5 -29.0 -28.5 -28.0 -27.5 -27.0 -26.5 -26.0 -25.5 -25.0 -24.5 -24.0 -23.5 -23.0 -22.5 -22.0 -21.5 -21.0 -20.5 -20.0 -19.5 -19.0 -18.5 -18.0 -17.5 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF -16.5 -16.0 -15.5 -15.0 -14.5 -14.0 -13.5 -13.0 -12.5 -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 Playback Effect Volume Control Register INDEX MAPCON 0x0 R W 0x70 0x71 b07 (Initial) b06 b05 1 1 1 b04 b03 Effect VOL 1 1 b02 b01 b00 1 1 1 b02 b01 b00 1 1 1 Playback Effect Volume Control Register B MAPCON 0x2 INDEX R 0x70 W 0x71 b07 (Initial) b06 b05 1 1 1 b04 b03 Effect VOLB 1 1 This register sets the digital Volume Gain of the reproduction course. If COEFSEL=0, then register level of Effect Vol is effective. If COEFSEL=1, then value of the Effect Vol B register becomes effective. MUTE could be set from -71.5dB to 0.0dB by 0.5dB step. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 62/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Effect Vol[7:0]/ Effect Vol B[7:0 Sets the Digital Volume Gain. Effect Vol/ Gain(dB) Setting Effect Vol B This is prohibited 0x93 0x00 - 0x6E from setting 0x6F MUTE 0x94 0x70 -71.5 0x95 0x71 -71.0 0x96 0x72 -70.5 0x97 0x73 -70.0 0x98 0x74 -69.5 0x99 0x75 -69.0 0x9A 0x76 -68.5 0x9B 0x77 -68.0 0x9C 0x78 -67.5 0x9D 0x79 -67.0 0x9E 0x7A -66.5 0x9F 0x7B -66.0 0xA0 0x7C -65.5 0xA1 0x7D -65.0 0xA2 0x7E -64.5 0xA3 0x7F -64.0 0xA4 0x80 -63.5 0xA5 0x81 -63.0 0xA6 0x82 -62.5 0xA7 0x83 -62.0 0xA8 0x84 -61.5 0xA9 0x85 -61.0 0xAA 0x86 -60.5 0xAB 0x87 -60.0 0xAC 0x88 -59.5 0xAD 0x89 -59.0 0xAE 0x8A -58.5 0xAF 0x8B -58.0 0xB0 0x8C -57.5 0xB1 0x8D -57.0 0xB2 0x8E -56.5 0xB3 0x8F -56.0 0xB4 0x90 -55.5 0xB5 0x91 -55.0 0xB6 0x92 -54.5 0xB7 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 Gain(dB) Setting Gain(dB) Setting Gain(dB) -54.0 0xB8 -35.5 0xDD -17.0 -53.5 -53.0 -52.5 -52.0 -51.5 -51.0 -50.5 -50.0 -49.5 -49.0 -48.5 -48.0 -47.5 -47.0 -46.5 -46.0 -45.5 -45.0 -44.5 -44.0 -43.5 -43.0 -42.5 -42.0 -41.5 -41.0 -40.5 -40.0 -39.5 -39.0 -38.5 -38.0 -37.5 -37.0 -36.5 -36.0 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC -35.0 -34.5 -34.0 -33.5 -33.0 -32.5 -32.0 -31.5 -31.0 -30.5 -30.0 -29.5 -29.0 -28.5 -28.0 -27.5 -27.0 -26.5 -26.0 -25.5 -25.0 -24.5 -24.0 -23.5 -23.0 -22.5 -22.0 -21.5 -21.0 -20.5 -20.0 -19.5 -19.0 -18.5 -18.0 -17.5 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF -16.5 -16.0 -15.5 -15.0 -14.5 -14.0 -13.5 -13.0 -12.5 -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 63/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV EQ Band0 Gain Setting Register EQ Band1 Gain Setting Register EQ Band2 Gain Setting Register EQ Band3 Gain Setting Register EQ Band4 Gain Setting Register MAPCON 0x0 INDEX R 0x74 W 0x75 0x0 0x76 0x77 0x0 0x78 0x79 0x0 0x7a 0x7b 0x0 0x7c 0x7d b07 (Initial) b06 b05 b04 1 1 1 0 b03 b02 b01 b00 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 EQGAIN0 EQGAIN1 1 1 1 0 EQGAIN2 1 1 1 0 EQGAIN3 1 1 1 0 EQGAIN4 1 1 1 0 0 1 1 1 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EQ Band0 Gain Setting Register B EQ Band1 Gain Setting Register B EQ Band2 Gain Setting Register B EQ Band3 Gain Setting Register B EQ Band4 Gain Setting Register B MAPCON 0x2 INDEX R 0x74 W 0x75 0x2 0x76 0x77 0x2 0x78 0x79 0x2 0x7a 0x7b 0x2 0x7c 0x7d EQGAIN0B 0 0 EQGAIN1B 0 0 EQGAIN2B 0 0 EQGAIN3B 0 0 EQGAIN4B 0 0 This register sets the gain of each band of the equalizer. If COEFSEL=0, then the register level of EQGAIN0 to 4 is effective. If COEFSEL=1, then value of the EQGAIN0B to EQGAIN4B register becomes effective. This register can set EQ gain from -71.5dB to 12.0dB(step by step 0.5dB). Also it can set MUTE. EQ can work as a notch filter by MUTE setting. EQGAIN/ Gain EQGAIN/ Gain EQGAIN/ Gain EQGAIN/ Gain EQGAINB (0dB) EQGAINB (0dB) EQGAINB (dB) EQGAINB (dB) 0 - to 4 [7:0] 0 - to4[7:0] 0 - to4[7:0] 0 - to4[7:0] 0x00 - to 0x57 MUTE 0x82 -50.5 0xAD -29.0 0xD8 -7.5 0x58 -71.5 0x83 -50.0 0xAE -28.5 0xD9 -7.0 0x59 -71.0 0x84 -49.5 0xAF -28.0 0xDA -6.5 0x5A -70.5 0x85 -49.0 0xB0 -27.5 0xDB -6.0 0x5B -70.0 0x86 -48.5 0xB1 -27.0 0xDC -5.5 0x5C -69.5 0x87 -48.0 0xB2 -26.5 0xDD -5.0 0x5D -69.0 0x88 -47.5 0xB3 -26.0 0xDE -4.5 0x5E -68.5 0x89 -47.0 0xB4 -25.5 0xDF -4.0 0x5F -68.0 0x8A -46.5 0xB5 -25.0 0xE0 -3.5 0x60 -67.5 0x8B -46.0 0xB6 -24.5 0xE1 -3.0 0x61 -67.0 0x8C -45.5 0xB7 -24.0 0xE2 -2.5 0x62 -66.5 0x8D -45.0 0xB8 -23.5 0xE3 -2.0 0x63 -66.0 0x8E -44.5 0xB9 -23.0 0xE4 -1.5 0x64 -65.5 0x8F -44.0 0xBA -22.5 0xE5 -1.0 0x65 -65.0 0x90 -43.5 0xBB -22.0 0xE6 -0.5 0x66 -64.5 0x91 -43.0 0xBC -21.5 0xE7 0.0 0x67 -64.0 0x92 -42.5 0xBD -21.0 0xE8 0.5 0x68 -63.5 0x93 -42.0 0xBE -20.5 0xE9 1.0 0x69 -63.0 0x94 -41.5 0xBF -20.0 0xEA 1.5 0x6A -62.5 0x95 -41.0 0xC0 -19.5 0xEB 2.0 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 64/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 -62.0 -61.5 -61.0 -60.5 -60.0 -59.5 -59.0 -58.5 -58.0 -57.5 -57.0 -56.5 -56.0 -55.5 -55.0 -54.5 -54.0 -53.5 -53.0 -52.5 -52.0 -51.5 -51.0 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC -40.5 -40.0 -39.5 -39.0 -38.5 -38.0 -37.5 -37.0 -36.5 -36.0 -35.5 -35.0 -34.5 -34.0 -33.5 -33.0 -32.5 -32.0 -31.5 -31.0 -30.5 -30.0 -29.5 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 -19.0 -18.5 -18.0 -17.5 -17.0 -16.5 -16.0 -15.5 -15.0 -14.5 -14.0 -13.5 -13.0 -12.5 -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 High Pass Filter2 Cut-off Control Register INDEX MAPCON 0x0 R W 0x7e 0x7f b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - 0 HPF2CUT 0 0 This register is to set the cut-off frequency of the high-pass filter for the noise reduction during recording. Don’t change the setting of this register under the filter processing concerned(HPF2EN="1" and RELPLAY=0x1,0x3 or 0x7). HPF2CUT[2:0] These set the cut-off frequency of the noise reduction high-pass filter during recording and the numerical value of below list expresses 1.5dB damping and 3dB damping frequency in each second order filter(HPF2OD="1") and one order filter (HPF2OD="0"). HPF2CUT [2:0] 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 fs=8kHz, 16kHz, 32kHz 80 100 130 160 200 260 320 400 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 Cut-off Frequency(Hz) fs=11.025kHz, 22.05kHz, 44.1kHz 110 138 179 221 276 358 441 551 65/86 fs=12kHz, 24kHz, 48kHz 120 150 195 240 300 390 480 600 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Programmable Equalizer Band0 Coefficient-a0 (L) Register Programmable Equalizer Band0 Coefficient-a0 (H) Register Programmable Equalizer Band0 Coefficient-a1 (L) Register Programmable Equalizer Band0 Coefficient-a1 (H) Register Programmable Equalizer Band1 Coefficient-a0 (L) Register Programmable Equalizer Band1 Coefficient-a0 (H) Register Programmable Equalizer Band1 Coefficient-a1 (L) Register Programmable Equalizer Band1 Coefficient-a1 (H) Register Programmable Equalizer Band2 Coefficient-a0 (L) Register Programmable Equalizer Band2 Coefficient-a0 (H) Register Programmable Equalizer Band2 Coefficient-a1 (L) Register Programmable Equalizer Band2 Coefficient-a1 (H) Register Programmable Equalizer Band3 Coefficient-a0 (L) Register Programmable Equalizer Band3 Coefficient-a0 (H) Register Programmable Equalizer Band3 Coefficient-a1 (L) Register Programmable Equalizer Band3 Coefficient-a1 (H) Register Programmable Equalizer Band4 Coefficient-a0 (L) Register Programmable Equalizer Band4 Coefficient-a0 (H) Register Programmable Equalizer Band4 Coefficient-a1 (L) Register Programmable Equalizer Band4 Coefficient-a1 (H) Register MAPCON 0x0 INDEX R 0x80 W 0x81 0x0 0x82 0x83 0x0 0x84 0x85 0x0 0x86 0x87 0x0 0x88 0x89 0x0 0x8a 0x8b 0x0 0x8c 0x8d 0x0 0x8e 0x8f 0x0 0x90 0x91 0x0 0x92 0x93 0x0 0x94 0x95 0x0 0x96 0x97 0x0 0x98 0x99 0x0 0x9a 0x9b 0x0 0x9c 0x9d 0x0 0x9e 0x9f 0x0 0xa0 0xa1 0x0 0xa2 0xa3 0x0 0xa4 0xa5 0x0 0xa6 0xa7 b07 (Initial) b06 b05 b04 0 0 0 0 b03 b02 b01 b00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ0A0L EQ0A0H 0 0 0 0 EQ0A1L 0 0 0 0 EQ0A1H 0 0 0 0 EQ1A0L 0 0 0 0 EQ1A0H 0 0 0 0 EQ1A1L 0 0 0 0 EQ1A1H 0 0 0 0 EQ2A0L 0 0 0 0 EQ2A0H 0 0 0 0 EQ2A1L 0 0 0 0 EQ2A1H 0 0 0 0 EQ3A0L 0 0 0 0 EQ3A0H 0 0 0 0 EQ3A1L 0 0 0 0 EQ3A1H 0 0 0 0 EQ4A0L 0 0 0 0 EQ4A0H 0 0 0 0 EQ4A1L 0 0 0 0 EQ4A1H 0 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 0 0 0 66/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV INDEX MAPCON 0x2 R W 0x7e 0x7f 0x2 0x80 0x81 0x2 0x82 0x83 0x2 0x84 0x85 0x2 0x86 0x87 0x2 0x88 0x89 0x2 0x8a 0x8b 0x2 0x8c 0x8d 0x2 0x8e 0x8f 0x2 0x90 0x91 0x2 0x92 0x93 0x2 0x94 0x95 0x2 0x96 0x97 0x2 0x98 0x99 0x2 0x9a 0x9b 0x2 0x9c 0x9d 0x2 0x9e 0x9f 0x2 0xa0 0xa1 0x2 0xa2 0xa3 0x2 0xa4 0xa5 b07 (Initial) b06 b05 b04 0 0 0 0 b03 b02 b01 b00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EQ0A0LB EQ0A0HB 0 0 0 0 EQ0A1LB 0 0 0 0 EQ0A1HB 0 0 0 0 EQ1A0LB 0 0 0 0 EQ1A0HB 0 0 0 0 EQ1A1LB 0 0 0 0 EQ1A1HB 0 0 0 0 EQ2A0LB 0 0 0 0 EQ2A0HB 0 0 0 0 EQ2A1LB 0 0 0 0 EQ2A1HB 0 0 0 0 EQ3A0LB 0 0 0 0 EQ3A0HB 0 0 0 0 EQ3A1LB 0 0 0 0 EQ3A1HB 0 0 0 0 EQ4A0LB 0 0 0 0 EQ4A0HB 0 0 0 0 EQ4A1LB 0 0 0 0 EQ4A1HB 0 0 0 0 These registers are to set the coefficients a0 and a1 of each five band programmable equalizer. One coefficients value is specified by two bytes data. The centre frequency and band width of the filter can be set by changing these register value. Please don’t change the register setting during corresponding filter operation EQ0A0L to EQ4A1H are became effective at COEFSEL=0 and EQ0A0LB to EQ4A1HB are became effective at COEFSEL=1. The detailed setting value is described in the Filter function. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 67/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Zero Detection Setting Register INDEX MAPCON 0x0 R W 0xdc 0xdd b07 (Initial) b06 0 0 b05 b04 b03 b02 b01 b00 0 - - - ZDEN 0 ZDTIME 0 This register controls zero detection for low power consumption mode. When zero detection is enable and "0" data are inputted in succession, a part of internal clock and speaker amplifier goes to disable to operate under low power consumption. Controlling a zero detection function for low power consumption mode movement, and enabling this function, some internal clocks stop it, and a speaker amplifier is disabled. When data, not 0 data, is input, the disable block starts operation again. In addition, the zero detection is effective only speaker amplifier playing mode. In the other modes, please set ZDEN bit in "0". ZDEN Enables/Disables the zero detection function. ZDEN Explanation 0x0 A zero detection function is disabled. 0x1 A zero detection function is enabled. ZEROTIM Sets "0" detection period. When "0" continues more than the following set points in succession with LCH/RCH, it becomes low power consumption mode. ZEROTIM Explanation 0x00 256/fs 0x01 512/fs 0x02 1024/fs 0x03 2048/fs 0x04 4096/fs 0x05 8192/fs 0x06 16384/fs 0x07 32768/fs 0x08 65536/fs 0x09 131072/fs 0x0a 262144/fs This is prohibited 0x0b to 0x0f from setting MIC select Control Register INDEX MAPCON 0x0 R W 0xe8 0xe9 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - - MIN2EN 0 MIN1EN 1 This register sets microphone input. MIN1EN Using MIN1 terminal in analog MIC. Setting Explanation 0 Does not use MIN1 terminal. 1 Use MIN1 terminal. MIN2EN Using MIN2 terminal in analog MIC. Please set it in "0" when in the differential mode. Setting Explanation 0 Does not use MIN2 terminal. 1 Use MIN2 terminal. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 68/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV FPLL M setting Register FPLL N Setting (L) Register FPLL N Setting (H) Register FPLL D Setting Register FPLL F Setting (L) Register FPLL F Setting (H) Register FPLL F_D Setting (L) Register FPLL F_D Setting (H) Register FPLL V setting Register INDEX MAPCON 0x1 R W 0x02 0x03 0x1 0x04 0x05 0x1 0x06 0x07 0x1 0x08 0x09 0x1 0x0a 0x0b 0x1 0x0c 0x0d 0x1 0x0e 0x0f 0x1 0x10 0x11 0x1 0x12 0x13 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - 0 FPLLM 0 0 FPLLNL 0 - 0 - 0 - 0 0 0 - 0 FPLLD 0 - 0 FPLLNH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPLLFL 0 0 0 0 FPLLFH 0 0 0 0 FPLLFDL 0 0 0 0 FPLLFDH 0 - 0 - 0 - 0 - FPLLV 0 0 This register sets the output frequency of PLL. Please use your prepared clock setting register level that is computed separately using clock setting calculation tool. The register set point and the relations of the output frequency are streets of the lower expression. PLL output frequency (Hz)=PLL input frequency / FPLLM X (FPLLN+FPLLD/16+FPLLF/FPLLF_D/16) *2 / FPLLV Soft Clip Enable Register Soft Clip Threshold H Register Soft Clip Threshold M Register Soft Clip Threshold L Register Soft Clip Gain Register INDEX MAPCON R W 0x1 0x20 0x21 0x1 0x22 0x23 0x1 0x24 0x25 0x1 0x26 0x27 0x1 0x28 0x29 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - SCTHRH - - SCEN 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 SCGAIN 0 0 0 1 SCTHRM 0 0 0 0 SCTHRL 0 - 0 - 0 - 0 - This register controls the soft clip function. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 69/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV SCEN Sets the soft clip enable. Setting 0 Disable 1 Enable Explanation SCTHRH SCTHRM SCTHRL This register sets the soft clip threshold level. When PCM signal with more than of this bit is input, the LSI clips it according to a value of SCGAIN and works. The value of threshold level is 23bit (SCTHRM [6:0], SCTHRM [7:0], and SCTHRL [7:0]) Please do not change the value of this bit during Soft Clip function movement. SCGAIN This sets the magnification during soft clip. Setting 0x0 Double 0x1 1 time (default) 0x2 I double 1/2 0x3 I double 1/4 0x4 I double 1/8 0x5 I double 1/16 0x6 I double 1/32 0x7 I double 1/64 In addition, please do not change the value of this bit during movement. Explanation Touch ADC Control Register INDEX MAPCON 1 b07 R W (Initial) 0x60 0x61 TCHEN 0 b06 b05 b04 b03 TCHA2 1 TCHA1 1 TCHA0 1 1 b02 b01 TCHRSEL TCHMODE 0 0 b00 - This register controls the touch panel interface, and a light, please do "1" in bit 3. TCHEN This enables and disables the touch panel interface. In the case of "0", this bit is cleared after (an automatic mode in the case of enable), the lead of the AD conversion data of the touch panel interface TCHA2 bit by "0". TCHEN Explanation 0x0 A touch panel interface is disabled. 0x1 A touch panel interface is enabled. TCHA2 It controls the convert mode of the touch panel interface, and, in the case of "1", this bit interrupts it after the lead of the AD conversion data of the touch panel interface automatically and changes in a mode. The next conversion starts by an automatic mode leading AD conversion result in the case of disable. TCHA2 Explanation 0x0 An automatic mode is enabled. 0x1 An automatic mode is disabled. TCHA1, TCHA0 This controls the convert mode of the touch panel interface. TCHEN TCHA2 TCHA1, TCHA0 TCHEN=1 * 0x0 * 0x1 * 0x2 * 0x3 TCHEN=0 0x0 0x3 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 70/86 Explanation It becomes the X-axis measurement mode. It becomes the Y-axis measurement mode. It becomes the Z1 axis measurement mode. It becomes the Z2 axis measurement mode. It becomes the interrupt mode. TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV TCHRSEL Choose interrupt pull up resistance using for one of a touch panel interface. TCHRSEL Explanation 0x0 I interrupt it, and pulling up resistance becomes 50kΩ. 0x1 I interrupt it, and pulling up resistance becomes 90kΩ. TCHMODE Choose touch panel interface mode. TCHMODE 0x0 12Bit Mode 0x1 8Bit Mode Explanation Touch ADC result1 Register Touch ADC result2 Register INDEX MAPCON 0x1 0x1 R W 0x62 0x63 0x64 b07 (Initial) b06 b05 b04 0 0 0 0 0 0 b03 b02 b01 b00 0 - 0 - 0 - 0 - ADCR1 ADCR2 0x65 0 0 This register is to get analog-to-digital conversion data of the touch panel interface ADC. register in order of ADCR1 ($62h), ADCR2 ($64h). In the 12bit mode, please read TOUTCHAD1 This register is to get analog-to-digital conversion data of the touch panel interface ADC. In the 8 bit mode, please read only this register. In the 12 bit mode, this register is higher 8 bits of the 12bit ADC output data. TOUTCHAD2 This register is to get analog-to-digital conversion data of the touch panel interface ADC. In the 8 bit mode, this register value is "0". In the 12 bits mode, this register is lower 4 bits of the 12bit ADC output data. Headphone Amplifier Input Control Register INDEX MAPCON 0x1 R W 0x82 0x83 b07 (Initial) b06 - - b05 b04 HPRIN2EN HPRIN1EN 0 0 This register is to set the input path of the headphones amplifier. to "1" simultaneously. Please set only either bit to " 1 ". b03 b02 b01 b00 - - - HPLIN1EN 0 Please do not set HPRIN1EN bit and the HPRIN2EN bit HPLIN1EN This bit is to set the input path of the Lch headphones amplifier. HPLIN1EN Explanation 0x0 Disconnect the output of Lch-DAC to Lch headphones amplifier. 0x1 Connect the output of Lch-DAC to Lch headphones amplifier. HPRIN1EN This bit is to set the input path of the Rch headphones amplifier. HPRIN1EN Explanation 0x0 Disconnect the output of Lch-DAC to Rch headphones amplifier. 0x1 Connect the output of Lch-DAC to Rch headphones amplifier. HPRIN2EN This bit is to set the input path of the Rch headphones amplifier. HPRIN2EN Explanation 0x0 Disconnect the output of Rch-DAC to Rch headphones amplifier. 0x1 Connect the output of Rch-DAC to Rch headphones amplifier. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 71/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Speaker Amplifier Input Control Register INDEX MAPCON 0x1 R W 0x84 0x85 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - SPIN2EN 0 SPIN1EN 0 0 0 SPVOL This register is to set the input path and the volume of the speaker amplifier. SPVOL This register is to set the volume level of the speaker amplifier. SPVOL Explanation 0x0 0dB 0x1 6dB 0x2 12dB 0x3 18dB SPIN1EN This bit is to set the input path of the speaker amplifier. SPIN1EN Explanation 0x0 Disconnect the output of the Lch volume to a speaker amplifier. 0x1 Connect the output of the Lch volume to a speaker amplifier. SPIN2EN This bit is to set the input path of the speaker amplifier. SPIN2EN Explanation 0x0 Disconnect the output of the Rch volume to a speaker amplifier. 0x1 Connect the output of the Rch volume to a speaker amplifier. Play Programmable LPF Setting Register INDEX MAPCON 0x1 R W 0xa0 0xa1 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - - PLPFOD 0 PLPFEN 0 This register is to set “LPF” block for DAC-path (playback) in digital signal flow. This is to set Enable/Disable and filter order. This function is effective for DAC-path (playback) at “PLPFEN=1” and “SEMODE [7] =1”. PLPFEN This bit is to set Enable/Disable of low pass filter for DAC-path. PLPFEN Explanation 0 LPF for DAC-path is Disable 1 LPF for DAC-path is Enable PLPFOD This bit is to set number of low pass filter order for DAC-path. PLPFOD Explanation 0 LPF for DAC-path is second-order 1 LPF for DAC-path is first-order Play Programmable LPF Coef (L) Register Play Programmable LPF Coef (H) Register MAPCON 0x1 0x1 INDEX R 0xa2 0xa4 W 0xa3 b07 (Initial) b06 b05 b04 0 0 0 0 b03 b02 b01 b00 0 0 0 0 0 0 0 0 PLPFC0L PLPFC0H 0xa5 0 0 0 0 This register is to set “LPF” block for DAC-path (playback) in digital signal flow. This is to set Enable/Disable and filter order. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 72/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV PLPFC0L [7:0] / PLPFCOH [7:0] This bit is to set low pass filter cut off frequency for DAC-path. This value has to change by sampling frequency. Please use Filter Setting Calculation program for *PLPFC0L / PLPFC0H setting. Rec Programmable LPF Setting Register INDEX MAPCON 0x1 R W 0xa6 0xa7 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - - RLPFOD 0 RLPFEN 0 This register is to set “LPF” block for ADC-path (record) in digital signal flow. This is to set Enable/Disable and filter order. This function is exclusive to “HPF2” controlled by HPF2EN of DSP Filter Function Enable register. This function is effective for ADC-path (record) at “RLPFEN=1” and “SEMODE [7] =1”. RLPFEN This bit is to set Enable/Disable of low pass filter for ADC-path. RLPFEN Explanation 0 LPF for DAC-path is Disable (HPF2 is available) 1 LPF for DAC-path is Enable (HPF2 is not available. HPF2EN-bit is not valid) RLPFOD This bit is to set number of low pass filter order for ADC-path. RLPFOD Explanation 0 LPF for ADC-path is second-order 1 LPF for ADC-path is first-order Rec Programmable LPF Coef (L) Register Rec Programmable LPF Coef (H) Register INDEX MAPCON 0x1 0x1 R W 0xa8 0xa9 0xaa b07 (Initial) b06 b05 b04 0 0 0 0 b03 b02 b01 b00 0 0 0 0 0 0 0 0 RLPFC0L RLPFC0H 0xab 0 0 0 0 This register is to set “LPF” block for ADC-path (playback) in digital signal flow. Audio Analog Control2 Register MAPCON 0x02 INDEX R W 0x04 0x05 b07 (initial) - b06 b05 b04 b03 b02 b01 b00 - 1 - HPLSEN 1 1 - - HPLSEN This bit controls the level shifter for headphone amplifier. Setting Explanation 0x0 Disable the level shifter for headphone amplifier 0x1 Enable the level shifter for headphone amplifier Audio Analog Control1 Register MAPCON 0x02 INDEX R W 0x12 0x13 b07 (initial) - www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 b06 b05 b04 b03 b02 b01 b00 - - - - - - AREFI1EN 1 73/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV AREFI1EN This bit controls the reference current of the analog circuit for the audio block. Setting Explanation 0x0 Disable the reference current of the analog circuit for the audio block. 0x1 Enable the reference current of the analog circuit for the audio block. Register MAP Control Register INDEX MAPCON 0x2 R W 0x1c 0x1d b07 (Initial) b06 b05 b04 b03 b02 b01 - - - - - - 0 b00 MAPCON 0 MAPCON Please refer to a register map about the target register to change front and back side of the register map, and to be replaced by. The register is to set register map. Please refer register map about the map of the changing object. Setting Explanation 0x0 It is accessible to register MAP0 0x1 It is accessible to register MAP1 0x2 It is accessible to register MAP2 0x3 Prohibit PLL External Components Setting Register INDEX MAPCON 2 R W 0x00 0x01 b07 (Initial) b06 b05 b04 b03 b02 b01 b00 - - - - - - - EXMODE 1 This register is to select use or not use the external filter for PLL. EXMODE This register is to select use or not use the external filter for PLL. please set it to "1" by all means. EXMODE Explanation 0x00 not use a external filter. 0x01 use a external filter. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 74/86 When you use PLL with BCLK clock as a clock source , TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Typical Performance Curves 0 0 -10 -10 -20 -20 MINVOL=9.0dB -30 S/(N+D)[dB] Output Level [dBFS] -30 -40 -50 MINVOL=18.0dB -60 -90 -80 -60 -50 -70 HVDD=TVDD=CPVDD =SPVDD=3.3V, 25℃ -80 -40 -60 MINVOL=27.0dB -70 HVDD=TVDD=CPVDD =SPVDD=3.3V, 25℃ LALCMXGAIN=6.0dB MINVOL=9.0dB -40 LALCMXGAIN=-9.0dB MINVOL=18.0dB -80 MINVOL=27.0dB -90 -20 0 -80 HVDD1=IOVDD=SPLVDD -20 0 =SPRVDD=3.3V, 25℃ -60 Input Level [dBV] -40 Input Level [dBV] Figure 42. MIC Input Level [dBV] vs S/(N+D) [dBFS] Analog Mic Input tot ADC out, PDATT=0 Figure 41. MIC Input Level [dBV] vs Output Level [dBFS] Analog Mic Input tot ADC out, PDATT=0 0 0 -10 -10 HVDD=TVDD=CPVDD =SPVDD=3.3V, 25℃ -20 THD+N[dB] Output Level [dBV] -30 -20 -30 -40 -50 -60 HVDD=TVDD=CPVDD =SPVDD=3.3V, 25℃ -40 -70 -80 -50 -50 -40 -30 -20 -10 -90 0 -50 -40 Input Level [dBFS] -20 -10 0 Input Level [dBFS] Figure 44. DAC input Level [dBFS] vs HPAMP THD+N[dB] Figure 43. DAC input Level [dBFS] vs HPAMP Output Level [dB] 0 0 HVDD=TVDD=CPVDD =SPVDD=3.3V, 25℃ -10 -10 -20 SPVOL =0dB -20 SPVOL=18dB THD+N[dB] Output Level [dBV] -30 SPVOL=6dB SPVOL=12dB -30 SPVOL=18dB -30 SPVOL=12dB -40 SPVOL=6dB -50 -40 HVDD=TVDD=CPVDD =SPVDD=3.3V, 25℃ -60 SPVOL=0dB -50 -50 -40 -30 -20 -10 -70 0 -50 Input Level [dBFS] -30 -20 -10 0 Input Level [dBFS] Figure 45. DAC input Level [dBFS] vs SPAMP-D Class Output Level [dB] www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 -40 Figure 46. DAC input Level [dBFS] vs SPAMP-D Class THD+N [dB] 75/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV 0 0 HVDD=TVDD=CPVDD =SPVDD=3.3V, 25℃ HVDD=TVDD=CPVDD =SPVDD=3.3V, 25℃ -10 -10 -20 THD+N[dB] Output Level [dBV] -20 SPVOL=0dB -30 SPVOL=6dB -40 SPVOL=18dB -30 SPVOL=12dB SPVOL=6dB -40 -50 SPVOL=12dB -60 SPVOL=18dB SPVOL=0dB -50 -50 -40 -30 -20 -10 -70 0 -50 Input Level [dBFS] -30 -20 -10 0 Input Level [dBFS] Figure 47. DAC input Level [dBFS] vs SPAMP-AB Class Output Level [dB] www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 -40 Figure 48. DAC input Level [dBFS] vs SPAMP-AB Class THD+N [dB] 76/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Power dissipation 4.00 power dissapation (W) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 20 40 60 80 100 120 140 ambient temperature : Ta(℃) Figure 49.VQFN040V6060 Package Measuring instrument: TH-156 (Kuwano Electrical) Measuring status: PCB mounting(Rohm) PCB size: 74.2mm × 74.2mm × 1.6mm (PCB with thermal via) The quarity of the material: FR4 The part of package bottom exposure heat sink connected PCB by solder. PCB (1): 1-layer board (Size of copper foil on bottom: 23.69mm2), θja = 125.0℃/W PCB (2): 4-layer board (Size of copper foil on top and bottom: 23.69mm2, 2nd and 3rd layer Size of copper foil on bottom: 5505mm2), θja = 33.2℃/W PCB (3): 4-layer board (Size of copper foil on bottom: 5505mm2), θja = 27.4℃/W Please consider power dissipation by an actual using status, and perform the thermal design which has a margin enough. Although this product is exposing the frame on the bottom side of a package, heat dissipation processing is performed to this portion, and we assume raising and using heat dissipation efficiency. Please use not only PCB-top pattern but also PCB-bottom pattern, taking heat dissipation pattern as large as possible at it. Although D-class speaker amplifier have very high efficiency compared with the conventional analog-speaker amplifier and there is also little generation of heat, when continuous action is carried out by the maximum output power, actual power dissipation may exceed Pd. Please consider the thermal design enough so that power dissipation of averaging output power does not exceed Pd. （Tjmax ： Maximum junction temperature=125℃, Ta ：Ambient temperature[℃], θja ：Package thermal registance[℃/W], Poav：Averaging output power[W], η：Efficiency） Package Power dissipation Pd （W） = （Tjmax - Ta）/ θja Circuit Power dissipation Pdiss（W） = Poav * （1 / η- 1） www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 77/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV I/O equivalence circuit(s) Terminal No. Terminal Name Terminal I/O Terminal Power Equivalent Circuit HPVDD 1 40 HPL HPR O HPVDD HPVSS CPVDD 2 HPVDD O CPVDD CPGND CPGND CPGND 4 HPVSS O CPN CPVDD HPVSS CPGND 5 CPN O CPVDD HPVSS 6 SPVDD - SPVDD SPGND SPVDD 7 8 SDOUT+ SPOUT- O SPVDD SPGND www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 78/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Terminal No. Terminal Name Terminal I/O Terminal Power Equivalent Circuit SPVDD 9 SPGND - - REGOUT REGOUT 10 VMID O REGOUT HGND2 HGND2 HVDD 11 MICBIAS CAP O HVDD HGND2 HGND2 REGOUT 12 13 MIN1 MIN2 I REGOUT HGND1 REGOUT 14 HGND2 - - REGOUT 15 HGND1 - - 16 N.C - - www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 HVDD 79/86 HVDD TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Terminal No. Terminal Name Terminal I/O Terminal Power 17 HVDD - HVDD Equivalent Circuit HGND1 HVDD 18 REGOUT - HVDD HGND1 HGND1 REGOUT 19 PLLC O REGOUT HGND1 HGND2 HVDD 20 RESETB I HVDD HGND1 HVDD 21 30 TSTO IRQB O HVDD HGND 1 HGND1 HVDD 22 23 25 28 MCLKI CSB/SCL SCLK/SAD SAI_SDIN I HVDD HGND1 www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 80/86 HGND1 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Terminal No. Terminal Name Terminal I/O Terminal Power Equivalent Circuit HVDD 24 26 27 SDATA/SDA SAI_LRCLK SAI_BCLK IO HVDD HGND1 HGND1 TVDD 31 32 33 34 YP XP XN YN O TVDD TGND TVDD 35 TGND - - 36 TVDD - TVDD TGND HPVDD 37 HPCOM - - HPVSS 38 CPVDD - CPVDD CPGND www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 81/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Terminal No. Terminal Name Terminal I/O Terminal Power Equivalent Circuit CPVDD 39 CPP - CPVDD CPGND www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 82/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Operational Notes 1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus don’t exceed the absolute maximum ratings of supply voltage, temperature. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. 2) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. 3) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. 4) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. 5) Thermal design If use speaker amplifier function, please consider power dissipation by an actual using status, and perform the thermal design which have a margin enough. If an input signal is made excessive in the state with insufficient heat dissipation, desired output power may not only be securable, but the thermal shutdown may operate. 6) Thermal shutdown This IC has the thermal shutdown circuit. If the thermal shutdown operates, speaker output terminal and line output terminal will stop in the open state(high inpedance state).The thermal shutdown is only a function for suspending the output operation of IC to the last at the time of the thermal run-away under the abnormal condition in which chip temperature(Tjmax) exceeded 170 degrees. It is a circuit to protect IC, and the purpose is not offering protection and a guarantee of the set. 7) Short protection of output terminals This IC has the short protect function for output terminals. If the short protect function operates, output terminal will be latched and stop in the open state(high inpedance state).After a stop, even if a short state is removed, it does not return to normal operation automatically. Please once turn off a power supply or a shutdown signal to make it return, and let turn on again and reboot. 8) Operating condition Operating voltage and operating temperature are ranges which perform basic function. Electrical characteristics and absolute maximum rating are not guaranteed in full voltage range or full temperature range. 9) Electrical characteristics specification Each audio characteristic specification, such as limit output power, total harmonic distortion shows the standard performance of the device, and depends for it on board layout / use parts / power supply part greatly. Typical specification value is a value when a device and each parts are directly mounted in the board of Rohm's standard. 10) Power supply Large peak current rushes into a SPVDD power supply line at the time of ClassD speaker amplifier use. The audio characteristic is affected by the value of a power supply decoupling capacitor, and layout. The power supply decoupling capacitor should be layouted (1uF or more) with sufficiently low ESR (equivalent series resistance) to most close of IC terminal. Moreover, in the design of a board pattern, the wiring of a power supply / GND line should become low impedance. In that case, even if digital power supply and analog power supply are same potential, please devide the digital power pattern and the analog power pattern and reduce a surroundings lump of the digital noise to the analog power supply by the common impedance of a wiring pattern. Please take the same pattern design into consideration also about a GND line. Moreover, while inserting a capacitor between power supply-GND terminals about all the power supply terminals of LSI, and please determine the value of capacitor after sufficient confirmation that there is no problem in the characteristics of capacitors to be used (a capacity omission happens at low temperature) in the case of electrolytic capacitors use. 11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. 12) Status of this document www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 83/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV The Japanese version of this document is formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document formal version takes priority. www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 84/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Ordering Information B U 2 6 1 5 Part Number 4 M U V - E2 Package MUV:VQFP040V6060 Packaging and forming specification E2: Embossed tape and reel Physical Dimension, Tape and Reel Information Package Name VQFN040V6060 <Tape and Reel information> Tape Embossed carrier tape Quantity 2000pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand 1pin Reel ) Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. Marking Diagrams VQFN040V6060 (TOP VIEW) Part Number Marking BU26154 LOT Number 1PIN MARK www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 85/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet BU26154MUV Revision History Date Revision 23.Jun.2014 26.Oct.2015 001 002 Changes Rev.001 First revision release P1. Change the Height of Package P4. Change the application circuit P13. Change the VMIC reference voltage (SPVDD=> HVDD) P38, P48,P49,P50,P51,P73 Register function explanation and register details explanation Removed MCLKOE bit and ADCREN bit、 Added Analog Input Power Management, Speaker Amplifier Power Management registers MAPCON setting Changed ZCEN explanation(PDATT => EFFECT VOLUME) Added the explanation of Playback Digital Attenuator Control Register /B “FFh setting” Changed HPLSEN bit of Audio analog contol2 register www.rohm.com © 2014 ROHM Co., Ltd. All rights reserved. TSZ22111 • 15 • 001 86/86 TSZ02201-0V2V0E500110-1-2 26.Oct.2015 Rev.002 Datasheet Notice Precaution on using ROHM Products 1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment, OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you (Note 1) , transport intend to use our Products in devices requiring extremely high reliability (such as medical equipment equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASSⅢ CLASSⅡb CLASSⅢ CLASSⅢ CLASSⅣ CLASSⅢ 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PGA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.002 Datasheet Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label QR code printed on ROHM Products label is for ROHM’s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PGA-E © 2015 ROHM Co., Ltd. All rights reserved. Rev.002 Datasheet General Precaution 1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents. ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny ROHM’s Products against warning, caution or note contained in this document. 2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s representative. 3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. Notice – WE © 2015 ROHM Co., Ltd. All rights reserved. Rev.001 Datasheet BU26154MUV - Web Page Buy Distribution Inventory Part Number Package Unit Quantity Minimum Package Quantity Packing Type Constitution Materials List RoHS BU26154MUV VQFN40 2000 2000 Taping inquiry Yes