TI1 INA826S Precision, 200-ua supply current, 3-v to 36-v supply instrumentation amplifier with rail-to-rail output and shutdown Datasheet

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INA826S
SBOS770A – MAY 2017 – REVISED JUNE 2017
INA826S Precision, 200-µA Supply Current, 3-V to 36-V Supply
Instrumentation Amplifier With Rail-to-Rail Output and Shutdown
1 Features
3 Description
•
•
The INA826S device is a low-cost instrumentation
amplifier that offers extremely low power consumption
along with shutdown and operates over a very wide
single- or dual-supply range. A single external resistor
sets any gain from 1 to 1000. The device offers
excellent stability over temperature, even at G > 1, as
a result of the low gain drift of only 35 ppm/°C (max).
1
•
•
•
•
•
•
•
•
•
•
•
Input Common-Mode Range: Includes V–
Common-Mode Rejection:
– 104 dB (Min, G = 10)
– 100 dB (Min at 5 kHz, G = 10)
Power-Supply Rejection: 100 dB (Min, G = 1)
Low Offset Voltage: 150 µV, max
Gain Drift: 1 ppm/°C (G = 1), 35 ppm/°C (G > 1)
Noise: 18 nV/√Hz, G ≥ 100
Bandwidth: 1 MHz (G = 1), 60 kHz (G = 100)
Inputs Protected up to ±40 V
Rail-to-Rail Output
Supply Current: 200 µA
– Shutdown Current: 2 µA
Supply Range:
– Single Supply: 3 V to 36 V
– Dual Supply: ±1.5 V to ±18 V
Specified Temperature Range:
–40°C to +125°C
Packages: 3-mm × 3-mm VSON
2 Applications
•
•
•
•
•
•
•
Industrial Process Controls
Circuit Breakers
Battery Testers
ECG Amplifiers
Power Automation
Medical Instrumentation
Portable Instrumentation
The INA826S is optimized to provide excellent
common-mode rejection ratio of over 100 dB (G = 10)
over frequencies up to 5 kHz. At G = 1, the commonmode rejection ratio exceeds 84 dB across the full
input common-mode range from the negative supply
all the way up to 1 V of the positive supply. Using a
rail-to-rail output, the INA826S is well-suited for low
voltage operation from a 3-V single supply as well as
dual supplies up to ±18 V.
Shutdown pins are provided to reduce supply current
below 2 µA. Additional circuitry protects the inputs
against overvoltage of up to ±40 V beyond the power
supplies by limiting the input currents to less than
8 mA.
The INA826S is available in a 10-pin, 3-mm ×
3-mm VSON surface-mount package. The INA826S
is specified over the –40°C to +125°C temperature
range.
Device Information(1)
PART NUMBER
INA826S
PACKAGE
BODY SIZE (NOM)
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
INA826S Simplified Internal Schematic
V+
0.1 mF
8
(1)
RS
-IN
1
RFI Filter
50 kW
50 kW
A1
VO = G ´ (VIN+ - VIN-)
2
24.7 kW
RG
G=1+
A3
24.7 kW
+
3
Load VO
50 kW
(1)
RS
+IN
4
49.4 kW
RG
7
50 kW
A2
6
REF
RFI Filter
TI Device
5
Copyright © 2017, Texas Instruments Incorporated
0.1 mF
V-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA826S
SBOS770A – MAY 2017 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 19
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
20
27
8
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application ................................................. 28
9
Power Supply Recommendations...................... 30
9.1 Low-Voltage Operation ........................................... 30
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 31
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2017) to Revision A
•
2
Page
Changed output stage offset voltage from 700 µV to 1000 µV .............................................................................................. 5
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SBOS770A – MAY 2017 – REVISED JUNE 2017
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
±IN
1
10
+VS
RG
2
9
OUT
RG
3
8
REF
+IN
4
7
±VS
EN
5
6
ENREF
Thermal pad
Not to scale
Pin Functions
NO.
I/O
EN
NAME
5
I
Enable pin; active low with respect to ENREF
ENREF
6
I
Enable pin reference
–IN
1
I
Negative (inverting) input
+IN
4
I
Positive (noninverting) input
OUT
9
O
Output
REF
8
I
Reference input. This pin must be driven by low impedance.
RG
2, 3
—
Gain setting pins. Place a gain resistor between pin 2 and pin 3.
–VS
7
—
Negative supply
+VS
10
—
Positive supply
Pad
—
Exposed thermal die pad on underside; connect thermal die pad to V–.
Soldering the thermal pad improves heat dissipation and provides specified performance.
Thermal pad
DESCRIPTION
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SBOS770A – MAY 2017 – REVISED JUNE 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Signal input pins
REF pin
Voltage
Current
MIN
MAX
UNIT
–20
20
V
(–VS) – 40
(+VS) + 40
–20
+20
ENREF pin
(–VS) – 0.3
(+VS) + 0.3
EN pin
(–VS) – 0.3
VENREF + 0.3
Signal input pins
–10
10
REF pin
–10
10
ENREF pin
–1
1
EN pin
–1
Output short-circuit (2)
Temperature
1
–50
150
Junction, TJ
175
Storage, Tstg
(2)
mA
Continuous
Operating, TA
(1)
V
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Single-supply
Supply voltage
Dual-supply
Specified temperature
NOM
MAX
3
36
±1.5
±18
–40
125
UNIT
V
°C
6.4 Thermal Information
INA826S
THERMAL METRIC (1)
VSON (DRC)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
51.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
58.2
°C/W
RθJB
Junction-to-board thermal resistance
25.8
°C/W
ψJT
Junction-to-top characterization parameter
2.0
°C/W
ψJB
Junction-to-board characterization parameter
25.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
RTI
40
150
vs temperature, TA = –40°C to +125°C
0.4
2
RTI
200
1000
2
5
UNIT
INPUT
VOSI
Input stage offset voltage (1)
VOSO
Output stage offset
voltage (1)
vs temperature, TA = –40°C to +125°C
G = 1, RTI
90
124
G = 10, RTI
100
130
G = 100, RTI
110
140
G = 1000, RTI
120
µV
µV/°C
µV
µV/°C
PSRR
Power-supply rejection ratio
zid
Differential impedance
20 || 1
GΩ || pF
zic
Common-mode impedance
10 || 5
GΩ || pF
RFI filter, –3-dB frequency
VCM
Operating input range
140
20
V–
(2)
VS = ±3 V to ±18 V, TA = –40°C to +125°C
Input overvoltage range
Common-mode rejection
ratio
V
See Figure 12 to Figure 19
±40
G = 1, VCM = (V–) to (V+) – 1 V
82
95
G = 10, VCM = (V–) to (V+) – 1 V
104
115
G = 100, VCM = (V–) to (V+) – 1 V
120
130
G = 1000, VCM = (V–) to (V+) – 1 V
120
130
G = 1, VCM = (V–) to (V+) – 1 V,
TA = –40°C to +125°C
At 5 kHz,
RTI
MHz
(V+) – 1
TA = –40°C to 125°C
At dc to
60 Hz, RTI
CMRR
dB
V
80
G = 1, VCM = (V–) to (V+) – 1 V
84
G = 10, VCM = (V–) to (V+) – 1 V
100
G = 100, VCM = (V–) to (V+) – 1 V
105
G = 1000, VCM = (V–) to (V+) – 1 V
105
dB
BIAS CURRENT
IB
Input bias current
IOS
Input offset current
VCM = VS / 2
35
TA = –40°C to +125°C
65
nA
95
VCM = VS / 2
0.7
TA = –40°C to +125°C
5
nA
10
NOISE VOLTAGE
eNI
eNO
In
(1)
(2)
Input stage voltage noise (3)
Output stage voltage noise
Noise current
(3)
f = 1 kHz, G = 100, RS = 0 Ω
nV/√Hz
0.52
µVPP
f = 1 kHz, G = 1, RS = 0 Ω
110
nV/√Hz
fB = 0.1 Hz to 10 Hz, G = 1, RS = 0 Ω
3.3
µVPP
f = 1 kHz
100
fA/√Hz
fB = 0.1 Hz to 10 Hz
5
pAPP
Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
Input voltage range of the INA826S input stage. The input range depends on the common-mode voltage, differential voltage, gain, and
reference voltage.
(eNI)2 +
(3)
18
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
Total RTI voltage noise is equal to:
eNO
G
2
.
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Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GAIN
G
Gain equation
G
Range of gain
Gain error
GE
Gain vs temperature (4)
Gain nonlinearity
1 + (49.4 kΩ / RG)
1
V/V
1000
G = 1, VO = ±10 V
±0.003%
±0.020%
G = 10, VO = ±10 V
±0.03%
±0.15%
G = 100, VO = ±10 V
±0.04%
±0.15%
G = 1000, VO = ±10 V
±0.04%
±0.15%
G = 1, TA = –40°C to +125°C
±0.1
±1
G > 1, TA = –40°C to +125°C
±10
±35
G = 1 to 100, VO = –10 V to 10 V
1
5
G = 1000, VO = –10 V to 10 V
5
20
V/V
ppm/°C
ppm
OUTPUT
Voltage swing
RL = 10 kΩ
(V–) + 0.1
Load capacitance stability
ZO
Open-loop output impedance
ISC
Short-circuit current
(V+) – 0.15
1000
V
pF
See Figure 59
Continuous to VS / 2
±16
mA
1
MHz
FREQUENCY RESPONSE
G=1
BW
SR
Bandwidth, –3 dB
Slew rate
G = 10
500
G = 100
60
G = 1000
6
G = 1, VSTEP = 10 V
1
G = 100, VSTEP = 10 V
1
0.01%
tS
Settling time
0.001%
G = 1, VSTEP = 10 V
12
G = 10, VSTEP = 10 V
12
G = 100, VSTEP = 10 V
24
G = 1000, VSTEP = 10 V
224
G = 1, VSTEP = 10 V
14
G = 10, VSTEP = 10 V
14
G = 100, VSTEP = 10 V
31
G = 1000, VSTEP = 10 V
278
kHz
V/µs
µs
REFERENCE INPUT
RIN
Input impedance
100
Voltage range
(V–)
Gain to output
kΩ
(V+)
1
Reference gain error
V
V/V
0.01%
ENABLE INPUT
Enable threshold voltage
Disable threshold voltage
Referenced to ENREF pin
–0.75
TA = –40°C to +125°C
–1.0
Referenced to ENREF pin
TA = –40°C to +125°C
–0.7
VENREF = 1.5 V, VEN = 0 V
3
ENREF pin input current
VENREF = 1.5 V, VEN = 0 V
–3
EN pin voltage range
ENREF voltage range
6
µA
µA
V–
VENREF
(V–) + 1.5 V
V+
Enable delay
(4)
V
–0.40
EN pin input current
100
V
V
V
µs
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
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Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
Power-supply voltage
IQ
Quiescent current
IQSD
Shutdown current
Single
Dual
3
36
±1.5
±18
VIN = 0 V
200
TA = –40°C to +125°C
250
320
VS = 3 V to 36 V, VIN = 0 V
2
TA = –40°C to +125°C
5
6
V
µA
µA
TEMPERATURE RANGE
Specified
–40
125
°C
Operating
–50
150
°C
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6.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
30
15
10
5
0
25
20
15
10
5
0
-2
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Percent of Population (%)
20
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Percent of Population (%)
25
Input Offset Voltage Drift ( V/ƒC)
Input Offset Voltage ( V)
C001
C001
1024 units
5977 units
Figure 2. Typical Distribution of
Input Offset Voltage Drift
30
30
25
25
20
15
10
20
15
10
5
5
0
0
Output Offset Voltage ( V)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
Percent of Population (%)
35
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
Percent of Population (%)
Figure 1. Typical Distribution of
Input Offset Voltage
Output Offset Voltage Drift ( V/ƒC)
C001
C001
1024 units
5977 units
Figure 4. Typical Distribution of
Output Offset Voltage Drift
60
25
50
20
15
10
5
0
40
30
20
10
0
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Percent of Population (%)
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
Percent of Population (%)
Figure 3. Typical Distribution of
Output Offset Voltage
Input Bias Current (nA)
Input Offset Current (nA)
C001
1024 units
Figure 5. Typical Distribution of
Input Bias Current
8
C001
1024 units
Figure 6. Typical Distribution of
Input Offset Current
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
45
30
Percent of Population (%)
Percent of Population (%)
40
35
30
25
20
15
10
25
20
15
10
5
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
0
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
5
Common-Mode Rejection Ratio ( V/V)
Common-Mode Rejection Ratio ( V/V)
C001
C001
1024 units
1024 units
Figure 7. Typical Distribution of CMRR (G = 1)
Figure 8. Typical Distribution of CMRR (G = 100)
35
20
18
Percent of Population (%)
25
20
15
10
16
14
12
10
8
6
4
5
2
0
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Percent of Population (%)
30
Gain Error (m%)
Gain Error (m%)
C001
C001
1024 units
1024 units
Figure 10. Gain Error (G = 10)
3
40
2.5
35
Common-Mode Voltage (V)
Percent of Population (%)
Figure 9. Typical Distribution of Gain Error (G = 1)
45
30
25
20
15
10
5
2
1.5
1
0.5
0
-0.5
-0.5
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
VREF = 0 V
VREF = 1.35 V
-1
0
Gain Error Drift (ppm/ƒC)
0.5
1
1.5
2
Output Voltage (V)
2.5
C001
3
D035
Single supply, VS = 3 V, G = 1
5977 units
Figure 11. Typical Gain Error Drift Distribution
(G = 1)
Figure 12. Input Common-Mode Voltage vs Output Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
3
5
VREF = 0 V
VREF = 1.35 V
Common-Mode Voltage (V)
Common-Mode Voltage (V)
2.5
VREF = 0 V
VREF = 2.5 V
4.5
2
1.5
1
0.5
0
-0.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1
0
0.5
1
1.5
2
Output Voltage (V)
2.5
3
0
0.5
Single supply, VS = 3 V, G = 100
1.5
2
2.5
3
3.5
Output Voltage (V)
4
4.5
5
D034
Single supply, VS = 5 V, G = 1
Figure 13. Input Common-Mode Voltage vs Output Voltage
Figure 14. Input Common-Mode Voltage vs Output Voltage
3
5
VREF = 0 V
VREF = 2.5 V
4.5
4
G=1
G = 100
2
Common-Mode Voltage (V)
Common-Mode Voltage (V)
1
D036
3.5
3
2.5
2
1.5
1
0.5
0
1
0
-1
-2
-3
-0.5
-4
-1
0
0.5
1
1.5
2
2.5
3
3.5
Output Voltage (V)
4
4.5
-4
5
Single supply, VS = 5 V, G = 100
G=1
G = 100
3
Common-Mode Voltage (V)
Common-Mode Voltage (V)
4
2
1
0
-1
-2
-3
-4
-5
-6
-4
-3
-2 -1
0
1
2
Output Voltage (V)
3
4
5
6
16
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-16
D038
Dual supply, VS = ±5 V, VREF = 0 V
2
3
4
D039
VS = r15 V
VS = r12 V
-12
-8
-4
0
4
Output Voltage (V)
8
12
16
D040
Dual supply, VS = ±15 V and ±12 V, G = 1, VREF = 0 V
Figure 17. Input Common-Mode Voltage vs Output Voltage
10
-1
0
1
Output Voltage (V)
Figure 16. Input Common-Mode Voltage vs Output Voltage
5
-5
-2
Dual supply, VS = ±3.3 V, VREF = 0 V
Figure 15. Input Common-Mode Voltage vs Output Voltage
-6
-3
D037
Figure 18. Input Common-Mode Voltage vs Output Voltage
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Typical Characteristics (continued)
12
16
9
12
6
8
3
4
0
0
-3
-4
-6
-8
VS = r15 V
VS = r12 V
-9
-12
-8
-4
0
4
Output Voltage (V)
8
12
-12
-40
16
-32
Dual supply, VS = ±15 V and ±12 V, G = 100, VREF = 0 V
12
4
8
2
4
0
0
-2
-4
-4
-8
-6
-24
-16
-8
0
8
Input Voltage (V)
16
24
16
24
D065
Figure 20. Input Current vs Input Voltage
-12
IIN
VOUT
-16
32
40
Common-Mode Rejection Ratio (dB)
6
-8
0
8
Input Voltage (V)
160
Output Voltage (V)
Input Current (mA)
16
-32
-16
-12
IIN
VOUT
-16
32
40
G = 1, VS = ±15 V, RS = 0 Ω
Figure 19. Input Common-Mode Voltage vs Output Voltage
8
-8
-40
-24
D040
Output Voltage (V)
16
14
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-16
Input Current (mA)
Common-Mode Voltage (V)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
140
120
100
80
60
40
G=1
G = 10
G = 100
G = 1000
20
0
10
100
D064
1k
Frequency (Hz)
10k
100k
D001
G = 1, VS = ±15 V, RS = 10 kΩ
Figure 21. Input Current vs Input Voltage
with 10-kΩ Resistance
Figure 22. CMRR vs Frequency (RTI)
Positive Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
140
G=1
G = 10
G = 100
G = 1000
120
100
80
60
40
20
0
10
100
1k
Frequency (Hz)
10k
Figure 23. CMRR vs Frequency
(RTI, 1-kΩ Source Imbalance)
100k
160
G=1
G = 10
G = 100
G = 1000
140
120
100
80
60
40
20
0
10
100
D002
1k
Frequency (Hz)
10k
100k
D003
Figure 24. Positive PSRR vs Frequency (RTI)
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Typical Characteristics (continued)
160
70
140
60
G=1
G = 10
G = 100
G = 1000
50
120
40
100
Gain (dB)
Negative Power-Supply Rejection Ratio (dB)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
80
60
30
20
10
0
40
G=1
G = 10
G = 100
G = 1000
20
0
10
-10
-20
100
1k
Frequency (Hz)
10k
-30
10
100k
100
Figure 25. Negative PSRR vs Frequency (RTI)
10k
100k
Frequency (Hz)
1M
10M
D005
Figure 26. Gain vs Frequency
1k
1k
G=1
G = 10
G = 100
G = 1000
G=1
Current Noise (fA/—Hz)
Voltage Noise (nV/—Hz)
1k
D004
100
10
100
10
1
10
100
1k
Frequency (Hz)
10k
100k
1
10
100
Frequency (Hz)
D019
Figure 27. Voltage Noise Spectral Density
vs Frequency (RTI)
1k
10k
D020
Figure 28. Current Noise Spectral Density vs Frequency
(RTI)
400
3
300
2
Noise (nV/div)
Noise (PV/div)
200
1
0
-1
100
0
-100
-200
-2
-300
-400
-3
0
1
2
3
4
5
6
Time (s/div)
7
8
9
10
Figure 29. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1)
12
0
D007
1
2
3
4
5
6
Time (s/div)
7
8
9
10
D006
Figure 30. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1000)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
0
15
Input Bias Current (nA)
Noise (pA/div)
-40qC
25qC
125qC
-10
10
5
0
-5
-10
-20
-30
-40
-50
-60
-70
-15
0
1
2
3
4
5
6
Time (s/div)
7
8
9
-80
-1
10
-0.5
0
D008
0.5
1
1.5
2
Common-Mode Voltage (V)
2.5
3
D056
VS = 3 V
Figure 31. 0.1-Hz to 10-Hz RTI Current Noise
Figure 32. Input Bias Current vs Common-Mode Voltage
100
0
-40qC
25qC
125qC
90
80
-20
Input Bias Current (nA)
Input Bias Current (nA)
-10
-30
-40
-50
-60
70
60
50
40
30
20
-70
-80
-16
10
-12
-8
-4
0
4
8
Common-Mode Voltage (V)
12
0
-50
16
-25
0
D055
25
50
75
Temperature (qC)
100
125
150
D033
VS = ±15 V
Figure 33. Input Bias Current vs Common-Mode Voltage
Figure 34. Input Bias Current vs Temperature
10
40
Max Data
Min Data
Unit 1
Unit 2
Unit 3
6
4
30
20
Gain Error (ppm)
Input Offset Current (nA)
8
2
0
-2
-4
-6
0
-10
-20
-30
-40
-8
-10
-50
10
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
-60
-50
D053
Figure 35. Input Offset Current vs Temperature
-25
0
25
50
75
Temperature (qC)
100
125
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D031
Figure 36. Gain Error vs Temperature
(G = 1)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
10
Common-Mode Rejection Ratio (PV/V)
2000
1500
Gain Error (ppm)
1000
500
0
-500
-1000
-1500
-2000
-50
-25
0
25
50
75
Temperature (qC)
100
125
DUT11
DUT23
8
6
4
2
0
-2
-4
-6
-8
-10
-50
150
-25
0
25
50
75
Temperature (qC)
D054
Figure 37. Gain Error vs Temperature
(G > 1)
100
125
150
D032
Figure 38. CMRR vs Temperature (G = 1)
300
4
3
Nonlinearity (ppm)
Supply Current (PA)
250
200
150
100
2
1
50
VS = 2.7 V
VS = r15 V
0
-50
-25
0
25
50
75
Temperature (qC)
100
125
0
-10
150
-8
-6
-4
D043
Figure 39. Supply Current vs Temperature
-2
0
2
Output Voltage (V)
4
6
8
10
D021
Figure 40. Gain Nonlinearity (G = 1)
-10
4
-11
-12
Nonlinearity (ppm)
Nonlinearity (ppm)
3
2
-13
-14
-15
-16
-17
1
-18
-19
0
-10
-8
-6
-4
-2
0
2
Output Voltage (V)
4
6
8
10
-20
-10
D022
Figure 41. Gain Nonlinearity (G = 10)
14
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-8
-6
-4
-2
0
2
4
Output Voltage (V)
6
8
10
D023
Figure 42. Gain Nonlinearity (G = 100)
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Typical Characteristics (continued)
0
400
-2
350
-4
300
-6
Offset Voltage (PV)
Nonlinearity (ppm)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
-8
-10
-12
-14
-16
-50qC
-40qC
25qC
85qC
125qC
150qC
250
200
150
100
50
0
-18
-50
-20
-10
-8
-6
-4
-2
0
2
4
Output Voltage (V)
6
8
-100
-15.5
10
-15.3
D024
-15.1
-14.9
-14.7
Common-Mode Voltage (V)
-14.5
D057
VS = ±15 V
Figure 43. Gain Nonlinearity (G = 1000)
Figure 44. Offset Voltage vs
Negative Common-Mode Voltage
300
100
-50qC
-40qC
25qC
85qC
125qC
150qC
Offset Voltage (PV)
0
-50
-100
-50qC
-40qC
25qC
85qC
125qC
150qC
250
200
Offset Voltage (PV)
50
-150
-200
-250
150
100
50
0
-300
-50
-350
-400
13.8
13.9
14
14.1
14.2
Common-Mode Voltage (V)
14.3
-100
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2
Common-Mode Voltage (V)
14.4
D058
VS = ±15 V
0.4
0.5
D059
VS = 3 V
Figure 45. Offset Voltage vs
Positive Common-Mode Voltage
Figure 46. Offset Voltage vs
Negative Common-Mode Voltage
200
15
-50qC
-40qC
25qC
85qC
125qC
150qC
100
50
14.8
Output Voltage (V)
150
Offset Voltage (PV)
0.3
0
-50
14.6
14.4
-50qC
-40qC
25qC
85qC
125qC
150qC
-100
14.2
-150
-200
14
1
1.2
1.4
1.6
1.8
2
2.2
Common-Mode Voltage (V)
2.4
2.6
0
D060
VS = 3 V
2
4
6
8
10
Output Current (mA)
12
14
16
D045
VS = ±15 V
Figure 47. Offset Voltage vs
Positive Common-Mode Voltage
Figure 48. Positive Output Voltage Swing
vs Output Current
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
2.7
-14
-50qC
-40qC
25qC
85qC
125qC
150qC
-14.4
2.5
Output Voltage (V)
Output Voltage (V)
-14.2
25qC
2.6
-14.6
2.4
2.3
2.2
2.1
2
-14.8
1.9
-15
1.7
1.8
0
2
4
6
8
10
Output Current (mA)
12
14
0
16
2
4
D046
6
8
10
Output Current (mA)
VS = ±15 V
14
16
D048
VS = 3 V
Figure 49. Negative Output Voltage Swing
vs Output Current
Figure 50. Positive Output Voltage Swing
vs Output Current
30
1
25qC
0.9
0.8
24
0.7
21
0.6
0.5
0.4
0.3
18
15
12
9
0.2
6
0.1
3
0
1k
0
0
VS = r15 V
VS = +5 V
27
Output Voltage (V)
Output Voltage (V)
12
2
4
6
8
10
Output Current (mA)
12
14
16
10k
D049
100k
Frequency (Hz)
1M
D014
VS = 3 V
Figure 51. Negative Output Voltage Swing
vs Output Current
Figure 52. Large-Signal Frequency Response
25
100
0.01%
0.001%
21
100 pF
220 pF
500 pF
60
Amplitude (mV)
Settling Time (Ps)
1 nF
0 pF
80
17
13
40
20
0
-20
-40
9
-60
5
-100
-80
2
4
6
8
10
12
Step Size (V)
14
16
18
20
0
D061
Figure 53. Settling Time vs Step Size
(VS = ±15 V)
16
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4
8
12
16
20 24 28
Time (ps)
32
36
40
44
48
D013
Figure 54. Small-Signal Response vs
Capacitive Loads (G = 1)
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Typical Characteristics (continued)
100
100
80
80
60
60
40
40
Amplitude (mV)
Amplitude (mV)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
20
0
-20
20
0
-20
-40
-40
-60
-60
-80
-80
-100
-100
0
5
10
15
20
25
Time (Ps)
30
35
40
0
5
G = 1, RL = 1 kΩ, CL = 100 pF
80
80
60
60
40
40
20
0
-20
-60
-80
-80
-100
-100
100 120
Time (Ps)
140
160
180
0
200
100
200
D011
G = 100, RL = 10 kΩ, CL = 100 pF
D010
300
400 500 600
Time (Ps)
700
800
900 1000
D012
G = 1000, RL = 10 kΩ, CL = 100 pF
Figure 57. Small-Signal Response
Figure 58. Small-Signal Response
100k
15
Change in Input Offset Voltage (PV)
Ouput Impedence (:)
40
-20
-40
80
35
0
-60
60
30
20
-40
40
20
25
Time (Ps)
Figure 56. Small-Signal Response
100
Amplitude (mV)
Amplitude (mV)
Figure 55. Small-Signal Response
20
15
G = 10, RL = 10 kΩ, CL = 100 pF
100
0
10
D009
10k
1k
100
10
5
0
-5
-10
-15
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
0
D062
Figure 59. Open-Loop Output Impedance vs Frequency
2
4
6
8
10
Warm-Up Time (s)
12
14
16
D063
Figure 60. Change in Input Offset Voltage vs Warm-Up Time
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
2
0
0
-2
-0.4
-4
-6
0.4
-0.8
Time (50 S/div)
4
0.4
2
0
0
-2
-4
-6
C001
ENREF pin tied to 5 V
EN
ENREF
Input
Output
-0.4
Time (50 S/div)
-0.8
C001
ENREF pin tied to 5 V
Figure 61. Enable Output Response
18
0.8
6
Input / Output Voltage (0.4 V/div)
Enable Voltage (2 V/div)
4
0.8
Enable Voltage (2 V/div)
EN
ENREF
Input
Output
Input / Output Voltage (0.4 V/div)
6
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Figure 62. Disable Output Response
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7 Detailed Description
7.1 Overview
A simplified schematic of the INA826S is shown in as well as the basic connections required for proper
functionality. The INA826S consists of a 4-resistor difference amplifier, composed of amplifier A3 and 50-kΩ
resistors, as well as buffer amplifiers A1 and A2. The gain of the circuit is set by a single external resistor placed
across pins 2 and 3. Further information on the internal topology and setting the gain can be found in the Feature
Description section. High-precision thin-film resistors integrated on-chip allow for excellent rejection of commonmode interference signals and high gain accuracy. The INA826S also integrates radio frequency interference
(RFI) filters on the signal inputs to provide improved performance in the presence of high-frequency interference.
7.2 Functional Block Diagram
V+
0.1 mF
8
(1)
RS
-IN
1
RFI Filter
50 kW
50 kW
A1
VO = G ´ (VIN+ - VIN-)
2
24.7 kW
RG
G=1+
7
A3
24.7 kW
+
3
Load VO
50 kW
(1)
RS
+IN
4
49.4 kW
RG
50 kW
A2
6
REF
RFI Filter
TI Device
5
Copyright © 2017, Texas Instruments Incorporated
(1)
0.1 mF
V-
This resistor is optional if the input voltage stays above [(V–) – 2 V] or the signal source current drive capability is
limited to less than 3.5 mA. See the Input Protection section for more details.
Figure 63. Simplified Block Diagram
-IN
RG
+IN
TI Device
VO
REF
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Figure 64. INA826S Basic Connections
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7.3 Feature Description
7.3.1 Inside the INA826S
See the Functional Block Diagram section for a simplified representation of the INA826S. A more detailed
diagram (shown in Figure 65) provides additional details of the INA826S operation.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these
transistors limit input current to approximately 8 mA.
The differential input voltage is buffered by Q1 and Q2 and is impressed across RG, causing a signal current to
flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the
input signal and refers the output signal to the REF pin.
The equations shown in Figure 65 describe the output voltages of A1 and A2. The VBE and voltage drop across
R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V higher than the input voltages.
V+
V+
RG
(External)
50 kW
R1
24.7 kW
A1 Out = VCM + VBE + 0.125 V - VD/2 ´ G
A2 Out = VCM + VBE + 0.125 V + VD/2 ´ G
Output Swing Range A1, A2, (V+) - 0.1 V to (V-) + 0.1 V
V-
R2
24.7 kW
V-
V+
50 kW
VOUT
A3
50 kW
V+
VO = G ´ (VIN+ - VIN-) + VREF
Linear Input Range A3 = (V+) - 0.9 V to (V-) + 0.1 V
V-
50 kW
REF
VV+
V+
-IN
Q1
VD/2
Overvoltage
Protection
Q2
C1
V-
A1
A2
RB
VCM
C2
VB
V-
Overvoltage
Protection
RB
VD/2
V+IN
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Figure 65. INA826S Simplified Circuit Diagram
20
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Feature Description (continued)
7.3.2 Setting the Gain
Gain of the INA826S is set by a single external resistor, RG, connected between pins 2 and 3. Use Equation 1 to
select the value of RG:
G=1+
49.4 kW
RG
(1)
Table 1 lists several commonly-used gains and resistor values. The 49.4-kΩ term in Equation 1 comes from the
sum of the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate
absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy
and drift specifications of the INA826S.
Table 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN (V/V)
RG (Ω)
1
—
NEAREST 1% RG (Ω)
—
2
49.4 k
49.9 k
5
12.35 k
12.4 k
10
5.489 k
5.49 k
20
2.600 k
2.61 k
50
1.008 k
1k
100
499
499
200
248
249
500
99
100
1000
49.5
49.9
7.3.2.1 Gain Drift
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be directly inferred from the gain of Equation 1.
The best gain drift of 1 ppm/℃ can be achieved when the INA826S uses G = 1 without RG connected. In this
case, the gain drift is limited only by the slight mismatch of the temperature coefficient of the integrated 50-kΩ
resistors in the differential amplifier (A3). At G greater than 1, the gain drift increases as a result of the individual
drift of the 24.7-kΩ resistors in the feedback of A1 and A2, relative to the drift of the external gain resistor RG.
Process improvements of the temperature coefficient of the feedback resistors now make possible specifying a
maximum gain drift of the feedback resistors of 35 ppm/℃, thus significantly improving the overall temperature
stability of applications using gains greater than 1.
Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring
resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately
100 or greater. To ensure stability, avoid parasitic capacitance of more than a few picofarads at RG connections.
Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see typical
characteristic curves Figure 22 and Figure 23.
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7.3.3 Offset Trimming
Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF pin. Figure 66 shows an optional circuit for trimming the output offset voltage. The
voltage applied to the REF pin is summed at the output. The op amp buffer provides low impedance at the REF
pin to preserve good common-mode rejection.
VIN-
V+
RG
VIN+
VO
INA826S
100 mA
1/2 REF200
REF
OPA333
±10-mV
Adjustment Range
100 Ω
10 kΩ
100 Ω
100 mA
1/2 REF200
VCopyright © 2017, Texas Instruments Incorporated
Figure 66. Optional Trimming of Output Offset Voltage
7.3.4 Input Common-Mode Range
The linear input voltage range of the INA826S input circuitry extends from the negative supply voltage to 1 V
below the positive supply, and maintains 84-dB (minimum) common-mode rejection throughout this range. The
common-mode range for most common operating conditions is described in Figure 12 through Figure 18 and
Figure 44 through Figure 46. The INA826S can operate over a wide range of power supplies and VREF
configurations, making a comprehensive guide to common-mode range limits impractical to be provided for all
possible conditions.
The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A1 and A2,
which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A1
and A2 (see Figure 65) provides a check for the most common overload conditions. The designs of A1 and A2 are
identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when
the A2 output is saturated, A1 may continue to be in linear operation, responding to changes in the noninverting
input voltage. This difference can give the appearance of linear operation but the output voltage is invalid.
A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range
that extends to single-supply ground, the INA826S employs a current-feedback topology with PNP input
transistors; see Figure 65. The matched PNP transistors Q1 and Q2 shift the input voltages of both inputs up by a
diode drop, and through the feedback network, shift the output of A1 and A2 by approximately 0.8 V. With both
inputs and VREF at single-supply ground (negative power supply), the output of A1 and A2 is well within the linear
range, allowing differential measurements to be made at the GND level. As a result of this input level-shifting, the
voltages at pin 2 and pin 3 are not equal to the respective input pin voltages (pin 1 and pin 4). For most
applications, this inequality is not important because only the gain-setting resistor connects to these pins.
22
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7.3.5 Input Protection
The inputs of the INA826S are individually protected for voltages up to ±40 V. For example, a condition of –40 V
on one input and 40 V on the other input does not cause damage. However, if the input voltage exceeds (V–) –
2 V and the signal source current drive capability exceeds 3.5 mA, the output voltage switches to the opposite
polarity; see Figure 20. This polarity reversal can easily be avoided by adding resistance of 10 kΩ in series with
both inputs.
Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is
overloaded, the protection circuitry limits the input current to a safe value of approximately 8 mA. Figure 20 and
Figure 21 illustrate this input current limit behavior. The inputs are protected even if the power supplies are
disconnected or turned off.
7.3.6 Input Bias Current Return Path
The input impedance of the INA826S is extremely high—approximately 20 GΩ. However, a path must be
provided for the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance
means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 67 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA826S, and the input amplifiers saturate. If the differential source resistance is
low, as shown in the thermocouple example in Figure 67, the bias current return path can be connected to one
input. With higher source impedance, using two equal resistors provides a balanced input with possible
advantages of lower input offset voltage as a result of bias current and better high-frequency common-mode
rejection.
Microphone,
Hydrophone,
and So Forth
TI Device
47 kW
47 kW
Thermocouple
TI Device
10 kW
TI Device
Center tap provides
bias current return.
Copyright © 2017, Texas Instruments Incorporated
Figure 67. Providing an Input Common-Mode Current Path
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7.3.7 Reference Pin (REF)
The output voltage of the INA826S is developed with respect to the voltage on the reference terminal. Often, in
dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In singlesupply operation, offsetting the output signal to a precise mid-supply level can be useful (for example, 2.5 V in a
5-V supply environment). To accomplish this offset, a voltage source can be tied to the REF pin to level-shift the
output so that the INA826S can drive a single-supply ADC, for example.
For the best performance, keep the source impedance to the REF pin below 5 Ω. As shown in , the reference
resistor is at one end of a 50-kΩ resistor. Additional impedance at the REF pin adds to this 50-kΩ resistor. The
imbalance in the resistor ratios results in degraded common-mode rejection ratio (CMRR).
Figure 68 shows two different methods of driving the reference pin with low impedance. The OPA330 is a lowpower, chopper-stabilized amplifier, and therefore offers excellent stability over temperature. The OPA330 is
available in the space-saving SC70 and even smaller chip-scale package. The REF3225 is a precision reference
in the small SOT23-6 package.
+5 V
VIN-
+5 V
RG
VOUT
INA826S
VIN-
REF
VIN+
+5 V
RG
VOUT
INA826S
REF
+5 V
VIN+
+2.5 V
OPA330
a) Level shifting using the OPA330 as a low-impedance buffer
REF3225
+5 V
b) Level shifting using the low-impedance output of the REF3225
Copyright © 2017, Texas Instruments Incorporated
Figure 68. Options for Low-Impedance Level Shifting
24
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7.3.8 Shutdown (EN and ENREF) Pins
The INA826S provides two pins to shut the device down: EN (enable) and ENREF (enable reference). Figure 69
shows a basic schematic of the shutdown logic circuitry of the INA826S. A PNP transistor forms the basis of the
internal shutdown circuitry. The ENREF pin is connected to the emitter of the PNP transistor and is meant to be
connected to a voltage reference point for the enable logic. The EN pin is connected the base of the PNP
transistor. Applying a voltage to the EN pin that is 0.8 V or more below the enable reference voltage (at the
ENREF pin) causes a small current to flow in the internal PNP transistor that powers the INA826S internal bias
circuitry and powers-up the instrumentation amplifier. The shutdown circuitry functions properly with ENREF
connected to a voltage between (V–) + 1.5 V up to V+. The voltage on the EN pin can be as low as the negative
supply voltage (VS–) but cannot go above the voltage applied to the ENREF pin.
VS+
INA826S
ENREF
VS-
VS+
EN
VSTo amplifier internal
bias circuitry
Copyright © 2017, Texas Instruments Incorporated
Figure 69. Shutdown Pin Simplified Schematic
To better understand the functionality of these pins, consider the low-voltage, single-supply application shown in
Figure 70 with V+ = 3.3 V. ENREF is connected to the 3.3-V power supply of the microcontroller (labeled µC)
and the EN pin is toggled by a general-purpose input/output (GPIO) pin of the microcontroller. When the GPIO
pin is asserted low, such that the voltage at the GPIO pin output is at or near 0 V, the INA826S is enabled.
Conversely, if the GPIO pin is asserted high, with an output voltage at or near 3.3 V, the INA826S is disabled.
3.3 V
VDD
INA826S
IN-
±
REF EN
ADC IN
VS+
VS-
RG
ENREF
GPIO
+
IN+
C
ADC REF
Copyright © 2017, Texas Instruments Incorporated
Figure 70. Example Configuration in a Single-Supply System
(Pulling EN low enables the INA826S.)
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Figure 71 shows an alternate configuration of the enable logic pins. By grounding the enable pin, and toggling
the ENREF pin with the GPIO of the microcontroller, the enable logic is reversed. Now asserting high at the
GPIO output enables the INA826S, and pulling the GPIO pin low disables the INA826S.
3.3 V
VDD
GPIO
IN-
±
ADC IN
VS-
RG
REF EN
VS+
+
IN+
ENREF
INA826S
C
REF
Copyright © 2017, Texas Instruments Incorporated
Figure 71. Alternate Configuration for the Enable Logic Pins
(Pulling ENREF high enables the INA826S.)
The majority of INA826S applications benefit greatly from the reduction of quiescent current from the typical
200 µA to values at or below 6 µA. Achieving the lowest possible system-level current in a system requires
attention to other system voltages applied to the INA826S. When shutdown, voltages applied to the reference or
input pins of the INA826S can find paths for currents to flow up into the several microamps region. In many
systems these voltages are shut down when the INA826S is shutdown, simplifying the problem. Otherwise,
additional switching may be added to reduce currents to a minimum.
26
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7.4 Device Functional Modes
The INA826S features a shutdown mode that reduces the typical power-supply current consumption from 200 µA
to less than 6 µA. Disabling the INA826S turns off the bias circuitry that powers the internal amplifiers of the
INA826S. Figure 72 and Figure 73 show the output behavior of the INA826S when the shutdown state is toggled.
For these plots, the ENREF pin was connected to a 5-V potential and the EN pin was pulled low to enable the
INA826S. Figure 72 shows how quickly the INA826S output responds when transitioning from a shutdown state
to an enabled state. When the EN pin is pulled low, the INA826S output begins to track the input signal
approximately 60 µs later. When transitioning from enabled to shutdown, as shown in Figure 73, the output of the
INA826S stops tracking the input waveform in approximately 10 µs.
2
0
0
-2
-0.4
-4
-6
0.4
-0.8
Time (50 S/div)
0.8
6
Input / Output Voltage (0.4 V/div)
Enable Voltage (2 V/div)
4
0.8
4
Enable Voltage (2 V/div)
EN
ENREF
Input
Output
Input / Output Voltage (0.4 V/div)
6
0.4
2
0
0
-2
-4
-6
C001
Figure 72. Enable Output Response
EN
ENREF
Input
Output
-0.4
Time (50 S/div)
-0.8
C001
Figure 73. Disable Output Response
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The low power consumption and high performance of the INA826S make the device an excellent instrumentation
amplifier for many applications. The INA826S can be used in many low-power, portable applications because the
device has a low quiescent current (200 µA, typical) and comes in a small 10-pin VSON package. The input
protection circuitry, low maximum gain drift, low offset voltage, and 36-V maximum supply voltage also make the
INA826S an ideal choice for industrial applications as well.
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8.2 Typical Application
Figure 74 shows a three-terminal, programmable-logic controller (PLC) design for the INA826S. This PLC
reference design accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ± 2.3 V (or
200 mV to 4.8 V). Many PLCs typically have these input and output ranges.
±10 V
R1 = 100 NŸ
5V
15 V
R2 = 4.12 NŸ
±20 mA
REF3225
v
V+
RO = 100 Ÿ
R3 =
RG = 10.4 NŸ
INA826S
VREF
VOUT
2.5 V ± 2.3 V
20 Ÿ
+
V
RL = 10 NŸ
CO = 1.59 nF
15 V
Copyright © 2017, Texas Instruments Incorporated
Figure 74. Three-Terminal Analog Input for PLCs
8.2.1 Design Requirements
This design has the following requirements:
•
•
•
Supply voltage: ±15 V, 5 V
Inputs: ±10 V, ±20 mA
Output: 2.5 V, ±2.3 V
8.2.2 Detailed Design Procedure
There are two modes of operation for the circuit shown in Figure 74: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, Equation 2 calculates the current input mode transfer function.
VOUT-I = VD ´ G + VREF = -(IIN ´ R3) ´ G + VREF
where
•
G represents the gain of the instrumentation amplifier
(2)
Equation 3 shows the transfer function for the voltage input mode.
R2
VOUT-V = VD ´ G + VREF = - VIN ´
´ G + VREF
R 1 + R2
(3)
R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. 100 kΩ
is selected for R1 because increasing the R1 value also increases noise. The value of R3 must be extremely
small compared to R1 and R2. 20 Ω for R3 is selected because that resistance value is much smaller than R1 and
yields an input voltage of ±400 mV when operated in current mode (±20 mA).
Equation 4 can be used to calculate R2 given VD = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R2
R ´ VD
VD = VIN ´
® R2 = 1
= 4.167 kW
R 1 + R2
VIN - VD
28
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Typical Application (continued)
The value obtained from Equation 4 is not a standard 0.1% value, so 4.12 kΩ is selected. R1 and R2 also use
0.1% tolerance resistors to minimize error.
Use Equation 5 to calculate the ideal gain of the instrumentation amplifier.
V
- VREF 4.8 V - 2.5 V
V
= 5.75 V
G = OUT
=
VD
400 mV
(5)
Equation 6 calculates the gain-setting resistor value using the INA826S gain equation, Equation 1.
49.4 kW
49.4 kW
49.4 kW
GINA826 = 1 + R
® RG =
=
= 10.4 kW
GINA826 - 1 5.75 - 1
G
(6)
10.4 kΩ is a standard 0.1% resistor value that can be used in this design. Finally, the output RC filter
components are selected to have a –3-dB cutoff frequency of 1 MHz.
8.2.3 Application Curves
5
5
4
4
Output Voltage (V)
Output Voltage (V)
Figure 75 and Figure 76 show typical characteristic curves for Figure 74.
3
2
2
1
1
0
-10
3
-5
0
Input Voltage (V)
5
10
0
-0.02
-0.01
D071
Figure 75. PLC Output Voltage vs Input Voltage
0
Input Current (A)
0.01
0.02
D070
Figure 76. PLC Output Voltage vs Input Current
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9 Power Supply Recommendations
The INA826S operates over a power-supply range of 3 V to 36 V (±3 V to ±18 V). Supply voltages higher than
40 V (±20 V) can permanently damage the device. Parameters that vary over supply voltage or temperature are
illustrated in the Typical Characteristics section.
9.1 Low-Voltage Operation
The INA826S can operate on power supplies as low as 3 V. Most parameters vary only slightly throughout this
supply voltage range; see the Typical Characteristics section. Operation at very low supply voltage requires
careful attention to assure that the input voltages remain within the linear range. Voltage swing requirements of
internal nodes limit the input common-mode range with low power-supply voltage. The typical characteristic
curves Figure 12 through Figure 18 and Figure 44 through Figure 46 describe the range of linear operation for
various supply voltages, reference connections, and gains.
30
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications. The bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry, because noise can propagate into analog circuitry through the power
pins of the circuit as a whole and the op amp specifically.
• Connect the device reference pin to a low-impedance, low-noise, system reference point, such as an analog
ground. If a potential other than ground is used as a reference, a low output impedance (such as a voltage
divider with an op amp buffer) must be included.
• Minimize the parasitic capacitance and inductance present at the gain resistor connections. Place the gain
resistor as close to the device as possible, and remove the ground plane around the gain resistor to minimize
parasitic capacitances at these nodes.
• For best performance, route the input traces adjacent to each other as a differential pair.
• For proper amplifier function, connect the package thermal pad to the most negative supply voltage (VEE).
10.2 Layout Example
Copyright © 2017, Texas Instruments Incorporated
GND
Place bypass
capacitors as close to
IC as possible
GND
VS-
-IN
VS+
RG
OUT
Input traces routed
adjacent to each other
INA826S
RG
REF pin connected to
low-impedance
reference potential
REF
VS±
+IN
ENREF
EN
GND
GND
Ground plane
removed at gain
resistor to minimize
parasitic capacitance
VS-
GND
GND
Copper pour for thermal
pad must be connected to
negative supply (VS-)
Figure 77. INA826S PCB Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• OPAx330 50-μV VOS, 0.25-μV/°C, 35-μA CMOS Operational Amplifiers Zero-Drift Series
• REF32xx 4ppm/°C, 100μA, SOT23-6 Series Voltage Reference
• REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference
• SPICE-Based Analog Simulation Program
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA826SIDRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IN826S
INA826SIDRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
IN826S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jun-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
INA826SIDRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
INA826SIDRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA826SIDRCR
VSON
DRC
10
3000
367.0
367.0
35.0
INA826SIDRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
www.ti.com
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Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
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third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
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INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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