[ /Title (CD74 AC164 , CD74 ACT16 4) /Subject (8Bit SerialIn/ParallelOut Shift Register) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS , Harris Semiconductor, Advan ced TTL) /Creator () CD54/74AC164, CD54/74ACT164 Data sheet acquired from Harris Semiconductor SCHS240A 8-Bit Serial-In/Parallel-Out Shift Register September 1998 - Revised May 2000 Features Description • Buffered Inputs The ’AC164 and ’ACT164 are 8-bit serial-in/parallel-out shift registers with asynchronous reset that utilize Advanced CMOS Logic technology. Data is shifted on the positive edge of the clock (CP). A LOW on the Master Reset (MR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (DS1 and DS2) are provided; either one can be used as a Data Enable control. • Typical Propagation Delay - 6ns at VCC = 5V, TA = 25oC, CL = 50pF • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 • SCR-Latchup-Resistant CMOS Process and Circuit Design Ordering Information • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption PART NUMBER • Balanced Propagation Delays • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines TEMP. RANGE (oC) PACKAGE CD54AC164F3A -55 to 125 14 Ld CERDIP CD74AC164E -55 to 125 14 Ld PDIP CD74AC164M -55 to 125 14 Ld SOIC CD54ACT164F3A -55 to 125 14 Ld CERDIP CD74ACT164E -55 to 125 14 Ld PDIP CD74ACT164M -55 to 125 14 Ld SOIC NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Pinout CD54AC164, CD54ACT164 (CERDIP) CD74AC164, CD74ACT164 (PDIP, SOIC) TOP VIEW DS1 1 14 VCC DS2 2 13 Q7 Q0 3 12 Q6 Q1 4 11 Q5 Q2 5 10 Q4 Q3 6 9 MR GND 7 8 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © 2000, Texas Instruments Incorporated 1 CD54/74AC164, CD54/74ACT164 Functional Diagram 3 1 DS1 4 2 5 DS2 6 10 11 12 13 9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8 MR GND = 7 VCC = 14 CP MODE SELECT - TRUTH TABLE INPUTS H L h l X q ↑ OUTPUTS OPERATING MODE MR CP DS1 DS2 Q0 Q1 - Q7 RESET (CLEAR) L X X X L L-L SHIFT H ↑ l l L q0 - q6 H ↑ l h L q0 - q6 H ↑ h l L q0 - q6 H ↑ h h H q0 - q6 = = = = = = = HIGH voltage level steady state. LOW voltage level steady state. HIGH voltage level one setup time prior to the LOW-to_HIGH clock transition. LOW voltage level one setup time prior to the LOW-to-HIGH clock transition. Don’t care. Lowercase letters indicate the state of the referenced output prior to the LOW-to-HIGH clock transition. LOW-to-HIGH clock transition. 2 CD54/74AC164, CD54/74ACT164 I Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 5) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add ±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VIH - - 1.5 1.2 - 1.2 - 1.2 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH - VIH or VIL 3 2.1 - 2.1 - 2.1 - V 5.5 3.85 - 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V -0.05 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V - 3 CD54/74AC164, CD54/74ACT164 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V Input Leakage Current Quiescent Supply Current MSI ACT TYPES Low Level Output Voltage Input Leakage Current Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load VOL VIH or VIL II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD DS1, DS2 0.5 MR 0.74 CP 0.71 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 4 CD54/74AC164, CD54/74ACT164 Prerequisite For Switching Function PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX UNITS fMAX 1.5 7 - 6 - MHz 3.3 (Note 9) 62 - 54 - MHz 5 (Note 10) 86 - 75 - MHz 1.5 49 - 56 - ns 3.3 5.5 - 6.3 - ns 5 3.9 - 4.5 - ns 1.5 73 - 84 - ns 3.3 8.2 - 9.4 - ns 5 5.9 - 6.7 - ns 1.5 27 - 31 - ns 3.3 3.1 - 3.5 - ns 5 2.2 - 2.5 - ns 1.5 27 - 31 - ns 3.3 3.1 - 3.5 - ns 5 2.2 - 2.5 - ns 1.5 1 - 1 - ns 3.3 1 - 1 - ns 5 1 - 1 - ns fMAX 5 (Note 10) 80 - 70 - MHz MR Pulse Width tW 5 3.9 - 4.5 - ns CP Pulse Width tW 5 6.2 - 7.1 - ns Set-up Time tSU 5 2.2 - 2.5 - ns Hold Time tH 5 2.6 - 3 - ns tREM 5 0 - 0 - ns AC TYPES Max. Clock Frequency MR Pulse Width tW CP Pulse Width tW Set-up Time tSU Hold Time tH MR to CP Removal Time tREM ACT TYPES Max. Clock Frequency MR to CP Removal Time Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC PARAMETER -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 143 - - 157 ns 3.3 (Note 9) 4.5 - 15.9 4.4 - 17.5 ns 5 (Note 10) 3.2 - 11.4 3.1 - 12.5 ns AC TYPES Propagation Delay, CP to Qn 5 CD54/74AC164, CD54/74ACT164 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) (Continued) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 158 - - 174 ns 3.3 5 - 17.7 4.9 - 19.5 ns 5 3.6 - 12.6 3.5 - 13.9 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 150 - - 150 - pF Propagation Delay, CP to Qn tPLH, tPHL 5 (Note 10) 3.8 - 13.5 3.7 - 14.9 ns Propagation Delay, MR to Qn tPLH, tPHL 5 4.1 - 14.4 4 - 15.8 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 150 - - 150 - pF PARAMETER Propagation Delay, MR to Qn Input Capacitance Power Dissipation Capacitance ACT TYPES Input Capacitance Power Dissipation Capacitance NOTES: 8. Limits tested at 100%. 9. 3.3V Min at 3.6V, Max at 3V. 10. 5V Min at 5.5V, Max at 4.5V. 11. CPD is used to determine the dynamic power consumption per device. PD = CPDVCC2 fi Σ (CLVCC2 fo) + VCC ∆ICC, where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. tr tf tw INPUT 90% CP INPUT LEVEL VS 10% VS MR GND tw 1/fMAX tPLH tPHL ANY INPUT ANY 90% OUTPUT 10% VS tREC VS tTLH GND tPHL tTHL VS CP INPUT LEVEL GND FIGURE 1. FIGURE 2. VALID DS2 (1) INPUT LEVEL VS GND tSU tH DS1 (2) tSU CP INPUT LEVEL VS tH VS INPUT LEVEL VS DS2 (1) GND GND tREC tSU INPUT LEVEL tH INPUT LEVEL CP VS GND GND FIGURE 3. FIGURE 4. 6 CD54/74AC164, CD54/74ACT164 OUTPUT RL (NOTE) 500Ω DUT OUTPUT LOAD CL 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. AC ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC Input Level FIGURE 5. PROPAGATION DELAY TIMES 7 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) CD54AC164F3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type CD54ACT164F3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type CD74AC164E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74AC164EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74AC164M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC164M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC164M96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC164ME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT164E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74ACT164EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74ACT164M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT164M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT164M96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT164M96G4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT164ME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT164MG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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