ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Quad Channel 16-Bit, 100-MSPS High-SNR ADC Check for Samples: ADS5263 FEATURES APPLICATIONS • • • • • 1 • • • • • • • • • • • • • Maximum Sample Rate: 100 MSPS Programmable Device Resolution – Quad-Channel, 16-Bit, High-SNR Mode – Quad-Channel, 14-Bit, Low-Power Mode 16-Bit High-SNR Mode – 1.4 W Total Power at 100 MSPS – 355 mW / Channel – 4 Vpp Full-scale Input – 85-dBFS SNR at fin = 3 MHz, 100 MSPS 14-Bit Low-Power Mode – 785 mW Total Power at 100 MSPS – 195 mW/Channel – 2-Vpp Full-Scale Input – 74-dBFS SNR at fin = 10 MHz – Integrated Clamp (for interfacing to CCD sensors) Low-Frequency Noise Suppression Digital Processing Block – Programmable FIR Decimation Filters – Programmable Digital Gain: 0 dB to 12 dB – 2- or 4-Channel Averaging Programmable Mapping Between ADC Input Channels and LVDS Output Pins—Eases Board Design Variety of Test Patterns to Verify Data Capture by FPGA/Receiver Serialized LVDS Outputs Internal and External References 3.3-V Analog Supply 1.8-V Digital Supply Recovers From 6-dB Overload Within 1 Clock Cycle Package: – 9-mm × 9-mm 64-Pin QFN – Non-magnetic package option for MRI systems CMOS Technology Medical Imaging – MRI Spectroscopy CCD Imaging DESCRIPTION Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz. The device also has a 14-bit low power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The 14-bit mode supports a 2-Vpp full-scale input signal, with typical 74-dBFS SNR. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode. The ADS5263 has a digital processing block that integrates several commonly used digital functions, such as digital gain (up to 12 dB). It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This makes it very useful for narrow-band applications, where the filters can be used to improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR. A very unique feature is the programmable mapper module that allows flexible mapping between the input channels and the LVDS output pins. This helps to greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The data from each channel ADC is serialized and output on two pairs of LVDS output lines, along with a bit clock and a frame clock. Serial LVDS outputs reduce the number of interface lines. This, together with the low-power design, enables four channels to be packaged in a compact 9-mm × 9-mm QFN, allowing high system integration densities. In order to ease interfacing to CCD sensors, a clamp function is integrated in the device. Using this feature, the analog input pins can be clamped to an internal voltage, based on a SYNC signal. With this, the CCD sensor output can be easily ac-coupled to the ADS5263 analog inputs. The clamp feature and quad channels in a compact package make the ADS5263 attractive for industrial CCD imaging applications. The device integrates an internal reference trimmed to accurately match across devices. The device can optionally be driven with external references. Best performance can be achieved through the internal reference mode. The ADS5263 is available in a non-magnetic QFN package that does not create any MRI signature. The device is specified over the full industrial temperature range. 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 LGND LVDD AVDD AGND www.ti.com ADS 5263 IN1B_P OUT1P SERIALIZER IN1A_P 16 bit FE 14 bit ADC OUT1M DIGITAL OUT2P IN1A_M SERIALIZER OUT2M 16 bit ADC IN1B_M IN2B_P OUT3P SERIALIZER IN2A_P 16 bit FE 14 bit ADC OUT3M DIGITAL OUT4P IN2A_M SERIALIZER OUT4M 16 bit ADC IN2B_M IN3B_P OUT5P SERIALIZER IN3A_P 16 bit FE 14 bit ADC OUT5M DIGITAL OUT6P IN3A_M SERIALIZER OUT6M 16 bit ADC IN3B_M IN4B_P OUT7P SERIALIZER IN4A_P 16 bit FE 14 bit ADC OUT7M DIGITAL OUT8P IN4A_M SERIALIZER OUT8M 16 bit ADC IN4B_M Clamp signal Differential / Single-Ended Input Clock CLKP CLKM Sync signal Serializer clocks BIT CLOCK, 8X ADC Clocking LCLKP LCLKM CLOCK BUFFER FRAME CLOCK, 1X PLL CLOCKGEN ADCLKP ADCLKM ADC CONTROL SCLK SDOUT RESETZ CSZ PDN SYNC VCM REFB REFT INT/EXTZ ISET SDATA SERIAL INTERFACE REFERENCE Figure 1. ADS5263 Block Diagram Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 3 4 Channel 2 ADC Data Channel 3 ADC Data Channel 4 ADC Data 16-BIT ADC Submit Documentation Feedback Product Folder Link(s) :ADS5263 DIGITAL PROCESSING BLOCK for Average of 4 channels Average of 2 channels Channel 1 ADC Data CHANNEL 1 12-tap filter 23-tap filter (Odd Tap) 24-tap filter (Even Tap) Custom Coefficients 23-tap filter (Odd Tap) 24-tap filter (Even Tap) Built-in Coefficients Decimation by 2 or by 4 or by 8 Decimation by 2 or by 4 GAIN (0 to 12 dB , 1 dB steps ) Ramp - Test Patterns Serializer Wire 2 Channel 4 Serializer Wire 1 Serializer Wire 2 Channel 3 Serializer Wire 1 Serializer Wire 2 Channel 2 Serializer Wire 1 Serializer Wire 2 Channel 1 Serializer Wire 1 ADS 5263 MULTIPLEXER 8:8 MAPPER OUT 4B OUT 4A OUT 3B OUT 3A OUT 2B OUT 2A OUT 1B OUT 1A LVDS OUTPUTS ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Figure 2. ADS5263 Digital Processing Block Copyright © 2011, Texas Instruments Incorporated ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com RESETZ SCLK SDATA CSZ AVDD CLKM CLKP AVDD INT/EXTZ REFT REFB VCM SDOUT ISET AVDD SYNC PIN CONFIGURATION – ADS5263 64 QFN (THERMAL PAD) RGC Package (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 IN1A_P 1 IN4A_M IN1A_M 2 47 IN4A_P AGND 3 46 AGND IN1B_P 4 45 IN4B_M IN1B_M 5 44 IN4B_P AGND 6 43 AGND IN2A_P 7 42 IN3A_M IN2A_M 8 41 IN3A_P AGND 9 40 AGND 39 IN3B_M IN2B_P 10 IN2B_M 11 38 IN3B_P LGND 12 37 AGND PD 13 36 LGND LGND 14 35 LVDD OUT1P 15 34 OUT8M OUT1M 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 32 OUT8P OUT2P OUT2M OUT3P OUT3M OUT4P OUT4M ADCLKP ADCLKM LCLKP LCLKM OUT5P OUT5M OUT6P OUT6M OUT7P OUT7M Thermal Pad 64 QFN P0056-19 PIN FUNCTIONS PIN NAME PIN DESCRIPTION TYPE NO. 24 NO. OF PINS ADCLKM LVDS frame clock (1X) – negative output O ADCLKP LVDS frame clock (1X) – positive output O 23 AGND Analog ground I 3, 6, 9, 37, 40, 43, 46 7 AVDD Analog power supply, 3.3 V I 50, 57, 60 3 CLKM Negative differential clock input. For single-ended clock, tie CLKM to ground. I 59 1 CLKP Positive differential clock input I 58 1 CS Serial interface enable input, active LOW. The pin has an internal 300-kΩ pulldown resistor to ground I 61 1 IN1A_P, IN1A_M Differential analog input for channel 1, 16 bit ADC I 1, 2 2 IN1B_P, IN1B_M Differential analog input for channel 1, 14 bit ADC I 4, 5 2 IN2A_P, IN2A_M Differential analog input for channel 2, 16 bit ADC I 7, 8 2 IN2B_P, IN2B_M Differential analog input for channel 2, 14 bit ADC I 10, 11 2 IN3A_P, IN3A_M Differential analog input for channel 3, 16 bit ADC I 41, 42 2 IN3B_P, IN3B_M Differential analog input for channel 3, 14 bit ADC I 38, 39 2 IN4A_P, IN4A_M Differential analog input for channel 4, 16 bit ADC I 47, 48 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 5 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com PIN FUNCTIONS (continued) PIN NAME PIN DESCRIPTION TYPE NO. NO. OF PINS IN4B_P, IN4B_M Differential analog input for channel 4, 14 bit ADC I 44, 45 2 INT/EXT Internal/external reference mode select input Logic HIGH –internal reference Logic LOW – external reference I 56 1 ISET Bias pin – 56.2 kΩ resistor (1% tolerance value) to ground I 51 1 LCLKM LVDS bit clock (8X) – negative output O 26 1 LCLKP LVDS bit clock (8X) – positive output O 25 1 LGND Digital ground I 12, 14, 36 3 LVDD Digital and I/O power supply, 1.8 V I 35 1 OUT1P, OUT1M Wire 1, channel 1 LVDS differential output O 15, 16 2 OUT2P, OUT2M Wire 2, channel 1 LVDS differential output O 17, 18 2 OUT3P, OUT3M Wire 1, channel 2, LVDS differential output O 19, 20 2 OUT4P, OUT4M Wire 2, channel 2 LVDS differential output O 21, 22 2 OUT5P, OUT5M Wire 1, channel 3 LVDS differential output O 27, 28 2 OUT6P, OUT6M Wire 2, channel 3 LVDS differential output O 29, 30 2 OUT7P, OUT7M Wire 1, channel 4 LVDS differential output O 31, 32 2 OUT8P, OUT8M Wire 2, channel 4 LVDS differential output O 33, 34 2 PD Power-down input I 13 1 REFB Negative-reference input/output IO 54 1 REFT Positive-reference input/output IO 55 1 RESET Serial interface RESET input, active LOW. When using the serial interface mode, the user must initialize internal registers through hardware RESET by applying a low-going pulse on this pin or by using software reset option. See the Serial Interface section. I 64 1 SCLK Serial interface clock input. The pin has an internal 300-kΩ pulldown resistor. I 63 1 SDATA Serial interface data input. The pin has an internal 300-kΩ pulldown resistor. I 62 1 SDOUT Serial register readout This pin is in the high-impedance state after reset. When the <READOUT> bit is set, the SDOUT pin becomes active. This is a CMOS digital output running from the AVDD supply. O 52 1 SYNC Input signal to synchronize channels and chips when used with reduced output data rates Alternate function: Clamp signal input (14-bit ADC mode only) I 49 1 VCM Outputs the common-mode voltage (1.5 V) that can be used externally to bias the analog input pins. O 53 1 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE LEAD/BALL FINISH ADS5263 QFN-64 RGC –40°C to 85°C Cu Matte Sn (1) PACKAGE MARKING ORDERING NUMBER ADS5263 ADS5263IRGCT ADS5263IRGCR ADS5263NM ADS5263IRGCT-NM ADS5263IRGCR-NM TRANSPORT MEDIA, QTY Tape and reel Eco Plan – The planned eco-friendly classification: ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT Supply voltage range, AVDD –0.3 V to 3.9 V Supply voltage range, LVDD –0.3 V to 2.2 V –0.3 to 0.3 V –0.3V to minimum (3.6, AVDD + 0.3 V) V –0.3 V to AVDD + 0.3 V V Voltage between AGND and DRGND Voltage applied to analog input pins – INP_A, INM_A, INP_B, INM_B Voltage applied to input pins – CLKP, CLKM (2), RESET, SCLK, SDATA, CSZ Voltage applied to reference input pins –0.3 to 2.8 V Operating free-air temperature range, TA –40 to 85 °C Operating junction temperature range, TJ 125 °C Storage temperature range, Tstg ESD, human body model (1) (2) –65 to 150 °C 2 kV Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is < |0.3V|. This prevents the ESD protection diodes at the clock input pins from turning on. THERMAL INFORMATION ADS5263 THERMAL METRIC (1) QFN UNITS 64 PINS θJA Junction-to-ambient thermal resistance 20.6 θJCtop Junction-to-case (top) thermal resistance 6.1 θJB Junction-to-board thermal resistance 2.7 ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 2.6 θJCbot Junction-to-case (bottom) thermal resistance 0.4 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 7 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT 3 3.3 3.6 V 1.7 1.8 1.9 V SUPPLIES AVDD Analog supply voltage LVDD Digital supply voltage ANALOG INPUTS Differential input voltage range 16-bit ADC mode 4 VPP 14-bit ADC mode 2 VPP 1.5 ±0.1 Input common-mode voltage Maximum analog input frequency 4-Vpp input amplitude, 16-bit ADC mode 70 2-Vpp input amplitude, 16-bit ADC mode 140 V MHz CLOCK INPUT Input clock sample rate 10 Sine wave, ac-coupled Input clock amplitude differential LVPECL, ac-coupled (VCLKP-VCLKM) LVDS, ac-coupled 1.5 VPP 0.2 1.6 VPP 0.2 0.7 VPP LVCMOS, single-ended, ac-coupled Input clock duty cycle 100 MSPS 0.2 3.3 35% 50% V 65% DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DRGND RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) –40 Operating free-air temperature, TA 8 Submit Documentation Feedback 5 pF 100 Ω 85 °C Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS DYNAMIC PERFORMANCE – 16-BIT ADC Typical values are at 25°C, AVDD = 3.3V, LVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input (unless otherwise noted). MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, LVDD = 1.8 V PARAMETERS SNR Signal-to-noise ratio TEST CONDITIONS 100 MSPS 80 MSPS MIN TYP fin = 5 MHz at 25°C 81 84.5 85.5 fin = 5 MHz across temperature 80 fin = 10 MHz 84.6 85.3 fin = 30 MHz 82.7 83.1 fin = 65 MHz 78.9 79.4 78.2 78.8 77.5 79 74.8 76 71.6 72.5 fin = 5 MHz 76.6 SINAD fin = 10 MHz Signal-to-noise and distortion finn = 30 MHz ratio fin = 65 MHz MAX MIN TYP MAX UNITS dBFS dBFS ENOB Effective number of bits fin = 5 MHz 12.7 12.8 LSB DNL Differential non-linearity fin = 5 MHz ±0.1 ±0.1 LSB INL Integrated non-linearity fin = 5 MHz ±2.2 ±2.2 LSB 80 80 80 81 76 77 fin = 5 MHz 73.5 fin = 10 MHz SFDR Spurious-free dynamic range fin = 30 MHz fin = 65 MHz 74 75 78 78.8 fin = 10 MHz 77.4 79.2 fin = 30 MHz 74.5 76 71.4 72.4 83.5 85 fin = 10 MHz 81 84 fin = 30 MHz 80 83 75 76 80 80 fin = 10 MHz 80 81 fin = 30 MHz 75 77 fin = 65 MHz 74 75 fin = 5 MHz 80 90 fin = 10 MHz 85 90 finn = 30 MHz 85 88 fin = 5 MHz THD Total harominc distortion 72.5 fin = 65 MHz fin = 5 MHz HD2 Second harmonic Distortion 73.5 fin = 65 MHz fin = 5 MHz HD3 Third harmonic distortion Worst Spur Excluding HD2, HD3 73.5 dBc dBc dBc dBc dBc fin = 65 MHz 82 86 IMD 2-tone intermodulation distortion f1 = 8 MHz, f2 = 10 MHZ, each tone at –7 dBFS 92 92 dBFS Input overload recovery Recovery to within 1% (of final value) for 6-dB overload with sine wave input 1 1 clock cyles PSRR AC power supply rejection ratio For 50 mV signal on AVDD supply, up to 1 MHz ripple frequency 30 30 dB Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 9 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS GENERAL – 16-BIT ADC MODE Typical values are at 25°C, AVDD = 3.3V, LVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input (unless otherwise noted). MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, LVDD = 1.8V 100 MSPS PARAMETERS MIN 80 MSPS MA TYP X MI N TYP MAX UNITS ANALOG INPUT Differential input voltage range (0-dB gain) Differential input resistance (at dc) Differential input capacitance Analog input bandwidth Analog input common-mode current (per input pin) VCM common-mode output voltage VCM output current capability 4 4 Vpp 2.5 2.5 kΩ 12 12 pF 700 700 MHz 8 8 1.5 1.5 3 3 µA/MSPS V mA DC ACCURACY Offset error EGREF Gain error due to internal reference inaccuracy alone EGCHAN Gain error of channel alone -2.5 Gain matching ±10 ±30 ±10 mV ±0.5 ±0.5 % FS 1 1 % FS 0.5% 0.5% 2.5 POWER SUPPLY IAVDD Analog supply current 370 390 290 mA ILVDD Digital and output buffer supply current with 100-Ω external LVDS termination 110 150 100 mA Analog power 1.22 0.96 W Digital power 0.2 0.18 W Global power down Standby 10 Submit Documentation Feedback 63 110 63 mW 208 250 208 mW Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS DYNAMIC PERFORMANCE – 14-BIT ADC Typical values are at 25°C, AVDD = 3.3V, LVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input (unless otherwise noted). MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, LVDD = 1.8 V PARAMETERS SNR Signal-to-noise ratio TEST CONDITIONS fin = 5 MHz 100 MSPS MIN TYP 68.8 74 finv = 30 MHz 73 fin = 65 MHz SINAD Signal-to-noise and distortion ratio SFDR Spurious-free dynamic range THD Total harmonic distortion HD2 Second harmonic Distortion HD3 Third harmonic distortion fin = 5 MHz 65.8 71.9 70.3 71.8 81 fin = 65 MHz 78 69 78 fin = 65 MHz 76.5 84 fin = 65 MHz 80 71.8 81 fin = 65 MHz 78 Submit Documentation Feedback Product Folder Link(s) :ADS5263 dBc 85 fin = 30 MHz Copyright © 2011, Texas Instruments Incorporated dBc 92 fin = 30 MHz fin = 5 MHz dBc 83.5 fin = 30 MHz 71.8 dBFS 85 fin = 30 MHz fin = 5 MHz dBFS 73.5 finn = 65 MHz fin = 5 MHz UNITS 71.3 fin = 30 MHz fin = 5 MHz MAX dBc 11 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com DIGITAL CHARACTERISTICS The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = 3.3V, LVDD = 1.8V PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS – RESET, SCLK, SDATA, CS, PDN, SYNC, INT/EXT All digital inputs support 1.8-V and 3.3-V CMOS logic levels. VIH High-level input voltage VIL Low-level input voltage IIH High-level input current SDATA, SCLK, CS IIL Low-level input current SDATA, SCLK, CS 1.3 V 0.4 (1) V VHIGH = 1.8 V 5 μA VLOW = 0 V 0 μA DIGITAL CMOS OUTPUT – SDOUT VOH High-level output voltage IOH = 100 µA AVDD – 0.05 V VOL Low-level output voltage IOL = 100 µA 0.05 V DIGITAL OUTPUTS – LVDS INTERFACE (OUT1P/M TO OUT8P/M, ADCLKP/M, LCLKP/M) VODH High-level output differential voltage With external 100-Ω termination 275 VODL Low-level output differential voltage With external 100-Ω termination VOCM Output common-mode voltage (1) 370 465 mV –465 –370 –275 mV 1000 1200 1400 mV CS, SDATA, SCLK have internal 300-kΩ pulldown resistor. OUTP Logic Logic 0 0 VODL = -350 mV* Logic 0 VODH = +350 mV* OUTM VOCM GND GND *With external 100-W termination Figure 3. LVDS Output Voltage Levels 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TIMING REQUIREMENTS (1) Typical values are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, sampling frequency = 100 MSPS, sine wave input clock = 1.5 Vpp clock amplitude, CLOAD = 5 pF (2), RLOAD = 100 Ω (3), unless otherwise noted. MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, LVDD = 1.7 V to 1.9 V PARAMETER tj CONDITIONS MIN Aperture jitter TYP MAX 220 Wake-up time ADC latency Time to valid data after coming out of STANDBY mode 10 Time to valid data after coming out of global power down 60 Latency of ADC alone, excludes the delay from input clock to output clock (tPDI), Figure 5 16 UNIT fs rms μs Clock cycles 2 WIRE, 16× SERIALIZATION (4) tsu Data setup time Data valid (5) to zero-crossing of LCLKP 0.23 ns th Data hold time Zero-crossing of LCLKP to data becoming invalid (5) 0.31 ns tPDI Clock propagation delay Input clock rising edge crossover to output frame clock ADCLKP rising edge crossover, tPDI = (ts/4) + tdelay Variation of tPDI Between two devices at same temperature and LVDD supply ±0.6 LVDS bit clock duty cycle Duty cycle of differential clock, (LCLKP-LCLKM) 50% 6.8 8.8 10.8 ns ns tRISE tFALL Data rise time, Data fall time Rise time measured from –100 mV to 100 mV, Fall time measured from 100 mV to –100 mV 10 MSPS ≤ Sampling frequency ≤ 100 MSPS 0.17 ns tCLKRISE tCLKFALL Output clock rise time, Output clock fall time Rise time measured from –100 mV to 100 mV Fall time measured from 100 mV to –100 mV 10 MSPS ≤ Sampling frequency ≤ 100 MSPS 0.2 ns (1) (2) (3) (4) (5) Timing parameters are ensured by design and characterization and not tested in production. CLOAD is the effective external single-ended load capacitance between each output pin and ground. RLOAD is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Data valid refers to logic HIGH of 100 mV and logic LOW of –100 mV. Table 1. LVDS Timing at Lower Sampling Frequencies - 2 Wire, 16× Serialization SAMPLING FREQUENCY, MSPS SETUP TIME, ns Min Typ Max HOLD TIME, ns Min 80 0.47 0.47 65 0.56 0.7 50 0.66 1 20 2.7 2.8 Typ Max Table 2. LVDS Timing for 1 Wire 16× Serialization SAMPLING FREQUENCY, MSPS SETUP TIME, ns Min Typ Max HOLD TIME, ns Min 65 0.15 0.31 50 0.27 0.35 40 0.45 0.55 20 1.1 1.4 Clock Propagation Delay tPDI = (ts/8) + tdelay 10 MSPS < Sampling Frequency < 65 MSPS Typ tdelay, ns Typ Min Max 6.8 8.8 10.8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 Max 13 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Table 3. LVDS Timing for 2 Wire, 14× Serialization SAMPLING FREQUENCY, MSPS SETUP TIME, ns Min Typ Max HOLD TIME, ns Min 100 0.29 0.39 80 0.51 0.60 65 0.58 0.82 50 0.85 1.20 20 3.2 3.3 Clock Propagation Delay tPDI = (ts/3.5) + tdelay 10 MSPS < Sampling Frequency < 100 MSPS Typ Max tdelay, ns Typ Min Max 6.8 8.8 10.8 Table 4. LVDS Timing for 1 Wire, 14× Serialization SAMPLING FREQUENCY, MSPS SETUP TIME, ns Min Typ Max HOLD TIME, ns Min 65 0.19 0.28 50 0.37 0.42 30 0.70 1.0 20 1.3 1.5 Clock Propagation Delay tPDI = (ts/7) + tdelay 10 MSPS < Sampling Frequency < 65 MSPS Typ Max tdelay, ns MIN Typ Max 6.8 8.8 10.8 CLKM CLKM INPUT INPUTCLOCK CLOCK 1X 1X CLKP CLKP ttPDI PDI ADCLKM ADCLKM FRAME FRAME CLOCK CLOCK 0.5X X ADCLKP ADCLKP ttsusu t h th LCLKM LCLKM BIT CLOCK 4X 4X LCLKP LCLKP tsu OUTPUT DATA &FRAME CLK OUT 1, OUT 2 OUT 3, OUT 4 OUT 5, OUT 6 OUT 7, OUT 8 th Dn * th h tsu Dn +1* Figure 4. LVDS Timing 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 FRAME CLOCK Freq = 1 ´ x fS OUTPUT DATA Rate = 16 ´ x fS BIT CLOCK Freq = 8 ´ x fS INPUT CLOCK Freq = fS INPUT SIGNAL ADCLKP ADCLKM OUTM OUTP DCLKM DCLKP CLKP CLKM tA Sample N Sample N + 15 D15 D14 D13 D12 D11 D10 LATENCY = 16 Clocks D9 D7 D6 SAMPLE N – 1 D8 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 tPDI Sample N + 16 D9 D7 D6 SAMPLE N D8 D5 D4 D3 D2 D1 D0 Sample N + 17 D15 D14 www.ti.com SLAS760B – MAY 2011 – REVISED OCTOBER 2011 ADS5263 Figure 5. Latency Diagram Submit Documentation Feedback 15 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com DEVICE CONFIGURATION ADS5263 has several modes that can be configured using a serial programming interface, as described below. In addition, the device has dedicated parallel pins for controlling common functions such as power down and internal or external reference selection. Table 5. PDN CONTROL PIN VOLTAGE APPLIED ON PDN STATE OF REGISTER BIT <CONFIG PDN pin> DESCRIPTION 0V X (don't care) Normal operation 0 Device enters global power-down mode 1 Device enters standby mode Logic HIGH Table 6. INT/EXT CONTROL PIN VOLTAGE APPLIED ON INT/EXT 0V Logic HIGH DESCRIPTION External reference mode. Reference voltage must be forced on REFT and REFB pins. Internal reference SERIAL INTERFACE The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins CS (serial interface enable), SCLK (serial interface clock) and SDATA (serial interface data). When CS is low, • Serial shift of bits into the device is enabled. • Serial data (on SDATA pin) is latched at every rising edge of SCLK. • The serial data is loaded into the register at every 24th SCLK rising edge. In case the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active CS pulse. The first 8 bits form the register address and the remaining 16 bits form the register data. The interface can work with SCLK frequencies from 20 MHz down to very low speeds (a few hertz) and also with non-50% SCLK duty cycle. Register Initialization After power up, the internal registers MUST be initialized to their default values. This can be done in one of two ways: 1. Through a hardware reset by applying a low-going pulse on the RESET pin (of width greater than 10 ns) as shown in Figure 6. OR 2. By applying software reset. Using the serial interface, set the <RESET> bit (D7 in register 0x00) to HIGH. This initializes internal registers to their default values and then self-resets the <RESET> bit to low. In this case, the RESET pin is kept high (inactive). 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com REGISTER DATA REGISTER ADDRESS SDATA A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 tDSU D11 D10 D9 D7 D8 D6 D5 D4 D3 D2 D1 D0 tDH SCLK tSLOADH tSCLK tSLOADS CSZ RESETZ Figure 6. Serial Interface Timing SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, MIN and MAX values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, LVDD = 1.8 V, unless otherwise noted. PARAMETER MIN TYP > DC MAX UNIT 20 MHz fSCLK SCLK frequency (= 1/ tSCLK) tSLOADS CS to SCLK setup time 25 ns tSLOADH SCLK to CS hold time 25 ns tDS SDATA setup time 25 ns tDH SDATA hold time 25 ns RESET TIMING Typical values at 25°C, MIN and MAX values across the full temperature range TMIN = –40°C to TMAX = 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN t1 Power-on delay Delay from power up of AVDD and LVDD to RESET pulse active t2 Reset pulse duration Pulse duration of active RESET signal t3 Register write delay Delay from RESET disable to CS active TYP MAX 1 50 UNIT ms ns 100 ns POWER SUPPLY AVDD,DRVDD t1 RESET t2 t3 SEN NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET has to be tied permanently HIGH. Figure 7. Reset Timing Diagram Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 17 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Serial Register Readout The device includes a mode where the contents of the internal registers can be read back on SDOUT pin. This may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. By default, after power up and device reset, the SDOUT pin is in the high-impedance state. When the readout mode is enabled using the register bit <READOUT>, SDOUT outputs the contents of the selected register serially, described as follows. • Set register bit <READOUT> = 1 to put the device in serial readout mode. This disables any further writes into the internal registers, EXCEPT the register at address 1. Note that the <READOUT> bit itself is also located in register 1. The device can exit readout mode by writing <READOUT> to 0. Only the contents of register at address 1 cannot be read in the register readout mode. • Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content is to be read. • The device serially outputs the contents (D15–D0) of the selected register on the SDOUT pin. • The external controller can latch the contents at the rising edge of SCLK. • To exit the serial readout mode, reset register bit <READOUT> = 0, which enables writes into all registers of the device. At this point, the SDOUT pin enters the high-impedance state. A) Enable Serial Readout (<READOUT> = 1) REGISTER DATA (D15:D0) = 0x0001 REGISTER ADDRESS (A7:A0) = 0x01 SDATA 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SCLK CSZ Pin SDOUT Becomes Active and Forces Low Pin SDOUT is tri-stated SDOUT B) Read Contents of Register 0x0F. This Register has been Initialized with 0x0200 (The Device was earlier put in global power down) REGISTER DATA (D15:D0) = XXXX (don’t care) REGISTER ADDRESS (A7:A0) = 0x0F SDATA A7 A6 A5 A4 A3 A2 0 0 0 0 0 0 A1 A0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 SCLK CSZ SDOUT 0 0 0 0 0 0 1 SDOUT Output Contents of Register 0x0F in the same cycle, MSB first Figure 8. Serial Readout Timing 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com SERIAL REGISTER MAP Table 7. Summary of Functions Supported by Serial Interface (1) Register Address Register Data (2) A7-A0 in HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <RESET> 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <READOUT> 2 0 0 <EN SYNC> 0 0 0 0 0 0 0 0 0 0 0 0 0 <CONFIG PD PIN> <GLOBAL PDN> <STANDBY > <PDN CH 4B> <PDN CH 3B> <PDN CH 2B> <PDN CH 1B> <PDN CH 4A> <PDN CH 3A> <PDN CH 2A> <PDN CH 1A> F 0 11 0 0 0 0 0 0 0 0 0 <LVDS CURR DATA> 0 <LVDS CURR ADCLK> 0 <LVDS CURR LCLK> 12 0 <ENABLE LVDS TERM> 0 0 0 <LVDS TERM DATA> 0 <LVDS TERM ADCLK> 0 <LVDS TERM LCLK> 14 0 0 0 0 0 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 <RAMP TEST PATTERN> <DUAL CUSTOM PATTERN> <SINGLE CUSTOM PATTERN> <EN LFNS CH 4> <EN LFNS CH 3> CUSTOM PATTERN B DATA[15...14] <EN LFNS CH 2> <EN LFNS CH 1> CUSTOM PATTERN A DATA[15...14] 26 CUSTOM PATTERN A DATA[13..0] 0 0 27 CUSTOM PATTERN B DATA[13..0] 0 0 28 <EN WORDWISE CONTROL> 29 0 0 0 0 0 0 <GAIN CH4> 2A (1) (2) D0 0 0 0 0 0 0 <GAIN CH3> 0 0 <WORDWISE CH4 <WORDWISE CH3> <WORDWISE CH2> <WORD-WISE CH1> 0 0 <EN DIG FILTER> <EN AVG> <GAIN CH2> <AVG OUT 4> <GAIN CH1> <AVG OUT 3> <AVG OUT 2> <AVG OUT 1> 2C 0 0 0 0 0 0 2E 0 0 0 0 0 0 <FILTER TYPE CH1> <DEC by RATE CH1> 0 <ODD TAP CH1> 0 <USE FILTER CH1> 2F 0 0 0 0 0 0 <FILTER TYPE CH2> <DEC by RATE CH2> 0 <ODD TAP CH2> 0 <USE FILTER CH2> 30 0 0 0 0 0 0 <FILTER TYPE CH3> <DEC by RATE CH3> 0 <ODD TAP CH3> 0 <USE FILTER CH3> 31 0 0 0 0 0 0 <FILTER TYPE CH4> <DEC by RATE CH4> 0 <ODD TAP CH4> 0 <USE FILTER CH4> 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <OUTPUT RATE> 42 0 0 0 0 0 0 0 0 0 <PHASE_DDR> 0 0 0 0 0 <DESKEW PATTERN> <2-WIRE 0.5X FRAME> 45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <SYNC PATTERN> 46 <EN SERIALI ZATION> 0 0 0 <16× SERIALI ZATION> <14× SERIALI ZATION> 0 0 0 0 <PAD two 0s> 0 <MSB FIRST> <2S COMPL> 0 50 <EN MAP1> 0 0 0 <MAP_Ch1234_OUT2A> <MAP_Ch1234_OUT1B> <MAP_Ch1234_OUT1A> Multiple functions in a register can be programmed in a single write operation. All registers are cleared to zero after software or hardware reset is applied. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 19 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Table 7. Summary of Functions Supported by Serial Interface(1) (continued) Register Address Register Data (2) A7-A0 in HEX D15 D14 D13 D12 51 <EN MAP2> 0 0 0 52 <EN MAP3> 0 0 0 0 0 0 0 B3 <EN ADC MODE> 0 0 0 0 0 0 0 20 D11 D10 D9 D8 D7 <MAP_Ch1234_OUT3B> 0 Submit Documentation Feedback D6 D5 D4 D3 D2 D1 <MAP_Ch1234_OUT3A> <MAP_Ch1234_OUT2B> <MAP_Ch1234_OUT4B> <MAP_Ch1234_OUT4A> 0 0 0 0 0 0 D0 16B/14B ADC MODE Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Default State After Reset • Device is in normal operation mode with 16-bit ADC enabled for all 4 channels. • Output interface is 1-wire, 16× serialization with 8× bit clock and 1× frame clock frequency • Serial readout is disabled • PD pin is configured as global power-down pin • LVDS output current is set to 3.5 mA; internal termination is disabled. • Digital gain is set to 0 dB. • Digital modes such as LFNS, digital filters are disabled. DESCRIPTION OF SERIAL REGISTERS REGISTER ADDRESS A7–A0 IN HEX 0 REGISTER DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <RESET> D0 <RESET> 1 Software reset applied – resets all internal registers to their default values and self-clears to 0 A7–A0 IN HEX 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <READOUT> D0 <READOUT> 0 Serial readout of registers is disabled. Pin SDOUT is in the high-impedance state. 1 Serial readout enabled, SDOUT pin functions as serial data readout. A7–A0 IN HEX 2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 <EN SYNC> 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 <EN SYNC> 0 SYNC pin is disabled. 1 SYNC pin can be used to synchronize the decimation filters across channels and across multiple chips. A7–A0 IN HEX F D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 <CON FIG PD PIN> <GLO BAL PDN> <STA ND BY> <PDN CH 4B> <PDN CH 3B> <PDN CH 2B> <PDN CH 1B> <PDN CH 4A> <PDN CH 3A> <PDN CH 2A> <PDN CH 1A> D10 <CONFIG PDN PIN> Can be used to configure PDN pin as global power down or standby 0 PDN pin functions as global power down. 1 PDN pin functions as standby. D9 <GLOBAL PDN> 0 Normal ADC operation 1 Device is put in global power down. All four channels are powered down, including LVDS output data and clock buffers. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 21 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com D8 <STANDBY> 0 Normal ADC operation 1 Device is put in standby. All four ADCs are powered down. Internal PLL, LVDS bit clock, and frame clock are running. D7– D0 <PDN CH X> Individual channel power down 0 Channel X is powered up. 1 Channel X is powered down. REGISTER ADDRESS A7–A0 IN HEX 11 REGISTER DATA D15 D14 D13 D12 D11 0 0 0 0 0 D10 D9 D8 <LVDS CURR DATA> D7 0 D6 D5 D4 <LVDS CURR ADCLK> D3 0 D2 D1 D0 <LVDS CURR LCLK> D10–D8 <LVDS CURR DATA> LVDS current control for data buffers 000 3.5 mA 001 2.5 mA 010 1.5 mA 011 0.5 mA 100 7.5 mA 101 6.5 mA 110 5.5 mA 111 4.5 mA D6–D4 <LVDS CURR LCLK> LVDS current control for frame-clock buffer 000 3.5 mA 001 2.5 mA 010 1.5 mA 011 0.5 mA 100 7.5 mA 101 6.5 mA 110 5.5 mA 111 4.5 mA D2–D0 <LVDS CURR LCLK> LVDS current control for bit-clock buffer 000 3.5 mA 001 2.5 mA 010 1.5 mA 011 0.5 mA 100 7.5 mA 101 6.5 mA 110 5.5 mA 111 4.5 mA 22 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com REGISTER ADDRESS A7–A0 IN HEX 12 REGISTER DATA D15 D14 D13 D12 D11 0 <ENABLE LVDS TERM> 0 0 0 D14 <ENABLE LVDS TERM> 0 Internal termination disabled 1 Internal termination enabled D10 D9 D8 <LVDS TERM DATA> D7 0 D6 D5 D4 <LVDS TERM ADCLK> 0 D3 0 D2 D1 D0 <LVDS TERM LCLK> D10–D8 <LVDS TERM DATA> Internal LVDS termination for data buffers 000 No internal termination 001 150 Ω 010 100 Ω 011 60 Ω 100 80 Ω 101 55 Ω 110 45 Ω 111 35 Ω D6–D4 <LVDS TERM ADCLK> Internal LVDS termination for frame clock buffer 000 No internal termination 001 150 Ω 010 100 Ω 011 60 Ω 100 80 Ω 101 55 Ω 110 45 Ω 111 35 Ω D2–D0 <LVDS TERM LCLK> Internal LVDS termination for bit clock buffer 000 No internal termination 001 150 Ω 010 100 Ω 011 60 Ω 100 80 Ω 101 55 Ω 110 45 Ω 111 35 Ω Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 23 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 REGISTER ADDRESS A7–A0 IN HEX 14 www.ti.com REGISTER DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 <EN LFNS CH4> <EN LFNS CH3> <EN LFNS CH2> <EN LFNS CH1> D3–D0 <EN LFNS CH X> low-frequency noise-suppression mode is enabled for channel X. 0 LFNS mode is disabled. 1 LFNS mode is enabled for channel X. In 16-bit ADC mode, <EN LFNS CH X> enables LFNS for channel CH X. In 14-bit ADC mode, <EN LFNS CH X> enables LFNS for channel CH X B. A7–A0 IN HEX 25 D15 D14 D13 D12 D11 D10 D9 D8 D7 0 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0 <RAMP <DUAL <SINGLE CUSTOM CUSTOM TEST CUSTOM CUSTOM PATTERN B PATTERN A PATTERN PATTERN PATTERN DATA[15...14] DATA[15...14] > > > D6 <RAMP TEST PATTERN> 0 Ramp test pattern is disabled. 1 Ramp test pattern is enabled; output code increments by one LSB every clock cycle. D5 <DUAL CUSTOM PATTERN> 0 Dual custom pattern is disabled. 1 Dual custom pattern is enabled. Two custom patterns can be specified in registers PATTERN A and PATTERN B. The two patterns are output one after the other (instead of ADC data). D5 <SINGLE CUSTOM PATTERN> 0 Single custom pattern is disabled. 1 Single custom pattern is enabled. The custom pattern can be specified in register A and is output every clock cycle instead of ADC data. D3–D2 <CUSTOM PATTERN B bits D15 and D14> D1–D0 <CUSTOM PATTERN A bits D15 and D14> Specify bits D15 and D14 of custom pattern in these register bits. A7–A0 IN HEX 26 27 D15 D14 D13 D12 D11 D10 D9 D8 D7 CUSTOM PATTERN A DATA[13..0] CUSTOM PATTERN B DATA[13..0] D6 D5 D4 D3 D2 D1 D0 0 0 0 0 Specify bits D13 to D0 of custom pattern in these registers. 24 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com A7–A0 IN HEX 28 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 <EN WORDWISE CONTROL> D3 D2 D1 D0 <WORDWISE CH4> <WORDWISE CH3> <WORDWISE CH2> <WORDWISE CH1> D15 <EN WORD-WISE CONTROL> 0 Control of word-wise mode is disabled. 1 Control of word-wise mode is enabled. D3–D0 <WORD-WISE CH XL> 0 Output data is serially sent in byte-wise format. 1 Output data is serially sent in word-wise format ONLY when 2-wire mode is enabled (see register 0x46). A7–A0 IN HEX D15 D14 D13 D12 <GAIN CH4> 2A D11 D10 D9 D8 D7 <GAIN CH3> D6 D5 <GAIN CH2> D4 D3 D2 D1 D0 <GAIN CH1> <GAIN CH x> Individual channel gain control In 16-bit ADC mode, <GAIN CH X> sets gain for channel CH X A. In 14-bit ADC mode, <GAIN CH X> sets gain for channel CH X B. 0000 0 dB 0001 1 dB 0010 2 dB 0011 3 dB 0100 4 dB 0101 5 dB 0110 6 dB 0111 7 dB 1000 8 dB 1001 9 dB 1010 10 dB 1011 11 dB 1100 12 dB 1101 to 1111 Unused Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 25 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 A7–A0 IN HEX 2C www.ti.com D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 <AVG OUT 1> D7 D6 <AVG OUT 4> D5 D4 <AVG OUT 3> D3 D2 <AVG OUT 2> D1 D0 <AVG OUT 1> These bits determine which data stream is output on LVDS pins OUT1A/1B. (after global enable bit for averaging is enabled <EN AVG GLO> = 1) 00 LVDS OUT1A/1B buffers are powered down. 01 OUT1A/1B output digital data corresponding to the signal applied on analog input pin IN1. 10 OUT1A/1B output digital data corresponding to the average of signals applied on analog input pins IN1 and IN2. 11 OUT1A/1B output digital data corresponding to the average of signals applied on analog input pins IN1, IN2, IN3, and IN4. <AVG OUT 2> These bits determine which data stream is output on LVDS pins OUT2A/2B (after global enable bit for averaging is enabled <EN AVG GLO> = 1) 00 LVDS OUT2A/2B buffers are powered down. 01 OUT2A/2B output digital data corresponding to the signal applied on analog input pin IN2. 10 OUT2A/2B output digital data corresponding to the signal applied on analog input pin IN3. 11 OUT2A/2B output digital data corresponding to the average of signals applied on analog input pins IN3 and IN4. <AVG OUT 3> These bits determine which data stream is output on LVDS pins OUT3A/3B (after global enable bit for averaging is enabled <EN AVG GLO> = 1) 00 LVDS OUT3A/3B buffers are powered down. 01 OUT3A/3B output digital data corresponding to the signal applied on analog input pin IN3. 10 OUT3A/3B output digital data corresponding to the signal applied on analog input pin IN2. 11 OUT3A/3B output digital data corresponding to the average of signals applied on analog input pins IN1 and IN4. <AVG OUT 4> These bits determine which data stream is output on LVDS pins OUT4A/4B (after global enable bit for averaging is enabled <EN AVG GLO> = 1) 00 LVDS OUT4A/4B buffers are powered down. 01 OUT4A/4B output digital data corresponding to the signal applied on analog input pin IN4. 10 OUT4A/4B output digital data corresponding to the average of signals applied on analog input pins IN3 and IN4. 11 OUT4A/4B output digital data corresponding to the average of signals applied on analog input pins IN1, IN2, IN3, and IN4. 26 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com A7–A0 IN HEX 29 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <EN DIG FILTER> <EN AVG GLO> D1 <EN DIG FILTER> 0 Digital filter mode is disabled. 1 Digital filter mode is enabled on all channels. To turn filter on or off for individual channels, also set the <USE FILTER CH X> register bit. D0 <EN AVG GLO> 0 Averaging mode is disabled. 1 Averaging mode is enabled on all channels. A7–A0 IN HEX 2E D15 D14 D13 D12 D11 D10 D9 D8 D7 0 0 0 0 0 0 <FILTER TYPE CH1> 2F 0 0 0 0 0 0 30 0 0 0 0 0 0 31 0 0 0 0 0 0 <FILTER TYPE CH2> <FILTER TYPE CH3> <FILTER TYPE CH4> D6 D5 D4 D3 D2 D1 D0 <DEC by RATE CH1> 0 0 0 <USE FILTER CH1> <DEC by RATE CH2> <DEC by RATE CH3> <DEC by RATE CH4> 0 0 0 0 0 0 0 0 0 <USE FILTER CH2> <USE FILTER CH3> <USE FILTER CH4> D0 <USE FILTER CH X> 0 Filter is turned OFF on channel X 1 Filter is turned ON on channel X. D2 <ODD TAP CH X> select filter with even or odd tap for channel X 0 Even tap filter is selected. 1 Odd tap filter is selected. D6–D4 <DEC by RATE CH X> select decimation rates for channel X 000 Decimate-by-2 rate is selected. 001 Decimate-by-4 rate is selected. 100 Decimate-by-8 rate is selected. Other combinations x Do not use D9–D7 <FILTER TYPE CH X> select type of filter for channel X 000 Low-pass filter with decimate-by-2 rate 001 High-pass filter with decimate-by-2 rate 010 Low-pass filter with decimate-by-4 rate 011 Band-pass filter #1 with decimate-by-4 rate 100 Band-pass filter #2 with decimate-by-4 rate 101 High-pass filter with decimate-by-4 rate Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 27 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 A7–A0 IN HEX 38 www.ti.com D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D1–D0 <OUTPUT RATE> 00 Output data rate = 1× sample rate 01 Output data rate = 0.5× sample rate 02 Output data rate = 0.25× sample rate 03 Output data rate = 0.125× sample rate 28 Submit Documentation Feedback D1 D0 <OUTPUT RATE> Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com REGISTER ADDRESS A7–A0 IN HEX 42 REGISTER DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 0 0 0 0 0 0 0 0 0 D6 D5 <PHASE_DDR> D4 D3 D2 D1 D0 0 0 0 0 0 Register bits PHASE_DDR can be used to control the phase of LCLK (with respect to the rising edge of the frame clock, ADCLK). See Programmable LCLK Phase for details. A7–A0 IN HEX 45 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <SYNC PATTERN> <DESKEW PATTERN> D1 <SYNC PATTERN> 0 Sync pattern disabled 1 Sync pattern enabled. All channels output a repeating pattern of 8 1s and 8 0s instead of ADC data. Output data [15…0] = 0xFF00 D1 <DESKEW PATTERN> 0 Deskew pattern disabled 1 Deskew pattern enabled. All channels output a repeating pattern of 1010101010101010 instead of ADC data. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 29 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com A7-A0 IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 46 <ENABLE SERIAL’N> 0 0 0 <16b SERIAL’N> <14b SERIAL’N> 0 0 0 0 <PAD two 0s> 0 <MSB FIRST> <2S COMPL> 0 <2-WIRE 0.5X FRAME> D15 <ENABLE SERIAL’N> Enable bit for serialization bits in register 46> 0 Disable control of serialization register bits in register 0x46. 1 Enable control of serialization register bits in register 0x46. D11 <16b SERIAL’N> Enable 16-bit serialization, to be used in 16-bit ADC mode 0 Disable 16-bit serialization. 1 Enable 16-bit serialization. ADC data bits D[15..0] are serialized. D10 <14b SERIAL’N> Enable 14-bit serialization, to be used in 14-bit ADC mode 0 Disable 14-bit serialization. 1 Enable 14-bit serialization. ADC data bits D[13..0] are serialized. D5 <PAD two 0s> 0 Padding disabled 1 Two zero bits are padded to the ADC data on the LSB side and the combined data is then serialized. When the bit <4b SERIAL’N> is also enabled, two zero bits are padded to the 14-bit ADC data. The combined data (= ADC[13..0],0,0) is serially output. D3 <MSB First> 0 ADC data is output serially, with LSB bit first. 1 ADC data is output serially, with MSB bit first. D2 <2s COMPL> 0 Output data format is offset binary. 1 Output data format is 2s complement. D0 <2-WIRE 0.5× frame clock> 0 Enables 1-wire LVDS interface with 1× frame clock 1 Enables 2-wire LVDS interface with 0.5× frame clock A7–A0 IN HEX B3 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ENABLE ADC MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16B/14B ADC MODE D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D15 <ENABLE ADC MODE> 0 Disable selection of 14-bit ADC mode 1 Enables selection of 14 bit ADC mode D0 <16B/14B ADC MODE> 0 16-bit ADC operation is enabled 1 14-bit ADC operation is enabled A7–A0 IN HEX 50 30 D15 D14 D13 D12 <EN MAP1> 0 0 0 <MAP_Ch1234_OUT2A> <MAP_Ch1234_OUT1B> Submit Documentation Feedback D1 D0 <MAP_Ch1234_OUT1A> Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com D15 <EN MAP1> 0 Mapping function for outputs OUT1A, OUT1B, and OUT2A is disabled. 1 Mapping function for outputs OUT1A, OUT1B, and OUT2A is enabled. D3–D0 <MAP_Ch1234_OUT1A> 0000 MSB byte corresponding to input IN1 is output on OUT1A. 0001 LSB byte corresponding to input IN1 is output on OUT1A. 0010 MSB byte corresponding to input IN2 is output on OUT1A. 0011 LSB byte corresponding to input IN2 is output on OUT1A. 0100 MSB byte corresponding to input IN3 is output on OUT1A. 0101 LSB byte corresponding to input IN3 is output on OUT1A. 0110 MSB byte corresponding to input IN4 is output on OUT1A. 0111 LSB byte corresponding to input IN4 is output on OUT1A. 1xxx OUT1A LVDS buffer is powered down. D7–D4 <MAP_Ch1234_OUT1B> 0000 MSB byte corresponding to input IN1 is output on OUT1B. 0001 LSB byte corresponding to input IN1 is output on OUT1B. 0010 MSB byte corresponding to input IN2 is output on OUT1B. 0011 LSB byte corresponding to input IN2 is output on OUT1B. 0100 MSB byte corresponding to input IN3 is output on OUT1B. 0101 LSB byte corresponding to input IN3 is output on OUT1B. 0110 MSB byte corresponding to input IN4 is output on OUT1B. 0111 LSB byte corresponding to input IN4 is output on OUT1B. 1xxx OUT1B LVDS buffer is powered down. D11–D8 <MAP_Ch1234_OUT2A> 0000 MSB byte corresponding to input IN1 is output on OUT2A. 0001 LSB byte corresponding to input IN1 is output on OUT2A. 0010 MSB byte corresponding to input IN2 is output on OUT2A. 0011 LSB byte corresponding to input IN2 is output on OUT2A. 0100 MSB byte corresponding to input IN3 is output on OUT2A. 0101 LSB byte corresponding to input IN3 is output on OUT2A. 0110 MSB byte corresponding to input IN4 is output on OUT2A. 0111 LSB byte corresponding to input IN4 is output on OUT2A. 1xxx OUT2A LVDS buffer is powered down. A7–A0 IN HEX 51 D15 D14 D13 D12 <EN MAP2> 0 0 0 D11 D10 D9 D8 <MAP_Ch1234_OUT3B> D7 D6 D5 D4 <MAP_Ch1234_OUT3A> D15 <EN MAP2> 0 Mapping function for outputs OUT3B, OUT3A, and OUT2B is disabled. 1 Mapping function for outputs OUT3B, OUT3A, and OUT2B is enabled. D3–D0 <MAP_Ch1234_OUT2B> D3 D2 D1 <MAP_Ch1234_OUT2B> Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 D0 31 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com 0000 MSB byte corresponding to input IN1 is output on OUT2B. 0001 LSB byte corresponding to input IN1 is output on OUT2B. 0010 MSB byte corresponding to input IN2 is output on OUT2B. 0011 LSB byte corresponding to input IN2 is output on OUT2B. 0100 MSB byte corresponding to input IN3 is output on OUT2B. 0101 LSB byte corresponding to input IN3 is output on OUT2B. 0110 MSB byte corresponding to input IN4 is output on OUT2B. 0111 LSB byte corresponding to input IN4 is output on OUT2B. 1xxx OUT2B LVDS buffer is powered down. D7–D4 <MAP_Ch1234_OUT3A> 0000 MSB byte corresponding to input IN1 is output on OUT3A. 0001 LSB byte corresponding to input IN1 is output on OUT3A. 0010 MSB byte corresponding to input IN2 is output on OUT3A. 0011 LSB byte corresponding to input IN2 is output on OUT3A. 0100 MSB byte corresponding to input IN3 is output on OUT3A. 0101 LSB byte corresponding to input IN3 is output on OUT3A. 0110 MSB byte corresponding to input IN4 is output on OUT3A. 0111 LSB byte corresponding to input IN4 is output on OUT3A. 1xxx OUT3A LVDS buffer is powered down. D11–D8 <MAP_Ch1234_OUT3B> 0000 MSB byte corresponding to input IN1 is output on OUT3B. 0001 LSB byte corresponding to input IN1 is output on OUT3B. 0010 MSB byte corresponding to input IN2 is output on OUT3B. 0011 LSB byte corresponding to input IN2 is output on OUT3B. 0100 MSB byte corresponding to input IN3 is output on OUT3B. 0101 LSB byte corresponding to input IN3 is output on OUT3B. 0110 MSB byte corresponding to input IN4 is output on OUT3B. 0111 LSB byte corresponding to input IN4 is output on OUT3B. 1xxx OUT3B LVDS buffer is powered down. A7–A0 IN HEX 52 D15 D14 D13 D12 D11 D10 D9 D8 <EN MAP3> 0 0 0 0 0 0 0 D7 D5 D4 <MAP_Ch1234_OUT4B> D15 <EN MAP3> 0 Mapping function for outputs OUT4A and OUT4B is disabled. 1 Mapping function for outputs OUT4A and OUT4B is enabled. D3–D0 <MAP_Ch1234_OUT4A> 0000 MSB byte corresponding to input IN1 is output on OUT4A. 0001 LSB byte corresponding to input IN1 is output on OUT4A. 0010 MSB byte corresponding to input IN2 is output on OUT4A. 0011 LSB byte corresponding to input IN2 is output on OUT4A. 32 D6 Submit Documentation Feedback D3 D2 D1 D0 <MAP_Ch1234_OUT4B> Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com 0100 MSB byte corresponding to input IN3 is output on OUT4A. 0101 LSB byte corresponding to input IN3 is output on OUT4A. 0110 MSB byte corresponding to input IN4 is output on OUT4A. 0111 LSB byte corresponding to input IN4 is output on OUT4A. 1xxx OUT4A LVDS buffer is powered down. D7–D4 <MAP_Ch1234_OUT4B> 0000 MSB byte corresponding to input IN1 is output on OUT4B. 0001 LSB byte corresponding to input IN1 is output on OUT4B. 0010 MSB byte corresponding to input IN2 is output on OUT4B. 0011 LSB byte corresponding to input IN2 is output on OUT4B. 0100 MSB byte corresponding to input IN3 is output on OUT4B. 0101 LSB byte corresponding to input IN3 is output on OUT4B. 0110 MSB byte corresponding to input IN4 is output on OUT4B. 0111 LSB byte corresponding to input IN4 is output on OUT4B. 1xxx OUT4B LVDS buffer is powered down. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 33 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – 16 BIT ADC MODE All plots are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock = 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) 0 0 SNR = 85.6 dBFS SINAD = 83.5 dBFS THD = 86.7 dBc SFDR = 89.7 dBc −10 −20 −30 −30 −40 −40 Amplitude (dBFS) Amplitude (dBFS) −20 −50 −60 −70 −80 −50 −60 −70 −80 −90 −90 −100 −100 −110 −110 −120 −120 −130 −130 −140 0 5 10 Frequency (MHz) 15 SNR = 84.7 dBFS SINAD = 81.6 dBFS SFDR = 84.9 dBc THD = 83.4 dBc −10 −140 20 0 5 10 Frequency (MHz) 15 20 G001 G002 Figure 9. FFT for 3-MHz Input Signal, fS = 40 MSPS Figure 10. FFT for 15-MHz Input Signal, fS = 40 MSPS 0 0 SNR =85.7 dBFS SINAD = 81.4 dBFS THD = 82.4 dBc SFDR = 83.1 dBc −10 −20 −30 −30 −40 −40 Amplitude (dBFS) Amplitude (dBFS) −20 −50 −60 −70 −80 −50 −60 −70 −80 −90 −90 −100 −100 −110 −110 −120 −120 −130 −130 −140 0 5 10 15 20 25 Frequency (MHz) 30 35 SNR = 84.8 dBFS SINAD = 79.4 dBFS THD = 79.9 dBc SFDR = 82.7dBc −10 40 −140 0 G003 Figure 11. FFT for 3-MHz Input Signal, fS = 80 MSPS 34 5 10 15 20 25 Frequency (MHz) 30 35 40 G004 Figure 12. FFT for 15-MHz Input Signal, fS = 80 MSPS Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – 16 BIT ADC MODE (continued) All plots are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock = 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) 0 0 SNR = 78.9 dBFS SINAD = 73.9 dBFS THD = 74.6 dBc SFDR = 77.4 dBc −10 −20 −30 −30 −40 −40 Amplitude (dBFS) Amplitude (dBFS) −20 −50 −60 −70 −80 −50 −60 −70 −80 −90 −90 −100 −100 −110 −110 −120 −120 −130 −130 −140 0 5 10 15 20 25 Frequency (MHz) 30 35 SNR = 84.9 dBFS SINAD = 80.4 dBFS THD = 81.3 dBc SFDR = 83.5 dBc −10 −140 40 0 5 10 15 20 25 30 Frequency (MHz) 35 40 45 G005 G006 Figure 13. FFT for 65-MHz Input Signal, fS = 80 MSPS Figure 14. FFT for 3-MHz Input Signal, fS = 100 MSPS 0 0 SNR = 84.1 dBFS SINAD = 76.4 dBFS THD = 76.2 dBc SFDR = 77.7 dBc −10 −20 −20 −30 −30 −40 −40 −50 −60 −70 −80 −50 −60 −70 −80 −90 −90 −100 −100 −110 −110 −120 −120 −130 −130 −140 0 5 10 15 20 25 30 Frequency (MHz) 35 40 45 SNR = 78.8 dBFS SINAD = 73 dBFS THD = 73.2 dBc SFDR74.9 dBc −10 Amplitude (dBFS) Amplitude (dBFS) 50 50 −140 0 5 10 15 20 25 30 Frequency (MHz) 35 40 45 50 G007 G008 Figure 15. FFT for 15-MHz Input Signal, fS = 100 MSPS Figure 16. FFT for 65-MHz Input Signal, fS = 100 MSPS Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 35 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – 16 BIT ADC MODE (continued) All plots are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock = 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) 0 fIN1 = 8 MHz fIN2 =10 MHz Each Tone at −7 dBFS Amplitude Two-Tone IMD = 92.6 dBFS −10 −20 −30 Amplitude (dBFS) −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 0 5 10 15 20 25 30 Frequency (MHz) 35 40 45 50 G009 Figure 17. FFT for 130-MHz Input Signal, fS = 100 MSPS Figure 18. FFT for 2-Tone Input Signal 86 88 Fs = 100MSPS Fs = 80MSPS Fs = 100MSPS Fs = 80MSPS 87 84 86 85 84 SNR (dBFS) SFDR (dBc) 82 80 78 83 82 81 80 79 76 78 77 74 0 10 20 30 40 50 60 70 80 76 0 Input Frequency (MHz) 20 30 40 50 60 70 80 Input Frequency (MHz) Figure 19. SFDR vs Input Frequency 36 10 Submit Documentation Feedback Figure 20. SNR vs Input Frequency Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – 16 BIT ADC MODE (continued) All plots are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock = 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) 96 89 Gain=0dB Gain=2dB Gain=4dB Gain=6dB 92 Gain=8dB Gain=10dB Gain=12dB Gain=0dB Gain=2dB Gain=4dB Gain=6dB 87 Gain=8dB Gain=10dB Gain=12dB 85 88 SNR (dBFS) SFDR (dBc) 83 84 81 79 80 77 76 75 72 0 10 20 30 40 50 Input Frequency (MHz) 60 73 70 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Input Frequency (MHz) Figure 21. SFDR Across Gain Figure 22. SNR Across Gain 93 140 SNR SFDR (dBc) SFDR (dBFS) 91 110 90 100 89 90 88 80 87 70 86 60 85 50 84 40 83 30 82 20 81 10 −100 −90 80 −80 −70 −60 −50 −40 −30 Amplitude (dBFS) −20 −10 fIN = 10 MHz fIN = 70 MHz fIN = 130 MHz 0 88 86 SNR (dBFS) SFDR (dBc, dBFS) 120 90 92 SNR (dBFS) 130 84 82 80 78 76 −32 −28 −24 −20 −16 −12 Input Amplitude (dBFS) −8 −4 0 G041 Figure 23. Performance Across Input Amplitude, Single Tone Figure 24. SNR Across Input Amplitude vs Input Frequency Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 37 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – 16 BIT ADC MODE (continued) All plots are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock = 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) 90 88 SNR SFDR 88 Fin=3MHz fIN = 3 MHz 87 88 86 86 85 84 84 82 83 80 82 78 81 76 3 V AVDD 3.1 V AVDD 3.2 V AVDD 3.3 V AVDD 3.4 V AVDD 3.5 V AVDD 3.6 V AVDD 80 1.4 1.45 1.5 SFDR (dBc) 84 SFDR (dBc) SNR (dBFS) 86 82 80 78 74 1.6 1.55 76 −40 Input Common Mode Voltage (V) −15 10 35 60 85 Free-Air Temperature (°C) G016 Figure 26. SFDR Across Temperature vs AVDD Supply, Sample Rate = 80 MSPS fIN = 3 MHz fIN = 3 MHz 3 V AVDD 3.1 V AVDD 3.2 V AVDD 3.3 V AVDD 3.4 V AVDD 3.5 V AVDD 3.6 V AVDD 87.5 87 SNR (dBFS) 86.5 SNR (dBFS) 86 88 88 86 SNR SFDR 87.5 85 87 84 86.5 83 86 82 85.5 81 85 80 84.5 79 SFDR (dBc) Figure 25. Performance vs Input Common-Mode Voltage 85.5 85 84.5 84 1.7 84 −40 −15 10 35 60 1.75 1.8 1.85 78 1.9 Digital Supply Voltage (LVDD) (V) 85 G018 Free-Air Temperature (dB) G017 Figure 27. SNR Across Temperature vs AVDD Supply, Sample Rate = 80 MSPS 38 Figure 28. Performance Across LVDD Supply Voltage, Sample Rate = 80 MSPS Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – 16 BIT ADC MODE (continued) All plots are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock = 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) 88 85 Fin=3MHz 3V AVDD 3.1V AVDD 3.2V AVDD 3.3V AVDD 3.4V AVDD 3.5V AVDD 3.6V AVDD 84 83 86 85 81 80 79 84 83 82 78 81 77 80 76 75 −40 −15 10 35 60 79 −40 85 Free−Air Temperature (°C) 35 60 85 87 84 SNR SFDR SFDR SNR 84.5 81 84 80 83.5 79 83 78 82.5 77 1.75 1.8 1.85 76 1.9 83 86 82 85 81 84 80 83 79 82 78 0.2 0.4 Digital Supply Voltage (LVDD) (V) 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Input Clock Amplitude, Differential (dB) 2.2 SNR (dBFS) 82 SFDR (dBc) 85 SFDR (dBc) 83 85.5 SNR (dBFS) 10 Figure 30. SNR Across Temperature Sample Rate = 100 MSPS 84 86 Fin=3MHz −15 Free−Air Temperature (°C) Figure 29. SFDR Across Temperature Sample Rate = 100 MSPS 82 1.7 3V AVDD 3.1V AVDD 3.2V AVDD 3.3V AVDD 3.4V AVDD 3.5V AVDD 3.6V AVDD 87 SNR (dBFS) SFDR (dBc) 82 Fin=3MHz 81 2.4 G019 Figure 31. Performance Across LVDD Supply Sample Rate = 100 MSPS Figure 32. Performance Across Input Clock Amplitude, Sample Rate = 100 MSPS Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 39 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – 16 BIT ADC MODE (continued) All plots are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock = 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) 0 86 85.5 SNR SFDR 85.3 Fin = 3 MHz fIN = 3 MHz, −1 dBFS fA = 3-MHz full−scale input applied on near channel SNR= 83.7 dBFS −10 85 84 −30 84.9 83 −40 84.7 82 84.5 81 84.3 80 84.1 79 −100 83.9 78 −110 83.7 77 −50 Amplitude (dBFS) SFDR (dBc) SNR (dBFS) −20 85.1 −60 −70 −80 −90 −120 83.5 35 40 45 50 55 60 65 −130 −140 76 −150 Input Clock Dutycycle (MHz) 0 5 10 15 20 25 30 Frequency (MHz) 35 40 45 50 G021 Figure 33. Performance Across Input Clock Duty Cycle, Sample Rate = 100 MSPS Figure 34. Near-Channel Crosstalk Spectrum, Sample Rate = 100 MSPS 0 3 fIN = 3 MHz, −1 dBFS 3-MHz full-scale signal applied on far channel SNR = 84.8 dBFS −10 −20 2 −30 1 −50 0 −60 INL (LSB) Amplitude (dBFS) −40 −70 −80 −90 −100 −1 −2 −3 −110 −4 −120 −130 −5 −140 −150 0 5 10 15 20 25 30 Frequency (MHz) 35 40 45 50 −6 0 8192 16384 24576 32768 40960 49152 57344 65535 Output Codes (LSB) G022 Figure 35. Far-Channel Crosstalk Spectrum 40 Submit Documentation Feedback G023 Figure 36. Integral Non-Linearity Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – 16 BIT ADC MODE (continued) All plots are at 25°C, AVDD = 3.3 V, LVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock = 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32k point FFT (unless otherwise noted) 45 0.5 40 Code Occurrence (%) 0.4 0.3 DNL (LSB) 0.2 0.1 0 35 30 25 20 15 10 5 −0.1 32571 32570 32569 32568 32567 32566 32565 32564 32563 −0.3 32562 32561 0 −0.2 Output Code (LSB) G025 −0.4 −0.5 3500 13500 23500 33500 43500 Output Codes (LSB) 53500 Figure 37. Differential Non-Linearity 62000 Figure 38. Histogram of Output Code With Analog Inputs Shorted Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 41 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – 14-BIT ADC MODE 0 0 fIN = 3 MHz, −1 dBFS SNR = 74.3 dBFS SINAD = 73.4 dBFS THD = 79.8 dBc SFDR = 83.7 dBc −10 −20 −20 −30 −40 −40 −50 −50 Amplitude (dBFS) Amplitude (dBFS) −30 −60 −70 −80 −90 −60 −70 −80 −90 −100 −100 −110 −110 −120 −120 −130 −130 −140 −140 −150 0 5 10 15 20 25 30 Frequency (MHz) 35 40 45 fIN = 15 MHz, −1 dBFS SNR = 73.6 dBFS SINAD = 72.4 dBFS THD = 77.4 dBc SFDR = 80.4 dBc −10 −150 50 0 5 10 15 20 25 30 Frequency (MHz) G026 Figure 39. FFT for 3-MHz Input Signal, fS = 100 MSPS 35 40 45 50 G027 Figure 40. FFT for 15-MHz Input Signal, fS = 100 MSPS 0 fIN = 65 MHz, −1 dBFS SNR = 71.2 dBFS SINA = 70.1 dBFS THD = 75.2 dBc SFDR= 76 dBc −10 −20 −30 Amplitude (dBFS) −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 0 5 10 15 20 25 30 Frequency (MHz) 35 40 45 50 G028 Figure 41. FFT for 65-MHz Input Signal, fS = 100 MSPS 42 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – COMMON PLOTS 1200 240 16−Bit ADC 14−Bit ADC, Clamp Enabled 14−Bit ADC, Clamp Disabled 1100 1000 200 180 Digital Power (mW) AVDD Power (mW) 900 800 700 600 500 160 140 120 100 400 300 80 200 60 100 1Wire 2Wire 220 10 20 30 40 50 60 70 80 Sampling Frequency (MSPS) 90 100 Figure 42. Analog Power Across Sampling Frequencies 40 10 20 30 40 50 60 70 80 Sampling Frequency (MSPS) 90 100 Figure 43. 16-Bit Digital Power Across Sampling Frequencies 200 1Wire 2Wire 180 Digital Power (mW) 160 140 120 100 80 60 40 10 20 30 40 50 60 70 80 Sampling Frequency (MSPS) 90 100 Figure 44. 14-Bit Digital Power Across Sampling Frequencies Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 43 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – COMMON PLOTS (continued) SNR Contour across Sampling & Input Frequencies 100 78 90 84 Sampling Frequency, MSPS 85 83 82 81 80 79 80 70 86 60 84 85 83 82 81 80 79 78 50 40 30 85 20 3 10 77 84 20 78 83 82 81 80 78 30 40 50 Input Frequency, MHz 79 80 81 79 82 60 83 77 70 84 85 Figure 45. SNR Contour Across Sampling and Input Frequencies, 16-Bit ADC 44 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – COMMON PLOTS (continued) SFDR Contour Across Sampling & Input Frequencies 100 Sampling Frequency, MSPS 90 80 78 82 76 80 70 80 82 60 78 76 50 82 80 40 30 84 20 3 75 10 76 20 77 78 80 82 30 40 50 Input Frequency, MHz 78 79 80 76 60 81 82 70 83 84 Figure 46. SFDR Contour Across Sampling and Input Frequencies, 16-Bit ADC Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 45 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – COMMON PLOTS (continued) SNR Contour Across Sampling & Input frequencies 100 71.5 Sampling Frequency, MSPS 90 73.5 74 72.5 73 72 74.5 80 70 60 74 74.5 73.5 72.5 73 72 50 40 30 20 3 73.5 74 74.5 10 71.5 20 72 73 30 40 Input Frequency, MHz 72.5 73 72.5 72 50 73.5 60 74 65 74.5 Figure 47. SNR Contour Across Sampling and Input Frequencies, 14-Bit ADC 46 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS – COMMON PLOTS (continued) SFDR Contour Across Sampling & Input Frequencies 100 83 85 Sampling Frequency, MSPS 90 80 85 81 70 83 60 79 81 50 85 85 40 83 81 30 85 20 3 10 79 20 80 83 30 40 Input Frequency, MHz 81 82 50 83 60 84 65 85 Figure 48. SFDR Contour Across Sampling and Input Frequencies, 14-Bit ADC Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 47 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION ADS5263 is a high-performance 16-bit quad-channel ADC with sample rates up to 100 MSPS. The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 16 clock cycles. The output is available as 16-bit data in serial LVDS format, coded in either offset binary or binary 2s-complement format. The device also has a 14-bit low-power mode, where it operates as a quad-channel 14-bit ADC. The 16-bit front-end stage is powered down and the part consumes almost half the power, compared to the 16-bit mode. The ADS5263 can be dynamically switched between the two resolution modes. This allows systems to use the same part in a high-resolution, high-power mode or a low-resolution, low-power mode. The INxA pins are used as the 16-bit ADC inputs, and the INxB pins function as the 14-bit ADC inputs. ANALOG INPUT The analog input consists of a switched-capacitor based differential sample and hold architecture. This differential topology results in very good ac performance, even for high input frequencies at high sampling rates. The INxP and INxM pins must be externally biased around a common-mode voltage of 1.5 V, available on the VCM pin. For a full-scale differential input, each input pin INP, INM must swing symmetrically between VCM + 1 V and VCM – 1 V, resulting in a 4-Vpp differential input swing. Sampling switch Lpkg2 to 3 nH INxAP RCR Filter Cbond ~2 pF 50 W R 200 W 4 pF Lpkg2 to 3 nH 50 W Cpar2 1 pF Ron 8 to 12 W Cpar2 2.5 pF Csamp 10 pF Ron 12 W 2.5 kW 10 W INxAM Cbond ~2 pF R 200 W Sampling capacitor 10 W Csamp 10 pF Ron 8 to 12 W Cpar2 1 pF Sampling switch Cpar2 2.5 pF Sampling capacitor Figure 49. 16-Bit ADC – Analog Input Equivalent Circuit Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each input pin is recommended to damp out ringing caused by package parasitics. It is also necessary to present low impedance ( <50 Ω) for the common mode switching currents. This can be achieved by using two resistors from each input terminated to the common mode voltage (VCM). Note that the device includes an internal R-C-R filter across the input pins. The purpose of the filter is to absorb the glitches caused by the opening and closing of the sampling capacitors. The cutoff frequency of the R-C filter 48 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better, but also reduces the input bandwidth and the maximum input frequency that can be supported. On the other hand, with no internal R-C filter, high input frequency can be supported, but now the sampling glitches must be supplied by the external driving circuit. The inductance of the package bond wires limits the ability of the drive circuit to support these glitches. Figure 50 and Figure 51 show the impedance (Zin = Rin || Cin) looking across the differential ADC input pins. While designing the external drive circuit, the ADC input impedance must be considered. 3 Differential Input Resistance - kW 1 0.1 0.01 0 100 200 300 400 500 Input Frequency - MHz Figure 50. ADC Analog Input Resistance (Rin) Across Frequency CI - Differential input capacitance - pF 15 12 8 4 0 0 100 200 300 400 500 Input Frequency - MHz Figure 51. ADC Analog Input Capacitance (CIN) Across Frequency Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 49 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Large and Small Signal Input Bandwidth The small signal bandwidth of the analog input circuit is high, around 700 MHz. When using an amplifier to drive the ADS5263, the total noise of the amplifier up to the small signal bandwidth must be considered. The large signal bandwidth of the device depends on the amplitude of the input signal. The ADS5263 supports 4 VPP amplitude for input signal frequency up to 70 MHz. For higher frequencies (>70 MHz), the amplitude of the input signal must be decreased proportionally. For example, at 140 MHz, the device supports a maximum of 2 VPP signal and at 280 MHz, it can handle a maximum of 1 VPP. Figure 52. FullScale Input Amplitude Across Input Frequency CLAMP FUNCTION The 14-bit ADC analog inputs have an integrated clamp function that can be used to interface to a CCD sensor output. A typical CCD sensor output has three timing phases – a reset phase followed by a reference phase and the actual picture phase. The analog inputs of the ADS5263 are clamped to a voltage (V_clamp) decided by an internally generated CLAMP clock signal. The CLAMP clock signal is high for one ADC clock cycle and low for two cycles. A high-going signal on SYNC can be used to synchronize the CLAMP clock with the reset phase of the CCD sensor output. An equivalent circuit of the input pins and a detailed timing diagram showing the clamp action is shown in Figure 53. 50 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com V_Clamp_P 10 W Sampling Switch Ron 30 W CLAMP_Clock Lpkg2 to 3 nH Sampling Capacitor INxB_P Cbond ~2 pF Ron 20 W 10 W Csamp 2 pF Resr 100 W Ron 20 W Lpkg 2 to 3 nH INxB_M Cbond ~2 pF Csamp 2 pF Ron 20 W 10 W CLAMP_Clock Resr 100 W Sampling Capacitor Ron 30 W Sampling Switch 10 W V_Clamp_M Figure 53. 14-Bit ADC Analog Input Equivalent Circuit SYNC Input Signal ADC Input Clock CLKP ADC Sample Clock Internal Signal ADC Clamp Clock Internal Signal CLAMP ENABLED Data Sampled by ADC CLAMP DISABLED Sample CCD RESET Sample CCD Reference CLAMP DISABLED Sample CCD Picture CLAMP ENABLED Sample CCD RESET CLAMP DISABLED Sample CCD Reference External CCD Signal CCD Reset phase CCD Reference phase CCD Picture phase CCD Reset phase CCD Reference phase CCD Picture phase Figure 54. Clamp Timing Diagram Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 51 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com 100 pF Ro CCD sensor INBx_P Buffer INBx_M Ro 100 pF ADS5263 Figure 55. CCD Sensor Connections LOW-FREQUENCY NOISE SUPPRESSION The low-frequency noise suppression mode is specifically useful in applications where good noise performance is desired in the low frequency band of dc to 1 MHz. By setting this mode, the low-frequency noise spectrum band around dc is shifted to a similar band around (fS/2 or Nyquist frequency). As a result, the noise spectrum from dc to about 1 MHz improves significantly as shown by the following spectrum plots. This function can be selectively enabled in each channel using the register bits <EN LFNS CH x>. The following plots show the effect of this mode on the spectrum. 0 0 SFDR = 83.6dBc SNR with Chopper = 91.24dBFS SNR without Chopper = 90.3dBFS THD = 80.4dBc −10 −20 −20 −30 −30 −40 −50 −50 Amplitude (dB) Amplitude (dB) −40 −60 −70 −80 −60 −70 −80 −90 −90 −100 −100 −110 −110 −120 −120 −130 −130 LF Noise Suppression Enabled LF Noise Suppression Disabled −10 0 10 20 30 Frequency (MHz) 40 50 −140 0 G032 Figure 56. Full-Scale Input Amplitude 52 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Frequency (MHz) 0.8 0.9 1 G033 Figure 57. Spectrum (Zoomed) From DC to 1 MHz Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com 0 LF Noise Suppression Enabled LF Noise Suppression Disabled −10 −20 −30 −40 Amplitude (dB) −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 49 49.1 49.2 49.3 49.4 49.5 49.6 49.7 49.8 49.9 Frequency (MHz) 50 G034 Figure 58. Spectrum (Zoomed) in 1-MHz Band From 49 MHz to 50 MHz (fS=100 MSPS) DIGITAL PROCESSING BLOCKS The ADS5263 integrates a set of commonly useful digital functions that can be used to ease system design. These functions are shown in the digital block diagram of Figure 59 and described in the following sections. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 53 54 Channel 2 ADC Data Channel 3 ADC Data Channel 4 ADC Data 16-BIT ADC Submit Documentation Feedback Product Folder Link(s) :ADS5263 DIGITAL PROCESSING BLOCK for Average of 4 channels Average of 2 channels Channel 1 ADC Data CHANNEL 1 12-tap filter 23-tap filter (Odd Tap) 24-tap filter (Even Tap) Custom Coefficients 23-tap filter (Odd Tap) 24-tap filter (Even Tap) Built-in Coefficients Decimation by 2 or by 4 or by 8 Decimation by 2 or by 4 GAIN (0 to 12 dB , 1 dB steps ) Ramp - Test Patterns Serializer Wire 2 Channel 4 Serializer Wire 1 Serializer Wire 2 Channel 3 Serializer Wire 1 Serializer Wire 2 Channel 2 Serializer Wire 1 Serializer Wire 2 Channel 1 Serializer Wire 1 ADS 5263 MULTIPLEXER 8:8 MAPPER OUT 4B OUT 4A OUT 3B OUT 3A OUT 2B OUT 2A OUT 1B OUT 1A LVDS OUTPUTS ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Figure 59. Block Diagram – Digital Processing Copyright © 2011, Texas Instruments Incorporated ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com DIGITAL GAIN ADS5263 includes programmable digital gain settings from 0 dB to 12 dB in steps of 1 dB. The benefit of digital gain is to get improved SFDR performance. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades by about 1 dB. So, the gain can be used to trade off between SFDR and SNR. For each gain setting, the analog supported input full-scale range scales proportionally, as shown in Table 8. The full-scale range depends on the ADC mode used (16-bit or 14-bit). After a reset, the device comes up in the 0-dB gain mode. To use other gain settings, program the <GAIN CH x> register bits. Table 8. Analog Full-Scale Range Across Gains DIGITAL GAIN, dB 16-BIT ADC MODE 14-BIT ADC MODE ANALOG FULL-SCALE INPUT, Vpp ANALOG FULL-SCALE INPUT, Vpp 0 4.00 2 1 3.57 1.78 2 3.18 1.59 3 2.83 1.42 4 2.52 1.26 5 2.25 1.12 6 2.00 1.00 7 1.79 0.89 8 1.59 0.80 9 1.42 0.71 10 1.26 0.63 11 1.13 0.56 12 1.00 0.50 DIGITAL FILTER The digital processing block includes the option to filter and decimate the ADC data outputs digitally. Various filters and decimation rates are supported – decimation rates of 2,4, and 8 and low-pass, high-pass, and band-pass filters are available. The filters are internally implemented as a 24-tap symmetric FIR (even-tap) using pre-defined coefficients. Alternatively, some of the filters can be configured as a 23-tap symmetric FIR (or odd-tap filters). The coefficients used are 11-bit signed numbers (–1024 to 1023). In addition to these built-in filters, customers also have the option of using their own custom 11-bit signed coefficients. Due to the symmetric FIR implementation of the filters, the customers can specify only 12 coefficients. The 12 custom coefficients can be loaded into 12 separate registers for each channel. See Table 9 for choosing the right combination of decimation rate and filter types. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 55 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Table 9. Digital Filters <OUTPUT RATE> DEC by RATE CHx> <FILTER TYPE CHx> <SEL ODD TAP> <USE FILTER CHx> <EN CUSTOM FILT> Built-in low-pass odd-tap filter (pass band = 0 to fS/4) 001 000 000 1 1 0 Built-in high-pass odd-tap filter (pass band = 0 to fS/4) 001 000 001 1 1 0 Built-in low-pass even-tap filter (pass band = 0 to fS/8) 010 001 010 0 1 0 Built-in first band pass even tap filter(pass band = fS/8 to fS/4) 010 001 011 0 1 0 Built-in second band pass even tap filter(pass band = fS/4 to 3 fS/8) 010 001 100 0 1 0 DECIMATION Decimate by 2 Decimate by 4 TYPE OF FILTER Built-in high pass odd tap filter (pass band = 3 fS/8 to fS/2) 010 001 101 1 1 0 Decimate by 2 Custom filter (user programmablecoefficients) 001 000 000 0 and 1 1 1 Decimate by 4 Custom filter (user programmablecoefficients) 010 001 000 0 and 1 1 1 Decimate by 8 Custom filter (user programmablecoefficients) 011 100 000 0 and 1 1 1 Bypass decimation Custom filter (user programmablecoefficients) 0 and 1 1 1 30 Highpass Low pass 10 Normalized Amplitude (dB) Normalized Amplitude (dB) 20 0 −10 −20 −30 −40 −50 −60 −70 −80 0 0.1 0.2 0.3 0.4 Normalized Frequency (Fin/Fs) Figure 60. Filter Response – Decimate by 2 56 0.5 50 40 30 20 10 0 −10 −20 −30 −40 −50 −60 −70 −80 Low−pass Band−pass1 Band−pass2 High−pass 0 0.1 0.2 0.3 0.4 Normalized Frequency (Fin/Fs) 0.5 Figure 61. Filter Response – Decimate by 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com DIGITAL AVERAGING The ADS5263 includes an averaging function where the ADC digital data from two (or four) channels can be averaged. The averaged data is output on specific LVDS channels. Table 10 shows the combinations of the input channels that can be averaged and the LVDS channels on which averaged data is available Table 10. Using Channel Averaging Averaged Channels Output on Which Averaged Data Is Available Register Settings Channel 1, Channel 2 OUT1A, OUT1B Set <AVG OUT 1> = 10 and <EN AVG GLO> = 1 Channel 1, Channel 2 OUT3A, OUT3B Set <AVG OUT 3> = 11 and <EN AVG GLO> = 1 Channel 3, Channel 4 OUT4A, OUT4B Set <AVG OUT 4> = 10 and <EN AVG GLO> = 1 Channel 3, Channel 4 OUT2A, OUT2B Set <AVG OUT 2> = 11 and <EN AVG GLO> = 1 Channel 1, Channel 2, Channel 3, Channel 4 OUT1A, OUT1B Set <AVG OUT 1> = 11 and <EN AVG GLO> = 1 Channel 1, Channel 2, Channel 3, Channel 4 OUT1A, OUT1B Set <AVG OUT 4> = 11 and <EN AVG GLO> = 1 PERFORMANCE WITH DIGITAL PROCESSING BLOCKS The ADS5263 provides very high SNR along with high sampling rates. In applications where even higher SNR performance is desired, digital processing blocks such as averaging and decimation filters can be used advantageously to achieve this. Table 11 shows the improvement in SNR that can be achieved compared to the default value, using these modes. Table 11. SNR Improvement Using Digital Processing MODE TYPICAL SNR, dBFS (1) TYPICAL IMPROVEMENT in SNR, dB Default 84.5 With decimation-by-2 filter enabled 86.7 2.2 With decimation-by-4 filter enabled 87.7 3.2 With decimation-by-8 filter enabled 88.6 4.1 With two channels averaged and decimation-by-8 filter enabled 91.3 6.8 With four channels averaged 89.6 5.1 93 8.5 With four channels averaged and decimation-by-8 filter enabled (1) Custom coefficients used for decimation-by-8 filter. 18-Bit Data Output With Digital Processing As shown in Table 11, very high SNR can be achieved using the digital blocks. Now, the overall SNR is limited by the quantization noise of the 16-bit output data. (16-bit quantization SNR = 6n + 1.76 = 16 × 6 + 1.76 = 97.76 dBFS.) To overcome this, the digital processing blocks (averaging and digital filters) automatically output 18-bit data. With the two additional bits, the quantization SNR improves by 12 dB and no longer limits the maximum SNR that can be achieved using the ADS5263. For example, with four channels averaged and the decimation-by-8 filter, the typical SNR improves to about 94.5 dBFS using 18-bit data (an improvement of 1.5 dB over the SNR with 16-bit data). The 18-bit data can be output using the special 18× serialization mode (see Output LVDS Interface). Note that the user can choose either the default 16× serialization (which takes the upper 16 bits of the 18-bit data) or the 18× serialization mode (that outputs all 18 bits). FLEXIBLE MAPPING OF CHANNEL DATA TO LVDS OUTPUTS ADS5263 has a mapping function by the use of which the digital data for any channel can be routed to any LVDS output. So, as an example, in the 1-wire interface, the channel-1 ADC output can be output either on OUT1 pins or on OUT2 or OUT3 or OUT4 pins. This flexibility in mapping simplifies board designs by avoiding complex routing that would be caused by a rigid mapping of input channels and output pins. This can also lead to potential saving in PCB layers and hence cost. The mapping is programmable using the register bits <MAP_Ch1234_OUTn> as shown in Figure 62 and Figure 63. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 57 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com ADS5263 Channel 1 MSB Data[15:8] Set MAP_Ch1234_OUTn<3:0> = 0000 Channel 1 LSB Data[7:0] Set MAP_Ch1234_OUTn<3:0> = 0001 Channel 2 MSB Data[15:8] Set MAP_Ch1234_OUTn<3:0> = 0010 LVDS Output Buffer , OUTn Channel 2 LSB Data[7:0] Set MAP_Ch1234_OUTn<3:0> = 0011 IN OUT Channel 3 MSB Data[15:8] Set MAP_Ch1234_OUTn<3:0> = 0100 PDN Channel 3 LSB Data[7:0] Set MAP_Ch1234_OUTn<3:0> = 0101 Channel 4 MSB Data[15:8] Set MAP_Ch1234_OUTn<3:0> = 0110 Channel 4 LSB Data[7:0] Set MAP_Ch1234_OUTn<3:0> = 0111 Power down LVDS buffer OUTn Set MAP_Ch1234_OUTn<3:0> = 1xxx n = 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B Figure 62. Mapping in 2-Wire Interface ADS5263 Channel 1 Data[15:0] Set MAP_Ch1234_OUTn<3:0> = 0000 LVDS Output Buffer , OUTn Channel 2 Data[15:0] Set MAP_Ch1234_OUTn<3:0> = 0010 IN OUT Channel 3 Data[15:0] Set MAP_Ch1234_OUTn<3:0> = 0100 PDN Channel 4 Data[15:0] Set MAP_Ch1234_OUTn<3:0> = 0110 Power down LVDS buffer OUTn Set MAP_Ch1234_OUTn<3:0> = 1xxx n = 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B Figure 63. Mapping in 1-Wire Interface 58 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com OUTPUT LVDS INTERFACE The ADS5263 offers several flexible output options, making it easy to interface to an ASIC or an FPGA. Each of these options can be easily programmed using the serial interface. A summary of all the options is presented in Table 12, along with the default values after power up and reset. Following this, each option is described in detail. The output interface options are: 1. 1-wire, 16× serialization with DDR bit clock and 1× frame clock – The 16-bit ADC data is serialized and output over one LVDS pair per channel together with an 8× bit clock and 1× frame clock. The output data rate is 16× sample rate; hence, it is suited for low sample rates, typically up to 50 MSPS. 2. 2-wire, 8× serialization with DDR bit clock and 0.5× frame clock (16 bit ADC mode, Figure 65 and Figure 66) – Here, the 16 bit ADC data is serialized and output over two LVDS pairs per channel. The output data rate is 8x sample rate, with a 4x bit clock and 0.5x frame clock. Because the output data rate is half compared to the 1-wire case, this interface can be used up to the maximum sample rate of the device. 3. 2-wire, 8× serialization with DDR bit clock and 0.5× frame clock (14-bit ADC mode) – Here, the 14-bit ADC data is padded with two zero bits. The combined 16-bit data is then serialized and output over two LVDS pairs per channel. The output data rate is 8× sample rate, with a 4× bit clock and 0.5× frame clock Because the output data rate is half compared to the 1-wire case, this interface can be used up to the maximum sample rate of the device. 4. 1-wire, 14× serialization with DDR bit clock and 1× frame clock (14-bit ADC mode) – The 14-bit ADC data is serialized and output over one LVDS pair per channel together with a 7× bit clock and 1× frame clock. The output data rate is 14× sample rate; hence, it is suited for low sample rates, typically up to 50 MSPS. 5. 2-wire, 7× serialization with DDR bit clock and 0.5× frame clock (14-bit ADC mode, Figure 68 and Figure 69) – Here, the 14-bit ADC data is serialized and output over two LVDS pairs per channel. The output data rate is 7× sample rate, with a 3.5× bit clock and 0.5× frame clock. Because the output data rate is half compared to the 1-wire case, this interface can be used up to the maximum sample rate of the device. 6. 1-wire, 18× serialization with DDR bit clock and 1× frame clock – Here, the 18-bit data from the digital processing block is serialized and output over one LVDS pair per channel, together with a 9× bit clock and 1x frame clock. The output data rate is 18× sample rate; hence, it is suited for low sample rates, typically up to 40 MSPS. This interface is primarily intended to be used when the averaging and digital filters are enabled. Table 12. Summary of Output Interface Options FEATURE OPTIONS AVAILABLE IN 1 wire 2 wire Wire interface Serialization factor DDR bit-clock frequency 1 wire and 2 wire DEFAULT AFTER POWER UP AND RESET 1 wire 16× X 18× X 14× X 8× X 4× X X 7× X 3.5× 1 wire – ADC data is sent serially over one pair of LVDS pins 2 wire – ADC data is split and sent serially over two pairs of LVDS pins For 16-bit ADC mode Can also be used with 14-bit ADC mode – the 14-bit ADC data is padded with two zeros and the combined 16-bit data is serialized. 18-bit data is available when 16-bit ADC mode is used with averaging and decimation filters enabled. X For 14-bit ADC mode only 8× X 9× 16× BRIEF DESCRIPTION 16× serialization 16× serialization Only with 2-wire interface 18× serialization 14× serialization X 14× serialization Only with 2-wire interface Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 59 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Table 12. Summary of Output Interface Options (continued) FEATURE AVAILABLE IN OPTIONS 1 wire 2 wire Frame-clock frequency 1× sample rate 1/2× sample rate X Bit sequence Bytewise X Bitwise X Wordwise X DEFAULT AFTER POWER UP AND RESET X BRIEF DESCRIPTION 1× — Bytewise – The ADC data is split into upper and lower bytes, which are output on separate wires. Bitwise – The ADC data is split into even and odd bits, which are output on separate wires. Wordwise – Successive ADC data samples are sent over separate wires. These options are available only with 2-wire interface. INPUT CLOCK CLKP/M Freq = fS FRAME CLOCK ADCLKP/M Freq = 1 ´ fS BIT CLOCK (DDR) LCLKP/M Freq = 8 ´ fS OUTPUT DATA OUT2, 4, 6, 8 (P/M) D0 (D15) D1 (D14) D2 (D13) D3 (D12) D4 (D11) D5 (D10) D6 (D9) D7 (D8) D8 (D7) D9 (D6) D10 (D5) D11 (D4) D12 (D3) D13 (D2) D14 (D1) D15 (D0) D0 (D15) D1 (D14) D2 (D13) D3 (D12) Data Rate = 16 ´ fS Data Bit in LSB-First Mode White Cells — Sample N D0 (D15) Data Bit in MSB-First Mode Gray Cells — Sample N + 1 Figure 64. Output LVDS Interface, 1-Wire, 16× Serialization 60 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com INPUT CLOCK CLKP/M Freq = Fs FRAME CLOCK ADCLKP/M Freq = 0.5 X Fs In Byte-wise mode BIT CLOCK (DDR) LCLKP/M Freq = 4X Fs OUTPUT DATA OUT2, 4, 6, 8 (P/M) OUT1, 3, 5, 7 (P/M) D0 (D15) D1 (D14) D2 (D13) D3 (D12) D4 (D11) D5 (D10) D6 (D9) D7 (D8) D0 (D15) D1 (D14) D2 (D13) D3 (D12) D4 (D11) D5 (D10) D6 (D9) D7 (D8) D8 (D7) D9 (D6) D10 (D5) D11 (D4) D12 (D3) D13 (D2) D14 (D1) D15 (D0) D8 (D7) D9 (D6) D10 (D5) D11 (D4) D12 (D3) D13 (D2) D14 (D1) D15 (D0) Data rate = 8X Fs In Bit-wise mode OUTPUT DATA OUT2, 4, 6, 8 (P/M) OUT1, 3, 5, 7 (P/M) D1 (D14) D3 (D12) D5 (D10) D7 (D8) D9 (D6) D11 (D4) D13 (D2) D15 (D0) D1 (D14) D3 (D12) D5 (D10) D7 (D8) D9 (D6) D11 (D4) D13 (D2) D15 (D0) D0 (D15) D2 (D13) D4 (D11) D6 (D9) D8 (D7) D10 (D5) D12 (D3) D14 (D1) D0 (D15) D2 (D13) D4 (D11) D6 (D9) D8 (D7) D10 (D5) D12 (D3) D14 (D1) D0 (D15) Data bit in LSB First mode White cells – Sample N Data bit in MSB First mode Grey cells – Sample N+1 Figure 65. LVDS Output Interface, 2-Wire, 8× Serialization, Bytewise and Bitwise Modes INPUT CLOCK CLKP/M Freq = Fs FRAME CLOCK ADCLKP/M Freq = 0.5 X Fs BIT CLOCK (DDR) LCLKP/M Freq = 4X Fs OUTPUT DATA OUT2, 4, 6, 8 (P/M) OUT1, 3, 5, 7 (P/M) D0 (D15) D1 (D14) D2 (D13) D3 (D12) D4 (D11) D5 (D10) D6 (D9) D7 (D8) D8 (D7) D9 (D6) D10 (D5) D11 (D4) D12 (D3) D13 (D2) D14 (D1) D15 (D0) D0 (D15) D1 (D14) D2 (D13) D3 (D12) D4 (D11) D5 (D10) D6 (D9) D7 (D8) D8 (D7) D9 (D6) D10 (D5) D11 (D4) D12 (D3) D13 (D2) D14 (D1) D15 (D0) D0 (D15) Data bit in LSB First mode White cells – Sample N Data bit in MSB First mode Grey cells – Sample N+1 Figure 66. LVDS Output Interface, 2-Wire, 8× Serialization, Wordwise Mode Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 61 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com INPUT CLOCK CLKP/M Freq = Fs FRAME CLOCK ADCLKP/M Freq = 1X Fs BIT CLOCK (DDR) LCLKP/M Freq = 9X Fs OUTPUT DATA OUT2, 4, 6, 8 (P/M) D0 (D17) D1 (D16) D2 (D15) D3 (D14) D4 (D13) D5 (D12) D6 (D11) D7 (D10) D8 (D9) D9 (D8) D10 (D7) D11 (D6) D12 (D5) D13 (D4) D14 (D3) D15 (D2) D16 (D1) D17 (D0) D0 (D17) D1 (D16) D2 (D15) D3 (D14) D4 (D13) Data rate = 18X Fs White cells – Sample N Data bit in LSB First mode D0 (D17) Grey cells – Sample N+1 Data bit in MSB First mode Figure 67. LVDS Output Interface, 1-Wire, 18× Serialization INPUT CLOCK CLKP/M Freq = fS FRAME CLOCK ADCLKP/M Freq = 1 fS BIT CLOCK (DDR) LCLKP/M Freq = 8 fS OUTPUT DATA OUT2, 4, 6, 8 (P/M) D0 (D13) D1 (D12) D2 (D11) D3 (D10) D4 (D9) D5 (D8) D6 (D7) D7 (D6) Data Rate = 14 D0 (D15) D9 (D4) D8 (D5) D10 (D3) D11 (D2) D12 (D1) D13 (D0) D0 (D13) D1 (D12) D2 (D11) D3 (D10) fS Data Bit in LSB-First Mode Data Bit in MSB- First Mode White cells – Sample N Grey cells – Sample N+1 Figure 68. LVDS Output Interface, 1-Wire, 14× Serialization 62 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com INPUT CLOCK CLKP/M Freq = fS FRAME CLOCK ADCLKP/M Freq = 0.5 ´ fS BIT CLOCK (DDR) LCLKP/M Freq = 3.5 ´ fS In Bytewise Mode OUTPUT DATA OUT2, 4, 6, 8 (P/M) OUT1, 3, 5, 7 (P/M) D0 (D13) D1 (D12) D2 (D11) D3 (D10) D4 (D9) D5 (D8) D6 (D7) D0 (D13) D1 (D12) D2 (D11) D3 (D10) D4 (D9) D5 (D8) D6 (D7) D7 (D6) D8 (D5) D9 (D4) D10 (D3) D11 (D2) D12 (D1) D13 (D0) D7 (D6) D8 (D5) D9 (D4) D10 (D3) D11 (D2) D12 (D1) D13 (D0) Data Rate = 7 ´ fS In Bitwise Mode OUTPUT DATA OUT2, 4, 6, 8 (P/M) OUT1, 3, 5, 7 (P/M) D1 (D14) D3 (D12) D5 (D10) D7 (D8) D9 (D6) D11 (D4) D13 (D2) D1 (D14) D3 (D12) D5 (D10) D7 (D8) D9 (D6) D11 (D4) D13 (D2) D0 (D15) D2 (D13) D4 (D11) D6 (D9) D8 (D7) D10 (D5) D12 (D3) D0 (D15) D2 (D13) D4 (D11) D6 (D9) D8 (D7) D10 (D5) D12 (D3) D0 (D13) Data Bit in LSB-First Mode White Cells – Sample N Data Bit in MSB-First Mode Grey Cells – Sample N+1 Figure 69. LVDS Output Interface, 2-Wire, 7× Serialization PROGRAMMABLE LCLK PHASE The ADS5263 allows programmability of the edge of the output bit clock (LCLK) using register bits <PHASE_DDR> as follows: The default value of PHASE_DDR after reset is 10, and the default phase corresponds to Figure 70. PHASE_DDR<1:0> = 10 ADCLKp LCLKp DATA OUT Figure 70. Default LCLK Phase The phase can also be changed to one of the following states by changing the value of the <PHASE_DDR1:0> bits. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 63 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com PHASE_DDR<1:0> = 00 PHASE_DDR<1:0> = 10 ADCLKp ADCLKp LCLKp LCLKp DATA OUT DATA OUT PHASE_DDR<1:0> = 01 PHASE_DDR<1:0> = 11 ADCLKp ADCLKp LCLKp LCLKp DATA OUT DATA OUT Figure 71. Programmable LCLK Phases 64 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Board Design Considerations Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See ADS5263EVM Evaluation Module (SLAU344) for placement of components, routing and grounding. Supply Decoupling Because the ADS5263 already includes internal decoupling, minimal external decoupling can be used without loss in performance. For example, the ADS5263EVM uses a single 0.1µF decoupling capacitor for each supply, placed close to the device supply pins. Packaging Exposed Pad The exposed pad at the bottom of the package is the main path for heat dissipation. Therefore, the pad must be soldered to a ground plane on the PCB for best thermal performance. The pad must be connected to the ground plane through the optimum number of vias. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com). One can also visit TI’s thermal website at www.ti.com/thermal. Non-Magnetic Package An important requirement in magnetic resonance imaging (MRI) applications is the magnetic compatibility of components mounted close to the RF coil area. Any ferromagnetic material in the component package introduces an artifact in the MRI image. Therefore, it is preferred to have components with non-magnetic packages. The ADS5263 is available in a special non-magnetic package that does not create any image artifacts, even in the presence of high magnetic fields. The non-magnetic part is orderable with the suffix “-NM”. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 65 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel). Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate – The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as EGREF and EGCHAN. To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal. Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts. Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN. Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. SNR = 10Log10 PS PN (1) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. SINAD = 10Log10 PS PN + PD (2) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. 66 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (3) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (4) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The dc PSRR is typically given in units of mV/V. AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC output code (referred to the input), then: DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (5) Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from the expected values) is noted. Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is the resulting change of the ADC output code (referred to the input), then: DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (6) Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 67 ADS5263 SLAS760B – MAY 2011 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY Changes from Original (May 2011) to Revision A Page • Changed Features List Item - From: 1.35 W Total Power at 100 MSPS To: 1.4 W Total Power at 100 MSPS .................. 1 • Changed Features List Item - From: 338 mW / Channel To: 355 mW / Channel ................................................................ 1 • Added "Non-magnetic package option for MRI systems" to Features ................................................................................. 1 • Added Package Marking ADS5263NM and Ordering Number ADS5263IRGC-NM ............................................................ 7 • Changed the CLOCK INPUT values in the ROC table ......................................................................................................... 8 • Changed the ELECTRICAL CHARACTERISTICS DYNAMIC PERFORMANCE – 16-BIT ADC table ................................ 9 • Changed the ELECTRICAL CHARACTERISTICS GENERAL – 16-BIT ADC MODE table .............................................. 10 • Added theELECTRICAL CHARACTERISTICS DYNAMIC PERFORMANCE – 14-BIT ADC ............................................ 11 • Changed the values in DIGITAL OUTPUTS – LVDS INTERFACE .................................................................................... 12 • Added Table 2, Table 3, and Table 4 ................................................................................................................................. 13 • Added Figure 29, Figure 30, and Figure 31 ....................................................................................................................... 38 • Added section - Large and Small Signal Input Bandwidth ................................................................................................. 50 • Added Section - Board Design Considerations .................................................................................................................. 65 • Added Section - Packaging ................................................................................................................................................ 65 • Added Section - DEFINITION OF SPECIFICATIONS ........................................................................................................ 66 Changes from Revision A (August 2011) to Revision B Page • Changed the Revision from A August 2011 to B October 2011 ........................................................................................... 1 • Added register 42 between register 38 and register 45 ..................................................................................................... 29 • Added new Figure below Figure 16 .................................................................................................................................... 35 • Added new Figure below Figure 22 (now Figure 24) ......................................................................................................... 37 • Added new figure 52 in Large and Smll Signal Input Bandwidth section ........................................................................... 50 • Added new section below Digital Averaging titled: Performance with Didgital Processing Blocks .................................... 57 • Added listitem 6. to the OUTPUT LVDS INTERFACE section ........................................................................................... 59 • Added Added new figure in section Output LVDS Interface (Figure 66) ............................................................................ 61 • Added new section after Output LVDS Interface titled: Programmable LCLK Phase, also 2 new figures added. ............. 63 68 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ADS5263 PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ADS5263IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR ADS5263IRGCR-NM ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR ADS5263IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR ADS5263IRGCT-NM ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS5263IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS5263IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS5263IRGCT-NM VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS5263IRGCR VQFN RGC 64 2000 333.2 345.9 28.6 ADS5263IRGCT VQFN RGC 64 250 333.2 345.9 28.6 ADS5263IRGCT-NM VQFN RGC 64 250 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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