AD AD9706BCPZ 8-/10-/12-/14-bit, 175 msps txdac d/a converter Datasheet

8-/10-/12-/14-Bit, 175 MSPS
TxDAC® D/A Converters
AD9704/AD9705/AD9706/AD9707
FUNCTIONAL BLOCK DIAGRAM
FEATURES
1.7V TO 3.6V
0.1µF
1.0V REF
REFIO
FS ADJ
RSET
1.7V
TO
3.6V
CLKVDD
CLKCOM
CLK+
CLK–
1.7V TO
3.6V
AVDD
ACOM
CURRENT
SOURCE
ARRAY
SEGMENTED
SWITCHES
AD9707
LSB
SWITCHES
LATCHES
OTCM
IOUTA
IOUTB
SPI
DVDD
DCOM
DIGITAL INPUTS (DB13 TO DB0)
PIN/SPI/RESET
MODE/SDIO
CMODE/SCLK
SLEEP/CSB
05926-001
Pin-compatible family
Low power member of pin-compatible
TxDAC product family
Power dissipation @ 3.3 V
22 mW @ 10 MSPS
25 mW @ 25 MSPS
30 mW @ 50 MSPS
Sleep mode: 3.1 mW @ 3.3 V
Supply voltage: 1.7 V to 3.6 V
SFDR to Nyquist
AD9707: 84 dBc @ 5 MHz output
AD9707: 83 dBc @ 10 MHz output
AD9707: 75 dBc @ 20 MHz output
AD9707 NSD @ 10 MHz output, 125 MSPS: −147 dBc/Hz
Differential current outputs: 1 mA to 5 mA
Data format: twos complement or straight binary
On-chip 1.0 V reference
CMOS-compatible digital interface
Edge-triggered latches
Clock input: single-ended and differential
Output common mode: adjustable 0 V to 1.2 V
Power-down mode < 2 mW @ 3.3 V (SPI® controllable)
Serial peripheral interface (SPI)
Self-calibration
32-lead LFCSP_VQ, Pb-free package
Figure 1. AD9707
PRODUCT HIGHLIGHTS
1.
Pin Compatible. The AD970x line of TxDACs is pincompatible with the AD974x TxDAC line (LFCSP_VQ
package).
5.
CMOS Clock Input. High speed, single-ended, and
differential CMOS clock input supports 175 MSPS
conversion rate.
2.
Low Power. Complete CMOS DAC operates on a single
supply of 3.6 V down to 1.7 V, consuming 25 mW (3.3 V)
and 10 mW (1.8 V). The DAC full-scale current can be
reduced for lower power operation, and sleep and powerdown modes are provided for low power idle periods.
6.
SPI Control. SPI control offers a higher level of
programmability.
7.
Easy Interfacing to Other Components. Adjustable output
common mode from 0 V to 1.2 V allows for easy interfacing
to other components that accept common-mode levels
greater than 0 V.
8.
On-Chip Voltage Reference. The AD970x includes a 1.0 V
temperature-compensated band gap voltage reference.
9.
Industry-Standard 32-Lead LFCSP_VQ Package.
3.
Self-calibration. Self-calibration enables true 14-bit INL
and DNL performance in the AD9707.
4.
Twos Complement/Binary Data Coding Support. Data input
supports twos complement or straight binary data coding.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD9704/AD9705/AD9706/AD9707
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 29
Functional Block Diagram .............................................................. 1
Serial Peripheral Interface......................................................... 29
Product Highlights ........................................................................... 1
SPI Register Map ........................................................................ 31
Revision History ............................................................................... 2
SPI Register Descriptions.......................................................... 32
General Description ......................................................................... 3
Reference Operation .................................................................. 34
Specifications..................................................................................... 4
Reference Control Amplifier .................................................... 34
DC Specifications (3.3 V)............................................................ 4
DAC Transfer Function ............................................................. 34
Dynamic Specifications (3.3 V).................................................. 5
Analog Outputs .......................................................................... 35
Digital Specifications (3.3 V) ...................................................... 6
Adjustable Output Common Mode......................................... 35
DC Specifications (1.8 V)............................................................ 7
Digital Inputs .............................................................................. 36
Dynamic Specifications (1.8 V).................................................. 8
Clock Input.................................................................................. 36
Digital Specifications (1.8 V) ...................................................... 9
DAC Timing................................................................................ 36
Timing Diagram ........................................................................... 9
Power Dissipation....................................................................... 36
Absolute Maximum Ratings.......................................................... 10
Self-Calibration........................................................................... 38
Thermal Characteristics ............................................................ 10
Applications..................................................................................... 40
ESD Caution................................................................................ 10
Output Configurations .............................................................. 40
Pin Configurations and Function Descriptions ......................... 11
Differential Coupling Using a Transformer ............................... 40
AD9707 ........................................................................................ 11
Single-Ended Buffered Output Using an Op Amp ................ 40
AD9706 ........................................................................................ 12
Differential Buffered Output Using an Op Amp ................... 41
AD9705 ........................................................................................ 13
Evaluation Board ............................................................................ 42
AD9704 ........................................................................................ 14
General Description................................................................... 42
Typical Performance Characteristics ........................................... 15
Evaluation Board Schematics ................................................... 43
AD9707 ........................................................................................ 15
Evaluation Board Layout........................................................... 48
AD9704, AD9705, and AD9706............................................... 22
Outline Dimensions ....................................................................... 51
Terminology .................................................................................... 28
Ordering Guide .......................................................................... 51
REVISION HISTORY
7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 52
AD9704/AD9705/AD9706/AD9707
GENERAL DESCRIPTION
The AD9704/AD9705/AD9706/AD9707 are the fourthgeneration family in the TxDAC series of high performance,
CMOS digital-to-analog converters (DACs). This pin-compatible,
8–/10–/12–/14–bit resolution family is optimized for low power
operation, while maintaining excellent dynamic performance.
The AD970x family is pin-compatible with the AD9748/AD9740/
AD9742/AD9744 family of TxDAC converters and is specifically
optimized for the transmit signal path of communication systems.
All of the devices share the same interface, LFCSP_VQ package,
and pinout, providing an upward or downward component
selection path based on performance, resolution, and cost.
The AD970x offers exceptional ac and dc performance, while
supporting update rates up to 175 MSPS.
The flexible power supply operating range of 1.7 V to 3.6 V and
low power dissipation of the AD970x parts make them well-suited
for portable and low power applications.
Power dissipation of the AD970x can be reduced to 15 mW, with
a small trade-off in performance, by lowering the full-scale
current output. In addition, a power-down mode reduces the
standby power dissipation to approximately 2.2 mW.
The AD970x has an optional serial peripheral interface (SPI) that
provides a higher level of programmability to enhance performance
of the DAC. An adjustable output, common-mode feature allows
for easy interfacing to other components that require common
modes greater than 0 V.
Edge-triggered input latches and a 1.0 V temperature-compensated
band gap reference have been integrated to provide a complete,
monolithic DAC solution. The digital inputs support 1.8 V and
3.3 V CMOS logic families.
Rev. 0 | Page 3 of 52
AD9704/AD9705/AD9706/AD9707
SPECIFICATIONS
DC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.
Table 1.
Parameter
Min
RESOLUTION
DC ACCURACY 1
Integral Nonlinearity (INL)
Precalibration
Integral Nonlinearity (INL)
Postcalibration
Differential Nonlinearity (DNL)
Precalibration
Differential Nonlinearity (DNL)
Postcalibration
ANALOG OUTPUT
Offset Error
Gain Error (With External
Reference)
Gain Error (With Internal
Reference)
Full-Scale Output Current 2
Output Compliance Range
(From OTCM to IOUTA/IOUTB)
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current 3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
(Reference Powered Up)
Reference Input Resistance
(Reference Powered Down)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
14
Gain Drift (Without Internal
Reference)
Gain Drift (With Internal
Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
CLKVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD) 4
Clock Supply Current (ICLKVDD)4
Power Dissipation4
Supply Current Sleep Mode
(IAVDD)
Supply Current Power-Down
Mode (IAVDD)
AD9707
Typ
Max
Min
AD9706
Typ
Max
12
±1.4
AD9705
Typ
Max
10
±6.0
±0.41
±0.9
±1.2
Min
±1.48
±4.4
±0.35
±0.4
AD9704
Typ
Max
8
±0.10
±0.30
Min
±0.36
Bits
±0.03
±0.09
±0.10
±1.17
±0.09
±0.13
Unit
LSB
LSB
±0.31
±0.02
±0.08
±0.03
LSB
LSB
−0.03
−2.7
0
−0.1
+0.03
+2.7
−0.03
−2.7
0
−0.1
+0.03
+2.7
−0.03
−2.7
0
−0.1
+0.03
+2.7
−0.03
−2.7
0
−0.1
+0.03
+2.7
% of FSR
% of FSR
−2.7
−0.1
+2.7
−2.7
−0.1
+2.7
−2.7
−0.1
+2.7
−2.7
−0.1
+2.7
% of FSR
1
−0.8
2
5
+0.8
1
−0.8
2
5
+0.8
1
−0.8
2
5
+0.8
1
−0.8
2
5
+0.8
mA
V
200
5
0.98
1.025
100
0.1
200
5
1.08
0.98
1.25
0.1
1.025
100
200
5
1.08
0.98
1.25
0.1
1.025
100
200
5
1.08
0.98
1.25
0.1
1.025
100
MΩ
pF
1.08
V
nA
1.25
10
10
10
10
V
kΩ
1
1
1
1
MΩ
0.5
0.5
0.5
0.5
MHz
0
0
0
0
±29
±29
±29
±29
±40
±40
±40
±40
±25
±25
±25
±25
ppm of
FSR/°C
ppm of
FSR/°C
ppm of
FSR/°C
ppm/°C
3.3
3.3
3.3
5.2
5.9
4.1
50.2
3.6
3.6
3.6
6.7
6.6
4.7
57
3.3
3.3
3.3
5.2
5.4
4.1
48.5
3.6
3.6
3.6
6.7
6.6
4.7
57
3.3
3.3
3.3
5.1
5.0
4.1
46.9
3.6
3.6
3.6
6.7
6.6
4.7
57
3.3
3.3
3.3
5.1
4.6
4.1
45.5
3.6
3.6
3.6
6.7
6.6
4.7
57
V
V
V
mA
mA
mA
mW
0.37
0.4
0.37
0.4
0.37
0.4
0.37
0.4
mA
0.7
7.5
0.7
7.5
0.7
0.7
7.5
μA
Rev. 0 | Page 4 of 52
AD9704/AD9705/AD9706/AD9707
Parameter
Supply Current Clock PowerDown Mode (IDVDD) 5
Supply Current Clock PowerDown Mode (ICLKVDD)
Power Supply Rejection Ratio
(AVDD) 6
OPERATING RANGE
Min
AD9707
Typ
Max
−0.2
Min
AD9706
Typ
Max
Min
AD9705
Typ
Max
Min
AD9704
Typ
Max
Unit
0.6
1
0.6
1
0.6
1
0.6
1
mA
42.5
58
42.5
58
42.5
58
42.5
58
μA
+0.03
+0.2
−0.2
+0.03
+0.2
−0.2
+0.03
+0.2
−0.2
+0.03
+0.2
% of FSR/V
+85
−40
+85
−40
+85
−40
+85
°C
−40
1
Measured at IOUTA, driving a virtual ground, at 25°C only.
Nominal full-scale current, IOUTFS, is 32× the IREF current.
An external buffer amplifier with input bias current < 100 nA should be used to drive any external load.
4
Measured at fCLOCK = 175 MSPS and fOUT = 1.0 MHz, using differential clock.
5
Measured at fCLOCK = 100 MSPS and fOUT = 1.0 MHz, using differential clock.
6
±5% power supply variation.
2
3
DYNAMIC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, differential transformer coupled output,
453 Ω differentially terminated, 1 unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%) 2
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)2
Output Fall Time (10% to 90%)2
AC LINEARITY
Spurious-Free Dynamic Range
to Nyquist
fCLOCK = 10 MSPS; fOUT = 2.1 MHz
fCLOCK = 25 MSPS; fOUT = 2.1 MHz
fCLOCK = 65 MSPS; fOUT = 5.1 MHz
fCLOCK = 65 MSPS; fOUT = 10.1 MHz
fCLOCK = 80 MSPS; fOUT = 1.0 MHz
fCLOCK = 125 MSPS; fOUT = 15.1 MHz
fCLOCK = 125 MSPS; fOUT = 25.1 MHz
fCLOCK = 175 MSPS; fOUT = 20.1 MHz
fCLOCK = 175 MSPS; fOUT = 40.1 MHz
Noise Spectral Density
fCLOCK = 175 MSPS; fOUT = 6.0 MHz;
IOUTFS = 2 mA
ENOB at IOUTFS = 2 mA
fCLOCK = 175 MSPS; fOUT = 6.0 MHz;
IOUTFS = 5 mA
ENOB at IOUTFS = 5 mA
fCLOCK = 175 MSPS; fOUT = 6.0 MHz;
IOUTFS = 1 mA
ENOB at IOUTFS = 1 mA
1
2
Min
AD9707
Typ
Max
175
74
Min
AD9706
Typ
Max
175
Min
AD9705
Typ
Max
AD9704
Typ
Max
11
4
5
2.5
11
4
5
2.5
11
4
5
2.5
MSPS
ns
ns
pV-s
ns
2.5
2.5
2.5
2.5
ns
84
84
84
83
83
78
77
75
72
84
83
84
83
82
78
77
75
71
84
84
84
83
82
78
76
75
71
70
68
70
71
70
68
69
69
67
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc/
Hz
bits
dBc/
Hz
bits
dBc/
Hz
bits
72
175
Unit
11
4
5
2.5
72
175
Min
66
−149
−146
−137
−127
11.3
−157
10.9
9.5
8.0
12.5
−145
10.6
See Figure 71 for diagram.
Measured single-ended into 500 Ω load.
Rev. 0 | Page 5 of 52
AD9704/AD9705/AD9706/AD9707
DIGITAL SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS 1
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
CLK INPUTS 2
Input Voltage Range
Common-Mode Voltage
Differential Voltage
1
2
Min
2.1
AD9707
Typ
Max
3
0
−10
Min
2.1
0.9
+10
10
1.5
1.5
3
0
−10
5
1.3
0.7
2.8
0
0.75
0.5
AD9706
Typ
Max
Min
2.1
0.9
+10
10
0
0.75
0.5
1.5
1.5
3
0
−10
5
1.3
0.7
2.8
3
2.25
AD9705
Typ
Max
Min
2.1
0.9
+10
10
Includes CLK+ pin in single-ended clock input mode.
Applicable to CLK+ input and CLK– input when configured for differential clock input mode.
Rev. 0 | Page 6 of 52
0
0.75
0.5
1.5
1.5
3
0
−10
5
1.3
0.7
2.8
3
2.25
AD9704
Typ
Max
0.9
+10
10
5
1.3
0.7
2.8
3
2.25
0
0.75
0.5
1.5
1.5
3
2.25
Unit
V
V
μA
μA
pF
ns
ns
ns
V
V
V
AD9704/AD9705/AD9706/AD9707
DC SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 2 mA, unless otherwise noted.
Table 4.
Parameter
Min
RESOLUTION
DC ACCURACY 1
Integral Nonlinearity (INL)
Precalibration
Differential Nonlinearity (DNL)
Precalibration
ANALOG OUTPUT
Offset Error
Gain Error (With Internal
Reference)
Full-Scale Output Current 2
Output Compliance Range
(With OTCM = AGND)
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current 3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
(Reference Powered Up)
Reference Input Resistance
(External Reference)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
14
Gain Drift (Without Internal
Reference)
Gain Drift (With Internal
Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
CLKVDD
Analog Supply Current
(IAVDD)
Digital Supply Current
(IDVDD) 4
Clock Supply Current
(ICLKVDD)4
Power Dissipation4
Supply Current Sleep
Mode (IAVDD)
Supply Current PowerDown Mode (IAVDD)
Supply Current PowerDown Mode (IAVDD)
AD9707
Typ
Max
AD9706
Typ
Max
Min
12
Min
AD9705
Typ
Max
10
Min
AD9704
Typ
Max
8
Unit
Bits
±1.4
±6.03
±0.42
±1.50
±0.10
±0.36
±0.03
±0.09
LSB
±1.2
±4.34
±0.36
±1.17
±0.09
±0.30
±0.02
±0.07
LSB
−0.03
−2.7
0
−0.2
+0.03
+2.7
−0.03
−2.7
0
−0.2
+0.03
+2.7
−0.03
−2.7
0
−0.2
+0.03
+2.7
−0.03
−2.7
0
−0.2
+0.03
+2.7
% of FSR
% of FSR
1
−0.8
2
5
+0.8
1
−0.8
2
5
+0.8
1
−0.8
2
5
+0.8
1
−0.8
2
5
+0.8
mA
V
200
5
0.98
1.025
100
0.1
1.7
1.7
1.7
200
5
1.08
0.98
1.25
0.1
1.025
100
200
5
1.08
0.98
1.25
0.1
1.025
100
200
5
1.08
0.98
1.25
0.1
1.025
100
MΩ
pF
1.08
V
nA
1.25
10
10
10
10
V
kΩ
1
1
1
1
MΩ
0.5
0.5
0.5
0.5
MHz
0
0
0
0
±30
±30
±30
±30
±60
±60
±60
±60
±25
±25
±25
±25
ppm of
FSR/°C
ppm of
FSR/°C
ppm of
FSR/°C
ppm/°C
4.8
V
V
V
mA
1.8
1.8
1.8
3.8
1.7
1.7
1.7
4.8
1.8
1.8
1.8
3.8
1.3
1.5
1.3
1.5
1.7
1.7
1.7
4.8
1.8
1.8
1.8
3.8
1.7
1.7
1.7
4.8
1.8
1.8
1.8
3.8
1.2
1.5
1.1
1.5
1.0
1.5
mA
1.3
1.5
1.3
1.5
1.3
1.5
mA
11.5
13.2
11.3
13.2
11.1
13.2
11.0
13.2
mW
0.3
0.4
0.3
0.4
0.3
0.4
0.3
0.4
mA
5
6
5
6
5
6
5
6
μA
0.2
0.3
0.2
0.3
0.2
0.3
0.2
0.3
mA
Rev. 0 | Page 7 of 52
AD9704/AD9705/AD9706/AD9707
Parameter
Supply Current Clock
Power-Down Mode (IDVDD) 4
Supply Current Clock
Power-Down Mode (ICLKVDD)4
Power Supply Rejection
Ratio (AVDD) 5
OPERATING RANGE
Min
AD9707
Typ
Max
−1
AD9706
Typ
Max
Min
Min
AD9705
Typ
Max
Min
AD9704
Typ
Max
Unit
0.22
0.28
0.22
0.28
0.22
0.28
0.22
0.28
mA
9.5
16
9.5
16
9.5
16
9.5
16
μA
−0.1
+1
−1
−0.1
+1
−1
−0.1
+1
−1
−0.1
+1
+85
−40
+85
−40
+85
−40
% of
FSR/V
°C
−40
+85
1
Measured at IOUTA, driving a virtual ground, at 25°C only.
Nominal full-scale current, IOUTFS, is 32× the IREF current.
3
An external buffer amplifier with input bias current < 100 nA should be used to drive any external load.
4
Measured at fCLOCK = 80 MSPS and fOUT = 1 MHz, using differential clock.
5
±5% power supply variation, IOUTFS = 1 mA, at 25°C only.
2
DYNAMIC SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 1 mA, differential transformer coupled output,
453 Ω differentially terminated, 1 unless otherwise noted.
Table 5.
AD9707
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate
(fCLOCK)
Output Settling Time (tST) (to 0.1%) 2
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)2
Output Fall Time (10% to 90%)2
AC LINEARITY
Spurious-Free Dynamic Range
to Nyquist
fCLOCK = 10 MSPS; fOUT = 2.1 MHz
fCLOCK = 25 MSPS; fOUT = 2.1 MHz
fCLOCK = 25 MSPS; fOUT = 5.1 MHz
fCLOCK = 65 MSPS; fOUT = 10.1 MHz
fCLOCK = 65 MSPS; fOUT = 15.1 MHz
fCLOCK = 80 MSPS; fOUT = 1.0 MHz
fCLOCK = 80 MSPS; fOUT = 15.1 MHz
fCLOCK = 80 MSPS; fOUT = 30.1 MHz
Noise Spectral Density
fCLOCK = 80 MSPS; fOUT = 10 MHz;
IOUTFS = 1 mA
ENOB at IOUTFS = 1 mA
fCLOCK = 80 MSPS; fOUT = 10 MHz;
IOUTFS = 2 mA
ENOB at IOUTFS = 2 mA
1
2
Min
Typ
80
74
AD9706
Max
Min
Typ
AD9705
Max
80
Min
Typ
80
AD9704
Max
Min
Typ
80
Max
Unit
MSPS
11
5.6
5
2.5
11
5.6
5
2.5
11
5.6
5
2.5
11
5.6
5
2.5
ns
ns
pV-s
ns
2.5
2.5
2.5
2.5
ns
86
87
82
82
77
82
77
60
86
86
82
79
76
82
77
59
85
84
82
78
74
82
77
59
70
68
68
70
69
70
68
60
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc/
Hz
bits
dBc/
Hz
Bits
72
72
66
−141.0
−139.4
−135.1
−126.3
10.5
−145.7
10.2
9.5
8.0
10.3
See Figure 71 for diagram.
Measured single-ended into 500 Ω load.
Rev. 0 | Page 8 of 52
AD9704/AD9705/AD9706/AD9707
DIGITAL SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 1 mA, unless otherwise noted.
Table 6.
Parameter
DIGITAL INPUTS 1
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
CLK INPUTS 2
Input Voltage Range
Common-Mode Voltage
Differential Voltage
1
2
Min
1.2
AD9707
Typ
Max
1.8
0
−10
Min
AD9706
Typ
Max
1.2
0.5
+10
+10
1.8
0
0
0.4
0.5
0.9
1.5
1.2
0.5
+10
+10
−10
5
2.4
0.4
6.2
Min
0
0.4
0.5
1.8
0
−10
5
2.4
0.4
6.2
1.8
1.3
AD9705
Typ
Max
1.2
0.5
+10
+10
1.8
1.3
0
0.4
0.5
0.9
1.5
1.8
1.3
0
0.4
0.5
TIMING DIAGRAM
DBO TO DB13
tH
CLOCK
tLPW
tST
0.1%
Figure 2. Timing Diagram
Rev. 0 | Page 9 of 52
0.1%
05926-002
IOUTA
OR
IOUTB
1.8
0
0.5
+10
+10
5
2.4
0.4
6.2
Includes CLK+ pin in single-ended clock input mode.
Applicable to CLK+ input and CLK– input when configured for differential clock input mode.
tS
AD9704
Typ
Max
−10
5
2.4
0.4
6.2
0.9
1.5
tPD
Min
0.9
1.5
1.8
1.3
Unit
V
V
μA
μA
pF
ns
ns
ns
V
V
V
AD9704/AD9705/AD9706/AD9707
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
AVDD
DVDD
CLKVDD
ACOM
ACOM
DCOM
AVDD
AVDD
DVDD
CLOCK, SLEEP
Digital Inputs, MODE
IOUTA, IOUTB
REFIO, REFLO, FS ADJ,
OTCM
CLK+, CLK–, CMODE
Junction Temperature
Storage Temperature
Range
Lead Temperature
(10 sec)
With
Respect to
ACOM
DCOM
CLKCOM
DCOM
CLKCOM
CLKCOM
DVDD
CLKVDD
CLKVDD
DCOM
DCOM
ACOM
ACOM
CLKCOM
Rating
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−3.9 V to +3.9 V
−3.9 V to +3.9 V
−3.9 V to +3.9 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−1.0 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS 1
Table 8. Thermal Resistance
Package Type
32-Lead LFCSP_VQ
1
θJA
32.5
Unit
°C/W
Thermal impedance measurements were taken on a 4-layer board in still air,
in accordance with EIA/JESD51-7.
−0.3 V to CLKVDD + 0.3 V
150°C
−65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 10 of 52
AD9704/AD9705/AD9706/AD9707
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
32
31
30
29
28
27
26
25
DB8
DB9
DB10
DB11
DB12
DB13 (MSB)
DCOM
SLEEP/CSB
AD9707
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD9707
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
FS ADJ
REFIO
ACOM
IOUTA
IOUTB
OTCM
AVDD
PIN/SPI/RESET
05926-003
DB0 (LSB)
DCOM
CLKVDD
CLK+
CLK–
CLKCOM
CMODE/SCLK
MODE/SDIO
9
10
11
12
13
14
15
16
DB7
DB6
DVDD
DB5
DB4
DB3
DB2
DB1
Figure 3. AD9707 Pin Configuration
Table 9. AD9707 Pin Function Descriptions
Pin No.
27
28 to 32,
1, 2, 4 to 8
9
25
Mnemonic
DB13 (MSB)
DB12 to DB1
Description
Most Significant Data Bit (MSB).
Data Bit 12 to Data Bit 1.
DB0 (LSB)
SLEEP/CSB
23
REFIO
24
22
20
21
18
19
17
FS ADJ
ACOM
IOUTB
IOUTA
AVDD
OTCM
PIN/SPI/RESET
16
MODE/SDIO
15
CMODE/SCLK
14
13
12
11
10, 26
3
CLKCOM
CLK−
CLK+
CLKVDD
DCOM
DVDD
Least Significant Data Bit (LSB).
In pin mode, active high powers down chip.
In SPI mode, this pin is the serial port chip select (active low).
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference
output when internal reference activated. Requires a 0.1 μF capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
Analog Common.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Analog Supply Voltage (1.7 V to 3.6 V).
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.
Selects SPI mode or pin mode operation. Active high for pin mode operation. Active low for SPI mode
operation. Pulse high to reset SPI registers to default values.
In pin mode, this selects the input data format. Connect to DCOM for straight binary, DVDD for twos complement.
In SPI mode, this pin acts as SPI data input/output.
In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver
(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver.
In SPI mode, this pin is the serial data clock input.
Clock Common.
Differential Clock Input.
Differential Clock Input.
Clock Supply Voltage (1.7 V to 3.6 V).
Digital Common.
Digital Supply Voltage (1.7 V to 3.6 V).
Rev. 0 | Page 11 of 52
AD9704/AD9705/AD9706/AD9707
32
31
30
29
28
27
26
25
DB6
DB7
DB8
DB9
DB10
DB11 (MSB)
DCOM
SLEEP/CSB
AD9706
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD9706
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
FS ADJ
REFIO
ACOM
IOUTA
IOUTB
OTCM
AVDD
PIN/SPI/RESET
NC = NO CONNECT
05926-083
NC
DCOM
CLKVDD
CLK+
CLK–
CLKCOM
CMODE/SCLK
MODE/SDIO
9
10
11
12
13
14
15
16
DB5
DB4
DVDD
DB3
DB2
DB1
DB0 (LSB)
NC
Figure 4. AD9706 Pin Configuration
Table 10. AD9706 Pin Function Descriptions
Pin No.
27
28 to 32,
1, 2, 4 to 6
7
25
Mnemonic
DB11 (MSB)
DB10 to DB1
Description
Most Significant Data Bit (MSB).
Data Bit 10 to Data Bit 1.
DB0 (LSB)
SLEEP/CSB
24
23
FS ADJ
REFIO
22
21
20
19
18
17
ACOM
IOUTA
IOUTB
OTCM
AVDD
PIN/SPI/RESET
16
MODE/SDIO
15
CMODE/SCLK
14
13
12
11
10, 26
8, 9
3
CLKCOM
CLK−
CLK+
CLKVDD
DCOM
NC
DVDD
Least Significant Data Bit (LSB).
In pin mode, active high powers down chip.
In SPI mode, this pin is the serial port chip select (active low).
Full-Scale Current Output Adjust.
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference
output when internal reference activated. Requires a 0.1 μF capacitor to ACOM when internal reference activated.
Analog Common.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.
Analog Supply Voltage (1.7 V to 3.6 V).
Selects SPI mode or pin mode operation. Active high for pin mode operation. Active low for SPI mode operation.
Pulse high to reset SPI registers to default values.
In pin mode, this selects the input data format. Connect to DCOM for straight binary, DVDD for twos complement.
In SPI mode, this pin acts as SPI data input/output.
In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver
(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver.
In SPI mode, this pin is the serial data clock input.
Clock Common.
Differential Clock Input.
Differential Clock Input.
Clock Supply Voltage (1.7 V to 3.6 V).
Digital Common.
No Connect.
Digital Supply Voltage (1.7 V to 3.6 V).
Rev. 0 | Page 12 of 52
AD9704/AD9705/AD9706/AD9707
32
31
30
29
28
27
26
25
DB4
DB5
DB6
DB7
DB8
DB9 (MSB)
DCOM
SLEEP/CSB
AD9705
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD9705
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
FS ADJ
REFIO
ACOM
IOUTA
IOUTB
OTCM
AVDD
PIN/SPI/RESET
NC = NO CONNECT
05926-085
NC
DCOM
CLKVDD
CLK+
CLK–
CLKCOM
CMODE/SCLK
MODE/SDIO
9
10
11
12
13
14
15
16
DB3
DB2
DVDD
DB1
DB0 (LSB)
NC
NC
NC
Figure 5. AD9705 Pin Configuration
Table 11. AD9705 Pin Function Descriptions
Pin No.
27
28 to 32,
1, 2, 4
5
25
Mnemonic
DB9 (MSB)
DB8 to DB1
Description
Most Significant Data Bit (MSB).
Data Bit 8 to Data Bit 1.
DB0 (LSB)
SLEEP/CSB
24
23
FS ADJ
REFIO
22
21
20
19
18
17
ACOM
IOUTA
IOUTB
OTCM
AVDD
PIN/SPI/RESET
16
MODE/SDIO
15
CMODE/SCLK
14
13
12
11
10, 26
6 to 9
3
CLKCOM
CLK−
CLK+
CLKVDD
DCOM
NC
DVDD
Least Significant Data Bit (LSB).
In pin mode, active high powers down chip.
In SPI mode, this pin is the serial port chip select (active low).
Full-Scale Current Output Adjust.
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference
output when internal reference activated. Requires a 0.1 μF capacitor to ACOM when internal reference activated.
Analog Common.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.
Analog Supply Voltage (1.7 V to 3.6 V).
Selects SPI mode or pin mode operation. Active high for pin mode operation. Active low for SPI mode
operation. Pulse high to reset SPI registers to default values.
In pin mode, this selects the input data format. Connect to DCOM for straight binary, DVDD for twos complement.
In SPI mode, this pin acts as SPI data input/output.
In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver
(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver.
In SPI mode, this pin is the serial data clock input.
Clock Common.
Differential Clock Input.
Differential Clock Input.
Clock Supply Voltage (1.7 V to 3.6 V).
Digital Common.
No Connect.
Digital Supply Voltage (1.7 V to 3.6 V).
Rev. 0 | Page 13 of 52
AD9704/AD9705/AD9706/AD9707
32
31
30
29
28
27
26
25
DB2
DB3
DB4
DB5
DB6
DB7 (MSB)
DCOM
SLEEP/CSB
AD9704
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD9704
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
FS ADJ
REFIO
ACOM
IOUTA
IOUTB
OTCM
AVDD
PIN/SPI/RESET
NC = NO CONNECT
05926-084
NC
DCOM
CLKVDD
CLK+
CLK–
CLKCOM
CMODE/SCLK
MODE/SDIO
9
10
11
12
13
14
15
16
DB1
DB0 (LSB)
DVDD
NC
NC
NC
NC
NC
Figure 6. AD9704 Pin Configuration
Table 12. AD9704 Pin Function Descriptions
Pin No.
27
28 to 32,
1
2
25
Mnemonic
DB7 (MSB)
DB6 to DB1
Description
Most Significant Data Bit (MSB).
Data Bit 6 to Data Bit 1.
DB0 (LSB)
SLEEP/CSB
24
23
FS ADJ
REFIO
22
21
20
19
18
17
ACOM
IOUTA
IOUTB
OTCM
AVDD
PIN/SPI/RESET
16
MODE/SDIO
15
CMODE/SCLK
14
13
12
11
10, 26
4 to 9
3
CLKCOM
CLK−
CLK+
CLKVDD
DCOM
NC
DVDD
Least Significant Data Bit (LSB).
In pin mode, active high powers down chip.
In SPI mode, this pin is the serial port chip select (active low).
Full-Scale Current Output Adjust.
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference
output when internal reference activated. Requires a 0.1 μF capacitor to ACOM when internal reference activated.
Analog Common.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.
Analog Supply Voltage (1.7 V to 3.6 V).
Selects SPI mode or pin mode operation. Active high for pin mode operation. Active low for SPI mode
operation. Pulse high to reset SPI registers to default values.
In pin mode, this selects the input data format. Connect to DCOM for straight binary, DVDD for twos complement.
In SPI mode, this pin acts as SPI data input/output.
In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver
(drive CLK+ and float CLK−). Connect to CLKVDD for differential receiver.
In SPI mode, this pin is the serial data clock input.
Clock Common.
Differential Clock Input.
Differential Clock Input.
Clock Supply Voltage (1.7 V to 3.6 V).
Digital Common.
No Connect.
Digital Supply Voltage (1.7 V to 3.6 V).
Rev. 0 | Page 14 of 52
AD9704/AD9705/AD9706/AD9707
TYPICAL PERFORMANCE CHARACTERISTICS
AD9707
VDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.
95
95
10MSPS
90
90
65MSPS
85
85
80
175MSPS
SFDR (dBc)
75
70
65
125MSPS
75
70
65
55
50
50
1
10
100
fOUT (MHz)
45
0
5
10
90
85
85
80
80
75
75
SFDR (dBc)
90
70
65
60
55
50
50
3
4
5
fOUT (MHz)
45
0
10
85
85
80
80
75
75
SFDR (dBc)
90
70
65
60
55
50
50
15
20
55
60
65
25
fOUT (MHz)
20
30
40
50
60
70
80
30
35
70
80
Figure 9. SFDR vs. fOUT @ 65 MSPS
2mA
1mA
65
55
10
50
5mA
70
60
05926-007
SFDR (dBc)
95
90
5
45
Figure 11. SFDR vs. fOUT @ 175 MSPS
95
0
40
fOUT (MHz)
Figure 8. SFDR vs. fOUT @ 10 MSPS
45
35
65
55
2
30
70
60
05926-006
SFDR (dBc)
95
1
25
Figure 10. SFDR vs. fOUT @ 125 MSPS
95
0
20
fOUT (MHz)
Figure 7. SFDR vs. fOUT
45
15
05926-009
45
05926-008
60
55
05926-010
60
05926-005
SFDR (dBc)
80
45
0
10
20
30
40
50
60
fOUT (MHz)
Figure 12. SFDR vs. fOUT and IOUTFS @ 175 MSPS
Rev. 0 | Page 15 of 52
AD9704/AD9705/AD9706/AD9707
95
–115
90
–120
85
–125
–130
NSD (dBc/Hz)
OTCM = 0
75
70
OTCM = 0.3V
65
OTCM = 1.2V
–140
–150
50
–155
20
30
40
50
60
70
–160
05926-011
10
80
fOUT (MHz)
5mA
0
40
50
60
70
80
95
90
90
65MSPS
85
85
125MSPS
80
SFDR (dBc)
75
175MSPS
70
75MSPS
80
65
175MSPS
75
70
65
60
55
55
50
50
45
–10
–8
–6
–4
AOUT (dBFS)
–2
0
45
0
20
30
40
50
60
95
–120
90
–125
85
125MSPS
25°C
80
–130
SFDR (dBc)
65MSPS
–135
175MSPS
–145
85°C
75
70
65
60
55
–155
50
20
30
40
50
60
70
fOUT (MHz)
80
05926-013
–150
10
80
Figure 17. Dual-Tone IMD vs. fOUT @ 0 dBFS
–115
0
70
LOWER fOUT (MHz)
Figure 14. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5
–140
10
05926-015
125MSPS
60
05926-012
SFDR (dBc)
30
Figure 16. NSD vs. fOUT and IOUTFS @ 175 MSPS
95
NSD (dBc/Hz)
20
fOUT (MHz)
Figure 13. SFDR vs. fOUT and OTCM @ 175 MSPS
–160
10
05926-014
55
0
2mA
–145
60
45
1mA
–135
Figure 15. NSD vs. fOUT and fCLOCK @ 0 dBFS
45
–40°C
0
10
20
30
40
50
60
70
80
LOWER fOUT (MHz)
Figure 18. Dual-Tone IMD vs. fOUT and Temperature @ 0 dBFS
Rev. 0 | Page 16 of 52
05926-016
SFDR (dBc)
80
AD9704/AD9705/AD9706/AD9707
0.6
1.0
0.5
0.4
DNL (LSB)
INL (LSB)
0.5
0
–0.5
0.3
0.2
0.1
0
–1.0
5000
10000
16384
CODE
0
5000
10000
15000
CODE
Figure 19. Typical Uncalibrated INL
05926-087
–0.2
0
05926-017
–1.5
–0.1
Figure 22. Typical Calibrated DNL
95
0.6
90
0.4
85
80
SFDR (dBc)
DNL (LSB)
0.2
0
–0.2
75
25°C
85°C
70
–40°C
65
60
–0.4
55
–0.6
5000
10000
16384
45
CODE
0
10
20
30
40
50
60
70
80
fOUT (MHz)
Figure 20. Typical Uncalibrated DNL
05926-019
0
05926-018
–0.8
50
Figure 23. SFDR vs. Temperature @ 175 MSPS
0.6
–10
fCLOCK = 78MSPS
fOUT = 15.0MHz
–20
–30
0
–40
MAGNITUDE (dBm)
0.2
–0.2
–0.4
–0.6
SFDR = 79dBc
AMPLITUDE = 0dBFS
–50
–60
–70
–80
–90
–0.8
0
5000
10000
CODE
15000
–110
1
6
11
16
21
26
FREQUENCY (MHz)
Figure 21. Typical Calibrated INL
Figure 24. Single-Tone SFDR
Rev. 0 | Page 17 of 52
31
36
05926-020
–100
–1.0
05926-086
INL (LSB)
0.4
AD9704/AD9705/AD9706/AD9707
–10
–10
–20
–30
SFDR = 74dBc
AMPLITUDE = 0dBFS
MAGNITUDE (dBm)
–40
–50
–60
–70
–80
–40
–60
–70
–80
–90
–90
–100
–110
1
6
11
16
21
26
FREQUENCY (MHz)
31
36
Figure 25. Dual-Tone SFDR
SFDR = 69dBc
AMPLITUDE = 0dBFS
–50
–100
05926-021
MAGNITUDE (dBm)
–30
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
fOUT3 = 15.8MHz
fOUT4 = 16.2MHz
–20
–110
1
6
11
16
21
26
FREQUENCY (MHz)
Figure 26. Four-Tone SFDR
Rev. 0 | Page 18 of 52
31
36
05926-022
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
AD9704/AD9705/AD9706/AD9707
VDD = 1.8 V, IOUTFS = 1 mA, unless otherwise noted.
95
95
10MSPS
90
90
65MSPS
85
85
80
65
75
70
65
60
60
55
55
50
50
45
1
10
100
fOUT (MHz)
45
0
5
10
90
85
85
80
80
75
75
SFDR (dBc)
90
70
65
55
55
50
50
3
4
5
fOUT (MHz)
45
0
85
85
80
80
75
75
SFDR (dBc)
90
70
65
55
55
50
50
20
25
fOUT (MHz)
20
25
30
35
30
35
40
1mA
65
60
15
15
70
60
05926-025
SFDR (dBc)
90
10
10
Figure 31. SFDR vs. fOUT and IOUTFS @ 65 MSPS
95
5
5
fOUT (MHz)
95
0
40
2mA
Figure 28. SFDR vs. fOUT @ 10 MSPS
45
35
1mA
65
60
2
30
70
60
05926-024
SFDR (dBc)
95
1
25
Figure 30. SFDR vs. fOUT @ 80 MSPS
95
0
20
fOUT (MHz)
Figure 27. SFDR vs. fOUT
45
15
05926-026
70
05926-027
SFDR (dBc)
75
05926-028
80MSPS
05926-023
SFDR (dBc)
80
45
2mA
0
5
10
15
20
25
30
fOUT (MHz)
Figure 32. SFDR vs. fOUT and IOUTFS @ 80 MSPS
Figure 29. SFDR vs. fOUT @ 65 MSPS
Rev. 0 | Page 19 of 52
35
AD9704/AD9705/AD9706/AD9707
95
95
90
90
85
85
80
70
65
65MSPS
55
55
50
50
–6
–4
–2
0
AOUT (dBFS)
45
95
–120
90
5
10
15
20
25
30
35
40
40
85
–125
80
65MSPS, 1mA
–40°C
80MSPS, 1mA
IMD (dBc)
–130
–135
–140
–145
85°C
70
65
25°C
60
80MSPS, 2mA
65MSPS, 2mA
–150
75
55
–155
50
5
10
15
20
25
30
35
40
fOUT (dBFS)
45
05926-030
0
0
5
10
15
20
25
30
35
LOWER fOUT (MHz)
Figure 34. NSD vs. fOUT, fCLOCK, and IOUTFS @ 0 dBFS
Figure 37. Dual-Tone IMD vs. fOUT and Temperature @ 80 MSPS,
IOUTFS = 1 mA and 0 dBFS
95
95
90
90
85
85
80
25°C
80
–40°C
65MSPS
IMD (dBc)
75
70
25MSPS
65
60
75
70
65
60
80MSPS
55
55
80°C
50
0
5
10
15
20
25
30
35
LOWER fOUT (MHz)
40
05926-031
45
50
Figure 35. Dual-Tone IMD vs. fOUT @ IOUTFS = 1 mA and 0 dBFS
45
0
5
10
15
20
25
30
35
40
LOWER fOUT (MHz)
Figure 38. Dual-Tone IMD vs. fOUT and Temperature @ 80 MSPS,
IOUTFS = 2 mA and 0 dBFS
Rev. 0 | Page 20 of 52
05926-034
NSD (dBc/Hz)
0
Figure 36. Dual-Tone IMD vs. fOUT @ IOUTFS = 2 mA and 0 dBFS
–115
–160
80MSPS
LOWER fOUT (MHz)
Figure 33. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5
IMD (dBc)
65
60
–8
25MSPS
70
60
45
–10
65MSPS
75
05926-032
IMD (dBc)
75
05926-033
80MSPS
05926-029
SFDR (dBc)
80
AD9704/AD9705/AD9706/AD9707
–10
1.0
fCLOCK = 78MSPS
fOUT = 15.0MHz
–20
MAGNITUDE (dBm)
INL (LSB)
SFDR = 80dBc
AMPLITUDE = 0dBFS
–30
0.5
0.0
–0.5
–1.0
–40
–50
–60
–70
–80
–90
0
5000
10000
16384
CODE
–110
05926-035
–1.5
1
6
11
16
21
Figure 39. Typical Uncalibrated INL
31
36
Figure 42. Single-Tone SFDR
0.6
–10
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
–20
0.4
–30
MAGNITUDE (dBm)
0.2
DNL (LSB)
26
FREQUENCY (MHz)
05926-039
–100
0
–0.2
–0.4
SFDR = 77dBc
AMPLITUDE = 0dBFS
–40
–50
–60
–70
–80
–90
–0.6
10000
16384
CODE
–110
1
6
–10
90
–20
MAGNITUDE (dBm)
75
85°C
25°C
60
–60
–70
–80
–90
–100
5
10
15
20
25
30
fOUT (MHz)
36
35
40
SFDR = 77dBc
AMPLITUDE = 0dBFS
–50
50
0
31
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
fOUT3 = 15.8MHz
fOUT4 = 16.2MHz
–40
55
05926-037
SFDR (dBc)
80
45
26
–30
–40°C
65
21
Figure 43. Dual-Tone SFDR
95
70
16
FREQUENCY (MHz)
Figure 40. Typical Uncalibrated DNL
85
11
05926-038
5000
–110
1
6
11
16
21
26
FREQUENCY (MHz)
Figure 44. Four-Tone SFDR
Figure 41. SFDR vs. Temperature @ 80 MSPS
Rev. 0 | Page 21 of 52
31
36
05926-040
0
05926-036
–0.8
–100
AD9704/AD9705/AD9706/AD9707
AD9704, AD9705, AND AD9706
VDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.
0.01
–115
AD9704
–120
–125
AD9705
–135
INL (LSB)
NSD (dBc/Hz)
–130
–140
0
–145
AD9706
–150
AD9707
20
30
40
50
60
70
80
fOUT (MHz)
–0.01
0
200
400
600
800
1024
05926-044
10
1024
05926-045
0
05926-041
–160
4096
05926-046
–155
CODE
Figure 48. AD9705 Typical Uncalibrated INL
Figure 45. AD9704, AD9705, AD9706 NSD vs. fOUT @ 0 dBFS
0.01
0.03
0.01
DNL (LSB)
INL (LSB)
0.02
0
0
–0.01
0
50
100
150
200
256
CODE
–0.01
05926-043
–0.02
0
200
400
600
800
CODE
Figure 49. AD9705 Typical Uncalibrated DNL
Figure 46. AD9704 Typical Uncalibrated INL
0.01
0.3
0.2
0.1
INL (LSB)
0
–0.01
–0.1
–0.2
–0.02
–0.3
–0.4
–0.03
0
50
100
150
200
CODE
256
05926-042
DNL (LSB)
0
Figure 47. AD9704 Typical Uncalibrated DNL
–0.5
0
1000
2000
3000
CODE
Figure 50. AD9706 Typical Uncalibrated INL
Rev. 0 | Page 22 of 52
AD9704/AD9705/AD9706/AD9707
–10
0.01
fCLOCK = 78MSPS
fOUT = 15.0MHz
SFDR = 75dBc
AMPLITUDE = 0dBFS
–20
–30
MAGNITUDE (dBm)
DNL (LSB)
0
–0.01
–0.02
–40
–50
–60
–70
–80
–90
–0.03
0
1000
2000
3000
4096
CODE
–110
05926-047
1
26
31
36
–30
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
11
16
21
26
31
36
FREQUENCY (MHz)
–110
05926-048
6
SFDR = 73dBc
AMPLITUDE = 0dBFS
–40
1
6
11
16
21
26
31
36
FREQUENCY (MHz)
Figure 52. AD9704 Single-Tone SFDR
05926-061
MAGNITUDE (dBm)
–40
1
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
–20
SFDR = 67dBc
AMPLITUDE = 0dBFS
–30
MAGNITUDE (dBm)
21
–10
fCLOCK = 78MSPS
fOUT = 15.0MHz
–20
Figure 55. AD9705 Dual-Tone SFDR
–10
–10
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
–20
–30
MAGNITUDE (dBm)
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–100
1
6
11
16
21
26
FREQUENCY (MHz)
31
36
SFDR = 77dBc
AMPLITUDE = 0dBFS
–30
SFDR = 67dBc
AMPLITUDE = 0dBFS
–40
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
–20
05926-049
MAGNITUDE (dBm)
16
Figure 54. AD9705 Single-Tone SFDR
–10
–110
11
FREQUENCY (MHz)
Figure 51. AD9706 Typical Uncalibrated DNL
–110
6
Figure 53. AD9704 Dual-Tone SFDR
–110
1
6
11
16
21
26
FREQUENCY (MHz)
Figure 56. AD9706 Single-Tone SFDR
Rev. 0 | Page 23 of 52
31
36
05926-062
–0.04
05926-050
–100
AD9704/AD9705/AD9706/AD9707
–10
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
–20
SFDR = 77dBc
AMPLITUDE = 0dBFS
–40
–50
–60
–70
–80
–90
–100
–110
1
6
11
16
21
26
FREQUENCY (MHz)
31
36
05926-063
MAGNITUDE (dBm)
–30
Figure 57. AD9706 Dual-Tone SFDR
Rev. 0 | Page 24 of 52
AD9704/AD9705/AD9706/AD9707
VDD = 1.8 V, IOUTFS = 1 mA, unless otherwise noted.
–115
0.08
–120
AD9704
0.06
–125
0.04
AD9705
0.02
–135
INL (LSB)
–140
–145
AD9706
–0.02
AD9707
–150
–0.04
–155
10
15
20
25
30
35
40
fOUT (MHz)
–0.08
0
200
400
600
800
1024
05926-067
5
1024
05926-068
–0.06
0
05926-064
–160
0
4096
05926-069
NSD (dBc/Hz)
–130
CODE
Figure 61. AD9705 Typical Uncalibrated INL
Figure 58. AD9704, AD9705, AD9706 NSD vs. fOUT @ 0 dBFS
0.04
0.02
0
0.03
–0.02
DNL (LSB)
INL (LSB)
0.02
0.01
–0.04
–0.06
0
–0.08
–0.01
0
50
100
150
200
256
CODE
–0.12
05926-065
–0.02
–0.10
0
200
400
600
800
CODE
Figure 59. AD9704 Typical Uncalibrated INL
Figure 62. AD9705 Typical Uncalibrated DNL
0.3
0.01
0.2
0.1
INL (LSB)
0
–0.01
–0.1
–0.2
–0.3
–0.02
–0.4
–0.03
0
50
100
150
200
CODE
256
05926-066
DNL (LSB)
0
–0.5
0
1000
2000
3000
CODE
Figure 63. AD9706 Typical Uncalibrated INL
Figure 60. AD9704 Typical Uncalibrated DNL
Rev. 0 | Page 25 of 52
AD9704/AD9705/AD9706/AD9707
0.1
–10
fCLOCK = 78MSPS
fOUT = 15.0MHz
–20
SFDR = 73dBc
AMPLITUDE = 0dBFS
–30
MAGNITUDE (dBm)
DNL (LSB)
0
–0.1
–0.2
–0.3
–40
–50
–60
–70
–80
–90
0
1000
2000
3000
4096
CODE
–110
05926-070
1
26
31
36
–30
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
11
16
21
26
31
36
FREQUENCY (MHz)
–110
05926-071
6
SFDR = 71dBc
AMPLITUDE = 0dBFS
–40
1
6
11
16
21
26
31
36
FREQUENCY (MHz)
Figure 65. AD9704 Single-Tone SFDR
05926-074
MAGNITUDE (dBm)
–40
1
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
–20
SFDR = 67dBc
AMPLITUDE = 0dBFS
–30
MAGNITUDE (dBm)
21
–10
fCLOCK = 78MSPS
fOUT = 15.0MHz
–20
Figure 68. AD9705 Dual-Tone SFDR
–10
–10
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
–20
–30
MAGNITUDE (dBm)
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–100
1
6
11
16
21
26
FREQUENCY (MHz)
31
36
SFDR = 73dBc
AMPLITUDE = 0dBFS
–30
SFDR = 67dBc
AMPLITUDE = 0dBFS
–40
fCLOCK = 78MSPS
fOUT = 15.0MHz
–20
05926-072
MAGNITUDE (dBm)
16
Figure 67. AD9705 Single-Tone SFDR
–10
–110
11
FREQUENCY (MHz)
Figure 64. AD9706 Typical Uncalibrated DNL
–110
6
Figure 66. AD9704 Dual-Tone SFDR
–110
1
6
11
16
21
26
FREQUENCY (MHz)
Figure 69. AD9706 Single-Tone SFDR
Rev. 0 | Page 26 of 52
31
36
05926-075
–0.4
05926-073
–100
AD9704/AD9705/AD9706/AD9707
–10
fCLOCK = 78MSPS
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
–20
SFDR = 73dBc
AMPLITUDE = 0dBFS
–40
–50
–60
–70
–80
–90
–100
–110
1
6
11
16
21
26
FREQUENCY (MHz)
31
36
05926-076
MAGNITUDE (dBm)
–30
Figure 70. AD9706 Dual-Tone SFDR
Rev. 0 | Page 27 of 52
AD9704/AD9705/AD9706/AD9707
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero to full scale.
Power Supply Rejection
Power supply rejection is the maximum change in the full-scale
output as the supplies are varied from nominal to minimum
and maximum specified voltages.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band about its final value,
measured from the start of the output transition.
Monotonicity
A digital-to-analog converter is monotonic if the output either
increases or remains constant as the digital input increases.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in picovolt-seconds (pV-s).
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the output signal and the peak spurious signal over
the specified bandwidth.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the output when all inputs
are set to 1, minus the output when all inputs are set to 0. The
ideal gain is calculated using the measured VREF. Therefore,
the gain error does not include effects of the reference.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal.
It is expressed as a percentage or in decibels (dB).
Multitone Power Ratio
Multitone power ratio is the spurious-free dynamic range
containing multiple carrier tones of equal amplitude. It is
measured as the difference between the rms amplitude of
a carrier tone to the peak spurious signal in the region of
a removed tone.
Output Compliance Range
Output compliance range is the range of allowable voltage at the
output of a current output DAC. Operation beyond the maximum
compliance limits can cause either output stage saturation or
breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For offset
and gain drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.
Noise Spectral Density (NSD)
Noise spectral density is the average noise power normalized to
a 1 Hz bandwidth, with the DAC converting and producing an
output tone.
1.7V TO 3.6V
RSET
16kΩ
ADT1-1WT
1.0V REF
REFIO
FS ADJ
1.7V TO 3.6V
10kΩ
ACOM
CURRENT
SOURCE
ARRAY
CLKVDD
CLKCOM
SEGMENTED
SWITCHES
AD9707
LSB
SWITCHES
IOUTA
0.1µF
CLK–
1.7V
TO
10kΩ 3.6V
LATCHES
453Ω
SPI
DVDD
0Ω
SPECTRUM ANALYZER
AGILENT OR
RHODE AND SCHWARZ
9:1
ROTCM
0Ω
DCOM
CLOCK
OUTPUT
LOW JITTER RF SOURCE
AGILENT OR ROHDE AND SCHWARZ
ADTL1-12
IOUTB
CLK+
50Ω
MINI-CIRCUITS
ADT9-1T
OTCM
SLEEP/CSB
DIGITAL
DATA
DIGITAL DATA SOURCE DPG,
SONY/TEK OR ROHDE AND SCHWARZ
Figure 71. Basic AC Characterization Test Setup
Rev. 0 | Page 28 of 52
05926-004
0.1µF
AVDD
AD9704/AD9705/AD9706/AD9707
THEORY OF OPERATION
Figure 72 shows a simplified block diagram of one of the
AD970x parts, the AD9707 The AD970x consists of a DAC,
digital control logic, and full-scale output current control. The
DAC contains a PMOS current source array capable of providing
a nominal full-scale current (IOUTFS) of 2 mA and a maximum of
5 mA. The array is divided into 31 equal currents that make up the
five most significant bits (MSBs). The next four bits, or middle
bits, consist of 15 equal current sources whose value is 1/16 of an
MSB current source. The remaining LSBs are binary weighted fractions of the current sources of the middle bits. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the AD970x dynamic performance for multitone
or low amplitude signals and helps maintain the high output
impedance of the DAC (that is, >200 MΩ).
The external resistor, in combination with both the reference
control amplifier and voltage reference, VREFIO, sets the reference
current, IREF, which is replicated to the segmented current sources
with the proper scaling factor. The full-scale current, IOUTFS, is
32 × IREF.
The AD970x provides the option of setting the output common
mode to a value other than ACOM via the output common mode
(OTCM) pin. This facilitates interfacing the output of the AD970x
directly to components that require common-mode levels greater
than 0 V.
SERIAL PERIPHERAL INTERFACE
The AD970x serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including the Motorola
SPI and Intel® SSR protocols. The interface allows read/write
access to all registers that configure the AD970x. Single or multiple
byte transfers are supported, as well as MSB first or LSB first
transfer formats. The serial interface port of the AD970x is
configured as a single pin I/O.
All of these current sources are switched to one of the two
output nodes (IOUTA or IOUTB) via PMOS differential current
switches. The switches are based on the architecture pioneered
in the AD9764 family, with further refinements made to reduce
distortion contributed by the switching transient. This switch
architecture also reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
General Operation of the Serial Interface
The analog and digital sections of the AD970x have separate power
supply inputs (AVDD and DVDD) that can operate independently
over a 1.7 V to 3.6 V range. The digital section, which is capable
of operating at a rate of up to 175 MSPS, consists of edge-triggered
latches and segment decoding logic circuitry. The analog section
includes the PMOS current sources, the associated differential
switches, a 1.0 V band gap voltage reference, and a reference
control amplifier.
There are two phases to a communication cycle with the AD970x.
Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD970x, coincident with the first eight SCLK
rising edges. The instruction byte provides the AD970x serial port
controller with information regarding the data transfer cycle, which
is Phase 2 of the communication cycle. The Phase 1 instruction
byte defines whether the upcoming data transfer is read or write,
the number of bytes in the data transfer, and the starting register
address for the first byte of the data transfer. The first eight
SCLK rising edges of each communication cycle are used to write
the instruction byte into the AD970x.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 1 mA to 5 mA via an external
resistor, RSET, connected to the full-scale adjust (FS ADJ) pin.
1.7V TO 3.6V
1.0V REF
REFIO
FS ADJ
RSET
1.7V
TO
3.6V
CLKVDD
CLKCOM
CLK+
CLK–
1.7V TO
3.6V
AVDD
ACOM
CURRENT
SOURCE
ARRAY
SEGMENTED
SWITCHES
AD9707
LSB
SWITCHES
LATCHES
OTCM
IOUTA
IOUTB
SPI
DVDD
DCOM
DIGITAL INPUTS (DB13 TO DB0)
SLEEP/CSB
Figure 72. Simplified Block Diagram
Rev. 0 | Page 29 of 52
PIN/SPI/RESET
MODE/SDIO
CMODE/SCLK
05926-103
0.1µF
AD9704/AD9705/AD9706/AD9707
A logic high on Pin 17 (PIN/SPI/RESET), followed by a logic
low, resets the SPI port timing to the initial state of the
instruction cycle. This is true regardless of the present state of
the internal registers or the other signal levels present at the
inputs to the SPI port. If the SPI port is in the midst of an
instruction cycle or a data transfer cycle, none of the present
data is written.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD970x
and the system controller. Phase 2 of the communication cycle
is a transfer of one, two, three, or four data bytes, as determined
by the instruction byte. Using one multibyte transfer is the
preferred method. Single byte data transfers are useful to reduce
CPU overhead when register access requires one byte only.
Registers change immediately upon writing to the last bit of
each transfer byte.
Instruction Byte
The instruction byte contains the information shown in the
following bit map:
MSB
7
R/W
6
5
4
3
2
1
LSB
0
N1
N0
A4
A3
A2
A1
A0
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write. Logic 1
indicates a read operation. Logic 0 indicates a write operation.
N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine the
number of bytes to be transferred during the data transfer cycle.
The bit decodes are shown in Table 13.
A4, A3, A2, A1, and A0, which are Bit 4, Bit 3, Bit 2, Bit 1, and
Bit 0 of the instruction byte, respectively, determine which register
is accessed during the data transfer portion of the communication
cycle. For multibyte transfers, this address is the starting byte
address. The remaining register addresses are generated by the
AD970x, based on the DATADIR bit (Register 0x00, Bit 6).
N0
0
1
0
1
SDIO—Serial Data I/O. This pin is used as a bidirectional data
line to transmit and receive data.
MSB/LSB Transfers
The AD970x serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the DATADIR bit (Register 0x00,
Bit 6). The default is MSB first (DATADIR = 0).
When DATADIR = 0 (MSB first), the instruction and data bytes
must be written from most significant bit to least significant bit.
Multibyte data transfers in MSB first format start with an
instruction byte that includes the register address of the most
significant data byte. Subsequent data bytes should follow in
order from high address to low address. In MSB first mode, the
serial port internal byte address generator decrements for each
data byte of the multibyte communication cycle.
When DATADIR = 1 (LSB first), the instruction and data bytes
must be written from least significant bit to most significant bit.
Multibyte data transfers in LSB first format start with an instruction
byte that includes the register address of the least significant data
byte followed by multiple data bytes. The serial port internal byte
address generator increments for each byte of the multibyte
communication cycle.
The AD970x serial port controller data address decrements
from the data address written toward 0x00 for multibyte I/O
operations if the MSB first mode is active. The serial port
controller address increments from the data address written
toward 0x1F for multibyte I/O operations if the LSB first mode
is active.
Notes on Serial Port Operation
Table 13. Byte Transfer Count
N1
0
0
1
1
CSB—Chip Select. Active low input starts and gates a communication cycle. It allows more than one device to be used on the same
serial communications lines. The SDIO pin goes to a high impedance state when this input is high. Chip select should stay low
during the entire communication cycle.
The AD970x serial port configuration is controlled by
Register 0x00, Bit 7. It is important to note that the configuration
changes immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register can occur during
the middle of communication cycle. Care must be taken to
compensate for this new configuration for the remaining bytes
of the current communication cycle.
Description
Transfer 1 byte
Transfer 2 bytes
Transfer 3 bytes
Transfer 4 bytes
Serial Interface Port Pin Descriptions
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD970x and to run the internal state
machines. The SCLK maximum frequency is 20 MHz. All data
input to the AD970x is registered on the rising edge of SCLK.
All data is driven out of the AD970x on the falling edge of SCLK.
The same considerations apply to setting the software reset,
SWRST (Register 0x00, Bit 5). All registers are set to their default
values except Register 0x00, which remains unchanged.
Use of single byte transfers is recommended when changing
serial port configurations or initiating a software reset to
prevent unexpected device behavior.
Rev. 0 | Page 30 of 52
AD9704/AD9705/AD9706/AD9707
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CSB
A0
SDIO
A1 A2
A3
A4
N0
N1 R/W
SCLK
D10 D20
D4N D5N D6 N D7N
D1 0 D20
D4N D5N D6 N D7N
A2
A1 A0 D7N D6N D5N
D30 D20 D10 D00
SDO
D0
Figure 73. Serial Register Interface Timing, MSB First Write
INSTRUCTION CYCLE
05926-088
R/W N1 N0 A4 A3
SDIO
05926--091
D0
Figure 76. Serial Register Interface Timing, LSB First Read
DATA TRANSFER CYCLE
tDS
CSB
tSCLK
CSB
SCLK
tPWH
A3
A2 A1 A0
D6N D5N
D30 D20 D10 D00
D6N D5 N
D30 D20 D10 D00
D7
SDO
SCLK
D7
tDS
INSTRUCTION BIT 6
Figure 77. Timing Diagram for SPI Register Write
Figure 74. Serial Register Interface Timing, MSB First Read
INSTRUCTION CYCLE
tDH
INSTRUCTION BIT 7
SDIO
05926-092
A4
05926-090
R/W N1 N0
SDIO
tPWL
CSB
DATA TRANSFER CYCLE
CSB
tDNV
A0
SDIO
A1 A2 A3
A4 N0
N1 R/W D00 D10 D20
D4N D5N D6N D7N
05926-089
SCLK
SDIO I1
I0
D7
tDV
D6
D5
05926-093
SCLK
Figure 78. Timing Diagram for SPI Register Read
Figure 75. Serial Register Interface Timing, LSB First Write
SPI REGISTER MAP
Table 14.
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI CTL
0x00
SDIODIR
DATADIR
SWRST
LNGINS
PDN
SLEEP
CLKOFF
EXREF
DATA
0x02
DATAFMT
DCLKPOL
DESKEW
CLKDIFF
VERSION
0x0D
VER[3]
VER[2]
VER[1]
VER[0]
CALMEM
0x0E
DIVSEL[2]
DIVSEL[1]
DIVSEL[0]
MEMRDWR
0x0F
CALMEM[1]
CALSTAT
CALMEM[0]
CALEN
SMEMWR
SMEMRD
CALCLK
UNCAL
MEMADDR
0x10
MEMADDR[5]
MEMADDR[4]
MEMADDR[3]
MEMADDR[2]
MEMADDR[1]
MEMADDR[0]
MEMDATA
0x11
MEMDATA[5]
MEMDATA[4]
MEMDATA[3]
MEMDATA[2]
MEMDATA[1]
MEMDATA[0]
TRIM
0x14
CALDACFS
Rev. 0 | Page 31 of 52
AD9704/AD9705/AD9706/AD9707
SPI REGISTER DESCRIPTIONS
Table 15. SPI CTL—Register 0x00
Bit Name
SDIODIR
Bit
7
Direction (I/O)
I
Default
1
DATADIR
6
I
0
SWRST
LNGINS
5
4
I
I
0
0
PDN
SLEEP
CLKOFF
EXREF
3
2
1
0
I
I
I
I
0
0
0
0
Description
0: SDIO pin configured for input only during data transfer (4-wire interface)
1: SDIO pin configured for input or output during data transfer (3-wire interface)
0: Serial data uses MSB first format
1: Serial data uses LSB first format
1: Initiate a software reset; this bit is set to 0 upon reset completion
0: Use 1 byte preamble (5 address bits)
1: Use 2 byte preamble (13 address bits)
1: All analog and digital circuitry off, except serial interface
1: DAC output current off
1: Disables internal master clock.
0: Internal bandgap reference
1: External reference
Table 16. DATA—Register 0x02
Bit Name
DATAFMT
Bit
7
Direction (I/O)
I
Default
0
DCLKPOL
4
I
0
DESKEW
3
I
0
CLKDIFF
2
I
0
CALCLK
0
I
0
Description
0: Unsigned binary input data format
1: Twos complement input data format
0: Data latched on DATACLK rising edge always
1: Data latched on DATACLK falling edge (only active in DESKEW mode)
0: DESKEW mode disabled
1: DESKEW mode enabled (adds a register in digital data path to remove
skew in received data; one clock cycle of latency is introduced)
0: Single-ended clock input
1: Differential clock input
0: Calibration clock disabled
1: Calibration clock enabled
Table 17. VERSION—Register 0x0D
Bit Name
VER[3:0]
Bit
[3:0]
Direction (I/O)
O
Default
Description
Hardware version identifier
Table 18. CALMEM—Register 0x0E
Bit Name
CALMEM[1:0]
Bit
[5:4]
Direction (I/O)
O
Default
00
DIVSEL[2:0]
[2:0]
I
000
Description
Calibration memory
00: Uncalibrated
01: Self-calibration
10: Not Used
11: User input
Calibration clock divide ratio from DAC clock rate
000: /256
001: /128
:
110: /4
111: /2
Rev. 0 | Page 32 of 52
AD9704/AD9705/AD9706/AD9707
Table 19. MEMRDWR—Register 0x0F
Bit Name
CALSTAT
CALEN
SMEMWR
SMEMRD
UNCAL
Bit
7
6
3
2
0
Direction (I/O)
O
I
I
I
I
Default
0
0
0
0
0
Description
1: Calibration cycle complete
1: Initiate device self-calibration
1: Write to static memory (calibration coefficients)
1: Read from static memory (calibration coefficients)
1: Reset calibration coefficients to default (uncalibrated)
Table 20. MEMADDR—Register 0x10
Bit Name
MEMADDR[5:0]
Bit
[5:0]
Direction (I/O)
I/O
Default
000000
Description
Address of static memory to be accessed
Table 21. MEMDATA—Register 0x11
Bit Name
MEMDATA[5:0]
Bit
[5:0]
Direction (I/O)
I/O
Default
111111
Description
Data for static memory access
Direction (I/O)
I
Default
0
Description
0: Calibration DAC full-scale uses AVDD
1: Calibration DAC full-scale uses AVDD/2
Table 22. TRIM—Register 0x14
Bit Name
CALDACFS
Bit
4
Rev. 0 | Page 33 of 52
AD9704/AD9705/AD9706/AD9707
REFERENCE OPERATION
The AD970x contains an internal 1.0 V band gap reference.
The internal reference can be disabled by writing a Logic 1 to
Register 0x00, Bit 0 (EXREF) in the SPI.
To use the internal reference, decouple the REFIO pin to ACOM
with a 0.1 μF capacitor, enable the internal reference, and write
a Logic 0 to Register 0x00, Bit 0 in the SPI. (Note that this is the
default configuration.) The internal reference voltage is present
at REFIO. If the voltage at REFIO is to be used anywhere else in
the circuit, an external buffer amplifier with an input bias
current of less than 100 nA should be used. An example of the
use of the internal reference is shown in Figure 79.
VBG
1.0V
REFIO
RSET
AVSS
DAC
CURRENT
SCALING
x32
IOUTFS
05926-094
+
IREF
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz. This allows the device to be used for
low frequency, small signal multiplying applications.
DAC TRANSFER FUNCTION
The AD970x provides complementary current outputs, IOUTA
and IOUTB. IOUTA provides a near full-scale current output,
IOUTFS, when all bits are high (that is, DAC CODE = 2N − 1,
where N = 8, 10, 12, or 14 for the AD9704, AD9705, AD9706,
and AD9707, respectively); while IOUTB, the complementary
output, provides no current. The current output appearing at
IOUTA and IOUTB is a function of both the input code and IOUTFS
and can be expressed as
–
FSADJ
0.1µF
AD9704/AD9705/
AD9706/AD9707
The control amplifier allows a 5:1 adjustment span of IOUTFS
from 1 mA to 5 mA by setting IREF between 31.25 μA and
156.25 μA (RSET between 6.4 kΩ and 32 kΩ). The wide adjustment
span of IOUTFS provides several benefits. The first relates directly
to the power dissipation of the AD970x, which is proportional
to IOUTFS (see the Power Dissipation section). The second benefit
relates to the ability to adjust the output over a 14 dB range, which
is useful for controlling the transmitted power.
IOUTA = (DAC CODE/2N) × IOUTFS
(1)
IOUTB = ((2N − 1) − DAC CODE)/2N × IOUTFS
(2)
Figure 79. Internal Reference Configuration
REFIO serves as either an input or an output, depending on
whether the internal or an external reference is used. Table 23
summarizes the reference operation.
Table 23. Reference Operation
Reference
Mode
Internal
REFIO Pin
Connect 0.1 μF capacitor
External
Apply external reference
Register Setting
Register 0x00, Bit 0 = 0
(default)
Register 0x00, Bit 0 = 1
(for power saving)
An external reference can be used in applications requiring
tighter gain tolerances or lower temperature drift. Also, a variable
external voltage reference can be used to implement a method
for gain control of the DAC output. The external reference is
applied to the REFIO pin. Note that the 0.1 μF compensation
capacitor is not required. The internal reference can be directly
overdriven by the external reference, or the internal reference
can be powered down. The input impedance of REFIO is 10 kΩ
when powered up and 1 MΩ when powered down.
REFERENCE CONTROL AMPLIFIER
The AD970x contains a control amplifier that regulates the fullscale output current, IOUTFS. The control amplifier is configured
as a V-I converter, as shown in Figure 79. The output current,
IREF, is determined by the ratio of the VREFIO and an external
resistor, RSET, as stated in Equation 4. IREF is mirrored to the
segmented current sources with the proper scale factor to set
IOUTFS, as stated in Equation 3.
where DAC CODE = 0 to 2N − 1 (that is, decimal representation).
IOUTFS is a function of the reference current, IREF, which is
nominally set by a reference voltage, VREFIO, and an external
resistor, RSET. It can be expressed as
IOUTFS = 32 × IREF
(3)
where
IREF = VREFIO/RSET
(4)
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and
IOUTB should be connected to matching resistive loads, RLOAD,
that are tied to analog common, ACOM. The single-ended
voltage output appearing at the IOUTA and IOUTB nodes is
VIOUTA = IOUTA × RLOAD
(5)
VIOUTB = IOUTB × RLOAD
(6)
Note: To achieve the maximum output compliance of 1 V at the
nominal 2 mA output current, RLOAD must be set to 500 Ω.
Rev. 0 | Page 34 of 52
AD9704/AD9705/AD9706/AD9707
Also note that the full-scale value of VIOUTA and VIOUTB should
not exceed the specified output compliance range to maintain
specified distortion and linearity performance.
VDIFF = (IOUTA – IOUTB) × RLOAD
(7)
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be
expressed as
N
N
VDIFF = {(2 × DAC CODE – (2 − 1))/2 } ×
(32 × VREFIO/RSET) × RLOAD
(8)
Equation 7 and Equation 8 highlight some of the advantages of
operating the AD970x differentially. First, the differential operation
helps cancel common-mode error sources associated with IOUTA
and IOUTB, such as noise, distortion, and dc offsets. Second,
the differential code dependent current and subsequent voltage,
VDIFF, is twice the value of the single-ended voltage output
(that is, VIOUTA or VIOUTB), thus providing twice the signal power
to the load.
Note that the gain drift temperature performance for a singleended output (VIOUTA and VIOUTB) or differential output (VDIFF)
of the AD970x can be enhanced by selecting temperature
tracking resistors for RLOAD and RSET, because of their ratiometric
relationship, as shown in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA, and
IOUTB can be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VIOUTA and VIOUTB, via a load
resistor, RLOAD, as described in the DAC Transfer Function
section by Equation 5 through Equation 8. The differential
voltage, VDIFF, existing between VIOUTA and VIOUTB, can also be
converted to a single-ended voltage via a transformer or a
differential amplifier configuration. The ac performance of the
AD970x is optimum and is specified using a differential
transformer-coupled output in which the voltage swing at
IOUTA and IOUTB is limited to ±0.5 V.
The distortion and noise performance of the AD970x can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed waveform
increases and/or its amplitude increases. This is due to the first
order cancellation of various dynamic common-mode distortion
mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Because the output currents of IOUTA and
IOUTB are complementary, they become additive when
processed differentially.
When the AD970x is being used at its nominal operating point
of 2 mA output current, and 0.5 V output swing is desired,
RLOAD must be set to 250 Ω. A properly selected transformer
allows the AD970x to provide the required power and voltage
levels to different loads.
The output impedance of IOUTA and IOUTB is determined by
the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 200 MΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, VIOUTA and VIOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration results in the
optimum dc linearity. Note that the INL/DNL specifications for
the AD970x are measured with IOUTA maintained at a virtual
ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The absolute maximum negative output
compliance range of −1 V is set by the breakdown limits of the
CMOS process. Operation beyond this maximum limit can result
in a breakdown of the output stage and affect the reliability of
the AD970x.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.0 V for an IOUTFS = 2 mA to 0.8 V for an IOUTFS = 1 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
ADJUSTABLE OUTPUT COMMON MODE
The AD970x provides the ability to set the output common
mode to a value other than ACOM via Pin 19 (OTCM). This
extends the compliance range of the outputs and facilitates
interfacing the output of the AD970x to components that
require common-mode levels other than 0 V. The OTCM pin
demands dynamically changing current and should be driven
by a low source impedance to prevent a common-mode signal
from appearing on the DAC outputs. For optimum performance,
set the voltage on OTCM equal to the center of the output
swing on IOUTA and IOUTB.
Rev. 0 | Page 35 of 52
AD9704/AD9705/AD9706/AD9707
(10)
DIGITAL INPUTS
The AD9707, AD9706, AD9705, and AD9704 have data inputs
of 14, 12, 10, and 8 bits, respectively; and each has a clock input.
The parallel data inputs can follow standard positive binary or
twos complement coding. IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a
complementary output with the full-scale current split between
the two outputs as a function of the input code.
DVDD
05926-078
DIGITAL
INPUT
Figure 80. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
175 MSPS. The clock can be operated at any duty cycle that meets
the specified latch pulsewidth. The setup and hold times can
also be varied within the clock cycle, as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
SPI Disabled
CMODE Pin
CLKCOM
CLKVDD
SPI Enabled
Register 0x02, Bit 2
0
1
Clock Input Mode
Single-ended
Differential
In differential input mode, the clock input functions as a high
impedance differential pair. The common-mode level of the
CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and the
differential voltage can be as low as 0.5 V p-p. This mode can be
used to drive the clock with a differential sine wave because the
high gain bandwidth of the differential inputs converts the sine
wave into a single-ended square wave internally.
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the time at
which the input data changes. The AD970x is rising-edge
triggered and so exhibits dynamic performance sensitivity when
the data transition is close to this edge. In general, the goal
when applying the AD970x is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 81 shows the relationship of SFDR
to clock placement with different sample rates.
95
90
85
80MSPS
80
75
125MSPS
70
65
60
55
CLOCK INPUT
A configurable clock input allows the device to be operated in
a single-ended or a differential clock mode. The mode selection
can be controlled either by the CMODE pin, if the device is in pin
mode; or through SPI Register 0x02, Bit 2 (CLKDIFF), if the SPI
is enabled. Connecting CMODE to CLKCOM selects the singleended clock input. In this mode, the CLK+ input is driven with
rail-to-rail swings, and the CLK− input is left floating. If CMODE
is connected to CLKVDD, the differential receiver mode is selected.
In this mode, both inputs are high impedance. Table 24 gives a
summary of clock mode control. There is no significant performance difference between the clock input modes.
50
45
–4
–3
–2
–1
0
1
DATA EDGE WITH RESPECT TO RISING CLOCK EDGE (ns)
Figure 81. SFDR vs. Clock Placement
POWER DISSIPATION
The power dissipation, PD, of the AD970x is dependent on
several factors that include
•
•
•
•
Rev. 0 | Page 36 of 52
The power supply voltages (AVDD, CLKVDD, and
DVDD)
The full-scale current output, IOUTFS
The update rate, fCLOCK
The reconstructed digital input waveform
05926-079
AVDD − VOTCM > 1.8 V
Table 24. Clock Mode Selection
SFDR (dBc)
Note that setting OTCM to a voltage greater than ACOM allows
the peak of the output signal to be closer to the positive supply
rail. To prevent distortion in the output signal due to limited
available headroom, the common-mode level must be chosen
such that the following expression is satisfied:
AD9704/AD9705/AD9706/AD9707
10
Power dissipation is directly proportional to the analog supply
current, IAVDD, and the digital supply current, IDVDD. IAVDD is equal
to a fixed current plus IOUTFS, as shown in Figure 82. IDVDD is
proportional to fCLOCK and increases with increasing analog
output frequencies. Figure 84 shows IDVDD as a function of fullscale sine wave output ratios (fOUT/fCLOCK) for various update rates
with DVDD = 3.3 V. ICLKVDD is directly proportional to fCLOCK
and is higher for differential clock operation than for singleended operation, as shown in Figure 86. This difference in clock
current is due primarily to the differential clock receiver, which is
disabled in single-ended clock mode.
9
175MSPS
8
IDVDD (mA)
7
6
125MSPS
5
4
75MSPS
3
25MSPS
2
10MSPS
0
0.01
9
0.1
1
fOUT/fCLOCK
8
Figure 84. IDVDD vs. fOUT/fCLOCK Ratio @ DVDD = 3.3 V
7
2.5
6
IAVDD (mA)
1
05926-081
10
05926-098
1
5
2.0
4
80MSPS
IDVDD (mA)
3
2
0
1
2
3
4
5
IOUTFS (mA)
50MSPS
1.0
05926-080
1
1.5
25MSPS
0.5
Figure 82. IAVDD vs. IOUTFS @ AVDD = 3.3 V
10MSPS
6
0
0.01
0.1
fOUT/fCLOCK
5
Figure 85. IDVDD vs. fOUT/fCLOCK Ratio @ DVDD = 1.8 V
5
3
4
2
0
1.00
1.25
1.50
1.75
IOUTFS (mA)
2.00
3
SE
2
1
Figure 83. IAVDD vs. IOUTFS @ AVDD = 1.8 V
0
0
50
100
150
fCLOCK (MSPS)
Figure 86. ICLKVDD vs. fCLOCK @ CLKVDD = 3.3 V
Rev. 0 | Page 37 of 52
200
05926-082
1
ICLKVDD (mA)
DIFF
05926-102
IAVDD (mA)
4
AD9704/AD9705/AD9706/AD9707
1.4
SELF-CALIBRATION
1.2
The AD970x has a self-calibration feature that improves the
DNL of the device. Performing a self-calibration on the device
improves device performance in low frequency applications.
The device performance in applications where the analog
output frequencies are above 1 MHz are generally influenced
more by dynamic device behavior than by DNL, and in these
cases, self-calibration is unlikely to provide any benefits for
single-tones, as shown in Figure 88. Figure 89 shows that selfcalibration is helpful up to 20 MHz for two-tone IMD spaced
10 kHz apart.
ICLKVDD (mA)
1.0
0.8
0.6
0.4
0
0
10
20
30
40
50
60
70
80
fCLOCK (MSPS)
90
05926-099
0.2
88
Figure 87. ICLKVDD vs. fCLOCK (Differential Clock Mode) @ CLKVDD = 1.8 V
CALIBRATED
86
84
82
The AD970x takes less than 50 ns to power down and approximately 5 μs to power back up.
80
Sleep and Power-Down Operation (SPI Mode)
78
UNCALIBRATED
The AD970x offers three power-down functions that can be
controlled through the SPI. These power-down modes can be
used to minimize the power dissipation of the device. The
power-down functions are controlled through SPI Register 0x00,
Bit 1 to Bit 3. Table 25 summarizes the power-down functions
that can be controlled through the SPI. The power-down mode
can be enabled by writing a Logic 1 to the corresponding bit in
Register 0x00.
(Reg. 0x00)
Bit #
1
2
3
Functional Description
Turn off clock
Turn off output current
Turn off output current and
internal voltage reference
0.4
0.6
0.8
Figure 88. AD9707 SFDR vs. fOUT @ 175 MSPS and IOUTFS = 2 mA
88
87
CALIBRATED
86
85
84
UNCALIBRATED
83
82
81
80
05926-097
Power-Down
Mode
Clock Off
Sleep
Power Down
0.2
fOUT (MHz)
IMD (dBc)
Table 25. Power-Down Mode Selection
0
05926-096
The AD970x has a sleep mode that turns off the output current
and reduces the total power consumed by the device. This mode
is activated by applying a Logic 1 to the SLEEP/CSB pin. The
SLEEP/CSB pin logic threshold is equal to 0.5 × AVDD. This
digital input also contains an active pull-down circuit.
SFDR (dBc)
Sleep and Power-Down Operation (Pin Mode)
79
78
0
5
10
15
LOWER fOUT (MHz)
Figure 89. IMD vs. fOUT @ 175 MSPS and IOUTFS = 2 mA
Rev. 0 | Page 38 of 52
20
AD9704/AD9705/AD9706/AD9707
To perform a device self-calibration, the following procedure
can be used.
The calibration clock frequency is equal to the DAC clock
divided by the division factor chosen by the DIVSEL value. The
frequency of the calibration clock must be set to under 10 MHz
for reliable calibrations. Best results are obtained by setting
DIVSEL[2:0] (Register 0x0E, Bit 2 to Bit 0) to produce the
lowest frequency calibration clock frequency that your system
requirements allow.
1.
Enable the calibration clock by setting the CALCLK bit
(Register 0x02, Bit 0).
2.
Enable self-calibration by writing 0x40 to Register 0x0F.
3.
Wait approximately 4500 calibration clock cycles. Each
calibration clock cycle is between 2 and 256 DAC clock
cycles, depending on the value of DIVSEL[2:0].
4.
Check if the self-calibration has completed by reading the
CALSTAT bit (Register 0x0F, Bit 7). A Logic 1 indicates the
calibration has completed.
5.
When the self-calibration has completed, write 0x00 to
Register 0x0F.
6.
Disable the calibration clock by clearing the CALCLK Bit
(Register 0x02, Bit 0).
The AD970x devices allow reading and writing of the calibration
coefficients. There are 33 coefficients in total. The read/write
feature of the coefficients could be useful for improving the results
of the self-calibration routine by averaging the results of several
calibration results and loading the averaged results back into the
device. The reading and writing routines follow.
To read the calibration coefficients
1.
Enable the calibration clock by setting the CALCLK bit
(Register 0x02, Bit 0).
2.
Write the address of the first coefficient (0x00) to
Register 0x10.
3.
Set the SMEMRD bit (Register 0x0F, Bit 2) by writing 0x04
to Register 0x0F.
4.
Read the value of the first coefficient by reading the
contents of Register 0x11.
5.
Clear the SMEMRD bit by writing 0x00 to Register 0x0F.
6.
Repeat Step 2 through Step 5 for each of the remaining 32
coefficients by incrementing the address by one each read.
7.
Disable the calibration clock by clearing the CALCLK Bit
(Register 0x02, Bit 0).
To write the calibration coefficients to the device:
1.
Enable the calibration clock by setting the CALCLK bit
(Register 0x02, Bit 0).
2.
Set the SMEMWR bit (Register 0x0F, Bit 3) by writing 0x08
to Register 0x0F.
3.
Write the address of the first coefficient (0x00) to
Register 0x10.
4.
Write the value of the first coefficient to Register 0x11.
5.
Repeat Step 2 and Step 3 for each of the remaining 32
coefficients by incrementing the address by one each write.
6.
Clear the SMEMWR bit by writing 0x00 to Register 0x0F.
7.
Disable the calibration clock by clearing the CALCLK bit
(Register 0x02, Bit 0).
Rev. 0 | Page 39 of 52
AD9704/AD9705/AD9706/AD9707
APPLICATIONS
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configurations for the AD970x. Unless otherwise noted, it is assumed that
IOUTFS is set to a nominal 2 mA. For applications requiring the
optimum dynamic performance, a differential output configuration
is suggested. A differential output configuration can consist of
either an RF transformer or a differential op amp configuration.
The transformer configuration provides the optimum high
frequency performance and is recommended for any application
that allows ac coupling. The differential op amp configuration is
suitable for applications requiring dc coupling, signal gain,
and/or a low output impedance.
A single-ended output is suitable for applications where low
cost and low power consumption are primary concerns.
A differential resistor, RDIFF, can be inserted in applications where
the output of the transformer is connected to the load, RLOAD, via
a passive reconstruction filter or cable. RDIFF, as reflected by the
transformer, is chosen to provide a source termination that
results in a low VSWR. Note that approximately half the signal
power is dissipated across RDIFF.
SINGLE-ENDED BUFFERED OUTPUT
USING AN OP AMP
An op amp can be used to perform a single-ended currentu AD970x is
to-voltage conversion, as shown in Figure 91.. The
configured with a pair of series resistors, RS, off each output.
The feedback resistor, RFB, determines the peak single-ended
output voltage by the formula
VOUT = RFB ×
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 90. The
distortion performance of a transformer typically exceeds that
available from standard op amps, particularly at higher frequencies.
Transformer coupling provides excellent rejection of commonmode distortion (that is, even-order harmonics) over a wide
frequency range. It also provides electrical isolation and can
deliver voltage gain without adding noise. Transformers with
different impedance ratios can also be used for impedance
matching purposes. The main disadvantages of transformer
coupling are the low frequency roll-off, lack of power gain, and
the higher output impedance.
I FS
2
The common-mode voltage of the output is determined by the
formula
VCM = VREF × (1 +
RFB
) − V OUT
RB
The maximum and minimum voltages out of the amplifier are
VMAX = VREF × (1 +
RFB
)
RB
VMIN = VMAX − I FS × RFB
respectively.
CF
IOUTB 22
AD9704/AD9705
AD9706/AD9707
RB
IOUTA 21
OPTIONAL RDIFF
05926-095
RLOAD
AD9704/AD9705
AD9706/AD9707
Rev. 0 | Page 40 of 52
+5V
RS
IOUTA 21
ADA4841
VOUT
REFIO 23
Figure 90. Differential Output Using a Transformer
IOUTB 20
RS
C
OTCM 19
05926-100
The center tap on the primary side of the transformer must be
connected to a voltage that keeps the voltages on IOUTA and
IOUTB within the output common voltage range of the device.
It should be noted that the dc component of the DAC output
current is equal to IFS/2 and flows out of both IOUTA and
IOUTB. The center tap of the transformer should provide a
path for this dc current. In many applications, AGND provides
the most convenient voltage for the transformer center tap. The
complementary voltages appearing at IOUTA and IOUTB (that
is, VIOUTA and VIOUTB) swing symmetrically around AGND and
should be maintained with the specified output compliance
range of the AD970x.
RFB
Figure 91. Single-Supply Single-Ended Buffer
AD9704/AD9705/AD9706/AD9707
CF
DIFFERENTIAL BUFFERED OUTPUT
USING AN OP AMP
RB
A dual op amp (see the circuit shown in Figure 92) can be used
in a differential version of the single-ended buffer shown in
Figure 91. The same R-C network is used to form a 1-pole
differential, low-pass filter to isolate the op amp inputs from the
high frequency images produced by the DAC outputs. The feedback resistors, RFB, determine the peak differential output
voltage by the formula
AD9704/AD9705
AD9706/AD9707
RFB
RS
IOUTA 21
ADA4841
REFIO 23
VOUT
C
OTCM 19
IOUTB 20
RS
ADA4841
VOUT = RFB × I FS
VMAX
R
= VREF × (1 + FB )
RB
RFB
Figure 92. Single-Supply Differential Buffer
V MIN = V MAX − VOUT
respectively. The common-mode voltage of the output is
determined by the formula
VCM = V MAX −
RB
V OUT
2
Rev. 0 | Page 41 of 52
05926-101
CF
The maximum and minimum voltages out of the amplifier are
AD9704/AD9705/AD9706/AD9707
EVALUATION BOARD
GENERAL DESCRIPTION
The TxDAC family evaluation boards allow for easy setup and
testing of any TxDAC products. Careful attention to layout and
circuit design, combined with a prototyping area, allows the user
to evaluate the AD970x easily and effectively in any application
where a low power, high resolution, high speed conversion is
required.
The AD970x board allows the user the flexibility to operate the
part in various configurations. Possible output configurations
include transformer coupled, resistor terminated, and single and
differential outputs. The digital inputs are designed to be driven
from various data pattern generators, with the on-board option
to add a resistor network for proper load termination. Provisions
are also made to operate the AD970x with either the internal or
external reference, or to exercise the power-down feature.
Rev. 0 | Page 42 of 52
Figure 93. Digital Inputs
Rev. 0 | Page 43 of 52
2
J1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
JP3
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
RIBBON R A
2
JP31
R20
R16
DNP
R28
R15
TP15
BLK
RC0805
TP7
BLK
R4
RC0805
DNP
R25
R26
R27
DNP
RC0805
DNP
RC0805
DNP
RC0805
DNP
RC0805
DNP
RC0805
DNP
RC0805
R21
R24
DNP
RC0805
R17
DNP
RC0805
RC0805
RC0805
DNP
2
TP10
BLK
2
TP11
BLK
CKEXTX
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
R8
R7
R6
R5
R4
R3
R2
R1
RP6
DNP
2
RP2
DNP
1
2
3
4
5
6
7
8
9
10
JP28
CKEXTX
DB0X
DB1X
DB2X
DB3X
DB4X
DB5X
DB6X
DB7X
DB8X
DB9X
DB10X
R18
R19
RC0805
DNP
2
12
22
11
10
9
5
6
7
8
14
22
13
4
22
15
2
3
16
1
9
7
22
22
10
6
8
12
22
11
5
14
22
13
4
2
3
16
22
15
1
R8
R7
R6
R5
R4
R3
R2
R1
RP5
DNP
RP1
DNP
1
2
3
4
5
6
7
8
9
10
HDR040RA
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DB11X
DB12X
R3
RC0805
R9
1
2
3
4
5
6
7
8
9
10
DNP
R9
1
2
3
4
5
6
7
8
9
10
DNP
CKEXT
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
05926-051
DB13X
AD9704/AD9705/AD9706/AD9707
EVALUATION BOARD SCHEMATICS
R1
R2
R3
R4
R5
R6
R7
R8
R9
RCOM
R1
R2
R3
R4
R5
R6
R7
R8
R9
Figure 94. Output Signal Conditioning
CMODE-SCLK
C
.1UF
CC0603
C24
DVDD
CVDD
CLK
CLKB
DB5
DB4
DB3
DB2
DB1
DB0
MODE-SDIO
.01UF
CC0603
C23
DB7
DB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD9707LCFSP
DB7
DB8
DB6
DB9
DVDD
DB10
DB5
DB11
DB4
DB12
DB3
DB13
DB2
DCOM1
DB1
SLEEP
FSADJ
DB0
DCOM
REFIO
U1
CVDD
ACOM
DNP
CLK
IA
CLKB
IB
OTCM
CCOM
CMODE/SCLK AVDD
MODE/SDIO RES/SPI
C
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4
3
SW1
JP11
10K
AGND;5
AVDD
OTCM
DB8
DB9
DB10
DB11
DB12
DB13
SLEEP-CSB
R7 RC0603
C25
.01UF
CC0603
C28
2
1
AVDD
RC0603
16K
0.1%
R49
R14
DNP
0
6.4K
0.1%
R51
C22
.1UF
CC0603
R56
R57
453
RC0603
0 RC0603
R55
RC0805
RC0805
RC0805
RC0603
FSADJ resistors must have low TC
32K
0.1%
R1
R13
DNP
WHT
WHT
C11
.1UF
CC0603
TP1
TP3
RC0603
.1UF
CC0603
C27
JP7
ERA6YEB323V,ERA6Y
Rev. 0 | Page 44 of 52
ERA6YEB323V,ERA6Y JP8
.01UF
CC0603
ERA6YEB323V,ERA6Y JP9
.1UF
CC0603
C26
3
1
4
5
T2
DNI
S
6
1
2
3
R22
0
4
ADTL1-12
PNC=2,5S
P
T2B
OTCM
1
2
3
NC=5
T1
JP25
ADT9-1T
S
JP24
P
6
4
R11
R9
DNP
OUT
RC0603
0
RC0603
CVDD
S3
AGND;3,4,5
05926-052
AVDD
AD9704/AD9705/AD9706/AD9707
RC0603
CLK
CLKB
C
Figure 95. Clock
Rev. 0 | Page 45 of 52
C29
R33
.1UF
R35
49.9
10K
RC0603
CC0603
RC0603
10K
6 S
5
4
2
P 1
3
C
CVDD
Signal ended sine clock input
ADT1-1WT
R34
.1UF
3
T3
Transformer Clock Input
C34
1
JP23
B A
2
Single-ended CMOS Clock Input
JP20
A B
2
1
JP2
JP21
RC0603
JP30
A B
2
3
1
3
R6
DNP
C
S5
CLK-IN
SMA50SMTUP
05926-053
CKEXT
AD9704/AD9705/AD9706/AD9707
JP16
RC0603
CC0603
Rev. 0 | Page 46 of 52
P1
1
2
3
4
5
6
TJAK06RAP
FCI-68898
DVDD
C33
C32
LC1812
L9 EXC-CL4532U1
RC0603
RC0603
RC0603
AVDD
.01UF
CC0603
.1UF
CSB R4,5K 3
SCLK R4,5K 4
SDI R4,5K 5
SDO
CC0603
DVDD2_OUT
DVDD2
R46
7.5K
JP1
JP13
JP27
RC0603
JP4
JP14
RC0603
Figure 96. SPI
JP5
R47
7.5K
R48
7.5K
U5
5
6
U5
DGND;7
DVDD2;14
8
R41
R40
R39
10
74VCX86MTC
9
DGND;7
DVDD2;14
U5
3
DGND;7
DVDD2;14
74VCX86MTC
4
2
11
DGND;7
DVDD2;14
U5
74VCX86MTC
1
13
74VCX86MTC
12
10K
RC0603
1K
RC0603
TP18
WHT
1K
RC0603
TP19
SDI
WHT
TP20
SDO
WHT
MODE-SDIO
CMODE-SCLK
SLEEP-CSB
05926-054
AVDD
AD9704/AD9705/AD9706/AD9707
RC0603
Rev. 0 | Page 47 of 52
DVDD2_IN
5V
.1UF
JP18
C15
JP19
LC1812
C
EXC-CL4532U1
L8
ACASE
ACASE
EXC-CL4532U1
LC1812
LC1812
L4
JP17
.1UF BLK
TP9
CC0603
RED
TP8
ACASE
EXC-CL4532U1
LC1812
L3
LC1812
L6
.1UF BLK
CC0603
TP6 EXC-CL4532U1
C9
L7
RED
TP5
C7
BLK
TP4 EXC-CL4532U1
LC1812
L2
ACASE
EXC-CL4532U1
LC1812
L5
BLK
TP2 EXC-CL4532U1
RED
TP13
C3
CC0603
5V
5V
AVDD_IN
DVDD_IN
5V
.1UF
CC0603
C1
10UF
6.3V
C5
10UF
6.3V
C4
10UF
6.3V
C2
10UF
6.3V
.1UF
.1UF
C16
CC0603
.1UF
C8
CC0603
.1UF
C6
CC0603
C
C10
CC0603
C
BLK
TP14
DVDD2_OUT
AVDD
DVDD
CVDD
J3
5V
2
SMAEDGE
1
5VGND;3,4,5
P2
1
C12
5V
1UF
CC0603
C37
5V
1UF
CC0603
C21
5V
1UF
CC0603
C18
5V
1UF
CC0603
5V
P2
2
5V
5V
5V
5V
1
2
3
4
1
2
3
4
RC0603
GND
ADP3334
NC
FB
OUT6
SD
IN3
U7
RC0603
8
7
6
5
8
7
6
5
R10
R5
R29
NC
OUT5
5V
78.7K
ADP3334
IN4
GND
FB
OUT6
SD
IN3
U6
5V
78.7K
NC
FB
OUT6
ADP3334
U4
OUT5
RC0603
OUT5
GND
SD
IN3
5V
78.7K
NC
FB
OUT6
ADP3334
U2
OUT5
IN4
1
2
3
4
GND
SD
IN3
IN4
1
2
3
4
IN4
DIGIKEY PART NUMBERS:277-1011-ND,277-1095-ND
8
7
6
5
8
7
6
5
C38
1
C30
1
C19
1
C13
CC0603
CC0603
100PF
2
A B 3
JP29
100PF
2
A B 3
JP26
100PF
2
A B 3
JP22
100PF
RC0603
EXC-CL4532U1
RC0603
LC1812
CC0603
CC0603
Figure 97. Power Supplies
RC0603
CVDD_IN
R32
R36
115K
R30
R31
76.8K
R12
R23
76.8K
C20
RC0603
64.9K
5V
1UF
RC0603
88.7K
5V
1UF
CC0603
C31
RC0603
64.9K
5V
5V
JP15
JP12
1UF
CC0603
C17
RC0603
JP10
1UF
5V
64.9K
CC0603
R8
R2
76.8K
C14
CC0603
JP6
5V
2
SMAEDGE
1
CVDD_IN
J5 AVDD_IN
J4 DVDD_IN
J2
DVDD2_IN
5V
2
SMAEDGE
5VGND;3,4,5
1
5VGND;3,4,5
5V
5VGND;3,4,5
05926-077
RED
TP12L1
AD9704/AD9705/AD9706/AD9707
RC0603
AD9704/AD9705/AD9706/AD9707
05926-055
EVALUATION BOARD LAYOUT
05926-056
Figure 98. Assembly—Primary Side
Figure 99. Assembly—Secondary Side
Rev. 0 | Page 48 of 52
05926-057
AD9704/AD9705/AD9706/AD9707
05926-058
Figure 100. Layer 1—Primary Side
Figure 101. Layer 4—Secondary Side
Rev. 0 | Page 49 of 52
05926-059
AD9704/AD9705/AD9706/AD9707
05926-060
Figure 102. Layer 2—Ground Plane
Figure 103. Layer 3—Power Plane
Rev. 0 | Page 50 of 52
AD9704/AD9705/AD9706/AD9707
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
32
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
17
16
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 104. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9704BCPZ 1
AD9704BCPZRL71
AD9705BCPZ1
AD9705BCPZRL71
AD9706BCPZ1
AD9706BCPZRL71
AD9707BCPZ1
AD9707BCPZRL71
AD9704-EB
AD9705-EB
AD9706-EB
AD9707-EB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 51 of 52
Package Option
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
AD9704/AD9705/AD9706/AD9707
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05926-0-7/06(0)
Rev. 0 | Page 52 of 52