Oscillator SMD, programmable APQO 5032 Features: - Small size 5x3.2 - Low cost to performance - 3.0 ~ 5.5 volt available - Tolerance and stability to ±25ppm - Ultra low jitter <11ps - Tristate or power down available Specifications APQO 5032 1MHz ~ 133MHz ±25ppm ~ ±100ppm 0°C ~ +70°C - -40°C ~ +85°C -55°C ~ +125°C 4.5V ~ 5.5V 3.0V ~ 3.6V ±5ppm CMOS / TTL Frequency range Frequency stability Operating temperature Storage temperature Programmable voltage 1 ~ 133 MHz Programmable voltage 1 ~ 100 MHz Aging (ppm / Year), Ta = 25C, Vdd = 5 / 3.3 V Programmable output level Remarks Please specify Please specify Please specify Operating conditions Description Vdd CTTL CCMOS Supply voltage Max capacitive load on outputs for TTL levels 4.5 V ~ 5.5 V Vdd £ 40 MHz 4.5 V ~ 5.5 V Vdd > 40 ~ 133 MHz Max capacitive load on outputs for CMOS levels 4.5 V ~ 5.5 V Vdd £ 66 MHz 4.5 V ~ 5.5 V Vdd > 66 ~ 133 MHz 3.0 V ~ 3.6 V Vdd £ 40 MHz 3.0 V ~ 3.6 V Vdd > 40 ~ 100 MHz Min Max Unit 3.0 5.5 V 50 25 pF pF 50 25 30 15 pF pF pF pF Drawing APQO 5032 Dimensions in mm Order key O - 10.000000M - APQO 5032 - 50 - 5.0 -A / T / Part Frequency Type/Package Tolerance Voltage Temperature Option Packaging O=Oscillator M=MHz APQO= programmable QO ±ppm 5.0=5.0Volt A= T= Tristate blank = tube 3.3=3.3Volt B= -10°C ~ +60°C 5032=SMD 5x3.2 0°C ~ +70°C C= -10°C ~ +70°C D= -20°C ~ +70°C E= -40°C ~ +85°C auris-GmbH [email protected] www.auris-gmbh.de All specifications are subject to change without notice. 4.7 P = Power down Oscillator SMD, programmable APQO 5032 Electrical characteristics Discription Test conditions Input characteristics (Pin 1) VIL, Low-level input voltage 4.5 ~ 5.5 V Vdd 3.0 ~ 3.6 V Vdd 4.5 ~ 5.5 V Vdd 3.0 ~ 3.6 V Vdd VIN = 0V VIN = Vdd TO Tri-state or power-down VIH, High-level input voltage TO Enable output or no connect IIL, Input low current IIH, Input high current Output characteristics VOL, Low-level output voltage VOHTTL, High-level output voltage TTL VOHCMOS High-level CMOS voltage Power supply current (unloaded) Standby current Input pull-up resistor (PIN 1) Tri-state leakage current Output enable mode Power down mode 4.5 V ~ 5.5 V Vdd, 16 mA IOL 3.0 V ~ 3.6 V Vdd, 8 mA IOL 4.5 V ~ 5.5 V Vdd, -16 mA IOL 4.5 ~ 5.5 Vdd, -16 mA IOL 3.0 V ~ 3.6 V Vdd, -8 mA IOL 4.5 ~ 5.5 Vdd, OUTPUT FREQ £ 133 MHz 3.0 ~ 3.6 Vdd, OUTPUT FREQ £ 100 MHz Min Typ Max Unit 0.8 0.2 Vdd V V V V µA µA 2.0 0.7 Vdd 10 5 0.4 0.4 2.4 Vdd - 0.4 Vdd - 0.4 4.5 ~ 5.5 Vdd, VIN = 0V 4.5 ~ 5.5 Vdd, VIN = 0.7 V 5.0 Vdd Output is tri-stated Output is tri-stated 1.1 50 10 3.0 100 20 Test conditions Min Typ £ 50 MHz, CL = 50 pF 50 ~ 66 MHz, CL = 15 pF 66 ~ 125 MHz, CL = 25 pF 125 ~ 133 MHz, CL = 15 pF 45 25 50 8.0 200 V V V V V mA mA µA M¸ K¨ µA Output clock switching characteristics Description Duty cycle TTL @ 1.4 V 4.5 ~ 5.5 Vdd Duty cycle: CMOS @ Vdd / 2 4.5 ~ 5.5 Vdd 3.0 ~ 3.6 Vdd Output clock rise / fall Start up time Power down delay time Synchronous Asynchronous Output disable time Synchronous Asynchronous Output enable time Period Jitter: ° Peak to peak Max Unit 45 45 40 40 55 55 60 60 % % % % 45 40 40 45 40 55 60 60 55 60 1.8 1.2 0.9 3.4 4.0 2.4 2 % % % % % ns ns ns ns ns ns ms T/2 10 T+10 15 ns ns OE pin LOW to output Hi-Z T = Frequency oscillator period T/2 10 1 - 133MHz £ 33.000 MHz > 33.000 MHz 8 65 65 T+10 15 100 11 99 80 ns ns ns ps ps ps £ 66 MHz, CL £ 25 pF 66 ~ 125 MHz, CL £ 25 pF 125 ~ 133 MHz, CL £ 15 pF £ 40 MHz, CL £ 30 pF 40 ~ 100 MHz, CL £ 15 pF 0.8 V ~ 2.0 V, 4.5 ~ 5.5 Vdd, CL = 50 0.8 V ~ 2.0 V, 4.5 ~ 5.5 Vdd, CL = 25 0.8 V ~ 2.0 V, 4.5 ~ 5.5 Vdd, CL = 15 0.2 ~ 0.8 Vdd, 4.5 ~ 5.5 Vdd, CL = 50 0.2 ~ 0.8 Vdd, 3.0 ~ 3.6 Vdd, CL = 30 0.2 ~ 0.8 Vdd, 3.0 ~ 3.6 Vdd, CL = 15 From power on PWR_DWN pin LOW to output Hi-Z auris-GmbH [email protected] www.auris-gmbh.de All specifications are subject to change without notice. 4.8