HN29WT800 Series HN29WB800 Series 1048576-word × 8-bit / 524288-word × 16-bit CMOS Flash Memory ADE-203-537A(Z) Rev. 1.0 May. 9, 1997 Description The Hitachi HN29WT800 Series, HN29WB800 Series are 1-Mword × 8-bit/512-kword × 16-bit CMOS Flash Memory with DINOR (DIvided bitline NOR) type memory cells, that realize programming and erase capabilities with a single 3.3 V power supply. The built-in Sequence Controller allows Automatic Program/Erase without complex external control. HN29WT800 Series, HN29WB800 Series enable the low power and high performance systems such as mobile, personal computing and communication products. Features • On-board single power supply (VCC): VCC = 3.3 V ± 0.3 V • Access time: 80/100/120 ns (max) • Low power dissipation: ICC = 30 mA (max) (Read) ICC = 200 µA (max) (Standby) ICC = 40 mA (max) (Program) ICC = 40 mA (max) (Erase) ICC = 1 µA (typ) (Deep powerdown) • Automatic page programming: Programming time: 25 ms (typ) Program unit: 128 word • Automatic erase: Erase time: 50 ms (typ) Erase unit: Boot block; 8-kword/16-kbyte × 1 Parameter block; 4-kword/8-kbyte × 2 Main block; 16-kword/32-kbyte × 1 32-kword/64-kbyte × 15 This product is compatible with M5M29FB/T800xx by Ltd. Mitsubishi. HN29WT800 Series, HN29WB800 Series • Block boot: HN29WT800 Series: Top boot HN29WB800 Series: Bottom boot • Program/Erase endurance 10,000 cycles • Other functions: Software command control Selective block lock Program suspend/Resume Erase suspend/Resume Status register read • Compatible with M5M29FB/T800xx by Ltd. Mitsubishi Ordering Information Type No. Access time Package HN29WT800T-8 HN29WT800T-10 HN29WT800T-12 80 ns 100 ns 120 ns 12 × 20.0 mm 2 48-pin plastic TSOP I (TFP-48D) HN29WB800T-8 HN29WB800T-10 HN29WB800T-12 80 ns 100 ns 120 ns HN29WT800R-8 HN29WT800R-10 HN29WT800R-12 80 ns 100 ns 120 ns HN29WB800R-8 HN29WB800R-10 HN29WB800R-12 80 ns 100 ns 120 ns 2 12 × 20.0 mm 2 48-pin plastic TSOP I (Reverse) (TFP-48DR) HN29WT800 Series, HN29WB800 Series Pin Arrangement HN29WT800T Series HN29WB800T Series A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RP NC WP RDY/Busy A18 A17 A7 A6 A5 A4 A3 A2 A1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A16 BYTE V SS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE V SS CE A0 (Top view) HN29WT800R Series HN29WB800R Series A16 BYTE V SS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE VSS CE A0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RP NC WP RDY/Busy A18 A17 A7 A6 A5 A4 A3 A2 A1 (Top view) 3 HN29WT800 Series, HN29WB800 Series Pin Description Pin name Function A-1 to A18 Address I/O0 to I/O15 Input/output CE Chip enable OE Output enable WE Write enable RP Reset/Powerdown RDY/Busy Ready/Busy WP Write protect BYTE Byte enable VCC Power supply VSS Ground NC No connection 4 HN29WT800 Series, HN29WB800 Series Block Diagram 128-word page buffer A8 to A18 X-address buffer X-decorder A0 to A7 Y-address buffer Y-decorder Boot block 8-kword Parameter block 1 4-kword Parameter block 2 4-kword Main block 16-kword Main block 32-kword . . Main block 32-kword Y-gate /Sens AMP. Status/ ID register Multiplexer CE OE WE WP RP BYTE CUI WSM Input/output buffers RDY/Busy V CC V SS I/O0 I/O15/A-1 CUI: Command User Interface WSM: Write State Machine 5 HN29WT800 Series, HN29WB800 Series Memory Map HN29WB800 Series Memory Map HN29WT800 Series Memory Map × 8 (Byte mode) × 16 (Word mode) × 8 (Byte mode) × 16 (Word mode) FC000H to FFFFFH 7E000H to 7FFFFH 8-kword boot block F0000H to FFFFFH 78000H to 7FFFFH 32-kword main block FA000H to FBFFFH 7D000H to 7DFFFH 4-kword parameter block E0000H to EFFFFH 70000H to 77FFFH 32-kword main block F8000H to F9FFFH 7C000H to 7CFFFH 4-kword parameter block D0000H to DFFFFH 68000H to 6FFFFH 32-kword main block F0000H to F7FFFH 78000H to 7BFFFH 16-kword main block C0000H to CFFFFH 60000H to 67FFFH 32-kword main block E0000H to EFFFFH 70000H to 77FFFH 32-kword main block B0000H to BFFFFH 58000H to 5FFFFH 32-kword main block D0000H to DFFFFH 68000H to 6FFFFH 32-kword main block A0000H to AFFFFH 50000H to 57FFFH 32-kword main block C0000H to CFFFFH 60000H to 67FFFH 32-kword main block 90000H to 9FFFFH 48000H to 4FFFFH 32-kword main block B0000H to BFFFFH 58000H to 5FFFFH 32-kword main block 80000H to 8FFFFH 40000H to 47FFFH 32-kword main block A0000H to AFFFFH 50000H to 57FFFH 32-kword main block 70000H to 7FFFFH 38000H to 3FFFFH 32-kword main block 90000H to 9FFFFH 48000H to 4FFFFH 32-kword main block 60000H to 6FFFFH 30000H to 37FFFH 32-kword main block 80000H to 8FFFFH 40000H to 47FFFH 32-kword main block 50000H to 5FFFFH 28000H to 2FFFFH 32-kword main block 70000H to 7FFFFH 38000H to 3FFFFH 32-kword main block 40000H to 4FFFFH 20000H to 27FFFH 32-kword main block 60000H to 6FFFFH 30000H to 37FFFH 32-kword main block 30000H to 3FFFFH 18000H to 1FFFFH 32-kword main block 50000H to 5FFFFH 28000H to 2FFFFH 32-kword main block 20000H to 2FFFFH 10000H to 17FFFH 32-kword main block 40000H to 4FFFFH 20000H to 27FFFH 32-kword main block 10000H to 1FFFFH 08000H to 0FFFFH 32-kword main block 30000H to 3FFFFH 18000H to 1FFFFH 32-kword main block 08000H to 0FFFFH 04000H to 07FFFH 16-kword main block 20000H to 2FFFFH 10000H to 17FFFH 32-kword main block 06000H to 07FFFH 03000H to 03FFFH 4-kword parameter block 10000H to 1FFFFH 08000H to 0FFFFH 32-kword main block 04000H to 05FFFH 02000H to 02FFFH 4-kword parameter block 00000H to 0FFFFH 00000H to 07FFFH 32-kword main block 00000H to 03FFFH 00000H to 01FFFH 8-kword boot block A-1 to A18 (Byte mode) A0 to A18 (Word mode) 6 A-1 to A18 (Byte mode) A0 to A18 (Word mode) HN29WT800 Series, HN29WB800 Series Top Boot Block Address Map*1 Address Size Block A18 A17 A16 A15 A14 A13 A12 × 8 (Byte mode) × 16 (Word mode) Block18 1 1 1 1 1 1 × 16-kbyte 8-kword Block17 1 1 1 1 1 0 1 8-kbyte 4-kword Block16 1 1 1 1 1 0 0 8-kbyte 4-kword Block15 1 1 1 1 0 × × 32-kbyte 16-kword Block14 1 1 1 0 × × × 64-kbyte 32-kword Block13 1 1 0 1 × × × 64-kbyte 32-kword Block12 1 1 0 0 × × × 64-kbyte 32-kword Block11 1 0 1 1 × × × 64-kbyte 32-kword Block10 1 0 1 0 × × × 64-kbyte 32-kword Block9 1 0 0 1 × × × 64-kbyte 32-kword Block8 1 0 0 0 × × × 64-kbyte 32-kword Block7 0 1 1 1 × × × 64-kbyte 32-kword Block6 0 1 1 0 × × × 64-kbyte 32-kword Block5 0 1 0 1 × × × 64-kbyte 32-kword Block4 0 1 0 0 × × × 64-kbyte 32-kword Block3 0 0 1 1 × × × 64-kbyte 32-kword Block2 0 0 1 0 × × × 64-kbyte 32-kword Block1 0 0 0 1 × × × 64-kbyte 32-kword 0 0 0 0 × × × 64-kbyte 32-kword Block0 Note: 1. × can be VIH. Address except block address must be V IH. 7 HN29WT800 Series, HN29WB800 Series Bottom Boot Block Address Map*1 Address Size Block A18 A17 A16 A15 A14 A13 A12 × 8 (Byte mode) × 16 (Word mode) Block18 1 1 1 1 × × × 64-kbyte 32-kword Block17 1 1 1 0 × × × 64-kbyte 32-kword Block16 1 1 0 1 × × × 64-kbyte 32-kword Block15 1 1 0 0 × × × 64-kbyte 32-kword Block14 1 0 1 1 × × × 64-kbyte 32-kword Block13 1 0 1 0 × × × 64-kbyte 32-kword Block12 1 0 0 1 × × × 64-kbyte 32-kword Block11 1 0 0 0 × × × 64-kbyte 32-kword Block10 0 1 1 1 × × × 64-kbyte 32-kword Block9 0 1 1 0 × × × 64-kbyte 32-kword Block8 0 1 0 1 × × × 64-kbyte 32-kword Block7 0 1 0 0 × × × 64-kbyte 32-kword Block6 0 0 1 1 × × × 64-kbyte 32-kword Block5 0 0 1 0 × × × 64-kbyte 32-kword Block4 0 0 0 1 × × × 64-kbyte 32-kword Block3 0 0 0 0 1 × × 32-kbyte 16-kword Block2 0 0 0 0 0 1 1 8-kbyte 4-kword Block1 0 0 0 0 0 1 0 8-kbyte 4-kword Block0 0 0 0 0 0 0 × 16-kbyte 8-kword Note: 8 1. × can be VIH. Address except block address must be V IH. HN29WT800 Series, HN29WB800 Series Mode Selection Word Mode (BYTE = VIH) Mode Pin CE OE WE RP RDY/Busy Read Array VIL VIL VIH VIH VOH (High-Z) Dout Status register VIL VIL VIH VIH ×* 5 Status Register Data VIL VIL VIH VIH × Lock bit data (I/O6) VIL VIL VIH VIH VOH (High-Z) 07H VIL VIL VIH VIH VOH (High-Z) 85H / 86H*6 VIL VIH VIH VIH × High-Z VIH ×* ×* VIH × High-Z Program VIL VIH VIL VIH × Command/Data in Erase VIL VIH VIL VIH × Command Others VIL VIH VIL VIH × Command × × × VIL VOH (High-Z) High-Z Lock bit status 1 Identifier (Maker)* , * 1 2 Identifier (Device)* , * Output disable Standby 4 Command write* Deep powerdown 3 5 5 I/O0 to I/O15 Notes: 1. The command programming mode is used to output the identifier code. Refer to the table of Software Command Definition. 2. A0 = VIL 3. A0 = VIH 4. Refer to the table of Software Command Definition. Programming and erase operation begins after mode setting by command input. 5. × can be VIL or VIH for control pins, and VOL or VOH (High-Z) for RDY/Busy pin. The RDY/Busy is an open drain output pin and indicates status of the internal WSM. When low, it indicates the WSM is Busy performing an operation. A pull-up resistor of 10 k to 100 k Ω is required to allow the RDY/Busy signal to transition high indicating a Ready WSM condition. 6. 85H: HN29WT800 Series, 86H: HN29WB800 Series. 9 HN29WT800 Series, HN29WB800 Series BYTE Mode (BYTE = VIL ) Mode Pin CE OE WE RP RDY/Busy Read Array VIL VIL VIH VIH VOH (High-Z) Dout Status register VIL VIL VIH VIH ×* 5 Status Register Data VIL VIL VIH VIH × Lock bit data (I/O6) VIL VIL VIH VIH VOH (High-Z) 07H VIL VIL VIH VIH VOH (High-Z) 85H / 86H*6 VIL VIH VIH VIH × High-Z VIH ×* ×* VIH × High-Z Program VIL VIH VIL VIH × Command/Data in Erase VIL VIH VIL VIH × Command Others VIL VIH VIL VIH × Command × × × VIL VOH (High-Z) High-Z Lock bit status 1 Identifier (Maker)* , * 1 2 Identifier (Device)* , * Output disable Standby 4 Command write* Deep powerdown 3 5 5 I/O0 to I/O7 Notes: 1. The command programming mode is used to output the identifier code. Refer to the table of Software Command Definition. 2. A0 = VIL 3. A0 = VIH 4. Refer to the table of Software Command Definition. Programming and erase operation begins after mode setting by command input. 5. × can be VIL or VIH for control pins, and VOL or VOH (High-Z) for RDY/Busy pin. The RDY/Busy is an open drain output pin and indicates status of the internal WSM. When low, it indicates the WSM is Busy performing an operation. A pull-up resistor of 10 k to 100 k Ω is required to allow the RDY/Busy signal to transition high indicating a Ready WSM condition. 6. 85H: HN29WT800 Series, 86H: HN29WB800 Series. 10 HN29WT800 Series, HN29WB800 Series Software Command Definition First bus cycle Second bus cycle Third bus cycle Data Data Data Operati on (I/O7 to Operati on (I/O7 Operati on (I/O7 mode Address I/O0)*1 mode Address to I/O0) mode Address to I/O0) Command Read array (memory) Write × FFH Read identifier codes Write × 90H Read IA*2 ID*2 Read status register Write × 70H Read × SRD*3 Clear status register Write × 50H Write × 41H Write WA0*4 WD0*4 Block erase Write × 20H Suspend Write × B0H Resume Write × D0H Read lock bit status Write × Lock bit program/confirm Write Erase all unlocked blocks Write Page program* 5 6 Write BA* 71H Read BA I/O6* 7 × 77H Write BA D0H × A7H Write × D0H Write WA1 WD1 D0H Notes: 1. In the word mode, upper byte data (I/O8 to I/O15) is ignored. 2. IA = Identifier address, A0 = VIL (Manufacture code), A0 = VIH (Device code), ID = ID code, BYTE = VIL: A-1, A1 to A18 = VIL, BYTE = VIH: A1 to A18 = VIL. 3. SRD = Status register data 4. WA = Write address, WD = Write data 5. BYTE = VIL: Write address and write data must be provided sequentially from 00H to FFH for A-1 to A6. Page size is 256 byte (256-byte × 8-bit). BYTE = VIH: Write address and write data must be provided sequentially from 00H to 7FH for A0 to A6. Page size is 128 word (128-word × 16-bit). 6. BA = Block address (A12 to A18), (Addresses except block address must be VIH) 7. I/O6 provides block lock status, I/O6 = 1: Block unlocked, I/O6 = 0: Block locked. 11 HN29WT800 Series, HN29WB800 Series Block Locking RP WP Lock bit (internally) Write protection provided VIL × × All blocks locked (Deep powerdown mode) VHH × × All blocks unlocked VIH VIL 0 Blocks locked (Depend on lock bit data) VIH VIL 1 Blocks unlocked (Depend on lock bit data) VIH VIH × All blocks unlocked Note: I/O6 provided lock status of each block after writing the Read lock status command (71H). WP pin must not be switched during performing Read/Write operations or WSM busy (WSMS = 0). Status Register Data (SRD) Symbol Function Definition SR. 7 (I/O7) Write state machine status 1 = Ready 0 = Busy SR. 6 (I/O6) Suspend status 1 = Suspend 0 = Operation in progress/completed SR. 5 (I/O5) Erase status 1 = Error 0 = Successful SR. 4 (I/O4) Program status 1 = Error 0 = Successful SR. 3 (I/O3) Block status after program 1 = Error 0 = Successful SR. 2 (I/O2) Reserved SR. 1 (I/O1) Reserved SR. 0 (I/O0) Reserved The function and the definition for these bits are to be determined. These bits should be masked out when the status register is polled. Note: The RDY/Busy is an open dran output pin and indicates status of the internal WSM. When low, it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10k Ω to 100k Ω is required to allow the RDY/Busy signal to transition high indicating a Ready WSM condition. I/O3 indicates the block status after the page programming. When I/O3 is High, the page has the overprogrammed cell. If over-program occures, the device is block failed. However, if I/O3 is High, please try the block erase to the block. The block may revive. 12 HN29WT800 Series, HN29WB800 Series Device Identifier Mode The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of Flash Memory. By this mode, the device will be automatically matched its own corresponding erase and programming algorithm. HN29WT800 Series, HN29WB800 Series Identifier Code Pins A0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Hex. data Manufacturer code 0 0 0 0 0 0 1 1 1 07H Device code (T series) 1 1 0 0 0 0 1 0 1 85H Device code (B series) 1 1 0 0 0 0 1 1 0 86H Notes: 1. Device identifier code can be read out by using the read identified codes command. 2. In the word mode, the same data as I/O7 to I/O0 is read out from I/O15 to I/O8. 3. A9 = VHH mode. A9 = 11.5 V to 13.0 V. Set A9 to VHH min 200 ns before falling edge of CE in ready status. Min 200 ns after return to V HH, device can’t be accessed. A1 to A8, A10 to A18, CE, OE, = VIL, WE = VIH, I/O15/A-1 = VIL (BYTE = L). Operations of the HN29WT800 Series, HN29WB800 Series The HN29WT800 Series, HN29WB800 Series include on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the RP pin is at VSS minimizing power consumption. Read: The HN29WT800 Series, HN29WB800 Series have three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the HN29WT800 Series, HN29WB800 Series automatically reset to read array mode. In the read array mode, low level input to CE and OE, high level input to WE and RP, and address signals to the address inputs (A0 to A18) output the data of the addressed location to the data input/output (I/O0 to I/O15). Write: Writes to the CUI enable reading of memory array data, device identifiers and reading and clearing of the Status Register, they also enable block erase and program. The CUI is written by bringing WE to low level, while CE is at low level and OE is at high level. Addresses and data are latched on the earlier rising edge of WE and CE. Standard micro-processor write timings are used. Output Disable: When O E is at V IH, output from the device is disabled. Data input/output are in a high impedance (High-Z) state. 13 HN29WT800 Series, HN29WB800 Series Standby: When CE is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high impedance (High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. Deep Powerdown: When RP is at VIL , the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high impedance (High-Z) state. After return from powerdown, the CUI is reset to Read Array and the Status Register is cleared to value 80H. During block erase or program modes, RP low will abort either operation. Memory array data of the block being altered become invalid. Functional Description The device operations are selected by writing specific software command into the CUI. Read Array Command (FFH): The device is in read array mode on initial device power up and after exit from deep power down, or by writing FFH to the CUI. The device remains in Read Array mode until the other commands are written. Read Device Identifier Command (90H): Though PROM programmers can normally read device identifier codes by raising A9 to high voltage, multiplexing high voltage onto address lines is not desired for microprocessor system. It is an other means to read device identifier codes that Read Device Identifier Code Command (90H) is written to the command latch. Following the write of the Read Device Identifier command of 90H, the manufacturer code and the device code can be read from addresses 00000H and 00001H, respectively. Read Status Register Command (70H): The Status Register is read after writing the read status register command of 70H to the CUI. The contents of Status Register are latched on the later falling edge of OE or CE. So CE or OE must be toggled every status read. Clear Status Register Command (50H): The Erase Status and Program Status bits are set to High by the Write State Machine and can be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. Block Erase/Confirm Command (20H/D0H): Automated block erase is initiated by writing the Block Erase of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Suspend/Resume Command (B0H/D0H): Writing the suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The device continues to output status register data when read, after the suspend command is written to it. Polling the WSM status and suspend status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the read array command to the CUI enables reading data from blocks other than that which is suspended. When the resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes. 14 HN29WT800 Series, HN29WB800 Series Page Program Command (41H): Page program allows fast programming of 128-word of data. Writing of 41H initiates the page program operation. From 2nd cycle to 129th cycle write data must be serially inputted. Address A6 to A0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation. Basically re-program must not be done on a page which has already programmed. Data Protection: The HN29WT800 Series, HN29WB800 Series provide selective block locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the HN29WT800 Series, HN29WB800 Series have a master write protect pin (WP) which prevents any modifications to memory blocks whose lock-bits are set to Low, when WP is low. When WP is high or RP is V HH , all blocks can be programmed or erased regardless of the state of lock-bits, and the lock-bits are cleared to High by erase. Power Supply Voltage: A delay time of 2 µs is required before any device operation is initiated. The delay time is measured from the time VCC reaches VCC min (3.0 V). During powerup, RP = V SS is recommended. Falling in Busy status is not recommended for possibility of damaging the device. Absolute Maximum Ratings Parameter Symbol Value Unit Notes VCC voltage VCC –0.2 to +4.6 V 1 All input and output voltages except V CC, A9, RP Vin, Vout –0.6 to +4.6 V 1, 2 A9, RP supply voltage VHH, VID –0.6 to +14.0 V 1, 2 Operating temperature range Topr 0 to +70 ˚C Storage temperature range Tstg –65 to +125 ˚C Storage temperature under bias Tbias –10 to +80 ˚C Notes: 1. Relative to VSS . 2. Minimum DC voltage is –0.5 V on input/output pins. During transition, this level may undershoot to –2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins are VCC +0.5 V which, during transitions, may overshoot to V CC +1.5 V for periods < 20 ns. Capacitance (Ta = 25˚C, f = 1 MHz) Parameter Symbol Min Typ Max Unit Test conditions Input capacitance Cin — — 8 pF Vin = 0 V Output capacitance Cout — — 12 pF Vout = 0 V 15 HN29WT800 Series, HN29WB800 Series DC Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to +70˚C) Parameter Symbol Min Typ Max Unit Test conditions Input leakage current I LI –1 — 1 µA Vin = VSS to V CC Output leakage current I LO –10 — 10 µA Vout = VSS to V CC Standby V CC current I SB1 — 50 200 µA Vin = VIH/V IL, CE = RP = WP = VIH I SB2 — 1 5 µA Vin = VSS or VCC , CE = RP = WP = VCC ± 0.3 V I SB3 — 5 15 µA Vin = VIH/V IL, RP = VIL I SB4 — 1 5 µA Vin = VSS or VCC, RP = VSS ± 0.3 V Read VCC current I CC1 — 7 30 mA Vin = VIH/V IL, CE = VIL, RP = OE = VIH, f = 10 MHz, Iout = 0 mA Write VCC current I CC2 — — 30 mA Vin = VIH/V IL, CE = WE = VIL, RP = OE = VIH Programming VCC current I CC3 — — 40 mA Vin = VIH/V IL, CE = RP = WP = VIH Erasing VCC current I CC4 — — 40 mA Vin = VIH/V IL, CE = RP = WP = VIH Suspend VCC current I CC5 — — 200 µA Vin = VIH/V IL, CE = RP = WP = VIH RP all block unlocked current I RP — — 100 µA RP = VHH max A9 intelligent identifier current I ID — — 100 µA A9 = VID max A9 intelligent identifier voltage VID 11.4 12.0 12.6 V RP unlocked voltage VHH 11.4 12.0 12.6 V Input voltage VIL –0.5 — 0.8 V VIH 2.0 — VCC + 0.5 V VOL — — 0.45 V I OL = 5.8 mA VOH1 0.85 × VC C — — V I OH = –2.5 mA VOH2 VCC - 0.4 — — V I OH = –100 µA VLKO 1.2 — V Deep powerdown V CC current Output voltage 2 Low VCC lock-out voltage* — Notes: 1. All currents are RMS unless otherwise noted. Typical values at VCC = 3.3 V, Ta = 25˚C. 2. To protect initiation of write cycle during V CC powerup/powerdown, a write cycle is locked out for VCC less than V LKO. If VCC is less than VLKO Write State Machine is reset to read mode. When the Wirte State Machine is in Busy state, if V CC is less than VLKO, the alternation of memory contents may occur. 16 HN29WT800 Series, HN29WB800 Series AC Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to +70˚C) Test Conditions • • • • • • Input pulse levels: VIL = 0 V, V IH = 3.0 V Input rise and fall time: ≤ 10 ns (HN29WT/WB800-10/12 Series) : ≤ 5 ns (HN29WT/WB800-8 Series) Output load: 1 TTL gate +100 pF (Including scope and jig.) (HN29WT/WB800-10/12 Series) : 1 TTL gate +30 pF (Including scope and jig.) (HN29WT/WB800-8 Series) Reference levels for measuring timing: 1.5 V VCC Powerup/Powerdown Timing Parameter Symbol Min Typ Max Unit RP = VIH setup time from VCC min t VCS 2 — — µs Note: During powerup/powerdown, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contents during powerup/powerdown. The delay time of min 2 µs is always required before read operation or write operation is initiated from the time VCC reaches VCC min during powerup/powerdown. By holding RP V IL, the contents of memory is protected during VCC powerup/powerdown. During powerup, RP must be held V IL for min 2 µs from the time VCC reaches VCC min. During powerdown, RP must be held V IL until V CC reaches VSS. RP doesn’t have latch mode, so RP must be held V IH during read operation or erase/program operation. Read/Write inhibit Read/Write inhibit Read/Write inhibit VCC t VCS RP CE t PS t PS WE 17 HN29WT800 Series, HN29WB800 Series Read Operation HN29WT800/HN29WB800 -8 -10 -12 Parameter Symbol Min Max Min Max Min Max Unit Read cycle time t RC 80 — 100 — 120 — ns Address to output delay t ACC — 80 — 100 — 120 ns CE to output delay t CE — 80 — 100 — 120 ns t OE — 40 — 50 — 60 ns t DF — 25 — 25 — 30 ns t OH 0 — 0 — 0 — ns OE hold from WE high Status register t OEH read in busy 80 — 100 — 120 — ns OE hold from WE high Other read t OEH 0 — 0 — 0 — ns RP recovery time before read t PS 500 — 500 — 500 — ns RP low to output High-Z t PHZ — 150 — 150 — 300 ns CE low to BYTE high or low t BCD — 5 — 5 — 5 ns Address to BYTE high or low t BAD — 5 — 5 — 5 ns BYTE to output delay t BYTE — 80 — 100 — 120 ns BYTE low to output High-Z t BHZ — 25 — 25 — 30 ns OE to output delay CE or OE high to output float * 1 Address to output hold Notes: 1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Timing measurements are made under read timing waveform. 18 HN29WT800 Series, HN29WB800 Series Read Timing Waveform (Byte Mode or Word Mode) Address Address valid t RC CE t DF OE t OEH t OE WE t CE t OH t ACC I/O Output valid t PS t PHZ RP 19 HN29WT800 Series, HN29WB800 Series Read Timing Waveform (Byte Mode, Word Mode Switch) Address valid A0 to A18 Address valid t ACC t DF CE t CE t OE OE t BAD t BYTE BYTE t BYTE t OH t BCD High-Z t BAD Output valid I/O0 to I/O7 Valid Output valid t BHZ t ACC High-Z Valid I/O8 to I/O14 I/O15/A-1 A-1 I/O15 Note: When BYTE = High, CE = OE = Low, I/O15/A-1 is output status. At this time, input signal must not be applied. 20 A-1 HN29WT800 Series, HN29WB800 Series Command Write Operation HN29WT800/HN29WB800 -8 -10 -12 Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Write cycle time t WC 80 — — 100 — — 120 — — ns Address setup time t AS 50 — — 50 — — 50 — — ns Address hold time t AH 10 — — 10 — — 10 — — ns Data setup time t DS 50 — — 50 — — 50 — — ns Data hold time t DH 10 — — 10 — — 10 — — ns CE setup time t CS 0 — — 0 — — 0 — — ns CE hold time t CH 0 — — 0 — — 0 — — ns Write pulse width t WP 60 — — 60 — — 60 — — ns Write pulse high time t WPH 20 — — 20 — — 20 — — ns WE setup time t WS 0 — — 0 — — 0 — — ns WE hold time t WH 0 — — 0 — — 0 — — ns CE pulse width t CEP 60 — — 60 — — 60 — — ns CE pulse high time t CEPH 20 — — 20 — — 20 — — ns Duration of program operation t DAP — 25 80 — 25 80 — 25 80 ms Duration of block erase operation t DAE — 50 600 — 50 600 — 50 600 ms BYTE high or low setup time t BS 50 — — 50 — — 50 — — ns BYTE high or low hold time t BH 80 — — 100 — — 120 — — ns RP high recovery to WE low t PS 500 — — 500 — — 500 — — ns Block lock setup to write enable high t BLS 80 — — 100 — — 120 — — ns t WPS 80 — — 100 — — 120 — — ns t BLH 0 — — 0 — — 0 — — ns t WPH 0 — — 0 — — 0 — — ns WE high to RDY/Busy low t WHRL — — 80 — — 100 — — 120 ns CE high to RDY/Busy low t EHRL — — 80 — — 100 — — 120 ns Block lock hold from valid SRD Note: Read operation parameters during command write operations mode are the same as during read timing waveform. Typical values at VCC = 3.3 V, Ta = 25˚C. 21 HN29WT800 Series, HN29WB800 Series Erase and Program Performance Parameter Min Typ Max Unit Main block write time (Page mode) — 6.4 20.4 s Page write time — 25 80 ms Block erase time — 50 600 ms Note: Typical values at V CC = 3.3 V, Ta = 25˚C. These values exclude system level overhead. Page Program Timing Waveform (WE control) Page program A7 to A18 Read status Write read register array command Address valid BYTE = Low (A-1 to A6) 00H 01H 02H to FEH FFH BYTE = High (A0 to A6) 00H 01H 02H to 7EH 7FH t AH t AS t WC t CE CE t CS OE t OE t CH t OEH t WP t DAP t WPH WE t DS t DH 41H I/O Din Din Din SRD Din t WHRL RDY/Busy t BS t BH BYTE VHH RP WP 22 t BLS t BLH t WPS t WPH t PS FFH HN29WT800 Series, HN29WB800 Series Page Program Timing Waveform (CE control) Page program A7 to A18 Read status Write read register array command Address valid BYTE = Low (A-1 to A6) 00H BYTE = High (A0 to A6) 00H CE 02H to FEH FFH 01H 02H to 7EH 7FH t CE t AH t AS t WC 01H t CEPH t OE t WH OE t WS t OEH t CEP t DAP WE t DS t DH 41H I/O Din Din Din SRD Din FFH t EHRL RDY/Busy t BS t BH BYTE VHH RP t BLS t BLH t WPS t WPH t PS WP 23 HN29WT800 Series, HN29WB800 Series Write Timing Waveform for Erase Operations (WE control) Program, Erase Address Read status Write read register array command Address valid t AH t AS t WC t CE CE t CS t OE t CH t OEH OE t WP t DAE t WPH WE t DS t DH 20H D0H I/O SRD t WHRL RDY/Busy tBS t BH BYTE VHH RP WP 24 t BLS t BLH t PS t WPS t WPH FFH HN29WT800 Series, HN29WB800 Series Write Timing Waveform for Erase Operations (CE control) Program, Erase Address Read status Write read register array command Address valid t AH t AS t WC t CE CE t CEPH t OE t WH OE t OEH t CEP t DAE t WS WE t DS t DH 20H D0H I/O SRD FFH t EHRL RDY/Busy tBS t BH BYTE VHH RP t BLS t BLH t PS t WPS t WPH WP 25 HN29WT800 Series, HN29WB800 Series Page Program Flowchart START Write 41H n=0 n=n+1 Write Address n, Data n n = FFH ? or n = 7FH ? NO YES Status register read Write B0H ? SR. 7 = 1 ? NO NO YES YES Full status check if desired Suspend loop Write D0H Page program completed YES 26 HN29WT800 Series, HN29WB800 Series Block Erase Flowchart START Write 20H Write D0H Block address Status register read Write B0H ? SR. 7 = 1 ? NO NO YES YES Full status check if desired Suspend loop Write D0H Block erase completed YES 27 HN29WT800 Series, HN29WB800 Series Full Status Check Procedure Status register read SR. 4 = 1 and SR. 5 = 1 ? NO SR. 5 = 0 ? Command sequence error YES NO Block erase error YES SR. 4 = 0 ? NO Program error (Page, lock bit) YES SR. 3 = 0 ? NO YES Successful (Block erase, program) 28 Program error (Block) HN29WT800 Series, HN29WB800 Series Suspend/Resume Flowchart START Write B0H Suspend Status register read SR. 7 = 1 ? NO YES SR. 6 = 1 ? NO Program/erase completed YES Write FFH Read array data Done reading? NO YES Write D0H Resume Operation resumed 29 HN29WT800 Series, HN29WB800 Series Lock Bit Program Flowchart START Write 77H Write D0H block address SR. 7 = 1 ? NO YES SR. 4 = 0 ? NO YES Lock bit program successful 30 Lock bit program failed HN29WT800 Series, HN29WB800 Series Data Protection Operation Page programming and Block Erasing can be locked by programming a nonvolatile lock bit for each block. When WP is V IL level, those locked blocks as reflected by the Block-Lock Status bits, are protected from inadvertent Page programming or Block Erasing. Programmed block data and Lock-Bit Data can be locked When WP is VIL level. Lock bit data programmed Lock bit data programmed WP = VIL level (Block lock!) WP = VIL level (Block lock!) Operation start Operation start Write page program command (41H) Write block erase command (20H) Write page program data (WDn, n = 00H to FFH, 00H to 7FH) Write erase confirm command (D0H) Block erase error (SR.5 = 1) Page program error (SR.4 = 1) Write clear status register command (50H) Write clear status register command (50H) Operation end Operation end 31 HN29WT800 Series, HN29WB800 Series Programmed block data and Lock-Bit Data can be erased by block erase command When WP is VIH level or RP is VHH level. Lock bit data programmed WP = VIH level or RP = VHH (Block unlock!) Operation start Write block erase command (20H) Write erase confirm command (D0H) Block data and lock bit data erase successful (SR.5 = 0) Operation end 32 HN29WT800 Series, HN29WB800 Series Operation Status and Effective Command Read/standby state Read status register 70H Read device identifier Read lock bit status 71H 90H Read array FFH Setup state 41H 20H 77H Page program setup Lock bit program setup WDi Inernal state i = 0-255 D0H Block erase setup D0H other Program and verify Erase and verify Read status register Read status register D0H Erase all unlocked blocks setup D0H other B0H A7H other D0H B0H Suspend state Read status register 70H Read device identifier Invalid data Read lock status 71H 90H Read array FFH 33 HN29WT800 Series, HN29WB800 Series Package Dimensions HN29WT800T/HN29WB800T Series (TFP-48D) Unit: mm 12.00 12.40 Max 25 18.40 48 1 24 0.50 34 20.00 ± 0.20 0 – 5° 0.13 ± 0.05 0.10 0.80 0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0.22 ± 0.08 0.08 M 0.20 ± 0.06 0.45 Max 0.50 ± 0.10 Hitachi Code JEDEC Code EIAJ Code Weight TFP-48D MO-142DD SC-669 0.49 g HN29WT800 Series, HN29WB800 Series Package Dimensions (cont.) HN29WT800R/HN29WB800R Series (TFP-48DR) Unit: mm 12.00 12.40 Max 24 48 25 18.40 1 0.50 20.00 ± 0.20 0 – 5° 0.13 ± 0.05 0.10 0.80 0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0.22 ± 0.08 0.08 M 0.20 ± 0.06 0.45 Max 0.50 ± 0.10 Hitachi Code JEDEC Code EIAJ Code Weight TFP-48DR MO-142DD SC-669 0.49 g 35 HN29WT800 Series, HN29WB800 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 36 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 HN29WT800 Series, HN29WB800 Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Jun. 14, 1996 Initial issue K. Izawa T. Muto 1.0 May. 9, 1997 Deletion of HN29WT/WB800FP Series Addition of Top Boot Block Address Map and Bottom Boot Block Address Map Software Command Definition Deletion of Sleep command Deletion of notes8 Deletion of Block Locking (SOP Package) Change of Status Register Data (SRD) DC Characteristics V LKO min: 1.5 V to 1.2 V V LKO max: 2.5 V to — AC Characteristics Test Conditions (HN29WT/WB800-10/12): 1TTL gate + 50 pF to 1TTL gate + 100 pF Change of parameter name: t RWH to tPS Deletion of t RP tPS min: 0/0/0 ns 500/500/500 ns tDAP max: 120/120/120 ms to 80/80/80 ms Erase and program performance Main block write time max: 38.4 s to 20.4 s Page write time max: 120 ms to 80 ms Change of Full Status Check Procedure and Operation Status and Effective Command Addition of Data Protection Operation 37