ISSI IS61LV3216-15KI 32k x 16 low voltage cmos static ram Datasheet

ISSI
®
IS61LV3216
32K x 16 LOW VOLTAGE CMOS STATIC RAM
FEATURES
• High-speed access time: 10, 12, 15, and 20 ns
• CMOS low power operation
— 150 mW (typical) operating
— 150 µW (typical) standby
• TTL compatible interface levels
• Single 3.3V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
• Available in 44-pin 400-mil SOJ package and
44-pin TSOP (Type 2)
NOVEMBER 1997
DESCRIPTION
The ISSI IS61LV3216 is a high-speed, 512K static RAM
organized as 32,768 words by 16 bits. It is fabricated using
ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields fast access times with low power consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61LV3216 is packaged in the JEDEC standard 44-pin
400-mil SOJ and 44-pin TSOP (Type 2).
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
32K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1
ISSI
IS61LV3216
PIN CONFIGURATIONS
44-Pin TSOP
44-Pin SOJ
NC
1
44
A0
A14
2
43
A1
A13
3
42
A2
A12
4
41
OE
A11
5
40
UB
CE
6
39
LB
I/O0
7
38
I/O15
I/O1
8
37
I/O14
I/O2
9
36
I/O13
I/O3
10
35
I/O12
Vcc
11
34
GND
GND
12
33
Vcc
I/O4
13
32
I/O11
I/O5
14
31
I/O10
I/O6
15
30
I/O9
I/O7
16
29
I/O8
WE
17
28
NC
A10
18
27
A3
A9
19
26
A4
A8
20
25
A5
A7
21
24
A6
NC
22
23
NC
®
NC
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
A8
A7
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC
PIN DESCRIPTIONS
A0-A14
Address Inputs
LB
Lower-byte Control (I/O0-I/O7)
I/O0-I/O15
Data Inputs/Outputs
UB
Upper-byte Control (I/O8-I/O15)
CE
Chip Enable Input
NC
No Connection
OE
Output Enable Input
Vcc
Power
WE
Write Enable Input
GND
Ground
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
2
WE
CE
OE
LB
UB
X
H
X
H
H
H
L
L
L
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
X
X
X
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
L
I/O PIN
I/O0-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Vcc Current
ISB1, ISB2
ICC
ICC
ICC
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61LV3216
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
VTERM
TSTG
PT
IOUT
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +4.6
–0.5 to Vcc + 0.5
–65 to +150
1.0
20
®
Note:
1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the
device. This is a stress rating only and
functional operation of the device at
these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods
may affect reliability.
Unit
V
V
°C
W
mA
OPERATING RANGE
Range
Commercial
Ambient Temperature
0°C to +70°C
1
2
3
VCC
3.3V ± 10%
4
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.2
VCC + 0.3
V
–0.3
0.8
V
Voltage(1)
VIL
Input LOW
ILI
Input Leakage
GND - VIN - VCC
–2
2
µA
ILO
Output Leakage
GND - VOUT - VCC, Outputs Disabled
–2
2
µA
5
6
7
Notes:
1. VIL (min.) = –3.0V for pulse width less than 10 ns.
8
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
-20 ns
Min. Max.
9
Symbol Parameter
Test Conditions
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
220
—
—
—
200
230
—
—
180
200
—
—
160
180
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE • VIH , f = 0
Com.
Ind.
—
—
10
—
—
—
10
20
—
—
10
20
—
—
10
20
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
CE • VCC – 0.2V,
VIN • VCC – 0.2V, or
VIN - 0.2V, f = 0
Com.
Ind.
—
—
5
—
—
—
5
10
—
—
5
10
—
—
5
10
mA
10
11
12
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
3
ISSI
IS61LV3216
®
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
-10
Min. Max.
Parameter
-12
Min. Max.
-15
Min. Max.
-20
Min. Max.
Unit
tRC
Read Cycle Time
10
—
12
—
15
—
20
—
ns
tAA
Address Access Time
—
10
—
12
—
15
—
20
ns
tOHA
Output Hold Time
3
—
3
—
3
—
3
—
ns
tACE
CE Access Time
—
10
—
12
—
15
—
20
ns
tDOE
OE Access Time
—
5
—
6
—
7
—
8
ns
tHZOE(2) OE to High-Z Output
0
5
0
6
0
7
0
8
ns
OE to Low-Z Output
0
—
0
—
0
—
0
—
ns
CE to High-Z Output
0
5
0
6
0
7
0
8
ns
tLZCE(2) CE to Low-Z Output
4
—
4
—
4
—
4
—
ns
tLZOE
(2)
tHZCE
(2
tBA
LB, UB Access Time
—
5
—
6
—
7
—
8
ns
tHZB
LB, UB to High-Z Output
0
5
0
6
0
7
0
8
ns
tLZB
LB, UB to Low-Z Output
5
—
5
—
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
319 Ω
3.3V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1a.
4
319 Ω
3.3V
353 Ω
5 pF
Including
jig and
scope
353 Ω
Figure 1b.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61LV3216
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
1
tRC
ADDRESS
2
tAA
tOHA
tOHA
DOUT
3
DATA VALID
PREVIOUS DATA VALID
4
READ CYCLE NO. 2(1,3)
5
tRC
ADDRESS
tAA
tOHA
6
OE
tHZOE
tDOE
7
tLZOE
CE
tACE
tHZCE
tBA
tHZB
tLZCE
8
LB, UB
DOUT
HIGH-Z
tLZB
DATA VALID
9
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
5
ISSI
IS61LV3216
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
Parameter
-10
Min. Max.
-12
Min. Max.
-15
Min. Max.
-20
Min. Max.
Unit
tWC
Write Cycle Time
10
—
12
—
15
—
20
—
ns
tSCE
CE to Write End
9
—
10
—
11
—
12
—
ns
tAW
Address Setup Time
to Write End
9
—
10
—
11
—
12
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
0
—
ns
tPWB
LB, UB Valid to End of Write
9
—
10
—
11
—
12
—
ns
tPWE
WE Pulse Width
7
—
8
—
10
—
11
—
ns
tSD
Data Setup to Write End
5
—
6
—
7
—
—
8
ns
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
WE LOW to High-Z Output
—
5
—
6
—
7
—
8
ns
tLZWE(2) WE HIGH to Low-Z Output
1
—
1
—
1
—
1
—
ns
tHD
tHZWE
(2)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be
in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61LV3216
®
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
1
tWC
2
ADDRESS
tHA
tSCE
3
CE
tPWB
LB, UB
4
tAW
tPWE
5
WE
tSA
6
WRITE(1)
tSD
tHD
7
DIN
tHZWE
DOUT
HIGH-Z
tLZWE
UNDEFINED
HIGH-Z
8
UNDEFINED
9
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
7
ISSI
IS61LV3216
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Speed (ns) Order Part No.
Package
®
Package
10
10
IS61LV3216-10T
IS61LV3216-10K
Plastic TSOP (Type 2)
400-mil Plastic SOJ
12
12
IS61LV3216-12TI
IS61LV3216-12KI
Plastic TSOP (Type 2)
400-mil Plastic SOJ
12
12
IS61LV3216-12T
IS61LV3216-12K
Plastic TSOP (Type 2)
400-mil Plastic SOJ
15
15
IS61LV3216-15TI
IS61LV3216-15KI
Plastic TSOP (Type 2)
400-mil Plastic SOJ
15
15
IS61LV3216-15T
IS61LV3216-15K
Plastic TSOP (Type 2)
400-mil Plastic SOJ
20
20
IS61LV3216-20TI
IS61LV3216-20KI
Plastic TSOP (Type 2)
400-mil Plastic SOJ
20
20
IS61LV3216-20T
IS61LV3216-20K
Plastic TSOP (Type 2)
400-mil Plastic SOJ
NOTICE
Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits
are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may
vary depending upon a user's specific application. While the information in this publication has been carefully checked,
Integrated Silicon Solution, Inc. shall not be liable for any damages arising as a result of any error or omission.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect
its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc.
receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes
all such risks; and (c) potential liability of Integrated Silicon Solution, Inc. is adequately protected under the circumstances.
Copyright 1997 Integrated Silicon Solution, Inc.
Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited.
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
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