TI1 DP83936AVUL-33 32-bit non-multiplexed address and data bus Datasheet

DP83936AVUL-20,DP83936AVUL-25,
DP83936AVUL-33
DP83936AVUL-20/25/33 MHz Full Duplex SONIC(TM)-T Systems-Oriented Network
Interface Controller with Twisted Pair Interface
Literature Number: SNLS105A
DP83936AVUL-20/25/33 MHz Full Duplex SONIC TM -T
Systems-Oriented Network Interface Controller
with Twisted Pair Interface
General Description
descriptors to the memory resource area. The transmit buffer management uses two areas in memory:
1. indicating status and control information;
2. fetching packet data.
The system can create a transmit queue allowing multiple
packets to be transmitted from a single transmit command.
The packet data can reside on any arbitrary byte boundary
and can exist in several non-contiguous locations.
Features
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The SONIC-T (Systems-Oriented Network Interface Controller with Twisted Pair) is a second-generation Ethernet Controller designed to meet the demands of today’s high-speed
32- and 16-bit systems. Its system interface operates with a
high speed DMA that typically consumes less than 5% of
the bus bandwidth. Selectable bus modes provide both big
and little endian byte ordering and a clean interface to standard microprocessors. The linked-list buffer management
system of SONIC-T offers maximum flexibility in a variety of
environments from PC-oriented adapters to high-speed
motherboard designs. The SONIC-T can be configured for
full duplex operation. Furthermore, the SONIC-T integrates
a fully-compatible IEEE 802.3 Encoder/Decoder (ENDEC)
and a Twisted Pair Interface which provide a one-chip solution for Ethernet when using 10BASE-T. When using
10BASE2 or 10BASE5, the SONIC-T may be paired with the
DP8392 Coaxial Transceiver Interface to achieve a simple
2-chip solution.
For increased performance, the SONIC-T implements a
unique buffer management scheme to efficiently process
receive and transmit packets in system memory. No intermediate packet copy is necessary. The receive buffer management uses three areas in memory for (1) allocating additional resources, (2) indicating status information, and (3)
buffering packet data. During reception, the SONIC-T stores
packets in the buffer area, then indicates receive status and
control information in the descriptor area. The system allocates more memory resources to the SONIC-T by adding
Y
Y
Y
Y
Y
Y
Y
Y
Y
ol
Y
32-bit non-multiplexed address and data bus
Configurable for Full Duplex operation
Auto AUI/TPI selection
High-speed interruptible DMA
Linked-list buffer management maximizes flexibility
Two independent 32-byte transmit and receive FIFOs
Bus compatibility for all standard microprocessors
Supports big and little endian formats
Integrated IEEE 802.3 ENDEC
Integrated Twisted Pair Interface
Complete address filtering for up to 16 physical and/or
multicast addresses
32-bit general-purpose timer
Loopback diagnostics
Fabricated in low-power CMOS
160 PQFP package
Full network management facilities support the 802.3
layer management standard
Integrated support for bridge and repeater applications
Y
Y
Y
Y
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Y
Y
System Diagram
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IEEE 802.3 Ethernet/Thin-Ethernet/10BaseT Station
TL/F/12597 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
SONICTM is a trademark of National Semiconductor Corporation.
C1996 National Semiconductor Corporation
TL/F/12597
RRD-B30M36/Printed in U. S. A.
http://www.national.com
DP83936AVUL-20/25/33 MHz Full Duplex SONIC-T Systems-Oriented
Network Interface Controller with Twisted Pair Interface
January 1996
Table of Contents
5.5 Transmit Buffer Management
1.0 CONNECTION DIAGRAMS
1.1 Pin Connection Diagram, National/Intel Mode
5.5.1 Transmit Descriptor Area (TDA)
1.2 Pin Connection Diagram, Motorola Mode
5.5.2 Transmit Buffer Area (TBA)
5.5.3 Preparing to Transmit
2.0 PIN DESCRIPTION
5.5.4 Dynamically Adding TDA Descriptors
3.0 FUNCTIONAL DESCRIPTION
6.0 SONIC-T REGISTERS
3.1 Twisted Pair Interface Module
6.1 The CAM Unit
3.2 IEEE 802.3 Encoder/Decoder (ENDEC) Unit
6.1.1 The Load CAM Command
3.2.1 ENDEC Operation
3.2.2 Selecting an External ENDEC
6.2 Full Duplex Operation
6.3 Status/Control Registers
3.3 Media Access Control (MAC) Unit
6.4 Register Description
3.3.1 MAC Receive Section
3.3.2 MAC Transmit Section
3.3.3 Full Duplex Operation
6.4.1 Command Register
6.4.2 Data Configuration Register
6.4.3 Receive Control Register
6.4.4 Transmit Control Register
6.4.5 Interrupt Mask Register
6.4.6 Interrupt Status Register
6.4.7 Data Configuration Register 2
6.4.8 Transmit Registers
6.4.9 Receive Registers
6.4.10 CAM Registers
6.4.11 Tally Counters
6.4.12 General Purpose Timer
6.4.13 Silicon Revision Register
3.4 Data Width and Byte Ordering
3.5 FIFO and Control Logic
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3.5.1 Receive FIFO
3.5.2 Transmit FIFO
3.6 Status and Configuration Registers
3.7 Bus Interface
3.8 Loopback and Diagnostics
3.8.1 Loopback Procedure
3.9 Network Management Functions
4.0 TRANSMIT/RECEIVE IEEE 802.3 FRAME FORMAT
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7.0 BUS INTERFACE
4.1 Preamble and Start of Frame Delimiter (SFD)
4.2 Destination Address
4.3 Source Address
4.5 Data Field
4.6 FCS Field
7.2 System Configuration
7.3 Bus Operations
7.3.1 Acquiring the Bus
7.3.2 Block Transfers
7.3.3 Bus Status
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4.4 Length/Type Field
7.1 Pin Configurations
4.7 MAC (Media Access Control) Conformance
7.3.4 Bus Mode Compatibility
7.3.5 Master Mode Bus Cycles
5.0 BUFFER MANAGEMENT
7.3.6 Bus Exceptions (Bus Retry)
7.3.7 Slave Mode Bus Cycle
7.3.8 On-Chip Memory Arbiter
5.1 Buffer Management Overview
5.2 Descriptor Areas
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5.2.1 Naming Convention for Descriptors
7.3.9 Chip Reset
5.2.2 Abbreviations
8.0 NETWORK INTERFACING
5.2.3 Buffer Management Base Addresses
8.1 Manchester Encoder and Differential Driver
5.3 Descriptor Data Alignment
8.1.1 Manchester Decoder
8.1.2 Collision Translator
8.1.3 Oscillator Inputs
8.1.4 Power Supply Considerations
5.4 Receive Buffer Management
5.4.1 Receive Resource Area (RRA)
5.4.2 Receive Buffer Area (RBA)
5.4.3 Receive Descriptor Area (RDA)
8.2 Twisted Pair Interface Module
5.4.4 Receive Buffer Management Initialization
5.4.5 Beginning of Reception
9.0 AC AND DC SPECIFICATIONS
5.4.6 End of Packet Processing
10.0 AC TIMING TEST CONDITIONS
5.4.7 Overflow Conditions
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1.0 Connection Diagrams
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1.1 PIN CONNECTION DIAGRAM, NATIONAL/INTEL MODE
TL/F/12597 – 2
3
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1.0 Connection Diagrams (Continued)
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1.2 PIN CONNECTION DIAGRAM, MOTOROLA MODE
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TL/F/12597 – 3
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2.0 Pin Description
Ie
Input
Oe
Output
TRI e TRI-STATE drivers. These pins are driven high, low
or TRI-STATE. Drive levels are CMOS compatible.
These pins may also be inputs (depending on the
pin).
OC e Open Collector type drivers. These drivers are
TRI-STATE when inactive and are driven low when
active. These pins may also be inputs (depending
on the pin).
TPI e Twisted Pair Interface.
Ze
TRI-STATEÉ Input, TTL compatible
ECL e Emitter Coupled Logic type drivers for interfacing to
the Attachment Unit Interface.
TP e Totem Pole type drivers. These drivers are driven
either high or low and are always driven. Drive levels are CMOS compatible.
Pin names which contain a ‘‘/’’ indicate dual function pins.
TABLE 2-1. Pin Description
Driver
Type
Symbol
Direction
Description
NETWORK INTERFACE PINS
I
EXTERNAL ENDEC SELECT: Tying this pin to VCC (EXT e 1) disables the internal
ENDEC and allows an external ENDEC to be used. Tying this pin to ground (EXT e 0)
enables the internal ENDEC. This pin must be tied either to VCC or ground. Note the
alternate pin definitions for CRSo/CRSi, COLo/COLi, RXDo/RXDi, RXCo/RXCi, and
TXCo/TXCi. When EXT e 0 the first pin definition is used and when EXT e 1 the second
pin definition is used.
AUI/TP
I
ATTACHMENT UNIT INTERFACE (AUI)/TWISTED PAIR (TP) SELECT: Tying this pin
to VCC (AUI/TP e 1) enables the AUI mode for interface with the ENDEC unit. Tying this
pin to GND (AUI/TP e 0) enables the TPI Module mode for interface with the ENDEC
unit.
et
e
EXT
TPI
O
TWISTED PAIR TRANSMIT OUTPUTS: These high drive CMOS level outputs are
resistively combined external to the chip to produce a differential output signal with
equalization to compensate for Intersymbol Interference (ISI) on the twisted pair medium.
RXI a , RXIb
TPI
I
TWISTED PAIR RECEIVE INPUTS: These inputs feed a differential amplifier which
passes valid data to the ENDEC module.
TXLED
TP
O
RXLED
TP
O
COLED
TP
O
TP
O
POLARITY: An active low output. This signal is normally inactive. When the TPI module
detects seven consecutive link pulses or three consecutive received packets with
reversed polarity, it is asserted.
TP
O
GOOD LINK: An active low output. This pin operates as an output to display link integrity
status if this function has not been disabled by the LNKDIS pin described below. This
output is off if the SONIC-T Controller is in AUI mode or if link testing is enabled and the
link integrity is bad (i.e., the twisted pair link has been broken).
This output is on if the SONIC-T Controller is in Twisted Pair Interface (TPI) mode, link
integrity checking is enabled and the link integrity is good (i.e., the twisted pair link has
not been broken) or if the link testing is disabled.
O
LINKLED
TRANSMIT: An active low output. It is asserted for approximately 50 ms whenever the
SONIC-T Controller transmits data in either AUI or TPI modes.
RECEIVE: An active low output. It is asserted for approximately 50 ms whenever receive
data is detected in either AUI or TPI mode.
COLLISION: An active low output. It is asserted for approximately 50 ms whenever the
SONIC-T Controller detects a collision in either AUI or TPI modes.
bs
POLED
ol
TXOd a , TXO a ,
TXOb, TXOdb
LNKDIS
I
LINK DISABLE: When this pin is tied to GND (LNKDIS e 0), the link test pulse
generation and integrity checking function are both disabled.
LOWSQL
I
LOW SQUELCH SELECT: Tying this pin to VCC (LOWSQL e 1) sets the squelch mode
to use a squelch threshold level lower than that of the 10BASE-T specification (see
Section 3.1).
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2.0 Pin Description (Continued)
TABLE 2-1. Pin Description (Continued)
Symbol
Driver
Type
Direction
Description
NETWORK INTERFACE PINS (Continued)
CD a
I
AUI COLLISION a : The positive differential collision input from the transceiver. This pin should
be unconnected when an external ENDEC is selected (EXT e 1).
CDb
I
AUI COLLISION b: The negative differential collision input from the transceiver. This pin should
be unconnected when an external ENDEC is selected (EXT e 1).
RX a
I
AUI RECEIVE a : The positive differential receive data input from the transceiver. This pin should
be unconnected when an external ENDEC is selected (EXT e 1).
RXb
I
AUI RECEIVE b: The negative differential receive data input from the transceiver. This pin
should be unconnected when an external ENDEC is selected (EXT e 1).
ECL
O
AUI TRANSMIT a : The positive differential transmit output to the transceiver. This pin should be
unconnected when an external ENDEC is selected (EXT e 1).
TXb
ECL
O
AUI TRANSMIT b: The negative differential transmit output to the transceiver. This pin should
be unconnected when an external ENDEC is selected (EXT e 1).
CRSo/
CRSi
TP
O
I
CARRIER SENSE OUTPUT (CRSo) from the internal ENDEC (EXT e 0): When EXT e 0 the
CRSo signal is internally connected between the ENDEC and MAC units. It is asserted on the first
valid high-to-low transition in the receive data (RX g ). This signal remains active 1.5 bit times
after the last bit of data. Although this signal is used internally by the SONIC-T, it is also provided
as an output to the user.
CARRIER SENSE INPUT (CRSi) from an external ENDEC (EXT e 1): The CRSi signal is
activated high when the external ENDEC detects valid data at its receive inputs.
COLo/
COLi
TP
O
I
COLLISION OUTPUT (COLo) from the internal ENDEC (EXT e 0): When EXT e 0 the COLo
signal is internally connected between the ENDEC and MAC units. This signal generates an
active high signal when the 10 MHz collision signal from the transceiver is detected. Although this
signal is used internally by the SONIC-T, it is also provided as an output to the user.
COLLISION DETECT INPUT (COLi) from an external ENDEC (EXT e 1): The COLi signal is
activated from an external ENDEC when a collision is detected. This pin is monitored during
transmissions from the beginning of the Start of Frame Delimiter (SFD) to the end of the packet.
At the end of transmission, this signal is monitored by the SONIC-T for CD heartbeat.
RXDo/
RXDi/
EXUSR0
TP
O
I
O, Z
This pin will be TRI-STATE until the DCR has been written to. (See Section 6.4.2,
EXBUS, for more information.)
RECEIVE DATA OUTPUT (RXDo) from the internal ENDEC (EXT e 0): NRZ data output. When
EXT e 0 the RXDo signal is internally connected between the ENDEC and MAC units. This
signal must be sampled on the rising edge of the receive clock output (RXCo). Although this
signal is used internally by the SONIC-T, it is also provided as an output to the user.
RECEIVE DATA INPUT (RXDi) from an external ENDEC (EXT e 1): The NRZ data decoded
from the external ENDEC. This data is clocked in on the rising edge of RXCi.
EXTENDED USER OUTPUT (EXUSR0): When EXBUS has been set (see Section 6.4.2), this pin
becomes a programmable output. It will remain TRI-STATE until the SONIC-T becomes a bus
master, at which time it will be driven according to the value programmed in the DCR2 (see
Section 6.4.7).
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bs
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TRI
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TX a
RXCo/
RXCi/
EXUSR1
TP
TRI
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I
O, Z
This pin will be TRI-STATE until the DCR has been written to. (See Section 6.4.2,
EXBUS, for more information.)
RECEIVE CLOCK OUTPUT (RXCo) from the internal ENDEC (EXT e 0): When EXT e 0 the
RXCo signal is internally connected between the ENDEC and MAC units. This signal is the
receive clock that is derived from the Manchester data stream. It remains active 5-bit times after
the deassertion of CRSo. Although this signal is used internally by the SONIC-T it is also provided
as an output to the user.
RECEIVE CLOCK INPUT (RXCi) from an external ENDEC (EXT e 1): The receive clock that is
derived from the Manchester data stream. This signal is generated from an external ENDEC.
EXTENDED USER OUTPUT (EXUSR1): When EXBUS has been set (see Section 6.4.2), this pin
becomes a programmable output. It will remain TRI-STATE until the SONIC-T becomes a bus
master, at which time it will be driven according to the value programmed in the DCR2 (see
Section 6.4.7).
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2.0 Pin Description (Continued)
TABLE 2-1. Pin Description (Continued)
Symbol
Driver
Type
Direction
Description
NETWORK INTERFACE PINS (Continued)
TP
TRI
O
O, Z
This pin will be TRI-STATE until the DCR has been written to. (See Section 6.4.2, EXBUS, for
more information.)
TRANSMIT DATA (TXD): The serial NRZ data from the MAC unit which is to be decoded by an
external ENDEC. Data is valid on the rising edge of TXC. Although this signal is used internally by
the SONIC-T it is also provided as an output to the user.
EXTENDED USER OUTPUT (EXUSR3): When EXBUS has been set (see Section 6.4.2), this pin
becomes a programmable output. It will remain TRI-STATE until the SONIC-T becomes a bus
master, at which time it will be driven according to the value programmed in the DCR2 (see
Section 6.4.7).
TXE
TP
O
TRANSMIT ENABLE: This pin is driven high when the SONIC-T begins transmission and remains
active until the last byte is transmitted. Although this signal is used internally by the SONIC-T it is
also provided as an output to the user.
TXCo/
TXCi/
STERM
TRI
O, Z
I
I
This pin will be TRI-STATE until the DCR has been written to. (See Section 6.4.2,
EXBUS, for more information.)
TRANSMIT CLOCK OUTPUT (TXCo) from the internal ENDEC (EXT e 0): This 10 MHz transmit
clock output is derived from the 20 MHz oscillator input. When EXT e 0 the TXCo signal is
internally connected between the ENDEC and MAC units. Although this signal is used internally
by the SONIC-T, it is also provided as an output to the user.
TRANSMIT CLOCK INPUT (TXCi) from an external ENDEC (EXT e 1): This input clock from an
external ENDEC is used for shifting data out of the MAC unit serializer. This clock is nominally
10 MHz.
SYNCHRONOUS TERMINATION (STERM): When the SONIC-T is a bus master, it samples this
pin before terminating its memory cycle. This pin is sampled synchronously and may only be used
in asynchronous bus mode when BMODE e 1. (See Section 7.3.5 for more details.)
LBK/
EXUSR2
TP
TRI
O
O, Z
This pin will be TRI-STATE until the DCR has been written to. (See Section 6.4.2, EXBUS, for
more information.)
LOOPBACK (LBK): When ENDEC Loopback mode is enabled, LBK is asserted high. Although
this signal is used internally by the SONIC-T it is also provided as an output to the user.
EXTENDED USER OUTPUT (EXUSR2): When EXBUS has been set (see Section 6.4.2), this pin
becomes a programmable output. It will remain TRI-STATE until the SONIC-T becomes a bus
master, at which time it will be driven according to the value programmed in the DCR2 (see
Section 6.4.7).
PCOMP
TRI
bs
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TXD/
EXUSR3
PACKET COMPRESSION: This pin is used with the Management Bus of the DP83950, Repeater
Interface Controller (RIC). The SONIC-T can be programmed to assert PCOMP whenever there is
a CAM match, or when there is not a match. The RIC uses this signal to compress (shorten) a
received packet for management purposes and to reduce memory usage. (See the DP83950
datasheet for more details on the RIC Management Bus.) The operation of this pin is controlled
by bits 1 and 2 in the DCR2 register. PCOMP will remain TRI-STATE until these bits are written to.
This signal is asserted right after the 4th bit of the 7th byte of the incoming packet and is
deasserted one transmit clock (TXC) after CSR is driven low.
O
O, Z
PREJ
I
PACKET REJECT: This signal is used to reject received packets. When asserted low for at least
two receive clock cycles (RXC), the SONIC-T will reject the incoming packet. This pin can be
asserted up to the 2nd to the last bit of reception to reject a packet.
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2.0 Pin Description (Continued)
TABLE 2-1. Pin Description (Continued)
Symbol
Driver
Type
Direction
Description
NETWORK INTERFACE PINS (Continued)
OSCIN
OSCOUT
TP
I
CRYSTAL FEEDBACK INPUT OR EXTERNAL OSCILLATOR INPUT: This signal is used to
provide clocking signals for the internal ENDEC. A crystal may be connected to this pin along
with OSCOUT, or an oscillator module may be used. See Section 8.1.3 for more information
about using an oscillator or crystal.
O
CRYSTAL FEEDBACK OUTPUT: This signal is used to provide clocking signals for the internal
ENDEC. A crystal can be connected to this pin along with OSCIN. See Section 8.1.3 for more
information about using an oscillator or crystal.
BUS INTERFACE PINS (BOTH BUS MODES)
I
BUS MODE: This input enables the SONIC-T to be compatible with standard microprocessor
buses. The level of this pin affects byte ordering (little or big endian) and controls the operation
of the bus interface control signals. A high level (tied to VCC) selects Motorola mode (big
endian) and a low level (tied to ground) selects National/Intel mode (little endian). Note the
alternate pin definitions for AS/ADS, MRW/MWR, INT/INT, BR/HOLD, BG/HLDA, SRW/SWR,
DSACK0/RDYo, and DSACK1/RDYi. (See Sections 7.3.1, 7.3.4, and 7.3.5 for bus interface
information.)
DATA BUS: These bidirectional lines are used to transfer data on the system bus. When the
SONIC-T is a bus master, 16-bit data is transferred on D15 – D0 and 32-bit data is transferred on
D31–D0. When the SONIC-T is accessed as a slave, register data is driven onto line D15 – D0.
D31–D16 are held TRI-STATE.
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BMODE
TRI
I, O, Z
A31 – A1
TRI
O, Z
ADDRESS BUS: These signals are used by the SONIC-T to drive the DMA address after the
SONIC-T has acquired the bus. Since the SONIC-T aligns data to word boundaries, only 31
address lines are needed.
RA5 – RA0
I
REGISTER ADDRESS BUS: These signals are used to access SONIC-T’s internal registers.
When the SONIC-T is accessed, the CPU drives these lines to select the desired SONIC-T
register.
RESET
I
RESET: This signal is used to hardware reset the SONIC-T. When asserted low, the SONIC-T
transitions into the reset state after 10 transmit clocks or 10 bus clocks if the bus clock period is
greater than the transmit clock period.
O
BUS STATUS: These three signals provide a continuous status of the current SONIC-T bus
operations See Section 7.3.3 for status definitions.
TP
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S2 – S0
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D31 – D0
BSCK
I
BUS CLOCK: This clock provides the timing for the SONIC-T DMA engine.
I
CHIP SELECT: The system asserts this pin low to access the SONIC-T’s registers. The
registers are selected by placing an address on lines RA5 – RA0.
Note: Both CS and MREQ must not be asserted concurrently. If these signals are successively
asserted, there must be at least two bus clocks between the deasserting edge of the first signal
and the asserting edge of the second signal.
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CS
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2.0 Pin Description (Continued)
TABLE 2-1. Pin Description (Continued)
Symbol
Driver
Type
Direction
Description
BUS INTERFACE PINS (BOTH BUS MODES) (Continued)
DS
I
TRI
BRT
ECS
TRI
SLAVE ADDRESS STROBE: The system asserts this pin to latch the register address on lines
RA0–RA5.
O, Z
DATA STROBE: When the SONIC-T is bus master, it drives this pin low during a read cycle to
indicate that the slave device may drive data onto the bus; in a write cycle, this pin indicates that
the SONIC-T has placed valid data onto the bus.
I
BUS RETRY: When the SONIC-T is bus master, the system asserts this signal to rectify a
potentially correctable bus error. This pin has two modes. Mode 1 (the LBR in the Data
Configuration Register is set to 0): Assertion of this pin forces the SONIC-T to terminate the
current bus cycle and will repeat the same cycle after BRT has been deasserted. Mode 2 (the
LBR bit in the Data Configuration register is set to 1): Assertion of this signal forces the SONIC-T
to retry the bus operation as in Mode 1. However, the SONIC-T will not continue DMA operations
until the BR bit in the ISR is reset.
O, Z
EARLY CYCLE START: This output gives the system earliest indication that a memory operation
is occurring. This signal is driven low at the rising edge of T1 and high at the falling edge of T1.
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SAS
SHARED-MEMORY ACCESS PINS
SMACK
TP
I
MEMORY REQUEST: The system asserts this signal low when it attempts to access the sharedbuffer RAM. The on-chip arbiter resolves accesses between the system and the SONIC-T.
Note: Both CS and MREQ must not be asserted concurrently. If these signals are successively
asserted, there must be at least two bus clocks between the deasserting edge of the first signal
and the asserting edge of the second signal.
O
SLAVE AND MEMORY ACKNOWLEDGE: SONIC-T asserts this dual function pin low in response
to either a Chip Select (CS) or a Memory Request (MREQ) when the SONIC-T’s registers or its
buffer memory is available for accessing. This pin can be used for enabling bus drivers for dualbus systems.
ol
MREQ
BUS INTERFACE PINS (NATIONAL/INTEL MODE, BMODE e 0)
TRI
O, Z
ADDRESS STROBE (ADS): The rising edge indicates valid status and address.
MWR
TRI
O, Z
MEMORY WRITE/READ STROBE MWR: When the SONIC-T has acquired the bus, this signal
indicates the direction of the data transfer. The signal is low during a read cycle and high during a
write cycle.
INT
TP
HOLD
TP
O
INTERRUPT (INT): Indicates that an interrupt (if enabled) is pending from one of the sources
indicated by the Interrupt Status register. Interrupts that are disabled in the Interrupt Mask register
will not activate this signal.
O
HOLD REQUEST (HOLD): The SONIC-T drives this pin high when it intends to use the bus and is
driven low when inactive.
I
HOLD ACKNOWLEDGE (HLDA): This signal is used to inform the SONIC-T that it has attained
the bus. When the system asserts this pin high, the SONIC-T has gained ownership of the bus.
O
HLDA
bs
ADS
BGACK
TRI
O, Z
BUS GRANT ACKNOWLEDGE: This pin is only used when BMODE e 1.
SWR
I
SLAVE READ/WRITE STROBE (SWR): The system asserts this pin to indicate whether it will
read from or write to the SONIC-T’s registers. This signal is asserted low during a read and high
during a write.
RDYi
I
READY INPUT (RDYi, BMODE e 0): When the SONIC-T is a bus master, the system asserts this
signal high to insert wait-states and low to terminate the memory cycle. This signal is sampled
synchronously or asynchronously depending on the state of the SBUS bit. (See Sections 7.3.5
and 6.4.2 for details.)
O
READY OUTPUT (RDYo): When a register is accessed, the SONIC-T asserts this signal to
terminate the slave cycle.
RDYo
TP
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2.0 Pin Description (Continued)
TABLE 2-1. Pin Description (Continued)
Symbol
Driver
Type
Direction
Description
BUS INTERFACE PINS (MOTOROLA MODE, BMODE e 1)
AS
TRI
O, Z
ADDRESS STROBE (AS): The falling edge indicates valid status and address. The rising edge
indicates the termination of the memory cycle.
MRW
TRI
O, Z
MEMORY READ/WRITE STROBE (MRW): When the SONIC-T has acquired the bus, this signal
indicates the direction of the data transfer. This signal is high during a read cycle and low during a
write cycle.
INT
OC
O, Z
INTERRUPT (INT): Indicates that an interrupt (if enabled) is pending from one of the sources
indicated by the Interrupt Status register. Interrupts that are disabled in the Interrupt Mask
register will not activate this signal.
BR
OC
O, Z
BUS REQUEST (BR): The SONIC-T asserts this pin low when it attempts to gain access to the
bus. When inactive this signal is at TRI-STATE.
O, Z
BUS GRANT ACKNOWLEDGE: The SONIC-T asserts this pin low when it has determined that it
can gain ownership of the bus. The SONIC-T checks the following conditions before driving
BGACK:
1. BG has been received through the bus arbitration process.
2. AS is deasserted, indicating that the previous master has finished using the bus.
3. DSACK0 and DSACK1 are deasserted, indicating that the previous slave device is off the bus.
4. BGACK is deasserted, indicating that the previous master is off the bus.
I
SLAVE READ/WRITE (SRW): The system asserts this pin to indicate whether it will read from or
write to the SONIC-T’s registers. This signal is asserted high during a read and low during a write.
I, O, Z
I, O, Z
DATA AND SIZE ACKNOWLEDGE 0 AND 1 (DSACK0,1 BMODE e 1): These pins are the
output slave acknowledge to the system when the SONIC-T registers have been accessed and
the input slave acknowledgement when the SONIC-T is busmaster. When a register has been
accessed, the SONIC-T drives both DSACK0 and DSACK1 pins low to terminate the slave cycle.
(Note that the SONIC-T responds as a 32-bit peripheral by driving both DSACK0 and DSACK1
low, but drives data only on lines D0 – D15. Lines D16 – D32 are driven, but invalid.)
When the SONIC-T is bus master, it samples these pins before terminating its memory cycle.
When SONIC-T is in 32-bit bus master mode, both DSACK0 and DSACK1 must be asserted to
terminate the cycle. However, if the SONIC-T is in 16-bit bus master mode, only the assertion of
DSACK1 is required to terminate the cycle. These pins are sampled synchronously or
asynchronously depending on the state of the SBUS bit in the Data Configuration register. (See
Section 7.3.5 for details.) Note that the SONIC-T does not allow dynamic bus sizing. Bus size is
statically defined in the Data Configuration register (see Section 6.4.2).
TRI
SRW
DSACK0
DSACK1
TRI
TRI
USER DEFINABLE PINS
TRI
I, O, Z
USER DEFINE 0,1: These signals are inputs when the SONIC-T is hardware reset and are
outputs when the SONIC-T is a bus master (HLDA or BGACK asserted). When hard reset (RST)
is low, these signals input directly into bits 8 and 9 of the Data Configuration Register (DCR)
respectively. The levels on these pins are latched on the rising edge of RST. During busmaster
operations (HLDA or BGACK is active), these pins are outputs whose levels are programmable
through bits 11 and 12 of the DCR respectively. The USR0,1 pins should be pulled up to VCC or
pulled down to ground. A 4.7 kX pull-up resistor is recommended.
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USR0,1
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BUS GRANT (BG): This signal is a bus grant. The system asserts this pin low to indicate potential
mastership of the bus.
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BGACK
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BG
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2.0 Pin Description (Continued)
TABLE 2-1. Pin Description (Continued)
Symbol
Driver
Type
Direction
Description
UNCONNECTED PINS
TEST
I
FACTORY TEST INPUT: Used to check the chip’s internal functions. This pin should be left
unconnected during normal operation.
POWER AND GROUND PINS
POWER: The a 5V power supply for the digital portions of the SONIC-T.
TXVCC
RXVCC
PLLVCC
OSCVCC
POWER: These pins are the a 5V power supply for the SONIC-T ENDEC unit. These pins must
be tied to VCC even if the internal ENDEC is not used.
RXTVCC
TPVCC
POWER: These pins are the a 5V power supply for the SONIC-T TPI unit. These pins must be
tied to VCC even if the internal TPI module is not used.
GND 1 – 10
GNDL
GND
GROUND: These pins are the ground references for the digital portions of the SONIC-T.
TXGND
RXGND
PLLGND
OSCGND
TPGND
GROUND: These pins are the ground references for the SONIC-T ENDEC unit and TPI module.
These pins must be tied to ground even if the internal ENDEC unit and/or the TPI module are
not used.
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VCC 1 – 9
VCCL
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3.0 Functional Description
The SONIC-T (Figure 3-1) consists of a twisted pair interface (TPI) module, an encoder/decoder (ENDEC) unit, a
media access control (MAC) unit, separate receive and
transmit FIFOs, a system buffer management engine, and a
user programmable system bus interface unit on a single
chip. SONIC-T is highly pipelined providing maximum system level performance. This section provides a functional
overview of the SONIC-T.
d. the Jabber, which disables the transmitter if it attempts to
transmit a longer than legal packet, and
e. the Transmitter, which utilizes a Transmit Driver and a
Pre-emphasis to transmit Manchester encoded data to
the twisted pair network via summing resistors and a
transformer/filter.
Smart Squelch: The SONIC-T Controller implements an intelligent receive squelch on the RXI g differential inputs to
ensure that impulse noise on the receive inputs will not be
mistaken for a valid signal.
The squelch circuitry employs a combination of amplitude
and timing mesurements to determine the validity of data on
the twisted pair inputs. There are two voltage level options
for the smart squelch. One mode, 10BASE-T mode (Figure
3-2) , uses levels that meet the 10BASE-T specification. The
second mode, reduced squelch mode, uses a lower squelch
threshold level, and can be used in longer cable applications where smaller signal levels may be applied. The
squelch level mode can be selected using the LOWSQL
input pin (see Section 2.0).
3.1 TWISTED PAIR INTERFACE MODULE
The TPI consists of five main logic functions:
a. the Smart Squelch, which determines when valid data is
present on the differential receive inputs (RXI g ),
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b. the Collision Detector, which checks for simultaneous
transmission and reception of data on the differential
transmit output (TXO g ) and differential receive input
(RXI g ) pins,
c. the Link Detector/Generator, which checks the integrity
of the cable connecting the two twisted pair modules,
TL/F/12597 – 4
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FIGURE 3-1. SONIC-T Block Diagram
TL/F/12597 – 5
FIGURE 3-2. Twisted Pair Squelch Waveform (10BASE-T Mode)
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3.0 Functional Description (Continued)
Transmitter: The transmitter consists of four signals, the
true and complement Manchester encoded data (TXO g )
and these signals delayed by 50 ns (TXOd g ).
The signal at the start of the packet is checked by the smart
squelch, and any pulses not exceeding the squelch level
(either positive or negative, depending upon polarity) will be
rejected. Once this first squelch level is overcome correctly,
the opposite squelch level must then be exceeded within
150 ns. Finally, the signal must exceed the original squelch
level within the next 150 ns time period to ensure that the
input waveform will not be rejected. The checking procedure typically results in the loss of three bits at the beginning of each packet.
Only after all these conditions have been satisfied will a
control signal be generated to indicate to the remainder of
the circuitry that valid data is present. At this time the smart
squelch circuitry is reset.
In the reduced squelch mode the operation is identical except that the lower squelch levels shown in Figure 3-2 are
used.
Valid data is considered to be present until either squelch
level has not been generated for a time period of more than
150 ns indicating the End of Packet. Once good data has
been detected, the squelch levels are reduced to minimize
the effect of noise causing premature End of Packet detection.
Collision: A collision is detected by the TPI module when
the receive and transmit channels are simultaneously active. If the TPI is receiving when a collision is detected it is
reported to the controller immediately. If, however, the TPI
is transmitting when a collision is detected, the collision is
not reported until seven bits have been received while in the
collision state. This prevents a collision being reported incorrectly due to noise on the network. The signal to the
controller remains for the duration of the collision.
Approximately 1 ms after the transmission of each packet, a
signal called the Signal Quality Error (SQE) is generated
which typically consists of 10 cycles of a 10 MHz signal.
This 10 MHz signal, also called the Heartbeat, ensures the
continued functioning of the collision circuitry.
Link Detector/Generator: The link generator is a timer circuit that generates a link pulse, produced by the transmitter
section, as defined by the 10BASE-T specification. The
100 ns wide pulse is transmitted on the TXO a output every
16 ms in the absence of transmit data.
This link pulse is used to check the integrity of the connection to the remote MAU. The link detection circuit checks for
valid pulses that are received from the remote unit. If valid
link pulses are not received, the link detector will disable the
transmit, receive, and collision detection functions.
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These four signals are resistively combined (see Section
8.2), TXO a with TXOdb and TXOb with TXOd a , in a configuration referred to as pre-emphasis. This digital pre-emphasis is required to compensate for the low-pass filter effects of the twisted pair cable which causes greater attenuation to the 10 MHz (50 ns) pulses of the Manchester encoded waveform than the 5 MHz (100 ns) pulses.
TL/F/12597 – 6
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FIGURE 3-3. Typical Summed Transmit Waveform
The signal with pre-emphasis is generated by resistively
combining TXO a and TXOdb (Figure 3-3) . This signal
along with its complement is passed to the transmit filter.
Status Information: Status information is provided by the
SONIC-T Controller on the RXLED, TXLED, COLED,
LINKLED, and POLED outputs as described in the pin description table. These outputs (Figure 3-4) are suitable for
driving status LEDs.
The LINKLED output can directly drive a LED to show that
there is a good twisted pair link. For normal conditions the
LED will be on. The link integrity function can be disabled by
asserting the LNKDIS input pin.
Jabber: The jabber timer monitors the transmitter and disables the transmission if the transmitter is active for greater
than 26 ms. The transmitter is then disabled for the whole
time that the ENDEC module’s internal transmit enable is
asserted. This signal has to be deasserted for approximately 750 ms (the unjab time) before the Jabber re-enables the
transmit outputs.
TL/F/12597 – 7
FIGURE 3-4. Typical SONIC-T LED Connection
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3.0 Functional Description (Continued)
Manchester Encoder and Differential Output Driver:
During transmission to the network, the ENDEC unit translates the NRZ serial data from the MAC unit into differential
pair Manchester encoded data. To perform this operation
the NRZ bit stream from the MAC unit is passed through the
Manchester encoder block of the ENDEC unit. Once the bit
stream is encoded, it is transmitted out differentially to the
transmit differential pair through the transmit driver.
The SONIC-T Controller is compatible with the IEEE 802.3
‘‘full-step’’ standard. That is, the Transmit a and Transmitb
differential outputs are at equal voltages while they are idle
at the primary of the isolation transformer at the network
interface. This voltage relationship provides a zero differential voltage for operation with transformer coupled loads.
(See Section 8.1 for network interfacing considerations.)
Manchester Decoder: During reception from the network,
the differential receive data from the transceiver is converted from Manchester encoded data into NRZ serial data and
a receive clock, which are sent to the receive data and
clock inputs of the MAC unit. To perform this operation, the
signal is passed to the PLL decoder block once it is received from the differential receiver. The PLL decodes the
data and generates a data receive clock and a NRZ serial
data stream to the MAC unit.
Data typically becomes valid from the decoder within 6 bit
times, and the decoder detects the end of a frame when no
more mid-bit transitions are detected. (See Section 8.1 for
network interfacing considerations.)
Special Signals: In addition to performing the Manchester
encoding and decoding function, the ENDEC unit provides
control and clocking signals to the MAC unit. The ENDEC
sends a carrier sense (CRS) signal that indicates to the
MAC unit that data is present from the network on the
ENDEC’s receive differential pair. When the ENDEC’s collision receiver detects a 10 MHz signal on the differential
collision input pair, the ENDEC unit provides the MAC unit
with a collision detection signal (COL). COL indicates that a
collision is taking place somewhere on the network.
3.2 IEEE 802.3 ENCODER/DECODER (ENDEC) UNIT
The Encoder/Decoder (ENDEC) unit is the interface between either the Twisted Pair Interface Module or the Ethernet transceiver and the Media Access Control (MAC) unit.
Providing the Manchester data encoding and decoding
functions for IEEE 802.3 Ethernet, Thin-Ethernet, or Twisted
Pair types of local area networks, the ENDEC operations of
SONIC-T are identical to those of the DP83910A CMOS
Serial Network Interface device. During transmission, the
ENDEC unit combines non-return-zero (NRZ) data from the
MAC section and clock pulses to produce Manchester data
and sends the converted data differentially to the transceiver. Conversely, during reception, an analog Phase Lock
Loop (PLL) decodes the Manchester data into both NRZ
formatted data and a receive clock. The SONIC-T ENDEC
unit is a functionally complete Manchester encoder/decoder incorporating a balanced driver and receiver, an on-board
crystal oscillator, a collision signal translator, and a diagnostic loopback. The features include:
# Compatibility with Ethernet I and II, IEEE 802.3
10BASE5, 10BASE2, and 10BASE-T
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# 10Mb/s Manchester encoding/decoding with receive
clock recovery
# No precision components requirement
# Loopback capability for diagnostics
# Squelch circuitry at the receive and collision inputs reject
noise
# Connection to the transceiver (Attachment Unit Interface) cable via external pulse transformer
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3.2.1 ENDEC Operation
The primary function of the ENDEC unit (Figure 3-5) is to
perform the encoding and decoding necessary for compatibility between the differential pair Manchester encoded data
of the transceiver and the Non-Return-to-Zero (NRZ) serial
data of the MAC unit data line. In addition to encoding and
decoding the data stream, the ENDEC also supplies all of
the special signals (e.g., collision detect, carrier sense, and
clocks) necessary to the MAC unit. The signals provided to
the MAC unit from the on-chip ENDEC are also provided as
outputs to the user.
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FIGURE 3-5. Block Diagram of Ethernet ENDEC
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3.0 Functional Description (Continued)
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3.0 Functional Description (Continued)
Address Field to the addresses stored in the chip’s Content
Addressable Memory (CAM) address registers. If a match
occurs, the deserializer passes the remainder of the packet
to the receive FIFO. The packet is decapsulated when the
carrier sense input pin (CRS) goes inactive. At the end of
reception the receive section checks the following:
Ð Frame alignment errors
Ð CRC errors
Ð Length errors (runt packets)
The appropriate status is indicated in the Receive Control
register (see Section 6.4.3). In loopback operations, the receive section operates the same as during normal reception.
During transmission, the receive section remains active to
allow monitoring of the self-received packet. The Cyclic Redundancy Code (CRC) checker operates as normal, and the
Source Address field is compared with the CAM address
entries. Status of the CRC check and the source address
comparison is indicated by the PMB bit in the Transmit Control register (see Section 6.4.4). No data is written to the
receive FIFO during transmit operations.
The receive section consists of the following blocks detailed
below.
Receive State Machine (RSM): The RSM insures the proper sequencing for normal reception and self-reception during transmission. When the network is inactive, the RSM
remains in an idle state continually monitoring for network
activity. If the network becomes active, the RSM allows the
deserializer to write data into the receive FIFO. During this
state, the following conditions may prevent the complete
reception of the packet.
Ð FIFO OverrunÐThe receive FIFO has been completely
filled before the SONIC-T could buffer the data to memory.
Ð CAM Address MismatchÐThe packet is rejected because of a mismatch between the destination address of
the packet and the address in the CAM.
Ð Memory Resource ErrorÐThere are no more resources
(buffers or descriptors) available for buffering the incoming packets.
Ð Collision or Other ErrorÐA collision occurred on the network or some other error, such as a CRC error, occurred
(this is true if the SONIC-T has been told to reject packets on a collision, or reject packets with errors).
If these conditions do not occur, the RSM processes the
packet indicating the appropriate status in the Receive Control register.
The ENDEC also provides both the receive and transmit
clocks to the MAC unit. The transmit clock is one half of the
oscillator input and the receive clock is extracted from the
input data by the PLL.
Oscillator: The oscillator generates the 10 MHz transmit
clock signal for network timing. The oscillator is controlled
by a parallel resonant crystal or by an external clock (see
Section 8.1.3). The 20 MHz output of the oscillator is divided
by 2 to generate the 10 MHz transmit clock (TXC) for the
MAC section. The oscillator also provides an internal clock
signal for the encoding and decoding circuits.
Loopback Functions: The SONIC-T provides three loopback modes which allow for loopback testing at the MAC,
ENDEC and external transceiver level (see Section 3.7 for
details). It is important to note that when the SONIC-T is
transmitting, the transmitted packet will always be looped
back by the external transceiver. The SONIC-T takes advantage of this to monitor the transmitted packet. See the
explanation of the Receive State Machine in Section 3.3.1
for more information about monitoring transmitted packets.
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3.2.2 Selecting an External ENDEC
An option is provided on SONIC-T to disable the on-chip
ENDEC unit and use an external ENDEC. The internal IEEE
802.3 ENDEC can be bypassed by connecting the EXT pin
to VCC (EXT e 1). In this mode the MAC signals are redirected out from the chip, allowing an external ENDEC to be
used. See Section 2.0 for the alternate pin definitions.
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3.3 MEDIA ACCESS CONTROL (MAC) UNIT
The Media Access Control (MAC) unit performs the control
functions for the media access of transmitting and receiving
packets over Twisted Pair or AUI. During transmission, the
MAC unit frames information from the transmit FIFO and
supplies serialized data to the ENDEC unit. During reception, the incoming information from the ENDEC unit is deserialized, the frame checked for valid reception, and the data
is transferred to the receive FIFO. Control and status registers on the SONIC-T govern the operation of the MAC unit.
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3.3.1 MAC Receive Section
The receive section (Figure 3-6) controls the MAC receive
operations during reception, loopback, and transmission.
During reception, the deserializer goes active after detecting
the 2-bit Start of Frame Delimiter (SFD) pattern (see Section
4.1). It then frames the incoming bits into octet boundaries
and transfers the data to the 32-byte receive FIFO. Concurrently the address comparator compares the Destination
TL/F/12597 – 9
FIGURE 3-6. MAC Receiver
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3.0 Functional Description (Continued)
stream onto the network in conformance with the IEEE
802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) standard. The Transmit Section consists of
the following blocks.
Transmit State Machine (TSM): The TSM controls the
functions of the serializer, preamble generator, and JAM
generator. It determines the proper sequence of events that
the transmitter follows under various network conditions. If
no collision occurs, the transmitter prefixes a 62-bit preamble and 2-bit Start of Frame Delimiter (SFD) at the beginning
of each packet and then sends the serialized data. At the
end of the packet, an optional 4-byte CRC pattern is appended. If a collision occurs, the transmitter switches from
transmitting data to sending a 4-byte Jam pattern to notify
all nodes that a collision has occurred. Should the collision
occur during the preamble, the transmitter waits for it to
complete before jamming. After the transmission has completed, the transmitter writes status in the Transmit Control
register (see Section 6.4.4).
Protocol State Machine: The protocol state machine assures that the SONIC-T obeys the CSMA/CD protocol. Before transmitting, this state machine monitors the carrier
sense and collision signals for network activity. If any other
nodes are currently transmitting, the SONIC-T defers its
transmission until the network is quiet. It then transmits after
its Interframe Gap Timer (9.6 ms) has expired. The Interframe Gap time is divided into two portions. During the first
6.4 ms, any new network activity will restart the Interframe
Gap timer. Beyond this time, however, network activity is
ignored and the state machine waits the remaining 3.2 ms
before transmitting. If the SONIC-T experiences a collision
during a transmission, it switches from transmitting data to
transmitting a 4-byte JAM pattern (4 bytes of all 1’s), before
ceasing to transmit. The SONIC-T then waits a random
number of slot times (51.2 ms) determined by the Truncated
Binary Exponential Backoff Algorithm before reattempting
another transmission. In this algorithm, the number of slot
times to delay before the nth retransmission is chosen to be
a random integer r in the range of:
0 s r s 2k
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During transmission of a packet from the SONIC-T, the
transceiver will always loop the packet back to the
SONIC-T. The SONIC-T will use this to monitor the packet
as it is being transmitted. The CRC and source address of
the looped back packet are checked with the CRC and
source address that were transmitted. If they do not match,
an error bit is set in the status of the transmitted packet (see
Packet Monitored Bad, PMB, in the Transmit Control Register, Section 6.4.4). Data is not written to the receive FIFO
during this monitoring process unless a Loopback mode has
been selected (see Section 3.7).
Receive Logic: The receive logic contains the command,
control, and status registers that govern the operations of
the receive section. It generates the control signals for writing data to the receive FIFO, processes error signals obtained from the CRC checker and the deserializer, activates
the ‘‘packet reject’’ signal to the RSM for rejecting packets,
and posts the applicable status in the Receive Control register.
Deserializer: This section deserializes the serial input data
stream and provides a byte clock for the address comparator and receive logic. It also synchronizes the CRC checker
to begin operation (after SFD is detected), and checks for
proper frame alignment with respect to CRS going inactive
at the end of reception.
Address Comparator: The address comparator latches the
Destination Address (during reception or loopback) or
Source Address (during transmission) and determines
whether the address matches one of the entries in the CAM.
CRC Checker: The CRC checker calculates the 4-byte
Frame Check Sequence (FCS) field from the incoming data
stream and compares it with the last 4-bytes of the received
packet. The CRC checker is active for both normal reception and self-reception during transmission.
Content Addressable Memory (CAM): The CAM contains
16 user programmable entries and 1 pre-programmed
Broadcast address entry for complete filtering of received
packets. The CAM can be loaded with any combination of
Physical and Multicast Addresses (see Section 4.2). See
Section 6.1 for the procedure on loading the CAM registers.
where k e min(n,10)
If a collision occurs on the 16th transmit attempt, the
SONIC-T aborts transmitting the packet and reports an ‘‘Excessive Collisions’’ error in the Transmit Control register.
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3.3.2 MAC Transmit Section
The transmit section (Figure 3-7) is responsible for reading
data from the transmit FIFO and transmitting a serial data
TL/F/12597 – 10
FIGURE 3-7. MAC Transmitter
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3.0 Functional Description (Continued)
Serializer: After data has been written into the 32-byte
transmit FIFO, the serializer reads byte wide data from the
FIFO and sends a NRZ data stream to the Manchester encoder. The rate at which data is transmitted is determined
by the transmit clock (TXC). The serialized data is transmitted after the SFD.
Preamble Generator: The preamble generator prefixes a
62-bit alternating ‘‘1,0’’ pattern and a 2-bit ‘‘1,1’’ SFD pattern at the beginning of each packet. This allows receiving
nodes to synchronize to the incoming data. The preamble is
always transmitted in its entirety even in the event of a collision. This assures that the minimum collision fragment is 96
bits (64 bits of normal preamble, and 4 bytes, or 32 bits of
JAM pattern).
CRC Generator: The CRC generator calculates the 4-byte
FCS field from the transmitted serial data stream. If enabled, the 4-byte FCS field is appended to the end of the
transmitted packet (see Section 4.6).
For bridging or switched ethernet applications the CRC
Generator can be inhibited by setting bit 13 in the Transmit
Control Register (Section 6.4.4). This feature is used when
an ethernet segment has already received a packet with a
CRC appended and needs to forward it another ethernet
segment.
Jam Generator: The Jam generator produces a 4-byte pattern of all 1’s to assure that all nodes on the network sense
the collision. When a collision occurs, the SONIC-T stops
transmitting data and enables the Jam generator. If a collision occurs during the preamble, the SONIC-T finishes
transmitting the preamble before enabling the Jam generator (see Preamble Generator above).
32-Bit Long Word
31
24
23
Byte 3
16
Byte 2
15
8
7
Byte 1
0
Byte 0
MSB
LSB
Big Endian (Motorola) Mode (BMODE e 1): The byte orientation for received and transmitted data in the RBA and
TBA is as follows:
16-Bit Word
15
8
7
0
Byte 0
Byte 1
LSB
MSB
32-Bit Long Word
31
24
Byte 0
23
16
Byte 1
15
Byte 2
LSB
8
7
0
Byte 3
MSB
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3.5 FIFO AND CONTROL LOGIC
The SONIC-T incorporates two independent 32-byte FIFOs
for transferring data to/from the system interface and from/
to the network. The FIFOs, providing temporary storage of
data, free the host system from the real-time demands on
the network.
The way in which the FIFOS are emptied and filled is controlled by the FIFO threshold values and the Block Mode
Select bits (BMS) (see Section 6.4.2). The threshold values
determine how full or empty the FIFOs are allowed to be
before the SONIC-T will request access of the bus to get
more data from memory or buffer more data to memory.
When Block Mode is enabled, the number of bytes transferred is determined by the threshold value. For example, if
the threshold for the receive FIFO is 4 words, then the SONIC-T will always transfer 4 words from the receive FIFO to
memory. If Empty/Fill mode is enabled, however, the number of bytes transferred is the number required to fill the
transmit FIFO or empty the receive FIFO. The manner in
which the threshold affects reception and transmission of
packets is discussed below in Sections 3.5.1 and 3.5.2.
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3.3.3 Full Duplex Operation
When configured for Full Duplex operation the TSM and
RSM allow simultaneous transmission and reception of
packets. In Full Duplex mode the RSM operates as described earlier. Transmitted packets won’t be monitored.
The TSM will operate as described earlier, except that the
activity on the receive inputs will be ignored.
3.4 DATA WIDTH AND BYTE ORDERING
The SONIC-T can be programmed to operate with either
32-bit or 16-bit wide memory. The data width is configured
during initialization by programming the DW bit in the Data
Configuration Register (DCR) (see Section 6.4.2). If the
16-bit data path is selected, data is driven on pins D15–D0.
The SONIC-T also provides both Little Endian and Big Endian byte-ordering capability for compatibility with National/Intel or Motorola microprocessors respectively by selecting
the proper level on the Bus Mode (BMODE) pin.
Little Endian (National/Intel) Mode (BMODE e 0): The
byte orientation for received and transmitted data in the Receive Buffer Area (RBA) and Transmit Buffer Area (TBA) of
system memory is as follows:
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3.5.1 Receive FIFO
To accommodate the different transfer rates, the receive
FIFO (Figure 3-8) serves as a buffer between the 8-bit network (deserializer) interface and the 16/32-bit system interface. The FIFO is arranged as a 4-byte wide by 8 deep
memory array (8-long words, or 32 bytes) controlled by
three sections of logic. During reception, the Byte Ordering
logic directs the byte stream from the deserializer into the
FIFO using one of four write pointers. Depending on the
selected byte-ordering mode, data is written either least significant byte first or most significant byte first to accommodate little or big endian byte-ordering formats respectively.
As data enters the FIFO, the Threshold Logic monitors the
number of bytes written in from the deserializer. The programmable threshold (RFT1,0 in the Data Configuration
Register, see Section 6.4.2) determines the number of
words (or long words) written into the FIFO from the MAC
unit before a direct memory access (DMA) request for system memory occurs. When the threshold is reached, the
16-Bit Word
15
8
7
0
Byte 1
Byte 0
MSB
LSB
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3.0 Functional Description (Continued)
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FIGURE 3-8. Receive FIFO
3.5.2 Transmit FIFO
Similar to the Receive FIFO, the Transmit FIFO (Figure 3-9)
serves as a buffer between the 16/32-bit system interface
and the network (serializer) interface. The Transmit FIFO is
also arranged as a 4 byte by 8 deep memory array (8 long
words or 32 bytes) controlled by three sections of logic.
Before transmission can begin, the Buffer Management Engine fetches a programmed number of 16- or 32-bit words
from memory and transfers them to the FIFO. The Buffer
Management Engine writes either the upper or lower half
(16 bits) into the FIFO for 16-bit mode or writes the complete long word (32 bits) during 32-bit mode.
The Threshold Logic monitors the number of bytes as they
are written into the FIFO. When the threshold has been
reached, the Transmit Byte Ordering state machine begins
reading bytes from the FIFO to produce a continuous byte
stream for the serializer. The threshold is met when the
number of bytes in the FIFO is greater than the value of the
threshold. For example, if the transmit threshold is 4 words
(8 bytes), the Transmit Byte Ordering state machine will not
begin reading bytes from the FIFO until there are 9 or more
bytes in the buffer. The Buffer Management Engine continues replenishing the FIFO until the end of the packet. It
does this by making multiple DMA requests to the system
interface. Whenever the number of bytes in the FIFO is
equal to or less than the threshold value, the Buffer Management Engine will do a DMA request. If Block Mode is
set, then after each request has been granted by the system, the Buffer Management Engine will transfer a number
of bytes equal to the threshold value into the FIFO. If Empty/Fill Mode is set, the FIFO will be completely filled in one
DMA request.
Since data may be organized in big or little endian byte ordering format, the Transmit Byte Ordering state machine
uses one of four read pointers to locate the proper byte
within the 4 byte wide FIFO. It also determines the valid
number of bytes in the FIFO. For packets which begin or
end at odd bytes in the FIFO, the Buffer Management Engine writes extraneous bytes into the FIFO. The Transmit
Byte Ordering state machine detects these bytes and only
transfers the valid bytes to the serializer. The Buffer Management Engine can read data from memory on any byte
boundary (see Section 5.3). See Section 5.5 for more information on transmit buffering.
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Threshold Logic enables the Buffer Management Engine to
read a programmed number of 16- or 32-bit words (depending upon the selected data width) from the FIFO and transfer them to the system interface (the system memory) using
DMA. The threshold is reached when the number of bytes in
the receive FIFO is greater than the value of the threshold.
For example, if the threshold is 4 words (8 bytes), then the
Threshold Logic will not cause the Buffer Management Engine to write to memory until there are more than 8 bytes in
the FIFO.
The Buffer Management Engine reads either the upper or
lower half (16 bits) of the FIFO in 16-bit mode or reads the
complete long word (32 bits) in 32-bit mode. If, after the
transfer is complete, the number of bytes in the FIFO is less
than the threshold, then the SONIC-T is done. This is always the case when the SONIC-T is in Empty/Fill Mode. If,
however, for some reason (e.g., latency on the bus) the
number of bytes in the FIFO is still greater than the threshold value, the Threshold Logic will cause the Buffer Management Engine to do a DMA request to write to memory
again. This latter case is usually only possible when the
SONIC-T is in Block Mode.
When in Block Mode, each time the SONIC-T requests the
bus, only a number of bytes equal to the threshold value will
be transferred. The Threshold Logic continues to monitor
the number of bytes written in from the deserializer and enables the Buffer Management Engine every time the threshold has been reached. This process continues until the end
of the packet.
Once the end of the packet has been reached, the serializer
will fill out the last word (16-bit mode) or long word (32-bit
mode) if the last byte did not end on a word or long word
boundary respectively. The fill byte will be 0FFh. Immediately after the last byte (or fill byte) in the FIFO, the received
packets status will be written into the FIFO. The entire packet, including any fill bytes and the received packet status will
be buffered to memory. When a packet is buffered to memory by the Buffer Management Engine, it is always taken
from the FIFO in words or long words and buffered to memory on word (16-bit mode) or long word (32-bit mode)
boundaries. Data from a packet cannot be buffered on odd
byte boundaries for 16-bit mode, and odd word boundaries
for 32-bit mode (see Section 5.3). For more information on
the receive packet buffering process, see Section 5.4.
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3.0 Functional Description (Continued)
TL/F/12597 – 12
FIGURE 3-9. Transmit FIFO
MAC loopback, and the CSMA/CD MAC protocol is not
completely followed.
ENDEC Loopback: Transmitted data is looped back at the
ENDEC. If the internal ENDEC is used, data is switched
from the transmit section of the ENDEC to the receive section (Figure 3-5) . Data is not transmitted from the chip and
the collision lines, CD g , are ignored, hence, network activity does not affect ENDEC loopback. The LBK signal from
the MAC tells the internal ENDEC to go into loopback mode.
If an external ENDEC is used, it should operate in loopback
mode when the LBK signal is asserted. CSMA/CD MAC
protocol is followed even though data is not transmitted
from the chip.
Transceiver Loopback: Transmitted data is looped back at
the external transceiver (which is always the case regardless of the SONIC-T’s loopback mode). CSMA/CD MAC
protocol is followed since data will be transmitted from the
chip. This means that transceiver loopback is affected by
network activity. The basic difference between Transceiver
Loopback Mode and the other loopback modes is that the
SONIC-T loads the receive FIFO and buffers the packet to
memory. In normal operations, the SONIC-T only monitors
the packet that is looped back by the transceiver, but does
not fill the receive FIFO and buffer the packet.
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3.6 STATUS AND CONFIGURATION REGISTERS
The SONIC-T contains a set of status/control registers for
conveying status and control information to/from the host
system. The SONIC-T uses these registers for loading commands generated from the system, indicating transmit and
receive status, buffering data to/from memory, and providing interrupt control. Each register is 16 bits in length. See
Section 6.0 for a description of the registers.
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3.7 BUS INTERFACE
The system interface (Figure 3-10) consists of the pins necessary for interfacing to a variety of buses. It includes the
I/O drivers for the data and address lines, bus access control for standard microprocessors, ready logic for synchronous or asynchronous systems, slave access control, interrupt control, and shared-memory access control. The functional signal groups are shown in Figure 3-10 . See Section
7.0 for a complete description of the SONIC-T bus interface.
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3.8 LOOPBACK AND DIAGNOSTICS
The SONIC-T provides three loopback modes for self-testing from the controller interface to the transceiver interface.
The loopback function is provided to allow self-testing of the
chip’s internal transmit and receive operations. During loopback, transmitted packets are routed back to the receive
section of the SONIC-T where they are filtered by the address recognition logic and buffered to memory if accepted.
Transmit and receive status and interrupts remain active
during loopback. This means that when using loopback, it is
as if the packet was transmitted and received by two separate chips that are connected to the same bus and memory.
MAC Loopback: Transmitted data is looped back at the
MAC. Data is not sent from the MAC to either the internal
ENDEC or an external ENDEC (the external ENDEC interface pins will not be driven), hence, data is not transmitted
from the chip. Even though the ENDEC is not used in MAC
loopback, the ENDEC clock (an oscillator or crystal for the
internal ENDEC or TXC for an external ENDEC) must be
driven. Network activity, such as a collision, does not affect
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3.8.1 Loopback Procedure
The following procedure describes the loopback operation.
1. Initialize the Transmit and Receive Area as described in
Sections 5.4 and 5.5.
2. Load one of the CAM address registers (see Section 6.1),
with the Destination Address of the packet if you are verifying the SONIC-T’s address recognition capability.
3. Load one of the CAM address registers with the Source
Address of the packet if it is different than the Destination
Address to avoid getting a Packet Monitored Bad (PMB)
error in the Transmit Status (see Section 6.4.4).
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3.0 Functional Description (Continued)
4. Program the Receive Control register with the desired receive filter and the loopback mode (LB1, LB0). In case of
transceiver loopback, besides setting LB1 and LB0 to 1,
the XWRAP bit in the DCR2 must also set to 1.
5. Issue the transmit command (TXP) and enable the receiver (RXEN) in the Command register.
The SONIC-T completes the loopback operation after the
packet has been completely received (or rejected if there is
an address mismatch). The Transmit Control and Receive
Control registers treat the loopback packet as it would in
normal operation and indicate status accordingly. Interrupts
are also generated if enabled in the Interrupt Mask register.
3.9 NETWORK MANAGEMENT FUNCTIONS
The SONIC-T fully supports the Layer Management IEEE
802.3 standard to allow a node to monitor the overall performance of the network. These statistics are available on a
per packet basis at the end of reception or transmission.
In addition, the SONIC-T provides three tally counters to
tabulate CRC errors, Frame Alignment errors, and missed
packets. Table 3-1 shows the statistics indicated by the
SONIC-T.
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Note: For MAC Loopback, only one packet may be queued up for proper
operation. This restriction occurs because the transmit MAC section,
which does not generate an Interframe Gap (IFG) time between
transmitted packets, does not allow the receive MAC section to update receive status. There are no restrictions for the other loopback
modes.
TL/F/12597 – 13
*Note: DSACK0,1 are used for both Bus and Slave Access Control and are bidirectional. SMACK is used for both Slave access and shared memory access. The
BMODE pin selects between National/Intel or Motorola type busses.
FIGURE 3-10. SONIC-T Bus Interface Signals
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3.0 Functional Description (Continued)
TABLE 3-1. Network Management Statistics
Statistic
Register Used
Bits Used
Frames Transmitted OK
TCR (Note)
PTX
Single Collision Frames
(Note)
NC0 – NC4
Multiple Collision Frames
(Note)
NC0 – NC4
Collision Frames
(Note)
NC0 – NC4
Frames with Deferred Transmissions
TCR (Note)
DEF
Late Collisions
TCR (Note)
OWC
Excessive Collisions
TCR (Note)
EXC
Excessive Deferral
TCR (Note)
EXD
Internal MAC Transmit Error
TCR (Note)
BCM,FU
Frames Received OK
RCR (Note)
PRX
Multicast Frames Received OK
RCR (Note)
MC
Broadcast Frames Received OK
RCR (Note)
BC
CRCT
RCR
All
CRC
FAET
RCR
All
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Frame Check Sequence Errors
Alignment Errors
Note: The number of collisions and the contents of the Transmit Control register are posted in the TXpkt.status field (see
Section 5.5.1.2). The contents of the Receive Control register are posted in the RXpkt.status field (see Section 5.4.3).
4.0 Transmit/Receive IEEE 802.3 Frame Format
A standard IEEE 802.3 packet (Figure 4-1) consists of the
following fields: preamble, Start of Frame Delimiter (SFD),
destination address, source address, length, data and
Frame Check Sequence (FCS). The typical format is shown
in Figure 4-1 . The packets are Manchester encoded and
decoded by the ENDEC unit and transferred serially to/from
the MAC unit using NRZ data with a clock. All fields are of
fixed length except for the data field. The SONIC-T generates and appends the preamble, SFD and FCS field during
transmission. The Preamble and SFD fields are stripped
during reception. (The CRC is passed through to buffer
memory during reception.)
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4.1 PREAMBLE AND START OF FRAME DELIMITER
(SFD)
The Manchester encoded alternating 1,0 preamble field is
used by the ENDEC to acquire bit synchronization with an
incoming packet. When transmitted, each packet contains
62 bits of an alternating 1,0 preamble. Some of this preamble may be lost as the packet travels through the network.
Byte alignment is performed when the Start of Frame Delimiter (SFD) pattern, consisting of two consecutive 1’s, is detected.
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4.2 DESTINATION ADDRESS
The destination address indicates the destination of the
packet on the network and is used to filter unwanted pack-
Note: B e bytes
b e bits
TL/F/12597 – 14
FIGURE 4-1. IEEE 802.3 Packet Structure
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4.0 Transmit/Receive IEEE 802.3 Frame Format (Continued)
error-free packet results in a specific pattern in the CRC
generator. The AUTODIN II (X32 a X26 a X23 a X22 a
X16 a X12 a X11 a X10 a X8 a X7 a X5 a X4 a
X2 a X1 a 1) polynomial is used for the CRC calculations.
The SONIC-T may optionally append the CRC sequence
during transmission, and checks the CRC both during normal reception and self-reception during a transmission (see
Section 3.3.1).
4.7 MAC (MEDIA ACCESS CONTROL) CONFORMANCE
The SONIC-T is designed to be compliant to the IEEE 802.3
MAC Conformance specification. The SONIC-T implements
most MAC functions in silicon and provides hooks for the
user software to handle the remaining functions. The MAC
Conformance specifications are summarized in Table 4-1.
ets from reaching a node. There are three types of address
formats supported by the SONIC-T: Physical, Multicast, and
Broadcast.
Physical Address: The physical address is a unique address that corresponds only to a single node. All physical
addresses have the LSB of the first byte of the address set
to ‘‘0’’. These addresses are compared to the internally
stored CAM (Content Addressable Memory) address entries. All bits in the destination address must match an entry
in the CAM in order for the SONIC-T to accept the packet.
Multicast Address: Multicast addresses, which have the
LSB of the first byte of the address set to ‘‘1’’, are treated
similarly as physical addresses, i.e., they must match an
entry in the CAM. This allows perfect filtering of Multicast
packets and eliminates the need for a hashing algorithm for
mapping Multicast packets.
Broadcast Address: If the address consists of all 1’s, it is a
Broadcast address, indicating that the packet is intended for
all nodes.
The SONIC-T also provides a promiscuous mode which allows reception of all physical address packets. Physical,
Multicast, Broadcast, and promiscuous address modes can
be selected via the Receive Control register.
TABLE 4-1. MAC Conformance Specifications
Support By
Conformance
Test Name
SONIC-T
X
Maximum Frame Size
X
Notes
X
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Minimum Frame Size
User Driver
Software
X
Address Recognition
X
Pad Length Generation
X
Start Of Frame Delimiter
X
Length Field
X
Preamble Generation
X
Order of Bit Transmission
X
Inconsistent Frame Length
X
Non-Integral Octet Count
X
Incorrect Frame Check
Sequence
X
Frame Assembly
X
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4.3 SOURCE ADDRESS
The source address is the physical address of the sending
node. Source addresses cannot be multicast or broadcast
addresses. This field must be passed to the SONIC-T’s
transmit buffer from the system software. During transmission, the SONIC-T compares the Source address with its
internal CAM address entries before monitoring the CRC of
the self-received packet. If the source address of the packet
transmitted does not match a value in the CAM, the packet
monitored bad flag (PMB) will be set in the transmit status
field of the transmit descriptor (see Sections 5.5.1.2 and
6.4.4). The SONIC-T does not provide Source Address insertion. However, a transmit descriptor fragment, containing
only the Source Address, may be created for each packet.
(See Section 5.5.1.)
Address Generation
X
Carrier Deference
X
Interframe Spacing
X
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4.4 LENGTH/TYPE FIELD
For IEEE 802.3 type packets, this field indicates the number
of bytes that are contained in the data field of the packet.
For Ethernet I and II networks, this field indicates the type of
packet. The SONIC-T does not operate on this field.
FCS Generation and Insertion
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4.5 DATA FIELD
The data field has a variable octet length ranging from 46 to
1500 bytes as defined by the Ethernet specification. Messages longer than 1500 bytes need to be broken into multiple packets for IEEE 802.3 networks. Data fields shorter
than 46 bytes require appending a pad to bring the complete frame length to 64 bytes. If the data field is padded,
the number of valid bytes are indicated in the length field.
The SONIC-T does not append pad bytes for short packets
during transmission, nor check for oversize packets during
reception. However, the user’s driver software can easily
append the pad by lengthening the TXpkt.pktÐsize field
and TXpkt.fragÐsize field(s) to at least 64 bytes (see Section 5.5.1). Although the Ethernet specification defines the
maximum number of bytes in the data field, the SONIC-T
can transmit and receive packets up to 64k bytes.
Collision Detection
X
Collision Handling
X
Collision Backoff and
Retransmission
X
FCS Validation
X
Frame Disassembly
X
Back-to-Back Frames
X
Flow Control
X
Attempt Limit
X
Jam Size (after SFD)
X
Jam Size (in Preamble)
X
X
2
X
3
X
1
Note 1: The SONIC-T provides the byte count of the entire packet in the
RXpkt.byteÐcount (see Section 5.4.3). The user’s driver software may perform further filtering of the packet based upon the byte count.
Note 2: The SONIC-T does not provide Source Address insertion; however,
a transmit descriptor fragment, containing only the Source Address, may be
created for each packet. (See Section 5.5.1.)
Note 3: The SONIC-T does not provide Pad generation; however, the user’s
driver software can easily append the Pad by lengthening the TXpkt.pktÐ
size field and TXpkt.fragÐsize field(s) to at least 64 bytes. (See Section
5.5.1.)
4.6 FCS FIELD
The Frame Check Sequence (FCS) is a 32-bit CRC field
calculated and appended to a packet during transmission to
allow detection of error-free packets. During reception, an
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5.0 Buffer Management
rsrc e Resource descriptor
pkt e Packet descriptor
5.1 BUFFER MANAGEMENT OVERVIEW
The SONIC-T’s buffer management scheme is based on
separate buffers and descriptors (Figures 5-3 and 5-12 ).
Packets that are received or transmitted are placed in buffers called the Receive Buffer Area (RBA) and the Transmit
Buffer Area (TBA). The system keeps track of packets in
these buffers using the information in the Receive Descriptor Area (RDA) and the Transmit Descriptor Area (TDA). A
single (TDA) points to a single TBA, but multiple RDAs can
point to a single RBA (one RDA per packet in the buffer).
The Receive Resource Area (RRA), which is another form
of descriptor, is used to keep track of the actual buffer.
When packets are transmitted, the system sets up the packets in one or more TBAs with a TDA pointing to each TBA.
There can only be one packet per TBA/TDA pair. A single
TBA, however, may be made up of several fragments of
data dispersed in memory. There is one TDA pointing to
each TBA which specifies information about the buffer’s
size, location in memory, number of fragments and status
after transmission. The TDAs are linked together in a linked
list. The system causes the SONIC-T to transmit the packets by passing the first TDA to the SONIC-T and issuing the
transmit command.
Before a packet can be received, an RDA and RBA must be
set up by the system. RDAs are made up as a linked list
similar to TDAs. An RDA is not linked to a particular RBA,
though. Instead, an RDA is linked specifically to a packet
after it has been buffered into an RBA. More than one packet can be buffered into the same RBA, but each packet gets
its own RDA. A received packet can not be scattered into
fragments. The system only needs to tell the SONIC-T
where the first RDA and where the RDAs are. Since an RDA
never specifically points to an RBA, the RRA is used to
keep track of the RBAs. The RRA is a circular queue of
pointers and buffer sizes (not a linked list). When the
SONIC-T receives a packet, it is buffered into an RBA and a
unique corresponding RDA is written to so that it points to
and describes the new packet. If the RBA does not have
enough space to buffer the next packet, a new RBA is obtained from the RRA.
The last component consists of a field name to distinguish it
from the other fields of a descriptor. The field name is separated from the descriptor name by a period. (‘‘.’’). An example of a descriptor is shown in Figure 5-1 .
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FIGURE 5-1. Receive Buffer Descriptor Example
5.2.2 Abbreviations
Abbreviations are used to describe the SONIC-T registers
and data structures in memory. The ‘‘0’’ and ‘‘1’’ in the abbreviations indicate the least and most significant portions
of the registers or descriptors. Table 5-1 lists the naming
convention abbreviations for descriptors.
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5.2.3 Buffer Management Base Addresses
The SONIC-T uses three areas in memory to store descriptor information: the Transmit Descriptor Area (TDA), the Receive Descriptor Area (RDA), and the Receive Resource
Area (RRA). The SONIC-T accesses these areas by concatenating a 16-bit base address register with a 16-bit offset
register. The base address register supplies a fixed upper
16 bits of address and the offset registers provide the lower
16 bits of address. The base address registers are the Upper Transmit Descriptor Address (UTDA), Upper Receive
Descriptor Address (URDA), and the Upper Receive Resource Address (URRA) registers. The corresponding offset
registers are shown below.
5.2 DESCRIPTOR AREAS
Descriptors are the basis of the buffer management scheme
used by the SONIC-T. An RDA points to a received packet
within an RBA, an RRA points to an RBA and a TDA points
to a TBA which contains a packet to be transmitted. The
conventions and registers used to describe these descriptors are discussed in the next three sections.
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Upper Address Registers
Offset Registers
URRA
RSA,REA,RWP,RRP
URDA
CRDA
UTDA
CTDA
Table 5-1 defines the register mnemonics.
5.2.1 Naming Convention for Descriptors
The fields which make up the descriptors are named in a
consistent manner to assist in remembering the usage of
each descriptor. Each descriptor name consists of three
components in the following format.
[RX/TX] [descriptor name].[field]
The first two capital letters indicate whether the descriptor is
used for transmission (TX) or reception (RX), and is then
followed by the descriptor name having one of two names.
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Figure 5-2 shows an example of the Transmit Descriptor
Area and the Receive Descriptor Area being located by the
UTDA and URDA registers. The descriptor areas, RDA,
TDA, and RRA are allowed to have the same base address,
i.e., URRA e URDA e UTDA. Care, however, must be taken
to prevent these areas from overwriting each other.
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5.0 Buffer Management (Continued)
TABLE 5-1. Descriptor Abbreviations
TRANSMIT AND RECEIVE AREAS
BUFFER MANAGEMENT REGISTERS (Continued)
RRA
Receive Resource Area
TFC
Transmit Fragment Count Register
RDA
Receive Descriptor Area
TFS
Transmit Fragment Size Register
RBA
Receive Buffer Area
UTDA
TDA
Transmit Descriptor Area
Upper Transmit Descriptor
Address Register
TBA
Transmit Buffer Area
URRA
Upper Receive Resource Address
Register
URDA
Upper Receive Descriptor Address
Register
BUFFER MANAGEMENT REGISTERS
RSA
Resource Start Area Register
REA
Resource End Area Register
TRANSMIT AND RECEIVE DESCRIPTORS
RRP
Resource Read Pointer Register
Resource Write Pointer Register
RXrsrc.buffÐptr0,1
RXrsrc.buffÐwc0,1
Buffer Pointer Field in the RRA
RWP
CRDA
Current Receive Descriptor
Address Register
RXpkt.status
Receive Status Field in the RDA
CRBA0,1
Current Receive Buffer Address
Register
RXpkt.byteÐcount
Packet Byte Count Field in the
RDA
TCBA0,1
Temporary Current Buffer Address
Register
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RBWC0,1
Remaining Buffer Word Count
Register
TRBWC0,1
Temporary Remaining Buffer Word
Count Register
EOBC
End of Buffer Count Register
TPS
Transmit Packet Size Register
Current Transmit Descriptor
Address Register
Buffer Pointer Fields in the RDA
RXpkt.link
Receive Descriptor Link Field in
RDA
RXpkt.inÐuse
‘‘In Use’’ Field in RDA
TXpkt.fragÐcount
Fragment Count Field in TDA
TXpkt.pktÐsize
Packet Size Field in TDA
TXpkt.pktÐptr0,1
Packet Pointer Fields in TDA
TXpkt.fragÐsize
Fragment Size Field in TDA
TXpkt.link
Transmit Descriptor Link Field in
TDA
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Transmit Start Address Register
RXpkt.buffÐptr0,1
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TSA0,1
Buffer Word Count Fields in the
RRA
TL/F/12597 – 15
FIGURE 5-2. Transmit and Receive Descriptor Area Pointers
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5.0 Buffer Management (Continued)
5.3 DESCRIPTOR DATA ALIGNMENT
5.4.1 Receive Resource Area (RRA)
All fields used by descriptors (RXpkt.xxx, RXrsrc.xxx, and
TXpkt.xxx) are word quantities (16-bit) and must be aligned
to word boundaries (A0 e 0) for 16-bit memory and to long
word boundaries (A1,A0 e 0,0) for 32-bit memory. The Receive Buffer Area (RBA) must also be aligned to a word
boundary in 16-bit mode and a long word boundary in 32-bit
mode. The fragments in the Transmit Buffer Area (TBA),
however, may be aligned on any arbitrary byte boundary.
As buffer memory is consumed by the SONIC-T for storing
data, the Receive Resource Area (RRA) provides a mechanism that allows the system to allocate additional buffer
space for the SONIC-T. The system loads this area with
Resource Descriptors that the SONIC-T, in turn, reads as its
current buffer space is used up. Each Resource Descriptor
consists of a 32-bit buffer pointer locating the starting point
of the RBA and a 32-bit word count that indicates the size of
the buffer in words (2 bytes per word). The buffer pointer
and word count are contiguously located using the format
shown in Figure 5-4 with each component composed of
16-bit fields. The SONIC-T stores this information internally
and concatenates the corresponding fields to create 32-bit
long words for the buffer pointer and word count. Note that
in 32-bit mode the upper word (Dk31:16l) is not used by
the SONIC-T. This area may be used for other purposes
since the SONIC-T never writes into the RRA.
The SONIC-T organizes the RRA as a circular queue for
efficient processing of descriptors. Four registers define the
RRA. The first two, the Resource Start Area (RSA) and the
Resource End Area (REA) registers, determine the starting
and ending locations of the RRA, and the other two registers update the RRA. The system adds descriptors at the
address specified by the Resource Write Pointer (RWP),
and the SONIC-T reads the next descriptor designated by
the Resource Read Pointer (RRP). The RRP is advanced 4
words in 16-bit mode (4 long words in 32-bit mode) after the
SONIC-T finishes reading the RRA and automatically wraps
around to the beginning of the RRA once the end has been
reached. When a descriptor in the RRA is read, the
RXrsc.buffÐpt0,1 is loaded into the CRBA0,1 registers and
the RXrsc.buffÐwc0,1 is loaded into the RBWC0,1 registers.
The alignment of the RRA is confined to either word or long
word boundaries, depending upon the data width mode. In
16-bit mode, the RRA must be aligned to a word boundary
(A0 is always zero) and in 32-bit mode, the RRA is aligned
to a long word boundary (A0 and A1 are always zero).
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5.4 RECEIVE BUFFER MANAGEMENT
The Receive Buffer Management operates on three areas in
memory into which data, status, and control information are
written during reception (Figure 5-3) . These three areas
must be initialized (Section 5.4.4) before enabling the receiver (setting the RXEN bit in the Command Register). The
Receive Resource Area (RRA) contains descriptors that locate Receive Buffer Areas in system memory. These descriptors are denoted by R1, R2, etc. in Figure 5-3 . Packets
(denoted by P1, P2, etc.) can then be buffered into the corresponding RBAs. Depending on the size of each buffer
area and the size of the packet(s), multiple or single packets
are buffered into each RBA. The Receive Descriptor Area
(RDA) contains status and control information for each
packet (D1, D2, etc. in Figure 5-3 ) corresponding to each
received packet (D1 goes with P1, D2 with P2, etc.).
When a packet arrives, the address recognition logic checks
the address for a Physical, Multicast, or Broadcast match
and if the packet is accepted, the SONIC-T buffers the
packet contiguously into the selected Receive Buffer Area
(RBA). Because of the previous end-of-packet processing,
the SONIC-T assures that the complete packet is written
into a single contiguous block. When the packet ends, the
SONIC-T writes the receive status, byte count, and location
of the packet into the Receive Descriptor Area (RDA). The
SONIC-T then updates its pointers to locate the next available descriptor and checks the remaining words available in
the RBA. If sufficient space remains, the SONIC-T buffers
the next packet immediately after the previous packet. If the
current buffer is out of space the SONIC-T fetches a Resource Descriptor from the Receive Resource Area (RRA)
acquiring an additional buffer that has been previously allocated by the system.
TL/F/12597 – 16
FIGURE 5-3. Overview of Receive Buffer Management
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5.0 Buffer Management (Continued)
Note: The EOBC is a word count, not a byte count. Also, the value programmed into EOBC must be a double word (32-bit) quantity when
the SONIC-T is in 32-bit mode (e.g., in 32-bit mode, EOBC should be
set to 760 words, not 759 words even though the maximum size of an
IEEE 802.3 packet is 759 words for double work boundary alignment).
5.4.2 Receive Buffer Area (RBA)
The SONIC-T stores the actual data of a received packet in
the RBA. The RBAs are designated by the Resource Descriptors in the RRA as described above. The RXrsrc.buffÐ
wc0,1 fields of the RRA indicate the length of the RBA.
When the SONIC-T gets an RBA from the RRA, the
RXrsrc.buffÐwc0,1 values are loaded into the Remaining
Buffer Word Count registers (RBWC0,1). These registers
keep track of how much space (in words) is left in the buffer.
When a packet is buffered in a RBA, it is buffered contiguously (the SONIC-T will not scatter a packet into multiple
buffers or fragments). Therefore, if there is not enough
space left in a RBA after buffering a packet to buffer at least
one more maximum sized packet (the maximum legal sized
packet expected to be received from the network), a new
buffer must be acquired. The End of Buffer Count (EOBC)
register is used to tell the SONIC-T the maximum packet
size that the SONIC-T will need to buffer.
5.4.2.2 Buffering the Last Packet in an RBA
At the start of reception, the SONIC-T stores the packet
beginning at the Current Receive Buffer Address (CRBA0,1)
and continues until the reception is complete. Concurrent
with reception, the SONIC-T decrements the Remaining
Buffer Word Count (RBWC0,1) by one in 16-bit mode or by
two in 32-bit mode. At the end of reception, if the packet has
crossed the EOBC boundary, the SONIC-T knows that the
next packet might not fit in the RBA. This check is done by
comparing the RBWC0,1 registers with the EOBC. If
RBWC0,1 is less than the EOBC (the last packet buffered
has crossed the EOBC boundary), the SONIC-T fetches the
next resource descriptor in the RRA. If RBWC0,1 is greater
than or equal to the EOBC (the EOBC boundary has not
been crossed) the next packet reception continues at the
present location pointed to by CRBA0,1 in the same RBA.
Figure 5-5 illustrates the SONIC-T’s actions for (1)
RBWC0,1 t EOBC and (2) RBWC0,1 k EOBC. See Section 5.4.4.4 for specific information about setting the EOBC.
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5.4.2.1 End of Buffer Count (EOBC)
The EOBC is a boundary in the RBA based from the bottom
of the buffer. The value written into the EOBC is the maximum expected size (in words) of the network packet that
the SONIC-T will have to buffer. This word count creates a
line in the RBA that, when crossed, causes the SONIC-T to
fetch a new RBA resource from the RRA.
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Note: It is important that the EOBC boundary be ‘‘crossed.’’ In other words,
case Ý1 in Figure 5-5 must exist before case Ý2 exists. If case Ý2
occurs without case Ý1 having occurred first, the test for RBWC0,1
k EOBC will not work properly and the SONIC-T will not fetch a new
buffer. The result of this will be a buffer overflow (RBAE in the Interrupt Status Register, Section 6.4.6).
TL/F/12597 – 17
FIGURE 5-4. Receive Resource Area Format
TL/F/12597 – 18
Case Ý1
(RBWC0,1 t EOBC)
Case Ý2
(RBWC0,1 k EOBC)
Case Ý1: SONIC-T buffers next packet in same RBA.
Case Ý2: SONIC-T detects an exhausted RBA and will buffer the next packet in another RBA.
FIGURE 5-5. Receive Buffer Area
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5.0 Buffer Management (Continued)
5.4.3 Receive Descriptor Area (RDA)
15
After the SONIC-T buffers a packet to memory, it writes 6
words of status and control information into the RDA reads
the link field to the next Receive Descriptor, and writes to
the in-use field of the current descriptor. In 32-bit mode the
upper word, Dk31:16l, is not used. This unused area in
memory should not be used for other purposes, since the
SONIC-T may still write into these locations. Each Receive
Descriptor consists of the following sections: (Figure 5-6) .
RBA Sequence Number
(Modulo 256)
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13
12
11
10
9
8
BRD
PRO
AMC
LB1
LB0
MC
7
6
5
4
3
2
BC
LPKT
CRS
COL
CRCR
FAER
5.4.4 Receive Buffer Management Initialization
The Receive Resource, Descriptor, and Buffer areas (RRA,
RDA, RBA) in memory and the appropriate SONIC-T registers must be properly initialized before the SONIC-T begins
buffering packets. This section describes the initialization
process.
5.4.4.1 Initializing The Descriptor Page
All descriptor areas (RRA, RDA, and TDA) used by the
SONIC-T reside within areas up to 32k (word) or 16k (long
word) pages. This page may be placed anywhere within the
32-bit address range by loading the upper 16 address lines
into the UTDA, URDA, and URRA registers.
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RNT
0
Packet Sequence Number
(Modulo 256)
receive link field: a 15-bit pointer (A15 – A1) that locates
the next receive descriptor. The LSB of this field is the End
Of List (EOL) bit and indicates the last descriptor in the list.
(Initialized by the system.)
in-use field: this field provides a handshake between the
system and the SONIC-T to indicate the ownership of the
descriptor. When the system avails a descriptor to the
SONIC-T, it writes a non-zero value into this field. The
SONIC-T, in turn, sets this field to all ‘‘0’s’’ when it has
finished processing the descriptor. (That is, when the CRDA
register has advanced to the next receive descriptor.) Generally, the SONIC-T releases control after writing the status
and control information into the RDA. If, however, the SONIC-T has reached the last descriptor in the list, it maintains
ownership of the descriptor until the system has appended
additional descriptors to the list. The SONIC-T then relinquishes control after receiving the next packet. (See Section 5.4.6.1 for details on when the SONIC-T writes to this
field.) The receive packet descriptor format is shown in Figure 5-6 .
TL/F/12597–19
15
7
FIGURE 5-8. Receive Sequence Number Format
FIGURE 5-6. Receive Descriptor Format
receive status: indicates status of the received packet. The
SONIC-T writes the Receive Control register values into this
field. Figure 5-7 shows the receive status format. This field
is loaded from the contents of the Receive Control register.
Note that ERR, RNT, BRD, PRO, and AMC are configuration bits and are programmed during initialization. See Section 6.4.3 for the description of the Receive Control register.
ERR
8
1
0
LBK
PRX
FIGURE 5-7. Receive Status Format
byte count: gives the length of the complete packet from
the start of Destination Address to the end of Frame Check
Sequence (FCS).
packet pointer: a 32-bit pointer that locates the packet in
the RBA. The SONIC-T writes the contents of the CRBA0,1
registers into this field.
sequence numbers: this field displays the contents of two
8-bit counters (modulo 256) that sequence the RBAs used
and the packets buffered. These counters assist the system
in determining when an RBA has been completely processed. The sequence numbers allow the system to tally the
packets that have been processed within a particular RBA.
There are two sequence numbers that describe a packet:
the RBA Sequence Number and the Packet Sequence
Number. When a packet is buffered to memory, the
SONIC-T maintains a single RBA Sequence Number for all
packets in an RBA and sequences the Packet Number for
succeeding packets in the RBA. When the SONIC-T uses
the next RBA, it increments the RBA Sequence Number and
clears the Packet Sequence Number. The RBA’s sequence
counter is not incremented when the Read RRA command
is issued in the Command register. The format of the Receive Sequence Numbers is shown in Figure 5-8 . These
counters are reset during a SONIC-T hardware reset or by
writing zero to them.
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5.4.4.2 Initializing The RRA
The initialization of the RRA consists of loading the four
SONIC-T RRA registers and writing the resource descriptor
information to memory.
The RRA registers are loaded with the following values.
Resource Start Area (RSA) register: The RSA is loaded
with the lower 16-bit address of the beginning of the RRA.
Resource End Area (REA) register: The REA is loaded
with the lower 16-bit address of the end of the RRA. The
end of the RRA is defined as the address of the last
RXrsrc.ptr0 field in the RRA plus 4 words in 16-bit mode or 4
long words in 32-bit mode (Figure 5-4) .
Resource Read Pointer (RRP) register: The RRP is loaded with the lower 16-bit address of the first resource descriptor the SONIC-T reads.
Resource Write Pointer (RWP) register: The RWP is loaded with the lower 16-bit address of the next vacant location
where a resource descriptor will be placed by the system.
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Note: The RWP register must only point to either (1) the RXrsrc.ptr0 field of
one of the RRA Descriptors, (2) the memory address that the RSA
points to (the start of the RRA), or (3) the memory address that the
REA points to (the end of the RRA). When the RWP e RRP comparison is made, it is performed after the complete RRA descriptor has
been read and not during the fetch. Failure to set the RWP to any of
the above values prevents the RWP e RRP comparison from ever
becoming true.
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5.0 Buffer Management (Continued)
the SONIC-T to begin receive processing at the first descriptor. An example of two descriptors linked together is
shown in Figure 5-10 . The fields initialized by the system are
displayed in bold type. The other fields are written by the
SONIC-T after a packet is accepted. The RXpkt.inÐuse
field is first written by the system, and then by the SONIC-T.
Note that the descriptors must be aligned properly as discussed in Section 5.3. Also note that the URDA register is
concatenated with the CRDA register to generate the full
32-bit address.
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All RRA registers are concatenated with the URRA register
for generating the full 32-bit address.
The resource descriptors that the system writes to the RRA
consists of four fields: (1) RXrsrc.buffÐptr0, (2)
RXrsrc.buffÐptr1,
(3)
RXrsrc.buffÐwc0,
and
(4)
RXrsrc.buffÐwc1. The fields must be contiguous (they cannot straddle the end points) and are written in the order
shown in Figure 5-9 . The ‘‘0’’ and ‘‘1’’ in the descriptors
denote the least and most significant portions for the Buffer
Pointer and Word Count. The first two fields supply the
32-bit starting location of the Receive Buffer Area (RBA),
and the second two define the number of 16-bit words that
the RBA occupies.
Note that two restrictions apply to the Buffer Pointer and
Word Count. First, in 32-bit mode, since the SONIC-T always writes long words, an even count must be written to
RXrsrc.buffÐwc0. Second, the Buffer Pointer must either
be pointing to a word boundary in 16-bit mode (A0 e 0) or a
long word boundary in 32-bit mode (A0,A1 e 0,0). Note also
that the descriptors must be properly aligned in the RRA as
discussed in Section 5.3.
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TL/F/12597 – 20
FIGURE 5-9. RRA Initialization
After configuring the RRA, the RRA Read command (setting
RRRA bit in the Command register) may be given. This
command causes the SONIC-T to read the RRA descriptor
in a single block operation, and load the following registers
(see Section 6.2 for register mnemonics):
CRBA0 register w RXrsrc.buffÐptr0
CRBA1 register w RXrsrc.buffÐptr1
RBWC0 register w RXrsrc.buffÐwc0
RBWC1 register w RXrsrc.buffÐwc1
When the command has completed, the RRRA bit in the
Command register is reset to ‘‘0’’. Generally this command
is only issued during initialization. At all other times, the RRA
is automatically read as the SONIC-T finishes using an RBA.
TL/F/12597 – 21
FIGURE 5-10. RDA Initialization Example
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5.4.4.4 Initializing the Lower Boundary of the RBA
A ‘‘false bottom’’ is set in the RBA by loading the End Of
Buffer Count (EOBC) register with a value equal to the maximum size packet in words (16 bits) that may be received.
This creates a lower boundary in the RBA. Whenever the
Remaining Buffer Word Count (RBWC0,1) registers decrement below the EOBC register, the SONIC-T buffers the
next packet into another RBA. This also guarantees that a
packet is always contiguously buffered into a single Receive
Buffer Area (RBA). The SONIC-T does not buffer a packet
into multiple RBAs. Note that in 32-bit mode, the SONIC-T
holds the LSB always low so that it properly compares with
the RBWC0,1 registers.
After a hardware reset, the EOBC reset, the EOBC register
is automatically initialized to 2F8h (760 words or 1520
bytes). For 32-bit applications this is the suggested value for
EOBC. EOBC defaults to 760 words (1520 bytes) instead of
759 words (1518 bytes) because 1518 is not a double word
(32-bit) boundary (see Section 5.4.2.1). If the SONIC-T is
used in 16-bit mode, then EOBC should be set to 759 words
(1518 bytes) because 1518 is a word (16-bit) boundary.
Sometimes it may be desired to buffer a single packet per
RBA. When doing this, it is important to set EOBC and the
buffer size correctly. The suggested practice is to set EOBC
to a value that is at least 4 bytes, in 32-bit mode, or 2 bytes,
in 16-bit mode, less than the buffer size. An example of this
for 32-bit mode is to set EOBC to 760 words (1520 bytes)
5.4.4.3 Initializing The RDA
To accept multiple packets from the network, the receive
packet descriptors must be linked together via the
RXpkt.link fields. Each link field must be written with a 15-bit
(A15 – A1) pointer to locate the beginning of the next descriptor in the list. The LSB of the RXpkt.link field is the End
Of List (EOL) bit and is used to indicate the end of the
descriptor list. EOL e 1 for the last descriptor and EOL e 0
for the first or middle descriptors. The RXpkt.inÐuse field
indicates whether the descriptor is owned by the SONIC-T.
The system writes a non-zero value to this field when the
descriptor is available, and the SONIC-T writes all ‘‘0’s’’
when it finishes using the descriptor. At startup, the Current
Receive Descriptor Address (CRDA) register must be loaded with the address of the first RXpkt.status field in order for
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5.0 Buffer Management (Continued)
and the buffer size to 762 words (1524 bytes). A similar
example for 16-bit mode would be EOBC e 759 words
(1518 bytes) and the buffer size set to 760 words (1520
bytes). The buffer can be any size, but as long as the EOBC
is 2 words, for 32-bit mode, or 1 word, for 16-bit mode, less
than the buffer size, only one packet will be buffered in that
RBA.
5.4.6.1 Successful Reception
If the SONIC-T accepts the packet, it first writes 5 words of
descriptor information in the RDA beginning at the address
pointed to by the Current Receive Descriptor Address
(CRDA) register. It then reads the RXpkt.link field to advance the CRDA register to the next receive descriptor. The
SONIC-T also checks the EOL bit for a ‘‘1’’ in this field. If
EOL e 1, no more descriptors are available for the SONIC-T.
The SONIC-T recovers the address of the current RXpkt.link
field (from a temporary register) and generates a ‘‘Receive
Descriptors Exhausted’’ indication in the Interrupt Status
register. (See Section 5.4.7 on how to add descriptors.) The
SONIC-T maintains ownership of the descriptor by not writing to the RXpkt.inÐuse field. Otherwise, if EOL e 0, the
SONIC-T advances the CRDA register to the next descriptor
and resets the RXpkt.inÐuse field to all ‘‘0’s’’.
The SONIC-T accesses the complete 7 word RDA descriptor in a single block operation.
The SONIC-T also checks if there is remaining space in the
RBA. The SONIC-T compares the Remaining Buffer Word
Count (RBWC0,1) registers with the static End Of Buffer
Count (EOBC). If the RBWC is less than the EOBC, a maximum sized packet will no longer fit in the remaining space in
the RBA; hence, the SONIC-T fetches a resource descriptor
from the RRA and loads its registers with the pointer and
word count of the next available RBA.
Note 1: It is possible to filter out most oversized packets by setting the buffer size to 760 words (1520 bytes) in 32-bit mode or 759 words (1518
bytes) in 16-bit mode. EOBC would be set to 758 words (1516
bytes) for both cases. With this configuration, any packet over 1520
bytes, in 32-bit mode, or 1518 bytes, in 16-bit mode, will not be
completely buffered because the packet will overflow the buffer.
When a packet overflow occurs, a Receive Buffer Area Exceeded
interrupt (RBAE in the Interrupt Status Register, Section 6.4.6) will
occur.
Note 2: When buffering one packet per buffer, it is suggested that the values in Note 1 above be used. Since the minimum legal sized Ethernet packet is 64 bytes, however, it is possible to set EOBC as much
as 64 bytes less than the buffer size and still end up with one packet
per buffer. Figure 5-11 shows this ‘‘range.’’
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5.4.5 Beginning Of Reception
At the beginning of reception, the SONIC-T checks its internally stored EOL bit from the previous RXpkt.link field for a
‘‘1’’. If the SONIC-T finds EOL e 1, it recognizes that after
the previous reception, there were no more remaining receive packet descriptors. It re-reads the same RXpkt.link
field to check if the system has updated this field since the
last reception. If the SONIC-T still finds EOL e 1, reception
ceases. (See Section 5.5 for adding descriptors to the list.)
Otherwise, the SONIC-T begins storing the packet in the
RBA starting at the Current Receive Buffer Address
(CRBA0,1) registers and continues until the packet has
completed. Concurrent with the packet reception, the Remaining Buffer Word Count (RBWC0,1) registers are decremented after each word is written to memory. This register
determines the remaining words in the RBA at the end of
reception.
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5.4.6.2 Buffer Recovery For Runt Packets Or
Packets With Errors
If a runt packet (less than 64 bytes) or packet with errors
arrives and the Receive Control register has been configured to not accept these packets, the SONIC-T recovers its
pointers back to the original positions. The CRBA0,1 registers are not advanced and the RBWC0,1 registers are not
decremented. The SONIC-T recovers its pointers by maintaining a copy of the buffer address in the Temporary Receive Buffer Address registers (TRBA0,1). The SONIC-T recovers the value in the RBWC0,1 registers from the Temporary Buffer Word Count registers (TBWC0,1).
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5.4.6 End Of Packet Processing
At the end of a reception, the SONIC-T enters its end of
packet processing sequence to determine whether to accept or reject the packet based on receive errors and packet size. At the end of reception the SONIC-T enters one of
the following two sequences:
Ð Successful reception sequence
Ð Buffer recovery for runt packets or packets with errors
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5.4.7 Overflow Conditions
When an overflow condition occurs, the SONIC-T halts its
DMA operations to prevent writing into unauthorized memory. The SONIC-T uses the Interrupt Status register (ISR) to
indicate three possible overflow conditions that can occur
TL/F/12597 – 22
Range of EOBC e (RXrsrc.wc0,1 b 2 to RXrsrc.wc0,1 b 32)
FIGURE 5-11. Setting EOBC for Single Packet RBA
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5.0 Buffer Management (Continued)
and the Transmit Buffer Area (TBA). During transmission,
the SONIC-T fetches control information from the TDA,
loads its appropriate registers, and then transmits the data
from the TBA. When the transmission is complete, the SONIC-T writes the status information in the TDA. From a single
transmit command, packets can either be transmitted singly
or in groups if several descriptors have been linked together.
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when its receive resources have been exhausted. The system should respond by replenishing the resources that have
been exhausted. These overflow conditions (Descriptor Resources Exhausted, Buffer Resources Exhausted, and RBA
Limit Exceeded) are indicated in the Interrupt Status register
and are detailed as follows:
Descriptor Resources Exhausted: This occurs when the
SONIC-T has reached the last receive descriptor in the list,
meaning that the SONIC-T has detected EOL e 1. The
system must supply additional descriptors for continued reception. The system can do this in one of two ways: 1)
appending descriptors to the existing list, or 2) creating a
separate list.
1. Appending descriptors to the existing list. This is the easiest and preferred way. To do this, the system, after creating the new list, joins the new list to the existing list by
simply writing the beginning address of the new list into
the RXpkt.link field and setting EOL e 0. At the next
reception, the SONIC-T re-reads the last RXpkt.link field,
and updates its CRDA register to point to the next descriptor.
2. Creating a separate list. This requires an additional step
because the lists are not joined together and requires
that the CRDA register be loaded with the address of the
RXpkt.link field in the new list.
During this overflow condition, the SONIC-T maintains ownership of the descriptor (RXpkt.inÐuse i 00h) and waits for
the system to add additional descriptors to the list. When
the system appends more descriptors, the SONIC-T releases ownership of the descriptor after writing 0000h to the
RXpkt.inÐuse field.
Buffer Resources Exhausted: This occurs when the
SONIC-T has detected that the Resource Read Pointer
(RRP) and Resource Write Pointer (RWP) registers are
equal (i.e., all RRA descriptors have been exhausted). The
RBE bit in the Interrupt Status register is set when the
SONIC-T finishes using the second to last receive buffer
and reads the last RRA descriptor. Actually, the SONIC-T is
not truly out of resources, but gives the system an early
warning of an impending out of resources condition. To continue reception after the last RBA is used, the system must
supply additional RRA descriptor(s), update the RWP register, and clear the RBE bit in the ISR. The SONIC-T rereads
the RRA after this bit is cleared.
RBA Limit Exceeded: This occurs when a packet does not
completely fit within the remaining space of the RBA. This
can occur if the EOBC register is not programmed to a value
greater than the largest packet that can be received. When
this situation occurs, the packet is truncated and the
SONIC-T reads the RRA to obtain another RBA. Indication
of an RBA limit being exceeded is signified by the Receive
Buffer Area Exceeded (RBAE) interrupt being set (see Section 6.4.6). An RDA will not be set up for the truncated packet and the buffer space will not be re-used. To rectify this
potential overflow condition, the EOBC register must be
loaded with a value equal to or greater than the largest
packet that can be accepted. (See Section 5.4.2.)
TL/F/12597 – 23
FIGURE 5-12. Overview of Transmit Buffer Management
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5.5.1 Transmit Descriptor Area (TDA)
The TDA contains descriptors that the system has generated to exchange status and control information. Each descriptor corresponds to a single packet and consists of the
following 16-bit fields.
TXpkt.status: This field is written by the SONIC-T and provides status of the transmitted packet. (See Section 5.5.1.2
for more details.)
TXpkt.config: This field allows programming the SONIC-T
to one of the various transmit modes. The SONIC-T reads
this field and loads the corresponding configuration bits
(PINTR, POWC, CRCI, and EXDIS) into the Transmit Control
register. (See Section 5.5.1.1 for more details.)
TXpkt.pktÐsize: This field contains the byte count of the
entire packet.
TXpkt.fragÐcount: This field contains the number of fragments the packet is segmented into.
TXpkt.fragÐptr0,1: This field contains a 32-bit pointer
which locates the packet fragment to be transmitted in the
Transmit Buffer Area (TBA). This pointer is not restricted to
any byte alignment.
TXpkt.fragÐsize: This field contains the byte count of the
packet fragment. The minimum fragment size is 1 byte.
TXpkt.link: This field contains a 15-bit pointer (A15 – A1) to
the next TDA descriptor. The LSB, the End Of List (EOL) bit,
indicates the last descriptor in the list when set to a ‘‘1’’.
When descriptors have been linked together, the SONIC-T
transmits back-to-back packets from a single transmit command.
The data of the packet does not need to be contiguous, but
can exist in several locations (fragments) in memory. In this
case, the TXpkt.fragÐcount field is greater than one, and
additional TXpkt.fragÐptr0,1 and TXpkt.fragÐsize fields
corresponding to each fragment are used. The descriptor
format is shown in Figure 5-13. Note that in 32-bit mode the
upper word, Dk31:16l, is not used.
5.5 TRANSMIT BUFFER MANAGEMENT
To begin transmission, the system software issues the
Transmit command (TXP e 1 in the CR). The Transmit Buffer Management uses two areas in memory for transmitting
packets (Figure 5-12), the Transmit Descriptor Area (TDA)
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5.0 Buffer Management (Continued)
nores the extraneous bytes which are written into the FIFO
during odd byte alignment fragments. The minimum allowed
fragment size is 1 byte. Figure 5-12 shows the relationship
between the TDA and the TBA for single and multi-fragmented packets.
5.5.3 Preparing To Transmit
All fields in the TDA descriptor and the Current Transmit
Descriptor Address (CTDA) register of the SONIC-T must be
initialized before the Transmit Command (setting the TXP bit
in the Command register) can be issued. If more than one
packet is queued, the descriptors must be linked together
with the TXpkt.link field. The last descriptor must have EOL
e 1 and all other descriptors must have EOL e 0. To begin
transmission, the system loads the address of the first
TXpkt.status field into the CTDA register. Note that the upper 16-bits of address are loaded in the Upper Transmit
Descriptor (UTDA) register. The user performs the following
transmit initialization.
1. Initialize the TDA
2. Load the CTDA register with the address of the first transmit descriptor
3. Issue the transmit command
Note that if the Source Address of the packet being transmitted is not in the CAM, the Packet Monitored Bad (PMB)
bit in the TXpxt.status field will be set (see Section 6.4.4).
TL/F/12597–24
FIGURE 5-13. Transmit Descriptor Area
15
14
13
12
PINTR POWC CRCI EXDIS
11
10
9
8
X
X
X
X
6
5
4
3
2
1
0
X
X
X
X
X
X
X
Note: x e don’t care
FIGURE 5-14. TXpkt.config Field
5.5.3.1 Transmit Process
When the Transmit Command (TXP e 1 in the Command
register) is issued, the SONIC-T fetches the control information in the TDA descriptor, loads its appropriate registers
(shown below) and begins transmission. (See Section 6.2
for register mnemonics.)
TCR w TXpkt.config
TPS w TXpkt.pktÐsize
TFC w TXpkt.fragÐcount
TSA0 w TXpkt.fragÐptr0
TSA1 w TXpkt.fragÐptr1
TFS w TXpkt.fragÐsize
CTDA w TXpkt.link
(CTDA is loaded after all fragments have been read and
successfully transmitted. If the halt transmit command is issued (HTX bit in the Command register is set) the CTDA
register is not loaded.)
During transmission, the SONIC-T reads the packet descriptor in the TDA and transmits the data from the TBA. If
TXpkt.fragÐcount is greater than one, the SONIC-T, after
finishing transmission of the fragment, fetches the next
TXpkt.fragÐptr0,1 and TXpkt.fragÐsize fields and transmits
the next fragment. This process continues until all fragments of a packet are transmitted. At the end of packet
transmission, status is written in to the TXpkt.status field.
The SONIC-T then reads the TXpkt.link field and checks if
EOL e 0. If it is ‘‘0’’, the SONIC-T fetches the next descriptor and transmits the next packet. If EOL e 1 the SONIC-T
generates a ‘‘Transmission Done’’ indication in the Interrupt
Status register and resets the TXP bit in the Command register.
In the event of a collision, the SONIC-T recovers its pointer
in the TDA and retransmits the packet up to 15 times. The
SONIC-T maintains a copy of the CTDA register in the Temporary Transmit Descriptor Address (TTDA) register.
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5.5.1.1 Transmit Configuration
The TXpkt.config field allows the SONIC-T to be programmed into one of the transmit modes before each transmission. At the beginning of each transmission, the
SONIC-T reads this field and loads the PINTR, POWC,
CRCI, and EXDIS bits into the Transmit Control Register
(TCR). The configuration bits in the TCR correspond directly
with the bits in the TXpkt.config field as shown in Figure 514. See Section 6.4.4 for the description on the TCR.
15
14
13
12
11
10
9
8
NC4
NC3
NC2
NC1
NC0
EXD
DEF
NCRS
O
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5.5.1.2 Transmit Status
At the end of each transmission the SONIC-T writes the
status bits (k10:0l) of the Transmit Control Register (TCR)
and the number of collisions experienced during the transmission into the TXpkt.status field (Figure 5-15 , res e reserved). Bits NC4–NC0 indicate the number of collisions
where NC4 is the MSB. See Section 6.4.4 for the description of the TCR.
7
CRSL
6
5
4
3
2
1
0
EXC
OWC
res
PMB
FU
BCM
PTX
FIGURE 5-15. TXpkt.status Field
5.5.2 Transmit Buffer Area (TBA)
The TBA contains the fragments of packets that are defined
by the descriptors in the TDA. A packet can consist of a
single fragment or several fragments, depending upon the
fragment count in the TDA descriptor. The fragments also
can reside anywhere within the full 32-bit address range,
and be aligned to any byte boundary. When an odd byte
boundary is given, the SONIC-T automatically begins reading data at the corresponding word boundary in 16-bit mode
or a long word boundary in 32-bit mode. The SONIC-T ig-
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32
5.0 Buffer Management (Continued)
6.0 SONIC-T Registers
The SONIC-T performs a block operation of 6, 3, or 2 accesses in the TDA, depending on where the SONIC-T is in
the transmit process. For the first fragment, it reads the
TXpkt.config to TXpkt.fragÐsize (6 accesses). For the next
fragment, if any, it reads the next 3 fields from TXpkt.fragÐ
ptr0 to TXpkt.fragÐsize (3 accesses). At the end of transmission it writes the status information to TXpkt.status and
reads the TXpkt.link field (2 accesses).
The SONIC-T contains two sets of registers: The status/
control registers and the CAM memory cells. The status/
control registers are used to configure, control, and monitor
SONIC-T operation. They are directly addressable registers
and occupy 64 consecutive address locations in the system
memory space (selected by the RA5 – RA0 address pins).
There are a total of 64 status/control registers divided into
the following categories:
User Registers: These registers are accessed by the user
to configure, control, and monitor SONIC-T operation.
These are the only SONIC-T registers the user needs to
access. Figure 6-3 shows the programmer’s model and Table 6-1 lists the attributes of each register.
Internal Use Registers: These registers (Table 6-2) are
used by the SONIC-T during normal operation and are not
intended to be accessed by the user.
National Factory Test Registers: These registers (Table
6-3) are for National factory use only and should never be
accessed by the user. Accessing these registers during normal operation can cause improper functioning of the
SONIC-T.
5.5.3.2 Transmit Completion
The SONIC-T stops transmitting under two conditions. In
the normal case, the SONIC-T transmits the complete list of
descriptors in the TDA and stops after it detects EOL e 1.
In the second case, certain transmit errors cause the
SONIC-T to abort transmission. If FIFO Underrun, Byte
Count Mismatch, Excessive Collision, or Excessive Deferral
(if enabled) errors occur, transmission ceases. The CTDA
register points to the last packet transmitted. The system
can also halt transmission under software control by setting
the HTX bit in the Command register. Transmission halts
after the SONIC-T writes to the TXpkt.status field.
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5.5.4 Dynamically Adding TDA Descriptors
Descriptors can be dynamically added during transmission
without halting the SONIC-T. The SONIC-T can also be
guaranteed to transmit the complete list including newly appended descriptors (barring any transmit abort conditions)
by observing the following rule: The last TXpkt.link field
must point to the next location where a descriptor will be
added (see step 3 below and Figure 5-16 ).
The procedure for appending descriptors consists of:
1. Creating a new descriptor with its TXpkt.link pointing to
the next vacant descriptor location and its EOL bit set to
a ‘‘1’’.
2. Resetting the EOL bit to a ‘‘0’’ of the previously last descriptor.
3. Re-issuing the Transmit command (setting the TXP bit in
the Command register).
Step 3 assures that the SONIC-T will transmit all the packets in the list. If the SONIC-T is currently transmitting, the
Transmit command has no effect and continues transmitting
until it detects EOL e 1. If the SONIC-T had just finished
transmitting, it continues transmitting from where it had previously stopped.
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6.1 THE CAM UNIT
The CAM unit memory cells are indirectly accessed by programming the CAM descriptor area in system memory and
issuing the LCAM command (setting the LCAM bit in the
Control register). The CAM cells do not occupy address locations in register space and, thus, are not accessible
through the RA5 – RA0 address pins. The CAM control registers, however, are part of the user register set and must be
initialized before issuing the LCAM command (see Section
6.4.10).
The Content Addressable Memory (CAM) consists of sixteen 48-bit entries for complete address filtering (Figure 6-1)
of network packets. Each entry corresponds to a 48-bit destination address that is user programmable and can contain
any combination of Multicast or Physical addresses. Each
entry is partitioned into three 16-bit CAM cells accessible
through CAM Address Ports (CAP2, CAP1 and CAP0) with
CAP0 corresponding to the least significant 16 bits of the
Destination Address and CAP2 corresponding to the most
significant bits. The CAM is accessed in a two step process.
First, the CAM Entry Pointer is loaded to point to one of the
16 entries. Then, each of the CAM Address Ports is accessed to select the CAM cell. The 16 user programmable
CAM entries can be masked out with the CAM Enable register (see Section 6.4.10).
O
Note: It is not necessary to program a broadcast address into the CAM
when it is desired to accept broadcast packets. Instead, to accept
broadcast packets, set the BRD bit in the Receive Control register. If
the BRD bit has been set, the CAM is still active. This means that it is
possible to accept broadcast packets at the same time as accepting
packets that match physical addresses in the CAM.
6.1.1 The Load CAM Command
Because the SONIC-T uses the CAM for a relatively long
period of time during reception, it can only be written to via
the CAM Descriptor Area (CDA) and is only readable when
TL/F/12597 – 25
FIGURE 5-16. Initializing Last Link Field
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6.0 SONIC-T Registers (Continued)
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TL/F/12597 – 26
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FIGURE 6-1. CAM Organization
2. Initialize the CDA as described above.
the SONIC-T is in software reset. The CDA resides in the
same 64k byte block of memory as the Receive Resource
3. Initialize the CAM Descriptor Count with the number of
Area (RRA) and contains descriptors for loading the CAM
CAM descriptors. Note, only the lower 5 bits are used in
registers. These descriptors are contiguous and each dethis register. The other bits are don’t cares. (See Section
scriptor consists of four 16-bit fields (Figure 6-2). In 32-bit
6.4.10.)
mode the upper word, D k31:16l, is not used. The first field
4. Initialize the CAM Descriptor Pointer to locate the first
contains the value to be loaded into the CAM Entry Pointer
descriptor in the CDA. This register must be reloaded
and the remaining fields are for the three CAM Address
each time a new Load CAM command is issued.
Ports (see Section 6.4.10). In addition, there is one more
5.
Issue the Load CAM command (LCAM) in the Command
field after the last descriptor containing the mask for the
register. (See Section 6.4.1.)
CAM Enable register. Each of the CAM descriptors are adIf a transmission or reception is in progress, the CAM DMA
dressed by the CAM Descriptor Pointer (CDP) register.
function will not occur until these operations are complete.
After the system has initialized the CDA, it can issue the
When the SONIC-T completes the Load CAM command,
Load CAM command to program the SONIC-T to read the
the CDP register points to the next location after the CAM
CDA and load the CAM. The procedure for issuing the Load
enable field and the CDC equals zero. The SONIC-T resets
CAM command is as follows.
the LCAM bit in the Command register and sets the Load
1. Initialize the Upper Receive Resource Address (URRA)
CAM Done (LCD) bit in the ISR.
register. Note that the CAM Descriptor Area must reside
within the same 64k page as the Receive Resource Area.
(See Section 6.4.9.)
TL/F/12597 – 27
FIGURE 6-2. CAM Descriptor Area Format
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34
6.0 SONIC-T Registers (Continued)
6.2 FULL DUPLEX OPERATION
The SONIC-T can be configured to allow Full Duplex operation. All other operation of the SONIC-T is the same except
that collisions are ignored.
3. Disable Heartbeat detection by setting the HD bit (bit 11)
in the DCR2.
6.2.1 Configuring the SONIC-T DCR2
In order to use the SONIC-T in full duplex mode, the HD and
FD bits must be set in DCR2:
1. Put the SONIC-T in software reset by setting RST bit (bit
7) in the CR.
2. Enable Full Duplex operation by setting the FD bit (bit 5)
in the DCR2.
6.2.2 Increased Buffering
In order to avoid Receive Buffer Exhaustions (RBE’s) due to
increased traffic in Full Duplex mode, it is recommended
that the number if entries in the RRA be increased to be
greater than what typically is used for Half Duplex (see Section 5.4.4.2 Initializing the RRA).
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4. Take the SONIC-T out of software reset by clearing the
RST bit (bit 7) in the CR.
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6.0 SONIC-T Registers (Continued)
Status and
Control Registers
$
Transmit
Registers
RAk5:0l
15
0h Command Register
Status and Control Fields
0
1
Data Configuration Register
Control Fields
2
Receive Control Register
Status and Control Fields
3
Transmit Control Register
Status and Control Fields
4
Interrupt Mask Register
Mask Fields
5
Interrupt Status Register
Status Fields
3F Data Configuration Register 2
Control Fields
6
Upper 16-bit Address Base
)7
Upper Transmit Descriptor Address Register
Current Transmit Descriptor Address Register Lower 16-bit Address Offset
0D Upper Receive Descriptor Address Register
Upper 16-bit Address Base
0E Current Receive Descriptor Address Register Lower 16-bit Address Offset
Upper 16-bit Address Base
15 Resource Start Address Register
Lower 16-bit Address Offset
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Receive
Registers
14 Upper Receive Resource Address Register
16 Resource End Address Register
Lower 16-bit Address Offset
17 Resource Read Register
18 Resource Write Register
2B Receive Sequence Counter
21 CAM Entry Pointer
22 CAM Address Port 2
23 CAM Address Port 1
$
Watchdog
Timer
Count Value
4
Middle 16 bits of CAM Entry
Least Significant 16 bits of CAM Entry
25 CAM Enable Register
Mask Fields
26 CAM Descriptor Pointer
Lower 16-bit Address Offset
27 CAM Descriptor Count
2C DRC Error Tally Counter
Count Value
)
2D Frame Alignment Error Tally
Count Value
2E Missed Packet Tally
Count Value
Ð
29 Watchdog Timer 0
Lower 16-bit Count Value
2A Watchdog Timer 1
Upper 16-bit Count Value
28 Silicon Revision Register
Chip Revision Number
FIGURE 6-3. SONIC-T Register Programming Model
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8 7
Most Significant 16 bits of CAM Entry
O
Tally
Counters
Count Value
bs
24 CAM Address Port 0
CAM
Registers
Lower 16-bit Address Offset
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$
Lower 16-Bit Address Offset
36
5
Count Value
6.0 SONIC-T Registers (Continued)
ing interrupt control. The registers are selected by asserting
chip select to the SONIC-T and providing the necessary address on register address pins RA5 – RA0. Tables 6-1, 6-2,
and 6-3 show the locations of all SONIC-T registers and
where information on the registers can be found in the data
sheet.
6.3 STATUS/CONTROL REGISTERS
This set of registers is used to convey status/control information to/from the host system and to control the operation
of the SONIC-T. These registers are used for loading commands generated from the system, indicating transmit and
receive status, buffering data to/from memory, and provid-
TABLE 6-1. User Registers
RA5 – RA0
Access
Register
Symbol
Description
(section)
6.4.1
COMMAND AND STATUS REGISTERS
R/W
Command
CR
R/W
Data Configuration
DCR
6.4.2
02
R/W
Receive Control
RCR
6.4.3
03
R/W
Transmit Control
TCR
6.4.4
04
R/W
Interrupt Mask
IMR
6.4.5
05
R/W
Interrupt Status
ISR
6.4.6
3F (Note 3)
R/W
Data Configuration 2
DCR2
6.4.7
06
R/W
Upper Transmit Descriptor Address
UTDA
6.4.8, 5.4.4.1
07
R/W
Current Transmit Descriptor Address
CTDA
6.4.8, 5.5.3
R/W
Upper Receive Descriptor Address
URDA
6.4.9, 5.4.4.1
6.4.9, 5.4.4.3
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00h
01 (Note 3)
TRANSMIT REGISTERS
RECEIVE REGISTERS
0D
R/W
Current Receive Descriptor Address
CRDA
13
R/W
End of Buffer Word Count
EOBC
6.4.9, 5.4.2
14
R/W
Upper Receive Resource Address
URRA
6.4.9, 5.4.4.1
15
R/W
Resource Start Address
RSA
6.4.9, 5.4.1
16
R/W
17
R/W
Resource End Address
REA
6.4.9, 5.4.1
Resource Read Pointer
RRP
6.4.9, 5.4.1
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2B
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0E
R/W
Resource Write Pointer
RWP
6.4.9, 5.4.1
R/W
Receive Sequence Counter
RSC
6.4.9, 5.4.3.2
R/W
CAM Entry Pointer
CEP
6.1, 6.4.10
R
CAM Address Port 2
CAP2
6.1, 6.4.10
R
CAM Address Port 1
CAP1
6.1, 6.4.10
CAM REGISTERS
21
22 (Note 1)
O
23 (Note 1)
24 (Note 1)
R
CAM Address Port 0
CAP0
6.1, 6.4.10
25 (Note 2)
R/W
CAM Enable
CE
6.1, 6.4.10
26
R/W
CAM Descriptor Pointer
CDP
6.1, 6.4.10
27
R/W
CAM Descriptor Count
CDC
6.1, 6.4.10
TALLY COUNTERS
2C (Note 4)
R/W
CRC Error Tally
CRCT
6.4.11
2D (Note 4)
R/W
FAE Tally
FAET
6.4.11
2E (Note 4)
R/W
Missed Packet Tally
MPT
6.4.11
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6.0 SONIC-T Registers (Continued)
TABLE 6-1. User Registers (Continued)
RA5 – RA0
Access
Register
Symbol
Description
(section)
WATCHDOG COUNTERS
29
R/W
Watchdog Timer
WT0
6.4.12
2A
R/W
Watchdog Timer 1
WT1
6.4.12
R
Silicon Revision
SR
6.4.13
SILICON REVISION
28
Note 1: These registers can only be read when the SONIC-T is in reset mode (RST bit in the CR is set). The SONIC-T gives invalid data when these registers are
read in non-reset mode.
Note 2: This register can only be written to when the SONIC-T is in reset mode. This register is normally only loaded by the Load CAM command.
Note 3: The Data Configuration registers, DCR and DCR2, can only be written to when the SONIC-T is in reset mode (RST bit in CR is set). Writing to these
registers while not in reset mode does not alter the registers.
Note 4: The data written to these registers is inverted before being latched. That is, if a value of FFFFh is written, these registers will contain and read back the
value of 0000h. Data is not inverted during a read operation.
TABLE 6-2. Internal Use Registers (Users should not write to these registers)
Access
Register
TRANSMIT REGISTERS
Symbol
Description
(section)
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(RA5 – RA0)
08 (Note 1)
R/W
Transmit Packet Size
TPS
5.5
09
R/W
Transmit Fragment Count
TFC
5.5
0A
R/W
Transmit Start Address 0
TSA0
5.5
0B
R/W
Transmit Start Address 1
TSA1
5.5
R/W
Transmit Fragment Size
TFS
5.5
20
R/W
Temporary Transmit Descriptor Address
TTDA
5.5.4
2F
R
Maximum Deferral Timer
MDT
6.4.4
0F
R/W
Current Receive Buffer Address 0
CRBA0
5.4.2, 5.4.4.2
10
R/W
Current Receive Buffer Address 1
CRBA1
5.4.2, 5.4.4.2
11
R/W
Remaining Buffer Word Count 0
RBWC0
5.4.2, 5.4.4.2
R/W
Remaining Buffer Word Count 1
RBWC1
5.4.2, 5.4.4.2
R/W
Temporary Receive Buffer Address 0
TRBA0
5.4.6.2
R/W
Temporary Receive Buffer Address 1
TRBA1
5.4.6.2
R/W
Temporary Buffer Word Count 0
TBWC0
5.4.6.2
R/W
Temporary Buffer Word Count 1
TBWC1
5.4.6.2
R/W
Last Link Field Address
LLFA
none
12
19
1A
1B
1C
O
1F
bs
RECEIVE REGISTERS
ol
0C (Note 2)
ADDRESS GENERATORS
1D
R/W
Address Generator 0
ADDR0
none
1E
R/W
Address Generator 1
ADDR1
none
Note 1: The data that is read from these registers is the inversion of what has been written to them.
Note 2: The value that is written to this register is shifted once in 16-bit mode and shifted twice in 32-bit mode.
TABLE 6-3. National Factory Test Registers (Users should not access these registers)
(RA5 – RA0)
Access
Register
Symbol
Description
(section)
R/W
These registers are for factory use only. Users must not
address these registers or improper SONIC-T operation
can occur.
none
none
30
#
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6.0 SONIC-T Registers (Continued)
6.4 REGISTER DESCRIPTION
6.4.1 Command Register
(RAk5:0l e 0h)
This register (Figure 6-4) is used for issuing commands to the SONIC-T. These commands are issued by setting the corresponding bits for the function. For all bits, except for the RST bit, the SONIC-T resets the bit after the command is completed. With the
exception of RST, writing a ‘‘0’’ to any bit has no effect. Before any commands can be issued, the RST bit must first be reset to
‘‘0’’. This means that, if the RST bit is set, two writes to the Command Register are required to issue a command to the
SONIC-T; one to clear the RST bit, and one to issue the command.
This register also controls the general purpose 32-bit Watchdog Timer. After the Watchdog Timer register has been loaded, it
begins to decrement once the ST bit has been set to ‘‘1’’. An interrupt is issued when the count reaches zero if the Timer
Complete interrupt is enabled in the IMR.
During hardware reset, bits 7, 4, and 2 are set to a ‘‘1’’; all others are cleared. During software reset bits 9, 8, 1, and 0 are
cleared and bits 7 and 2 are set to a ‘‘1’’; all others are unaffected.
15
14
13
12
11
10
0
0
0
0
0
0
9
8
7
LCAM RRRA RST
r/w
r/w
r/w
6
5
4
0
ST
STP
r/w
r/w
r/w
3
2
1
RXEN RXDIS TXP
r/w
r/w
0
HTX
r/w
r e read only, r/w e read/write
Bit
9
Description
Must be 0
LCAM: LOAD CAM
Setting this bit causes the SONIC-T to load the CAM with the descriptor that is pointed to by the CAM Descriptor
Pointer register.
bs
15 – 10
Meaning
LOAD CAM
READ RRA
SOFTWARE RESET
START TIMER
STOP TIMER
RECEIVER ENABLE
RECEIVER DISABLE
TRANSMIT PACKET(S)
HALT TRANSMISSION
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Field
LCAM
RRRA
RST
ST
STP
RXEN
RXDIS
TXP
HTX
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FIGURE 6-4. Command Register
Note: This bit must not be set during transmission (TXP is set). The SONIC-T will lock up if both bits are set simultaneously.
RRRA: READ RRA
Setting this bit causes the SONIC-T to read the next RRA descriptor pointed to by the Resource Read Pointer (RRP)
register. Generally this bit is only set during initialization. Setting this bit during normal operation can cause improper
receive operation.
7
RST: SOFTWARE RESET
Setting this bit resets all internal state machines. The CRC generator is disabled and the Tally counters are halted,
but not cleared. The SONIC-T becomes operational when this bit is reset to ‘‘0’’. A hardware reset sets this bit to a
‘‘1’’. It must be reset to ‘‘0’’ before the SONIC-T becomes operational.
O
8
6
Must be 0
5
ST: START TIMER
Setting this bit enables the general-purpose watchdog timer to begin counting or to resume counting after it has
been halted. This bit is reset when the timer is halted (i.e., STP is set). Setting this bit resets STP.
4
STP: STOP TIMER
Setting this bit halts the general-purpose watchdog timer and resets the ST bit. The timer resumes when the ST bit is
set. This bit powers up as a ‘‘1’’. Note: Simultaneously setting bits ST and STP stops the timer.
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6.0 SONIC-T Registers (Continued)
6.4.1 Command Register (Continued)
Bit
Description
3
RXEN: RECEIVER ENABLE
Setting this bit enables the receive buffer management engine to begin buffering data to memory. Setting this bit
resets the RXDIS bit. Note: If this bit is set while the MAC unit is currently receiving a packet, both RXEN and RXDIS
are set until the network goes inactive (i.e., the SONIC-T will not start buffering in the middle of a packet being
received). When both RXEN and RXDIS are set, RXEN could be cleared by writing zero to it.
2
RXDIS: RECEIVER DISABLE
Setting this bit disables the receiver from buffering data to memory or the Receive FIFO. If this bit is set during the
reception of a packet, the receiver is disabled only after the packet is processed. The RXEN bit is reset when the
receiver is disabled. Tally counters remain active regardless of the state of this bit.
Note: If this bit is set while the SONIC-T is currently receiving a packet, both RXEN and RXDIS are set until the packet is fully received. When both
RXEN and RXDIS are set, RXDIS could be cleared by writing zero to it.
TXP: TRANSMIT PACKET(S)
Setting this bit causes the SONIC-T to transmit packets which have been set up in the Transmit Descriptor Area
(TDA). The SONIC-T loads its appropriate registers from the TDA, then begins transmission. The SONIC-T clears
this bit after any of the following conditions have occurred: (1) transmission had completed (i.e., after the SONIC-T
has detected EOL e 1), (2) the Halt Transmission command (HTX) has taken effect, or (3) a transmit abort condition
has occurred. This condition occurs when any of the following bits in the TCR have been set: EXC, EXD, FU, or BCM.
This bit must not be set if a Load CAM operation is in progress (LCAM is set). The SONIC-T will lock up if both bits
are set simultaneously.
0
HTX: HALT TRANSMISSION
Setting this bit halts the transmit command after the current transmission has completed. TXP is reset after
transmission has halted. The Current Transmit Descriptor Address (CTDA) register points to the last descriptor
transmitted. The SONIC-T samples this bit after writing to the TXpkt.status field.
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40
6.0 SONIC-T Registers (Continued)
6.4.2 Data Configuration Register
(RAk5:0l e 1h)
This register (Figure 6-5) establishes the bus cycle options for reading/writing data to/from 16- or 32-bit memory systems.
During a hardware reset, bits 15 and 13 are cleared; all other bits are unaffected. (Because of this, the first thing the driver
software does to the SONIC-T should be to set up this register.) All bits are unaffected by a software reset. This register must
only be accessed when the SONIC-T is in reset mode (i.e., the RST bit is set in the Command register).
15
14
13
12
EXBUS
0
LBR
PO1
PO0 SBUS USR1 USR0 WC1
r/w
r/w
r/w
r/w
11
10
r/w
9
r/w
8
7
r/w
r/w
6
5
WC0
DW
r/w
r/w
4
3
2
1
0
BMS RFT1 RFT0 TFT1 TFT0
r/w
r/w
r/w
r/w
r/w
r e read only, r/w e read/write
FIGURE 6-5. Data Configuration Register
Bit
Meaning
EXTENDED BUS MODE
LATCHED BUS RETRY
PROGRAMMABLE OUTPUTS
SYNCHRONOUS BUS MODE
USER DEFINABLE PINS
WAIT STATE CONTROL
DATA WIDTH SELECT
BLOCK MODE SELECT FOR DMA
RECEIVE FIFO THRESHOLD
TRANSMIT FIFO THRESHOLD
et
e
Field
EXBUS
LBR
PO0,PO1
SBUS
USR0, USR1
WC0, WC1
DW
BMS
RFT0, RFT1
TFT0, TFT1
Description
EXBUS: EXTENDED BUS MODE
Setting this bit enables the Extended Bus mode which enables the following:
1.Extended Programmable Outputs, EXUSR k3:0l: This changes the TXD, LBK, RXC and RXD pins from the
external ENDEC interface into four programmable user outputs, EXUSR k3:0l respectively, which are similar to
USR k1:0l. These outputs are programed with bits 15-12 in the DCR2 (see Section 6.4.7). On hardware reset,
these four pins will be TRI-STATE and will remain that way until the DCR is changed. If EXBUS is enabled, then
these pins will remain TRI-STATE until the SONIC-T becomes a bus master, at which time they will be driven
according to the DCR2. If EXBUS is disabled, then these four pins work normally as external ENDEC interface pins.
2. Synchronous Termination, STERM: This changes the TXC pin from the External ENDEC interface into a
synchronous memory termination input for compatibility with Motorola style processors. This input is only useful
when Asynchronous Bus mode is selected (bit 10 below is set to ‘‘0’’) and the Bus Mode is set to Motorola Mode
(BMODE e 1). On hardware reset, this pin will be TRI-STATE and will remain that way until the DCR is changed. If
EXBUS is enabled, this pin will remain TRI-STATE until the SONIC-T becomes a bus master, at which time it will
become the STERM input. If EXBUS is disabled, then this pin works normally as the TXC pin for the external ENDEC
interface.
3. Asynchronous Bus Retry: Causes BRT to be clocked in asynchronously off the falling edge of bus clock. This only
applies, however, when the SONIC-T is operating in asynchronous mode (bit 10 below is set to ‘‘0’’). If EXBUS is not
set, XTO (BRT) is sampled synchronously off the rising edge of bus clock.
14
Must be 0.
O
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ol
15
13
LBR: LATCHED BUS RETRY
The LBR bit controls the mode of operation of the BRT signal (see pin description, Section 2.0). It allows the BUS
Retry operation to be latched or unlatched.
0: Unlatched mode: The assertion of BRT forces the SONIC-T to finish the current DMA operation and get off the bus.
The SONIC-T will retry the operation when BRT is deasserted.
1: Latched mode: The assertion of BRT forces the SONIC-T to finish the current DMA operation as above, however,
the SONIC-T will not retry until BRT is deasserted and the BR bit in the ISR (see Section 6.4.6) has been reset and
BRT is deasserted. Hence, the mode has been latched on until the BR bit is cleared.
12, 11
PO1,PO0: PROGRAMMABLE OUTPUTS
The PO1,PO0 bits individually control the USR1,0 pins respectively when SONIC-T is a bus master (HLDA or BGACK
is active). When PO1/PO0 are set to a 1 the USR1/USR0 pins are high during bus master operations and when
these bits are set to a 0 the USR1/USR0 pins are low during bus master operations.
Note: Unless LBR is set to a ‘‘1’’, BRT must remain asserted at least until the SONIC-T has gone idle. See sec. 7.3.6.
41
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6.0 SONIC-T Registers (Continued)
6.4.2 Data Configuration Register (Continued)
Description
10
SBUS: SYNCHRONOUS BUS MODE
The SBUS bit is used to select the mode of system bus operation when SONIC-T is a bus master. This bit selects the internal
ready line to be either a synchronous or asynchronous input to SONIC-T during block transfer DMA operations.
0: Asynchronous mode. RDYi (BMODE e 0) or DSACK0,1 (BMODE e 1) are respectively internally synchronized
at the falling edge of the bus clock (T2 of the DMA cycle). No setup or hold times need to be met with kS2 –S5l
respect to this edge to guarantee proper bus operation. The minimum memory cycle time is 3 bus clocks.
1: Synchronous mode. RDYi (BMODE e 0) and DSACK0,1 (BMODE e 1) must respectively meet the setup and kS2 –S5l
hold times with respect to the rising edge of T1 or T2 to guarantee proper bus operation.
9, 8
USR1,0: USER DEFINABLE PINS
The USR1,0 bits report the level of the USR1,0 signal pins, respectively, after a chip hardware reset. If the USR1,0 signal pins
are at a logical 1 (tied to VCC) during a hardware reset the USR1,0 bits are set to a 1. If the USR1,0 pins are at a logical 0 (tied
to ground) during a hardware reset the USR1,0 bits are set to a 0. These bits are latched on the rising edge of RST. Once set
they remain set/reset until the next hardware reset.
7, 6
WC1,0: WAIT STATE CONTROL
These encoded bits determine the number of additional bus cycles (T2 states) that are added during each DMA cycle.
WC1
WC0
Bus Cycles Added
0
0
0
0
1
1
1
0
2
1
1
3
et
e
Bit
DW: DATA WIDTH SELECT
These bits select the data path width for DMA operations.
DW Data Width
0
16-bit
1
32-bit
4
BMS: BLOCK MODE SELECT FOR DMA
Determines how data is emptied or filled into the Receive or Transmit FIFO.
0: Empty/fill mode: All DMA transfers continue until either the Receive FIFO has emptied or the Transmit FIFO has
filled completely.
1: Block mode: All DMA transfers continue until the programmed number of bytes RFT0, (RFT1 during reception or
TF0, TF1 during transmission) have been transferred. (See note for TFT0, TFT1.)
bs
RFT1,RFT0: RECEIVE FIFO THRESHOLD
These encoded bits determine the number of words (or long words) that are written into the receive FIFO from the MAC unit
before a receive DMA request occurs. (See Section 3.5.)
LB1
LB0
Function
0
0
2 words or 1 long word (4 bytes)
0
1
4 words or 2 long words (8 bytes)
1
0
8 words or 4 long words (16 bytes)
1
1
12 words or 6 long words (24 bytes)
O
3, 2
ol
5
Note: In block mode (BMS bit e 1), the receive FIFO threshold sets the number of words (or long words) written to memory during a receive DMA block cycle.
1, 0
TFT1,TFT0: TRANSMIT FIFO THRESHOLD
These encoded bits determine the minimum number of words (or long words) the DMA section maintains in the transmit
FIFO. A bus request occurs when the number of words drops below the transmit FIFO threshold. (See Section 3.5.)
LB1
LB0
Function
0
0
4 words or 2 long words (8 bytes)
0
1
18 words or 4 long words (16 bytes)
1
0
12 words or 6 long words (24 bytes)
1
1
14 words or 7 long words (28 bytes)
Note: In block mode (BMS e 1), the number of bytes the SONIC-T reads in a single DMA burst equals the transmit FIFO threshold value. If the number of
words or long words needed to fill the FIFO is less than the threshold value, then only the number of reads required to fill the FIFO in a single DMA burst will be
made. Typically, with the FIFO threshold value set to 12 or 14 words, the number of memory reads needed is less than the FIFO threshold value.
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42
6.0 SONIC-T Registers (Continued)
6.4.3 Receive Control Register
(RAk5:0l e 2h)
This register is used to filter incoming packets and provide status information of accepted packets (Figure 6-6). Setting any of
bits 15 – 11 to a ‘‘1’’ enables the corresponding receive filter. If none of these bits are set, only packets which match the CAM
Address registers are accepted. Bits 10 and 9 control the loopback operations.
After reception, bits 8–0 indicate status information about the accepted packet and are set to ‘‘1’’ when the corresponding
condition is true. If the packet is accepted, all bits in the RCR are written into the RXpkt.status field. Bits 8 – 6 and 3 – 0 are
cleared at the reception of the next packet.
This register is unaffected by a software reset.
15
14
13
12
11
10
9
8
7
6
5
ERR
RNT
BRD
PRO
AMC
LB1
LB0
MC
BC
LPKT
CRS
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r
r
r
r
4
3
2
COL CRCR FAER
r
r
r
1
0
LBK
PRX
r
r
r e read only, r/w e read/write
FIGURE 6-6. Receive Control Register
15
14
et
e
Description
ERR: ACCEPT PACKET WITH CRC ERRORS OR COLLISIONS
0: Reject all packets with CRC errors or when a collision occurs.
1: Accept packets with CRC errors and ignore collisions.
bs
Bit
Meaning
ACCEPT PACKET WITH ERRORS
ACCEPT RUNT PACKETS
ACCEPT BROADCAST PACKETS
PHYSICAL PROMISCUOUS PACKETS
ACCEPT ALL MULTICAST PACKETS
LOOPBACK CONTROL
MULTICAST PACKET RECEIVED
BROADCAST PACKET RECEIVED
LAST PACKET IN RBA
CARRIER SENSE ACTIVITY
COLLISION ACTIVITY
CRC ERROR
FRAME ALIGNMENT ERROR
LOOPBACK PACKET RECEIVED
PACKET RECEIVED OK
ol
Field
ERR
RNT
BRD
PRO
AMC
LB0,LB1
MC
BC
LPKT
CRS
COL
CRCR
FAER
LBK
PRX
RNT: ACCEPT RUNT PACKETS
0: Normal address match mode.
1: Accept runt packets (packets less than 64 bytes in length).
Note: A hardware reset clears this bit.
BRD: ACCEPT BROADCAST PACKETS
0: Normal address match mode.
1: Accept broadcast packets (packets with addresses that match the CAM are also accepted).
O
13
Note: This bit is cleared upon hardware reset.
12
PRO: PHYSICAL PROMISCUOUS MODE
Enable all Physical Address packets to be accepted.
0: normal address match mode.
1: promiscuous mode.
11
AMC: ACCEPT ALL MULTICAST PACKETS
0: normal address match mode.
1: enables all multicast packets to be accepted. Broadcast packets are also accepted regardless
of the BRD bit. (Broadcast packets are a subset of multicast packets.)
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6.0 SONIC-T Registers (Continued)
6.4.3 Receive Control Register (Continued)
Bit
Description
10, 9 LB1,LB0: LOOPBACK CONTROL
These encoded bits control loopback operations for MAC loopback, ENDEC loopback and Transceiver lookback. For proper
loopback operation, the CAM Address registers and Receive Control register must be initialized to accept the Destination
address of the loopback packet (see Section 3.8).
LB1 LB0
Function
0
0 no loopback, normal operation
0
1 MAC loopback
1
0 ENDEC loopback
1
1 Transceiver loopback (Bit Ý6 of the DCR2 must also be set to 1)
MC: MULTICAST PACKET RECEIVED
This bit is set when a packet is received with a Multicast Address.
7
BC: BROADCAST PACKET RECEIVED
This bit is set when a packet is received with a Broadcast Address.
6
LPKT: LAST PACKET IN RBA
This bit is set when the last packet is buffered into a Receive Buffer Area (RBA). The SONIC-T detects this condition when its
Remaining Buffer Word Count (RBWC0,1) register is less than or equal to the End Of Buffer Count (EOBC) register. (See
Section 5.4.2.)
5
CRS: CARRIER SENSE ACTIVITY
Set when CRS is active. Indicates the presence of network activity.
4
COL: COLLISION ACTIVITY
Indicates that the packet received had a collision occur during reception.
3
CRCR: CRC ERROR
Indicates the packet contains a CRC error. If the packet also contains a Frame Alignment error, FAER will be set instead (see
below).
2
FAER: FRAME ALIGNMENT ERROR
Indicates that the incoming packet was not correctly framed on an 8-bit boundary. Note: if no CRC errors have occurred, this bit
is not set (i.e., this bit is only set when both a frame alignment and CRC errors occur).
1
LBK: LOOPBACK PACKET RECEIVED
Indicates that the SONIC-T has successfully received a loopback packet.
0
PRX: PACKET RECEIVED OK
Indicates that a packet has been received without CRC, frame alignment, length (run packet) errors or collisions.
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44
6.0 SONIC-T Registers (Continued)
6.4.4 Transmit Control Register
(RAk5:0l e 3h)
This register is used to program the SONIC-T’s transmit actions and provide status information after a packet has been
transmitted (Figure 6-7). At the beginning of transmission, bits 15, 14, 13 and 12 from the TXpkt.config field are loaded into the
TCR to configure the various transmit modes (see Section 5.5.1.1). When the transmission ends, bits 10 – 0 indicate status
information and are set to a ‘‘1’’ when the corresponding condition is true. These bits, along with the number of collisions
information, are written into the TXpkt.status field at the end of transmission (see Section 5.5.1.2). Bits 9 and 5 are cleared after
the TXpkt.status field has been written. Bits 10, 7, 6, and 1 are cleared at the commencement of the next transmission while bit 8
is set at this time.
.
A hardware reset sets bits 8 and 0 to a ‘‘1’’, and bit 1 to a ‘‘0’’. . . This register is unaffected by a software reset.
15
14
13
12
PINT POWC CRCI EXDIS
r/w
r/w
r/w
r/w
11
10
0
EXD
r
r
9
8
7
DEF NCRS CRSL
r
r
6
5
4
3
2
1
0
EXC
OWC
0
PMB
FU
BCM
PTX
r
r
r
r
r
r
r
r
r e read only, r/w e read/write
FIGURE 6-7. Transmit Control Register
Bit
et
e
Description
PINTR: PROGRAMMABLE INTERRUPT
This bit allows transmit interrupts to be generated under software control. The SONIC-T will issue an interrupt (PINT
in the Interrupt Status Register) immediately after reading a TDA and detecting that PINT is set in the TXpkt.config
field.
bs
15
Meaning
PROGRAMMABLE INTERRUPT
PROGRAMMED OUT OF WINDOW COLLISION TIMER
CRC INHIBIT
DISABLE EXCESSIVE DEFERRAL TIMER
EXCESSIVE DEFERRAL
DEFERRED TRANSMISSION
NO CRS
CRS LOST
EXCESSIVE COLLISIONS
OUT OF WINDOW COLLISION
PACKET MONITORED BAD
FIFO UNDERRUN
BYTE COUNT MISMATCH
PACKET TRANSMITTED OK
ol
Field
PINT
POWC
CRCI
EXDIS
EXD
DEF
NCRS
CRSL
EXC
OWC
PMB
FU
BCM
PTX
Note: In order for PINT to operate properly, it must be set and reset in the TXpkt.config field by alternating TDAs. This is necessary because after
PINT has been issued in the ISR, PINT in the Transmit Control Register must be cleared before it is set again in order to have the interrupt issued for
another packet. The only effective way to do this is to set PINT to a 1 no more often than every other packet.
POWC: PROGRAM ‘‘OUT OF WINDOW COLLISION’’ TIMER
This bit programs when the out of window collision timer begins.
0: timer begins after the Start of Frame Delimiter (SFD).
1: timer begins after the first bit of preamble.
O
14
13
CRCI: CRC INHIBIT
0: transmit packet with 4-byte FCS field
1: transmit packet without 4-byte FCS field
12
EXDIS: DISABLE EXCESSIVE DEFERRAL TIMER:
0: excessive deferral timer enabled
1: excessive deferral timer disabled
11
Must be 0.
10
EXD: EXCESSIVE DEFERRAL
Indicates that the SONIC-T has been deferring for 3.2 ms. The transmission is aborted if the excessive deferral timer
is enabled (i.e., EXDIS is reset). This bit can only be set if the excessive deferral timer is enabled.
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6.0 SONIC-T Registers (Continued)
6.4.4 Transmit Control Register (Continued)
Bit
Description
9
DEF: DEFERRED TRANSMISSION
Indicates that the SONIC-T has deferred its transmission during the first attempt. If subsequent collisions occur, this
bit is reset. This bit is cleared after the TXpkt.status field is written in the TDA.
8
NCRS: NO CRS
Indicates that Carrier Sense (CRS) was not present during transmission. CRS is monitored from the beginning of the
Start of Frame Delimiter to the last byte transmitted. The transmission will not be aborted. This bit is set at the start
of preamble and is reset if CRS is detected. Hence, if CRS is never detected throughout the entire transmission of
the packet, this bit will remain set.
Note: NCRS will always remain set in MAC loopback as long as there is no activity on the RX g .
7
CRSL: CRS LOST
Indicates that CRS has gone low or has not been present during transmission. CRS is monitored from the beginning
of the Start of Frame Delimiter to the last byte transmitted. The transmission will not be aborted.
Note: if CRS was never present, both NCRS and CRSL will be set simultaneously. Also, CRSL will always be set in MAC loopback.
EXC: EXCESSIVE COLLISIONS
Indicates that 16 collisions have occurred. The transmission is aborted.
5
OWC: OUT OF WINDOW COLLISION
Indicates that an illegal collision has occurred after 51.2 ms (one slot time) from either the first bit of preamble or
from SFD depending upon the POWC bit. The transmission backs off as in a normal transmission. This bit is cleared
after the TXpkt.status field is written in the TDA.
4
Must be 0.
3
PMB: PACKET MONITORED BAD
This bit is set, if after the receive unit has monitored the transmitted packet, the CRC has been calculated as invalid
as a result of a Frame Alignment error, or the Source Address does not match any of the CAM address registers.
Note 1: The SONIC-T’s CRC checker is active during transmission.
et
e
6
ol
Note 2: If CRC has been inhibited for transmissions (CRCI is set), this bit will always be low. This is true regardless of Frame Alignment or Source
Address mismatch errors.
Note 3: If a Receive FIFO overrun has occurred, the transmitted packet is not monitored completely. Thus, if PMB is set along with the RFO bit in the
ISR, then PMB has no meaning. The packet must be completely received before PMB has meaning.
Note 4: This bit is always zero in loopback mode. (True for all three types of looback mode.)
FU: FIFO UNDERRUN
Indicates that the SONIC-T has not been able to access the bus before the FIFO has emptied. This condition occurs
from excessive bus latency and/or slow bus clock. The transmission is aborted. (See Section 3.5.2.)
1
BCM: BYTE COUNT MISMATCH
This bit is set when the SONIC-T detects that the TXpkt.pktÐsize field is not equal to the sum of the
TXpkt.fragÐsize field(s). Transmission is aborted. This bit will also be set when Excessive Collisions (bit 6 of the
transmit control register) occur during transmission.
0
PTX: PACKET TRANSMITTED OK
Indicates that a packet has been transmitted without the following errors:
ÐExcessive Collisions (EXC)
ÐExcessive Deferral (EXD)
ÐFIFO Underrun (FU)
ÐByte Count Mismatch (BCM)
O
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6.0 SONIC-T Registers (Continued)
6.4.5 Interrupt Mask Register
(RAk5:0l e 4h)
This register masks the interrupts that can be generated from the ISR (Figure 6-8). Writing a ‘‘1’’ to the bit enables the
corresponding interrupt. During a hardware reset, all mask bits are cleared.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0 BREN HBLEN LCDEN PINTEN PRXEN PTXEN TXEREN TCEN RDEEN RBEEN RBAEEN CRCEN FAEEN MPEN RFOEN
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w e read/write
FIGURE 6-8. Interrupt Mask Register
Meaning
BUS RETRY OCCURRED ENABLE
HEARTBEAT LOST ENABLE
LOAD CAM DONE INTERRUPT ENABLE
PROGRAMMABLE INTERRUPT ENABLE
PACKET RECEIVED ENABLE
PACKET TRANSMITTED OK ENABLE
TRANSMIT ERROR ENABLE
TIMER COMPLETE ENABLE
RECEIVE DESCRIPTORS ENABLE
RECEIVE BUFFERS EXHAUSTED ENABLE
RECEIVE BUFFER AREA EXCEEDED ENABLE
CRC TALLY COUNTER WARNING ENABLE
FAE TALLY COUNTER WARNING ENABLE
MP TALLY COUNTER WARNING ENABLE
RECEIVE FIFO OVERRUN ENABLE
Bit
et
e
Field
BREN
HBLEN
LCDEN
PINTEN
PRXEN
PTXEN
TXEREN
TCEN
RDEEN
RBEEN
RBAEEN
CRCEN
FAEEN
MPEN
RFOEN
Description
Must be 0
14
BREN: BUS RETRY OCCURRED enabled:
0: disable
1: enables interrupts when a Bus Retry operation is requested.
13
HBLEN: HEARTBEAT LOST enable:
0: disable
1: enables interrupts when a heartbeat lost condition occurs.
12
LCDEN: LOAD CAM DONE INTERRUPT enable:
0: disable
1: enables interrupts when the Load CAM command has finished.
11
PINTEN: PROGRAMMABLE INTERRUPT enable:
0: disable
1: enables programmable interrupts to occur when the PINT bit the TXpkt.config field is set to a ‘‘1’’.
O
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15
10
PRXEN: PACKET RECEIVED enable:
0: disable
1: enables interrupts for packets accepted.
9
PTXEN: PACKET TRANSMITTED OK enable:
0: disable
1: enables interrupts for transmit completions.
8
TXEREN: TRANSMIT ERROR enable:
0: disable
1: enables interrupts for packets transmitted with error.
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6.0 SONIC-T Registers (Continued)
6.4.5 Interrupt Mask Register (Continued)
Bit
Description
TCEN: GENERAL PURPOSE TIMER COMPLETE enable:
0: disable
1: enables interrupts when the general purpose timer has rolled over from 0000 0000h to FFFF FFFFh.
6
RDEEN: RECEIVE DESCRIPTORS EXHAUSTED enable:
0: disable
1: enables interrupts when all receive descriptors in the RDA have been exhausted.
5
RBEEN: RECEIVE BUFFERS EXHAUSTED enable:
0: disable
1: enables interrupts when all resource descriptors in the RRA have been exhausted.
4
RBAEEN: RECEIVE BUFFER AREA EXCEEDED enable:
0: disable
1: enables interrupts when the SONIC-T attempts to buffer data beyond the end of the Receive Buffer Area.
3
CRCEN: CRC TALLY COUNTER WARNING enable:
0: disable
1: enables interrupts when the CRC tally counter has rolled over from FFFFh to 0000h.
2
FAEEN: FRAME ALIGNMENT ERROR (FAE) TALLY COUNTER WARNING enable:
0: disable
1: enables interrupts when the FAE tally counter rolled over from FFFFh to 0000h.
1
MPEN: MISSED PACKET (MP) TALLY COUNTER WARNING enable:
0: disable
1: enables interrupts when the MP tally counter has rolled over from FFFFh to 0000h.
0
RFOEN: RECEIVE FIFO OVERRUN enable:
0: disable
1: enables interrupts when the receive FIFO has overrun.
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48
6.0 SONIC-T Registers (Continued)
6.4.6 Interrupt Status Register
(RAk5:0l e 5h)
This register (Figure 6-9) indicates the source of an interrupt when the INT pin goes active. Enabling the corresponding bits in
the IMR allows bits in this register to produce an interrupt. When an interrupt is active, one or more bits in this register are set to
a ‘‘1’’. A bit is cleared by writing ‘‘1’’ to it. Writing a ‘‘0’’ to any bit has no effect.
This register is cleared by a hardware reset and unaffected by a software reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
BR
HBL
LCD
PINT
PKTRX
PTDN
TXER
TC
RDE
RBE
RBAE
CRC
FAE
MP
RFO
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w e read/write
FIGURE 6-9. Interrupt Status Register
Bit
et
e
Meaning
BUS RETRY OCCURRED
CD HEARTBEAT LOST
LOAD CAM DONE
PROGRAMMABLE INTERRUPT
PACKET RECEIVED
TRANSMISSION DONE
TRANSMIT ERROR
TIMER COMPLETE
RECEIVE DISCRIPTORS EXHAUSTED
RECEIVE BUFFERS EXHAUSTED
RECEIVE BUFFER AREA EXCEEDED
CRC TALLY COUNTER ROLLOVER
FRAME ALIGNMENT ERROR
MISSED PACKET COUNTER ROLLOVER
RECEIVE FIFO OVERRUN
ol
Field
BR
HBL
LCD
PINT
PKTRX
TXDN
TXER
TC
RDE
RBE
RBAE
CRC
FAE
MP
RFO
Description
Must be 0
14
BR: BUS RETRY OCCURRED
Indicates that a Bus Retry (BRT) operation has occurred. In Latched Bus Retry mode (LBR in the DCR), BR will only
be set when the SONIC-T is a bus master. Before the SONIC-T will continue any DMA operations, BR must be
cleared. In Unlatched mode, the BR bit should be cleared also, but the SONIC-T will not wait for BR to be cleared
before requesting the bus again and continuing its DMA operations. (See Sections 6.4.2 and 7.3.6 for more
information on Bus Retry.)
13
HBL: CD HEARTBEAT LOST
If the transceiver fails to provide a collision pulse (heart beat) during the first 6.4 ms of the Interframe Gap after
transmission, this bit is set.
12
LCD: LOAD CAM DONE
Indicates that the Load CAM command has finished writing to all programmed locations in the CAM.
(See Section 6.1.1.)
O
bs
15
11
PINT: PROGRAMMED INTERRUPT
Indicates that upon reading the TXpkt.config field, the SONIC-T has detected the PINT bit to be set.
(See Section 6.4.4.)
10
PKTRX: PACKET RECEIVED
Indicates that a packet has been received and been buffered to memory. This bit is set after the RXpkt.seqÐno field
is written to memory.
9
TXDN: TRANSMISSION DONE
Indicates that either (1) there are no remaining packets to be transmitted in the Transmit Descriptor Area (i.e., the
EOL bit has been detected as a ‘‘1’’), (2) the Halt Transmit command has been given (HTX bit in CR is set to a ‘‘1’’),
or (3) a transmit abort condition has occurred. This condition occurs when any of following bits in the TCR are set:
BCM, EXC, FU, or EXD. This bit is set after the TXpkt.status field has been written to.
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6.0 SONIC-T Registers (Continued)
6.4.6 Interrupt Status Register (Continued)
Bit
Description
TXER: TRANSMIT ERROR
Indicates that a packet has been transmitted with at least one of the following errors.
ÐByte count mismatch (BCM)
ÐExcessive collisions (EXC)
ÐFIFO underrun (FU)
ÐExcessive deferral (EXD)
The TXpkt.status field reveals the cause of the error(s).
7
TC: GENERAL PURPOSE TIMER COMPLETE
Indicates that the timer has rolled over from 0000 0000h to FFFF FFFFh. (See Section 6.4.12.)
6
RDE: RECEIVE DESCRIPTORS EXHAUSTED
Indicates that all receive packet descriptors in the RDA have been exhausted. This bit is set when the SONIC-T
detects EOL e 1. (See Section 5.4.7.)
5
RBE: RECEIVE BUFFER EXHAUSTED
Indicates that the SONIC-T has detected the Resource Read Pointer (RRP) is equal to the Resource Write Pointer
(RWP). This bit is set after the last field is read from the resource area. (See Section 5.4.7.)
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Note 1: This bit will be set as the SONIC-T finishes using the second to last receive buffer and reads the last RRA descriptor. This gives the system
an early warning of impending no resources.
Note 2: The SONIC-T will stop reception of packets when the last RBA has been used and will not continue reception until additional receive buffers
have been added (i.e., RWP is incremented beyond RRP) and this bit has been reset.
Note 3: If additional buffers have been added, resetting this bit causes the SONIC-T to read the next resource descriptor pointed to by the RRP in
the Receive Resource Area. Note that resetting this bit under this condition is similar to issuing the Read RRA command (setting the RRRA bit in the
Command Register). This bit should never be reset until after the additional resources have been added to the RRA.
RBAE: RECEIVE BUFFER AREA EXCEEDED
Indicates that during reception, the SONIC-T has reached the end of the Receive Buffer Area. Reception is aborted
and the SONIC-T fetches the next available resource descriptors in the RRA. The buffer space is not re-used and an
RDA is not set up for the truncated packet (see Section 5.4.7).
3
CRC: CRC TALLY COUNTER ROLLOVER
Indicates that the tally counter has rolled over from FFFFh to 0000h. (See Section 6.4.11.)
2
FAE: FRAME ALIGNMENT ERROR (FAE) TALLY COUNTER ROLLOVER
Indicates that the FAE tally counter has rolled over from FFFFh to 0000h. (See Section 6.4.11.)
1
MP: MISSED PACKET (MP) COUNTER ROLLOVER
Indicates that the MP tally counter has rolled over from FFFFh to 0000h. (See Section 6.4.11.)
0
RFO: RECEIVE FIFO OVERRUN
Indicates that the SONIC-T has been unable to access the bus before the receive FIFO has filled from the network.
This condition is due to excessively long bus latency and/or slow bus clock. Note that FIFO underruns are indicated
in the TCR. (See Section 3.5.1.)
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6.0 SONIC-T Registers (Continued)
6.4.7 Data Configuration Register 2
(RAk5:0l e 3Fh)
This register (Figure 6-10) is for enabling the extended bus interface options.
A hardware reset will set all bits in this register to ‘‘0’’ except for the Extended Programmable Outputs which are unknown until
written to. A software reset will not affect any bits in this register. This register should only be written to when the SONIC-T is in
software reset (the RST bit in the Command Register is set).
14
13
12
r/w
r/w
r/w
r/w
11
10
9
8
7
6
5
4
3
HD
0
JD
AUTO
0
XWRAP
FD
PH
0
r/w r/w r/w
r/w
r/w
r/w
r/w r/w r/w
FIGURE 6-10. Data Configuration Register 2
Field
EXPO3–0
HD
JD
AUTO
XWRAP
FD
PH
PCM
PCNM
RJCM
Bit
15 – 12
2
1
0
PCM PCNM RJCM
r/w
r/w
r/w
Meaning
EXTENDED PROGRAMMABLE OUTPUTS
HEART BEAT DISABLE
TPI JABBER TIMER DISABLE
AUI/TPI AUTO SELECTION
TPI TRANSCEIVER LOOPBACK
FULL DUPLEX
PROGRAM HOLD
PACKET COMPRESS WHEN MATCHED
PACKET COMPRESS WHEN NOT MATCHED
REJECT ON CAM MATCH
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EXPO3 EXPO2 EXPO1 EXPO0
Description
EXPOk3:0l EXTENDED PROGRAMMABLE OUTPUTS
11
HD: HEART BEAT DISABLE
This bit allows the SONIC-T to ignore the heart beat signal.
0: Enable heart beat.
1: Disable heart beat.
JD: TPI JABBER TIMER DISABLE
This bit allows the user to turn on/off the jabber timer.
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These bits program the level of the Extended User outputs (EXUSRk3:0l) when the SONIC-T is a bus master.
Writing a ‘‘1’’ to any of these bits programs a high level to the corresponding output. Writing a ‘‘0’’ to any of these
bits programs a low level to the corresponding output. EXUSRk3:0l are similiar to USRk1:0l except that
EXUSRk3:0l are only available when the Extended Bus mode is selected (bit 15 in the DCR is set to ‘‘1’’, see
Section 6.4.2).
0: Enable the jabber timer.
1: Disable the jabber timer.
AUTO: AUI/TPI AUTO SELECTION
This bit allows the SONIC-T to check for a good link on the TPI and AUI. SONIC-T will first look for a good link on the
TPI. If there is no good link on the TPI, SONIC-T will automatically select the AUI. If this bit is enable, the AUI/TPI pin
will be ignored.
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0: Disable AUI/TPI auto selection.
1: Enable AUI/TPI auto selection.
7
Must be zero.
6
XWRAP: TPI TRANSCEIVER LOOPBACK
This bit controls the loopback operation for the TPI transceiver. For proper operation, the CAM Address Registers
and Receiver Control Register must be initialized to accept the destination address of the loopback packet (refer to
loopback procedure). Also, both bits 9 and 10 of the RCR must be set to 1.
0: Disable TPI transceiver loopback.
1: Enable TPI transceiver loopback.
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6.0 SONIC-T Registers (Continued)
6.4.7 Data Configuration Register 2 (Continued)
Bit
Description
5
FD: FULL DUPLEX
This bit programs the SONIC-T to transmit and receive simultaneously (Full Duplex). This bit should only be set when
used in conjunction with a port that supports and is configured for Full Duplex Ethernet.
0: Disable full duplex mode.
1: Enable full duplex mode.
4
PH: PROGRAM HOLD
When this bit is set to ‘‘0’’, the HOLD request output is asserted/deasserted from the falling edge of bus clock. If this
bit is set to ‘‘1’’, HOLD will be asserted/deasserted (/2 clock later on the rising edge of bus clock.
3
Must be zero.
2
PCM: PACKET COMPRESS WHEN MATCHED
When this bit is set to a ‘‘1’’ (and the PCNM bit is reset to a ‘‘0’’), the PCOMP output will be asserted if the
destination address of the packet being received matches one of the entries in the CAM (Content Addressable
Memory). This bit, along with PCNM, is used with the Management Bus of the DP83950, Repeater Interface
Controller (RIC). See the DP83950 datasheet for more details on the RIC Management Bus. This mode is also called
the Managed Bridge Mode.
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Note 1: Setting PCNM and PCM to ‘‘1’’ at the same time is not allowed.
Note 2: If PCNM and PCM are both ‘‘0’’, the PCOMP output will remain TRI-STATE until PCNM or PCM are changed.
1
PCNM: COMPRESS WHEN NOT MATCHED
When this bit is set to a ‘‘1’’ (and the PCM bit is set to ‘‘0’’), the PCOMP output will be asserted if the destination
address of the packet does not match one of the entries in the CAM. See the PCM bit above. This mode is also
called the Managed Hub Mode.
Note: PCOMP will not be asserted if the destination address is a broadcast address. This is true regardless of the state of the BRD bit in the
Receive Control Register.
RJCM: REJECT ON CAM MATCH
When this bit is set to ‘‘1’’, the SONIC-T will reject a packet on a CAM match. Setting RJCM to ‘‘0’’ causes the
SONIC-T to operate normally by accepting packets on a CAM match. Setting this mode is useful for a small bridge
with a limited number of nodes attached to it. RJCM only affects the CAM, though. Setting RJCM will not invert the
function of the BRD, PRO or AMC bits (to accept broadcast, all physical or multicast packets respectively) in the
Receive Control Register (see Section 6.4.3). This means, for example, that it is not possible to set RJCM and BRD
to reject all broadcast packets. If RJCM and BRD are set at the same time, however, all broadcast packets will be
accepted, but any packets that have a destination address that matches an address in the CAM will be rejected.
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6.0 SONIC-T Registers (Continued)
the remaining number of words in the RBA after the packet
is received (i.e., EOBC l RBWC0,1), the Last Packet in
RBA bit, LPKT in the Receive Control Register, Section
6.4.3, is set and the SONIC-T fetches the next resource
descriptor. Hence, the next packet received will be buffered
in a new RBA. A hardware reset sets this register to 02F8H
(760 words or 1520 bytes). See Sections 5.4.2 and 5.4.4.4
for more information about using EOBC.
Upper Receive Resource Address Register (URRA): The
URRA is a 16-bit read/write register. It is programmed with
the base address of the receive resource area (RRA). This
16-bit upper address value (A k31:16l) locates the receive
resource area in system memory. SONIC-T uses the URRA
register when accessing the receive descriptors within the
RRA by concatenating the lower address value from one of
four receive resource registers (RSA, REA, RWP, or RRP).
Resource Start Address Register (RSA): The RSA is a
15-bit read/write register. The LSB is not used and always
reads back as a 0. The RSA is programmed with the lower
15 bits (Ak15:1l) of the starting address of the receive
resource area. SONIC-T concatenates the contents of this
register with the contents of the URRA to form the complete
32-bit address.
Resource End Address Register (REA): The REA is a
15-bit read/write register. The LSB is not used and always
reads back as a 0. The REA is programmed with the lower
15 bits (Ak15:1l) of the ending address of the receive
resource area. SONIC-T concatenates the contents of this
register with the contents of the URRA to form the complete
32-bit address.
Resource Read Pointer Register (RRP): The RRP is a
15-bit read/write register. The LSB is not used and always
reads back as a 0. The RRP is programmed with the lower
15-bit address (Ak15:1l) of the first field of the next descriptor the SONIC-T will read. SONIC-T concatenates the
contents of this register with the contents of the URRA to
form the complete 32-bit address.
Resource Write Pointer Register (RWP): The RWP is a
15-bit read/write register. The LSB is not used and always
reads back as a 0. The RWP is programmed with the lower
15-bit address (Ak15:1l) of the next available location the
system can add a descriptor. SONIC-T concatenates the
contents of this register with the contents of the URRA to
form the complete 32-bit address. In 32-bit mode, bit 1, corresponding to address signal A1, must be zero to insure the
proper equality comparison between this register and the
RRP register.
Receive Sequence Counter Register (RSC): This is a
16-bit read/write register containing two fields (Figure 6-11) .
The SONIC-T uses this register to provide status information on the number of packets within a RBA and the number
of RBAs. The RSC register contains two 8-bit (modulo 256)
counters. After each packet is received the packet sequence number is incremented. The SONIC-T maintains a
single sequence number for each RBA. When the SONIC-T
uses the next RBA, the packet sequence number is reset to
zero and the RBA sequence number is incremented. This
register is reset to 0 by a hardware reset or by writing zero
to it. A software reset has no affect.
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6.4.8 Transmit Registers
The transmit registers described in this section are part of
the User Register set. The UTDA and CTDA must be initialized prior to issuing the transmit command (setting the TXP
bit) in the Command register.
Upper Transmit Descriptor Address Register (UTDA):
This register contains the upper address bits (Ak31:16l)
for accessing the transmit descriptor area (TDA) and is concatenated with the contents of the CTDA when the SONICT accesses the TDA in system memory. The TDA can be as
large as 32k words or 16k long words and can be located
anywhere in system memory. This register is unaffected by
a hardware or software reset.
Current Transmit Descriptor Address Register (CTDA):
The 16-bit CTDA register contains the lower address bits
(Ak15:1l) of the 32-bit transmit descriptor address. During
initialization this register must be programmed with the lower address bits of the transmit descriptor. The SONIC-T
concatenates the contents of this register with the contents
of the UTDA to point to the transmit descriptor. For 32-bit
memory systems, bit 1, corresponding to address signal A1,
must be set to ‘‘0’’ for alignment to long-word boundaries.
Bit 0 of this register is the End of List (EOL) bit and is used
to denote the end of the list. This register is unaffected by a
hardware or software reset.
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6.4.9 Receive Registers
The receive registers described in this section are part of
the User Register set. A software reset has no effect on
these registers and a hardware reset only affects the EOBC
and RSC registers. The receive registers must be initialized
prior to issuing the receive command (setting the RXEN bit)
in the Command register.
Upper Receive Descriptor Address Register (URDA):
This register contains the upper address bits (Ak31:16l)
for accessing the receive descriptor area (RDA) and is concatenated with the contents of the CRDA when the
SONIC-T accesses the RDA in system memory. The RDA
can be as large as 32k words or 16k long words and can be
located anywhere in system memory. This register is unaffected by a hardware or software reset.
Current Receive Descriptor Address Register (CRDA):
The CRDA is a 16-bit read/write register used to locate the
received packet descriptor block within the RDA. It contains
the lower address bits (A k15:1l). The SONIC-T concatenates the contents of the CRDA with the contents of the
URDA to form the complete 32-bit address. The resulting
32-bit address points to the first field of the descriptor block.
For 32-bit memory systems, bit 1, corresponding to address
signal A1, must be set to ‘‘0’’ for alignment to long-word
boundaries. Bit 0 of this register is the End of List (EOL) bit
and is used to denote the end of the list. This register is
unaffected by a hardware or software reset.
End of Buffer Word Count Register (EOBC): The
SONIC-T uses the contents of this register to determine
where to place the next packet. At the end of packet reception, the SONIC-T compares the contents of the EOBC register with the contents of the Remaining Buffer Word Count
registers (RBWC0,1) to determine whether: (1) to place the
next packet in the same RBA or (2) to place the next packet
in another RBA. If the EOBC is less than or equal to the
remaining number of words in the RBA after a packet is
received (i.e., EOBC s RBWC0,1), the SONIC-T buffers the
next packet in the same RBA. If the EOBC is greater than
15
8
RBA Sequence Number
(Modulo 256)
7
0
Packet Sequence Number
(Modulo 256)
FIGURE 6-11. Receive Sequence Counter Register
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6.0 SONIC-T Registers (Continued)
reads back as 0. The CDP is programmed with the lower
address (Ak15:1l) of the first field of the CAM descriptor
block in the CAM descriptor area (CDA) of system memory.
SONIC-T uses the contents of the CDP register when accessing the CAM descriptors. This register must be programmed by the user before issuing the LCAM command.
During execution of the LCAM Command SONIC-T concatenates the contents of this register with the contents of the
URRA register to form the complete 32-bit address. During
the Load CAM operation this register is incremented to address the fields in the CDA. After the Load Command completes this register points to the next location after the CAM
Descriptor Area.
CAM Descriptor Count Register (CDC): The CDC is a
5-bit read/write register. It is programmed with the number
of CAM descriptor blocks in the CAM descriptor area. This
register must be programmed by the user before issuing the
LCAM command. SONIC-T uses the value in this register to
determine how many entries to place in the CAM during
execution of the LCAM command. During LCAM execution
SONIC-T decrements this register each time it reads a descriptor block. When the CDC decrements to zero SONIC-T
terminates the LCAM execution. Since the CDC register is
programmed with the number of CAM descriptor blocks in
the CAM Descriptor Area, the value programmed into the
CDC register ranges 1 to 16 (1h to 10h).
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6.4.10 CAM Registers
The CAM registers described in this section are part of the
User Register set. They are used to program the Content
Addressable Memory (CAM) entries that provide address
filtering of packets. These registers, except for the CAM
Enable register, are unaffected by a hardware or software
reset.
CAM Entry Pointer Register (CEP): The CEP is a 4-bit
register used by SONIC-T to select one of the sixteen CAM
entries. SONIC-T uses the least significant 4-bits of this register. The value of 0h points to the first CAM entry and the
value of Fh points to the last entry.
CAM Address Port 2, 1, 0 Registers (CAP2, CAP1,
CAP0): Each CAP is a 16-bit read-only register used to access the CAM cells (Figure 6-13) . Each CAM cell is 16 bits
wide and contains one third of the 48-bit CAM entry (Figure
6-12) which is used by the SONIC-T for address filtering.
The CAP2 register is used to access the upper bits
(k47:32l), CAP1 the middle bits (k31:16l) and CAP0 the
lower bits (k15:0l) of the CAM entry. Given the physical
address 60:50:40:30:20:10, which is made up of 6 octets or
bytes, where 10h is the least significant byte and 60h is the
most significant byte (60h would be the first byte received
from the network and 10h would be the last), CAP0 would
be loaded with 2010h, CAP1 with 4030h and CAP2 with
6050h.
To read a CAM entry, the user first places the SONIC-T in
software reset (set the RST bit in the Command register),
programs the CEP register to select one of sixteen CAM
entries, then reads CAP2, CAP1, and CAP0 to obtain the
complete 48-bit entry. The user can not write to the CAM
entries directly. Instead, the user programs the CAM descriptor area in system memory (see Section 6.1.1), then
issues the Load CAM command (setting LCAM bit in the
Command register). This causes the SONIC-T to read the
descriptors from memory and loads the corresponding CAM
entry through CAP2–0.
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6.4.11 Tally Counters
The SONIC-T provides three 16-bit counters used for monitoring network statistics on the number of CRC errors,
Frame Alignment errors, and missed packets. These registers rollover after the count of FFFFh is reached and produce an interrupt if enabled in the Interrupt Mask Register
(IMR). These counters are unaffected by the RXEN bit in the
CR, but are halted when the RST bit in the CR is set. The
data written to these registers is inverted before being
latched. This means that if a value of FFFFh is written to
these registers by the system, they will contain and read
back the value 0000h. Data is not inverted during a read
operation. The Tally registers, therefore, are cleared by writing all ‘‘1’s’’ to them. A software or hardware reset does not
affect the tally counters.
CRC Tally Counter Register (CRCT): The CRCT is a 16-bit
read/write register. This register is used to keep track of the
number of packets received with CRC errors. After a packet
is accepted by the address recognition logic, this register is
incremented if a CRC error is detected. If the packet also
contains a Frame Alignment error, this counter is not incremented.
FAE Tally Counter Register (FAET): The FAET is a 16-bit
read/write register. This register is used to keep track of the
number of packets received with frame alignment errors.
After a packet is accepted by the address recognition logic,
this register is incremented if a FAE error is detected.
Missed Packet Tally Counter Register (MPT): The MPT is
a 16-bit read/write register. After a packet is received, this
counter is incremented if there is: (1) lack of memory resources to buffer the packet, (2) a FIFO overrun, or (3) a
valid packet has been received, but the receiver is disabled
(RXDIS is set in the command register).
LSB
0
bs
MSB
47
Destination Address
FIGURE 6-12. CAM Entry
47
32
CAP2
31
16
CAP1
15
0
CAP0
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FIGURE 6-13. CAM Address Port Registers
CAM Enable Register (CE): The CE is a 16-bit read/write
register used to mask out or enable individual CAM entries.
Each register bit position corresponds to a CAM entry.
When a register bit is set to a ‘‘1’’ the corresponding CAM
entry is enabled. When ‘‘0’’ the entry is disabled, this register is unaffected by a software reset and cleared to zero
(disabling all entries) during a hardware reset. Under normal
operations the user does not access this register. Instead
the user sets up this register through the last entry in the
CAM descriptor area. The SONIC-T loads the CE register
during execution of the LCAM Command.
CAM Descriptor Pointer Register (CDP): The CDP is a
15-bit read/write register. The LSB is unused and always
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6.0 SONIC-T Registers (Continued)
count designs and complete bus compatibility, the user can
program the SONIC-T for the following bus modes:
6.4.12 General Purpose Timer
The SONIC-T contains a 32-bit general-purpose Watchdog
Timer for timing user-definable events (Figure 6-14) . This
timer is accessed by the user through two 16-bit read/write
registers (WT1 and WT0). The lower count value is programmed through the WT0 register and the upper count
value is programmed through the WT1 register.
These two registers are concatenated together to form the
complete 32-bit timer. This timer, clocked at (/2 the Transmit
Clock (TXC) frequency, counts down from its programmed
value and generates an interrupt, if it is enabled Interrupt
Mask register, when it rolls over from 0000 0000h to FFFF
FFFFh. When the counter rolls over it continues decrementing unless explicitly stopped (setting the STP bit). The timer
is controlled by the ST (Start Timer) and STP (Stop Timer)
bits in the Command register. A hardware or software reset
halts, but does not clear, the General Purpose timer.
Ð National/Intel bus operating in synchronous mode
16
WT1 (Upper Count Value)
15
Ð Motorola bus operating in synchronous mode
Ð Motorola bus operating in asynchronous mode
The Bus Mode pin (BMODE) along with the SBUS bit in the
Data Configuration Register are used to select the bus
mode.
This section illustrates some SONIC-T system interface examples and describes the various SONIC-T bus operations.
7.1 PIN CONFIGURATIONS
There are two user selectable pin configurations for
SONIC-T to provide the proper interface signals for either
the National/Intel or Motorola style buses. The state of the
BMODE pin is used to define the pin configuration. Section
1.0 shows the pin configurations for both National/Intel
Mode (BMODE e 0, tied to ground) and Motorola Mode
(BMODE e 1, tied to VCC).
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7.2 SYSTEM CONFIGURATION
Any device that meets the SONIC-T interface protocol and
electrical requirements (timing, threshold, and loading) can
be interfaced to SONIC-T. Since two bus protocols are provided, via the BMODE pin, the SONIC-T can interface directly to most microprocessors. Figure 7-1 shows a typical
interface to the National/Intel style bus (BMODE e 0) and
Figure 7-2 shows a typical interface to the Motorola style
bus (BMODE e 1).
The BMODE pin also controls byte ordering. When
BMODE e 1 big endian byte ordering is selected and when
BMODE e 0 little endian byte ordering is selected.
WT0 (Lower Count Value)
FIGURE 6-14. Watchdog Timer Register
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Ð National/Intel bus operating in asynchronous mode
6.4.13 Silicon Revision Register
This is a 16-bit read only register. It contains information on
the current revision of the SONIC-T. The DP83936AVUL revision register is 0201h.
7.0 Bus Interface
SONIC-T features a high speed non-multiplexed address
and data bus designed for a wide range of system environments. The data bus can be programmed (via the Data Configuration Register) to a width of either 32- or 16-bits.
SONIC-T contains an on-chip DMA and supplies all the necessary signals for DMA operation. With 31 address lines
SONIC-T can access a full 2 G-word address space. To
accommodate different memory speeds, wait states can be
added to the bus cycle by two methods. The memory subsystem can add wait states by simply withholding the appropriate handshake signals or the SONIC-T can be programmed (via the Data Configuration Register) to add wait
states.
The SONIC-T is designed to interface to both the National/
Intel and Motorola style buses. To facilitate minimum chip
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7.3 BUS OPERATIONS
There are two types of system bus operations: 1) SONIC-T
as a slave, and 2) SONIC-T as a bus master. When
SONIC-T is a slave (e.g., a CPU accessing SONIC-T registers) all transfers are non-DMA. When SONIC-T is a bus
master (e.g., SONIC-T accessing receive or transmit buffer/
descriptor areas) all transfers are block transfers using
SONIC-T’s on-chip DMA. This section describes the
SONIC-T bus operations. Pay special attention to all sections labeled as ‘‘Note’’. These conditions must be met for
proper bus operation.
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7.0 Bus Interface (Continued)
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FIGURE 7-1. SONIC-T to NS32532 Interface Example
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TL/F/12597 – 28
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7.0 Bus Interface (Continued)
TL/F/12597 – 29
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FIGURE 7-2. SONIC-T to Motorola 68030/20 Interface Example
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7.0 Bus Interface (Continued)
As shown in Figure 7-3, the SONIC-T will assert HOLD to
either the falling or rising edge of the bus clock (BSCK). The
default is for HOLD to be asserted on the falling edge. Setting the PH bit in the DCR2 (see Section 6.4.7) causes
HOLD to be asserted (/2 bus clock later on the rising edge
(shown by the dotted line). Before HOLD is asserted, the
SONIC-T checks the HLDA line. If HLDA is asserted, HOLD
will not be asserted until after HLDA has been deasserted
first.
7.3.1 Acquiring The Bus
The SONIC-T requests the bus when 1) its FIFO threshold
has been reached or 2) when the descriptor areas in memory (i.e., RRA, RDA, CDA, and TDA) are accessed. Note that
when the SONIC-T moves from one area in memory to another (e.g., RBA to RDA), it always deasserts its bus request
and then requests the bus again when accessing the next
area in memory.
The SONIC-T provides two methods to acquire the bus for
compatibility with National/Intel or Motorola type microprocessors. These two methods are selected by setting the
proper level on the BMODE pin.
Note: If HLDA is driven low to preempt the SONIC-T from the bus while the
SONIC-T is accessing the CAM (LCAM command), the SONIC-T will
get off the bus but will not deassert HOLD even though the status bit
will indicate idle state. If HLDA is driven low while the SONIC-T is
accessing descriptor areas (RRA, RDA, TDA), the SONIC-T will be
preempted normally (i.e., get off the bus and deassert HOLD) and the
HOLD signal will be reasserted again after one bus clock. If HLDA is
driven low while the SONIC-T is accessing data areas (RBA, TBA),
the SONIC-T will be preempted normally but may not reassert HOLD
unless required to do so depending on the threshold condition of the
FIFO.
Figures 7-3 and 7-4 show the National/Intel (BMODE e 0)
and Motorola (BMODE e 1) bus request timing. Descriptions of each mode follows. For both modes, when the
SONIC-T relinquishes the bus, there is an extra holding
state (Th) for one bus cycle after the last DMA cycle (T2).
This assures that the SONIC-T does not contend with another bus master after it has released the bus.
BMODE e 1
The Motorola protocol requires a 3-way handshake using a
BUS REQUEST, BUS GRANT, and BUS GRANT ACKNOWLEDGE handshake (Figure 7-4) . When using this protocol, the SONIC-T requests the bus by lowering BUS REQUEST BR. The CPU responds by issuing BUS GRANT BG.
Upon receiving BG, the SONIC-T assures that all devices
have relinquished control of the bus before using the bus.
The following signals must be deasserted before the SONIC-T acquires the bus:
BGACK
AS
DSACK0,1
STERM (Asynchronous Mode Only)
Deasserting BGACK indicates that the previous master has
released the bus. Deasserting AS indicates that the previous master has completed its cycle and deasserting
DSACK0,1 and STERM indicates that the previous slave
has terminated its connection to the previous master. The
SONIC-T maintains its mastership of the bus until it deasserts BGACK. It can not be preempted from the bus.
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BMODE e 0
The National/Intel processors require a 2-way handshake
using a HOLD REQUEST/HOLD ACKNOWLEDGE protocol
(Figure 7-3) . When the SONIC-T needs to access the bus, it
issues a HOLD REQUEST (HOLD) to the microprocessor.
The microprocessor, responds with a HOLD ACKNOWLEDGE (HLDA) to the SONIC-T. The SONIC-T then begins
its memory transfers on the bus. As long as the CPU maintains HLDA active, the SONIC-T continues until it has finished its memory block transfer. The CPU, however, can
preempt the SONIC-T from finishing the block transfer by
deasserting HLDA before the SONIC-T deasserts HOLD.
This allows a higher priority device to preempt the SONIC-T
from continuing to use the bus. The SONIC-T will request
the bus again later to complete any operation that it was
doing at the time of preemption. The HLDA signal is sampled synchronously by the SONIC-T at the rising edge of the
BSCK, setup time must be met to ensure proper operation.
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FIGURE 7-3. Bus Request Timing (BMODE e 0)
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FIGURE 7-4. Bus Request Timing (BMODE e 1)
TABLE 7-1. Bus Status
S2
S1
S0
1
1
1
The bus is idle. The SONIC-T is not
performing any transfers on the bus.
Status
1
0
1
The Transmit Descriptor Area (TDA) is
currently being accessed.
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7.3.2 Block Transfers
The SONIC-T performs block operations during all bus actions, thereby providing efficient transfers to memory. The
block cycle consists of three parts. The first part is the bus
acquisition phase, as discussed above, in which the
SONIC-T gains access to the bus. Once it has access of the
bus, the SONIC-T enters the second phase by transferring
data to/from its internal FIFOs or registers from/to memory.
The SONIC-T transfers data from its FIFOs in either EXACT
BLOCK mode or EMPTY/FILL.
EXACT BLOCK mode: In this mode the number of words
(or long words) transferred during a block transfer is determined by either the Transmit or Receive FIFO thresholds
programmed in the Data Configuration Register.
EMPTY/FILL mode: In this mode the DMA completely fills
the Transmit FIFO during transmission, or completely empties the Receive FIFO during reception. This allows for
greater bus latency.
When the SONIC-T accesses the Descriptor Areas (i.e.,
RRA, RDA, CDA, and TDA), it transfers data between its
registers and memory. All fields which need to be used are
accessed in one block operation. Thus, the SONIC-T performs 4 accesses in the RRA (see Section 5.4.4.2), 7 accesses in the RDA (see Section 5.4.6.1), 2, 3, or 6 accesses
in the TDA (see Section 5.5.4) and 4 accesses in the CDA.
0
1
The Transmit Buffer Area (TBA) is
currently being read.
0
1
1
The Receive Buffer Area (RBA) is
currently being written to. Only data is
being written, though, not a Source or
Destination address.
0
1
0
The Receive Buffer Area (RBA) is
currently being written to. Only the
Source or Destination address is being
written, though.
1
1
0
The Receive Resource Area (RRA) is
currently being read.
1
0
0
The Receive Descriptor Area (RDA) is
currently being accessed.
0
0
0
The CAM Descriptor Area (CDA) is
currently being accessed.
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7.3.3 Bus Status
The SONIC-T presents three bits of status information on
pins S2 – S0 which indicate the type of bus operation the
SONIC-T is currently performing (Table 7-1). Bus status is
valid when at the falling edge of AS or the rising edge of
ADS.
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7.0 Bus Interface (Continued)
reset the EOL bit since the last reception. If it has, the
SONIC-T buffers the packet as in the first case. Otherwise,
it rejects the packet and returns to idle.
7.3.3.1 Bus Status Transitions
When the SONIC-T acquires the bus, it only transfers data
to/from a single area in memory (i.e., TDA, TBA, RDA, RBA,
RRA, or CDA). Thus, the bus status pins remain stable for
the duration of the block transfer cycle with the following
three exceptions: 1) if the SONIC-T is accessed during a
block transfer, S2 –S0 indicates bus idle during the register
access, then returns to the previous status, 2) if the
SONIC-T finishes writing the Source Address during a block
transfer, S2 – S0 changes from [0,1,0] to [0,1,1], or 3) during
an RDA access between the RXpkt.seqÐno and RXpkt.link
access, and between the RXpkt.link and RXpkt.inÐuse access, S2 – S0 will respectively indicate idle [1,1,1] for 2 or 1
bus clocks. Status will be valid on the falling edge of AS or
rising edge of ADS.
7.3.4 Bus Mode Compatibility
For compatibility with different microprocessor and bus architectures, the SONIC-T operates in one of two modes (set
by the BMODE pin) called the National/Intel or little endian
mode (BMODE tied low) and the Motorola or big endian
mode (BMODE tied high). The definitions for several pins
change depending on the mode the SONIC-T is in. Table
7-2 shows these changes. These modes affect both master
and slave bus operations with the SONIC-T.
TABLE 7-2. Bus Mode Compatibility
Pin Name
BMODE e 0
(National/Intel)
BMODE e 1
(Motorola)
BR/HOLD
HOLD
BR
BG/HLDA
HLDA
BG
MRW/MWR
MWR
MRW
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Figure 7-5 illustrates the SONIC-T’s transitions through
memory during the process of transmission and reception.
During transmission, the SONIC-T reads the descriptor information from the TDA and then transmits data of the
packet from the TBA. The SONIC-T moves back and forth
between the TDA and TBA until all fragments and packets
are transmitted. During reception, the SONIC-T takes one of
two paths. In the first case (path A), when the SONIC-T
detects EOL e 0 from the previous reception, it buffers the
accepted packet into the RBA, and then writes the descriptor information to the RDA. If the RBA becomes depleted
(i.e., RBWC0,1 k EOBC), it moves to the RRA to read a
resource descriptor. In the second case (path B), when the
SONIC-T detects EOL e 1 from the previous reception, it
rereads the RXpkt.link field to determine if the system has
SWR
SRW
DSACK0/RDYi
RDYi
DSACK0
DSACK1/RDYo
RDYo
DSACK1
AS/ADS
ADS
AS
INT/INT
INT
INT
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SRW/SWR
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FIGURE 7-5. Bus Status Transitions
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7.0 Bus Interface (Continued)
includes programmed wait states, the DSACK0,1, STERM
or RDYi lines must be asserted at their proper times at the
end of the cycle during the last T2, not during a programmed wait state. The only exception to this is asynchronous mode where DSACK0,1 or RDYi would be asserted
during the last programmed wait state, T2 (wait). See the
timing for these signals in the timing diagrams for more specific information. Programmed wait states do not affect
Slave Mode bus cycles.
7.3.5 Master Mode Bus Cycles
In order to add additional compatibility with different bus
architectures, there are two other modes that affect the operation of the bus. These modes are called the synchronous
and asynchronous modes and are programmed by setting
or resetting the SBUS bit in the Data Configuration Register
(DCR). The synchronous and asynchronous modes do not
have an effect on slave accesses to the SONIC-T but they
do affect the master mode operation. Within the particular
bus/processor mode, synchronous and asynchronous
modes are very similar. This section discusses all four
modes of operation of the SONIC-T (National/Intel vs.
Motorola, synchronous vs. asynchronous) when it is a bus
master.
In this section, the rising edge of T1 and T2 means the
beginning of these states, and the falling edge of T1 and T2
means the middle of these states.
7.3.5.2 Memory Cycle for BMODE e 1,
Synchronous Mode
On the rising edge of T1, the SONIC-T asserts ECS to indicate that the memory cycle is starting. The address (A31 –
A1), bus status (S2 – S0) and the direction strobe (MRW) are
driven and do not change for the remainder of the memory
cycle. On the falling edge of T1, the SONIC-T deasserts
ECS and asserts AS.
In synchronous mode, DSACK0,1 are sampled on the rising
edge of T2. T2 states will be repeated until DSACK0,1 are
sampled properly in a low state. DSACK0,1 must meet the
setup and hold times with respect to the rising edge of bus
clock for proper operation.
During read cycles (Figure 7-6) data (D31 – D0) is latched at
the falling edge of T2 and DS is asserted at the falling edge
of T1. For write cycles (Figure 7-7) data is driven on the
falling edge of T1. If there are wait states inserted, DS is
asserted on the falling edge of T2. DS is not asserted for
zero wait state write cycles. The SONIC-T terminates the
memory cycle by deasserting AS and DS at the falling edge
of T2.
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7.3.5.1 Adding Wait States
To accommodate different memory speeds, the SONIC-T
provides two methods for adding wait states for its bus operations. Both of these methods can be used singly or in
conjunction with each other. A memory cycle is extended by
adding additional T2 states. The first method inserts waitstates by withholding the assertion of DSACK0,1/STERM or
RDYi. The other method allows software to program waitstates. Programming the WC0, WC1 bits in the Data Configuration Register allows 1 to 3 wait-states to be added on
each memory cycle. These wait states are inserted between
the T1 and T2 bus states and are called T2 (wait) bus
states. The SONIC-T will not look at the DSACK0,1, STERM
or RDYi lines until the programmed wait states have
passed. Hence, in order to complete a bus operation that
TL/F/12597 – 33
FIGURE 7-6. Memory Read, BMODE e 1, Synchronous (1 Wait-State)
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7.0 Bus Interface (Continued)
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FIGURE 7-7. Memory Write, BMODE e 1, Synchronous (1 Wait-State)
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7.3.5.3 Memory Cycle for BMODE e 1,
Asynchronous Mode
On the rising edge of T1, the SONIC-T asserts ECS to indicate that the memory cycle is starting. The address (A31–
A1), bus status (S2–S0) and the direction strobe (MRW) are
driven and do not change for the remainder of the memory
cycle. On the falling edge of T1, the SONIC-T deasserts
ECS and asserts AS.
In asynchronous mode, DSACK0,1 are asynchronously
sampled on the falling edge of both T1 and T2. DSACK0,1
do not need to be synchronized to the bus clock because
the chip always resolves these signals to either a high or
low state. If a synchronous termination of the bus cycle is
required, however, STERM may be used. STERM is sampled on the rising edge of T2 and must meet the setup and
hold times with respect to that edge for proper operation.
Meeting the setup time for DSACK0,1 or STERM guarantees that the SONIC-T will terminate the memory cycle 1.5
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bus clocks after DSACK0,1 were sampled, or 1 cycle after
STERM was sampled. T2 states will be repeated until
DSACK0,1 or STERM are sampled properly in a low state
(see note below).
During read cycles (Figures 7-8 and 7-9 ), data (D31 – D0) is
latched at the falling edge of T2 and DS is asserted at the
falling edge of T1. For write cycles (Figures 7-10 and 7-11 )
data is driven on the falling edge of T1. If there are wait
states inserted, DS is asserted on the falling edge of the first
T2 (wait). DS is not asserted for zero wait state write cycles.
The SONIC-T terminates the memory cycle by deasserting
AS and DS at the falling edge of T2.
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Note: If the setup time for DSACK0,1 is met during T1, or the setup time for
STERM is met during the first T2, the full asynchronous bus cycle will
take only 2 bus clocks. This may be an unwanted situation. If so,
DSACK0,1 and STERM should normally be deasserted during T1 and
the start of T2 respectively.
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7.0 Bus Interface (Continued)
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FIGURE 7-8. Memory Read, BMODE e 1, Asynchronous (1 Wait-State)
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FIGURE 7-9. Memory Read, BMODE e 1, Asynchronous (2 Wait-State)
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7.0 Bus Interface (Continued)
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FIGURE 7-10. Memory Write, BMODE e 1, Asynchronous (1 Wait-State)
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FIGURE 7-11. Memory Write, BMODE e 1, Asynchronous (2 Wait-State)
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7.0 Bus Interface (Continued)
In Synchronous mode, RDYi is sampled on the rising edge
at the end of T2 (the rising edge of the next T1). T2 states
will be repeated until RDYi is sampled properly. In a low
state RDYi must meet the setup and hold times with respect
to the rising edge of bus clock for proper operation.
During read cycles (Figure 7-12) , data (D31 – D0) is latched
at the rising edge at the end of T2. For write cycles (Figure
7-13) , data is driven on the falling edge of T1 and stays
driven until the end of the cycle.
7.3.5.4 Memory Cycle for BMODE e 0,
Synchronous Mode
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On the rising edge of T1, the SONIC-T asserts ADS and
ECS to indicate that the memory cycle is starting. The address (A31–A1), bus status (S2–S0) and the direction
strobe (MWR) are driven and do not change for the remainder of the memory cycle. On the falling edge of T1, the
SONIC-T deasserts ECS. ADS is deasserted on the rising
edge of T2.
TL/F/12597 – 39
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FIGURE 7-12. Memory Read, BMODE e 0, Synchronous (1 Wait-State)
TL/F/12597 – 40
FIGURE 7-13. Memory Write, BMODE e 0, Synchronous (1 Wait-State)
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7.0 Bus Interface (Continued)
SONIC-T will terminate the memory cycle 1.5 bus clocks
after RDYi was sampled. T2 states will be repeated until
RDYi is sampled properly in a low state (see note below).
During read cycles (Figures 7-14 and 7-15 ), data (D31 – D0)
is latched at the falling edge of T2 and DS is asserted at the
rising edge of T1. For write cycles (Figures 7-16 and 7-17 )
data is driven on the falling edge of T1. If there are wait
states inserted, DS is asserted on the rising edge of the first
T2 (wait). DS is not asserted for zero wait state write cycles.
The SONIC-T terminates the memory cycle by deasserting
DS at the falling edge of T2.
7.3.5.5 Memory Cycle for BMODE e 0,
Asynchronous Mode
On the rising edge of T1, the SONIC-T asserts ADS and
ECS to indicate that the memory cycle is starting. The address (A31 – A1), bus status (S2–S0) and the direction
strobe (MWR) are driven and do not change for the remainder of the memory cycle. On the falling edge of T1, the
SONIC-T deasserts ECS. ADS is deasserted on the rising
edge of T2.
In Asynchronous mode, RDYi is asynchronously sampled
on the falling edge of both T1 and T2. RDYi does not need
to be synchronized to the bus clock because the chip always resolves these signals to either a high or low state.
Meeting the setup time for RDYi guarantees that the
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Note: If the setup time for RDYi is met during T1, the full asynchronous bus
cycle will take only 2 bus clocks. This may be an unwanted situation.
If so, RDYi should be deasserted during T1.
TL/F/12597 – 41
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FIGURE 7-14. Memory Read, BMODE e 0, Asynchronous (1 Wait-State)
TL/F/12597 – 42
FIGURE 7-15. Memory Read, BMODE e 0, Asynchronous (2 Wait-State)
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7.0 Bus Interface (Continued)
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FIGURE 7-16. Memory Write, BMODE e 0, Asynchronous (1 Wait-State)
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FIGURE 7-17. Memory Write, BMODE e 0, Asynchronous (2 Wait-State)
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7.0 Bus Interface (Continued)
er slave operation. Once SAS has been driven low, between
one and two bus clocks after the assertion of CS, SMACK
will be asserted to signify that the SONIC-T has started the
slave cycle. Although CS is an asynchronous input, meeting
its setup time (as shown in Figures 7-19 and 7-20 ) will guarantee that SMACK, which is asserted off of a falling edge,
will be asserted 1 bus clock after the falling edge that CS is
clocked in on. This is assuming that the SONIC-T is not a
bus master when CS was asserted. If the SONIC-T is a bus
master, then, when CS is asserted, the SONIC-T will complete its current master bus cycle and get off the bus temporarily (see Section 7.3.8). In this case, SMACK will be asserted 5 bus clocks after the falling edge that CS was
clocked in on. This is assuming that there were no wait
states in the current master mode access. Wait states will
increase the time for SMACK to go low by the number of
wait states in the cycle.
If the slave access is a read cycle (Figure 7-19) , then the
data will be driven off the same edge as SMACK. If it is a
write cycle (Figure 7-20) , then the data will be latched in
exactly 2 bus clocks after the assertion of SMACK. In either
case, DSACK0,1 are driven low 2 bus clocks after SMACK
to terminate the slave cycle. For a read cycle, the assertion
of DSACK0,1 indicates valid register data and for a write
cycle, the assertion indicates that the SONIC-T has latched
the data. The SONIC-T deasserts DSACK0,1, SMACK and
the data if the cycle is a read cycle at the rising edge of SAS
or CS depending on which is deasserted first.
7.3.6 Bus Exceptions (Bus Retry)
The SONIC-T provides the capability of handling errors during the execution of the bus cycle (Figure 7-18) .
The system asserts BRT (bus retry) to force the SONIC-T to
repeat the current memory cycle. When the SONIC-T detects the assertion of BRT, it completes the memory cycle
at the end of T2 and gets off the bus by deasserting BGACK
or HOLD. Then, if Latched Bus Retry mode is not set (LBR
in the Data Configuration Register, Section 6.4.2), the
SONIC-T requests the bus again to retry the same memory
cycle. If Latched Bus Retry is set, though, the SONIC-T will
not retry until the BR bit in the ISR (see Section 6.4.6) has
been reset and BRT is deasserted. BRT has precedence of
terminating a memory cycle over DSACK0,1, STERM or
RDYi.
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BRT may be sampled synchronously or asynchronously by
setting the EXBUS bit in the DCR (see Section 6.4.2). If
synchronous Bus Retry is set, BRT is sampled on the rising
edge of T2. If asynchronous Bus Retry is set, BRT is double
synchronized from the falling edge of T1. The asynchronous
setup time does not need to be met, but doing so will guarantee that the bus exception will occur in the current bus
cycle instead of the next bus cycle. Asynchronous Bus Retry may only be used when the SONIC-T is set to asynchronous mode.
Note 1: The deassertion edge of HOLD is dependent on the PH bit in the
DCR2 (see Section 6.4.7). Also, BGACK is driven high for about 0.5
bus clocks before going TRI-STATE.
Note 1: Although the SONIC-T responds as a 32-bit peripheral when it
drives DSACK0,1 low, it transfers data only on lines D k 15:0 l .
Note 2: If Latched Bus retry is set, BRT need only satisfy its setup time (the
hold time is not important). Otherwise, BRT must remain asserted
until after the Th state.
Note 2: For multiple register accesses, CS can be held low and SAS can be
used to delimit the slave cycle (this is the only case where CS may
be asserted before SAS). In this case, SMACK will be driven low
due to SAS going low since CS has already been asserted. Notice
that this means SMACK will not stay asserted low during the entire
time CS is low (as is the case for MREQ, Section 7.3.8).
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Note 3: If DSACK0,1, STERM or RDYi remain asserted after BRT, the next
memory cycle, may be adversely affected.
7.3.7 Slave Mode Bus Cycle
The SONIC-T’s internal registers can be accessed by one of
two methods (BMODE e 1 or BMODE e 0). In both methods, the SONIC-T is a slave on the bus. This section describes the SONIC-T’s slave mode bus operations.
Note 3: If memory request (MREQ) follows a chip select (CS), it must be
asserted at least 2 bus clocks after CS is deasserted. Both CS and
MREQ must not be asserted concurrently.
Note 4: When CS is deasserted, it must remain deasserted for at least one
bus clock.
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7.3.7.1 Slave Cycle for BMODE e 1
The system accesses the SONIC-T by driving SAS, CS,
SRW and RAk5:0l. These signals will be sampled each
bus cycle, but the SONIC-T will not actually start a slave
cycle until CS has also been asserted. CS should not be
asserted before SAS is driven low as this will cause improp-
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Note 5: The way in which SMACK is asserted due to CS is not the same as
the way in which SMACK is asserted due to MREQ. The assertion
of SMACK is dependent upon both CS and SAS being low, not just
CS. This is not the same as the case for MREQ (see Section 7.3.8).
The assertion of SMACK in these two cases should not be confused.
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FIGURE 7-18. Bus Exception (Bus Retry)
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7.0 Bus Interface (Continued)
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FIGURE 7-19. Register Read, BMODE e 1
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FIGURE 7-20. Register Write, BMODE e 1
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7.0 Bus Interface (Continued)
If the slave access is a read cycle (Figure 7-21) , then the
data will be driven off the same edge as SMACK. If it is a
write cycle (Figure 7-22) , then the data will be latched in
exactly 2 bus clocks after the assertion of SMACK. In either
case, RDYo is driven low 2.5 bus clocks after SMACK to
terminate the slave cycle. For a read cycle, the assertion of
RDYo indicates valid register data and for a write cycle, the
assertion indicates that the SONIC-T has latched the data.
The SONIC-T deasserts RDYi, SMACK and the data if the
cycle is a read cycle at the falling edge of SAS or the rising
edge of CS depending on which is first.
7.3.7.2 Slave Cycle for BMODE e 0
The system accesses the SONIC-T by driving SAS, CS,
SWR and RAk5:0l. These signals will be sampled each
bus cycle, but the SONIC-T will not actually start a slave
cycle until CS has been sampled low and SAS has been
sampled high. CS should not be asserted low before the
falling edge of SAS as this will cause improper slave operation. CS may be asserted low, however, before the rising
edge of SAS. In this case, it is suggested that SAS be driven
high within one bus clock after the falling edge of CS. Between one and two bus clocks after the assertion of CS,
once SAS has been driven high, SMACK will be driven low
to signify that the SONIC-T has started the slave cycle. Although CS is an asynchronous input, meeting its setup time
(as shown in Figures 7-21 and 7-22 ) will guarantee that
SMACK, which is asserted off a falling edge, will be asserted 1 bus clock after the falling edge that CS was clocked in
on. This is assuming that the SONIC-T is not a bus master
when CS is asserted. If the SONIC-T is a bus master, then,
when CS is asserted, the SONIC-T will complete its current
master bus cycle and get off the bus temporarily (see Section 7.3.8). In this case, SMACK will be asserted 5 bus
clocks after the falling edge that CS was clocked in on. This
is assuming that there were no wait states in the current
master mode access. Wait states will increase the time for
SMACK to go low by the number of wait states in the cycle.
Note 1: The SONIC-T transfers data only on lines D k 15:0 l during slave
mode accesses.
Note 2: For multiple register accesses, CS can be held low and SAS can be
used to delimit the slave cycle (this is the only case where CS may
be asserted before SAS). In this case, SMACK will be driven low
due to SAS going high since CS has already been asserted. Notice
that this means SMACK will not stay asserted low during the entire
time CS is low (as is the case for MREQ, Section 7.3.8).
Note 3: If memory request (MREQ) follows a chip select CS, it must be
asserted at least 2 bus clocks after CS is deasserted. Both CS and
MREQ must not be asserted concurrently.
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Note 4: When CS is deasserted, it must remain deasserted for at least one
bus clock.
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Note 5: The way in which SMACK is asserted due to CS is not the same as
the way in which SMACK is asserted due to MREQ. The assertion of
SMACK is dependent upon both CS and SAS being low, not just CS.
This is not the same as the case for MREQ (see Section 7.3.8). The
assertion of SMACK in these two cases should not be confused.
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FIGURE 7-21. Register Read, BMODE e 0
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7.0 Bus Interface (Continued)
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FIGURE 7-22. Register Write, BMODE e 0
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FIGURE 7-23. On-Chip Memory Arbiter
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7.0 Bus Interface (Continued)
After power-on, the SONIC-T must be hardware reset before it will become operational. This is done by asserting
RESET for a minimum of 10 transmit clocks (10 ethernet
transmit clock periods, TXC). If the bus clock (BSCK) period
is greater than the transmit clock period, RESET should be
asserted for 10 bus clocks instead of 10 transmit clocks. A
hardware reset places the SONIC-T in the following state.
(The registers affected are listed in parentheses. See Table
7-3 and Section 6.4 for more specific information about the
registers and how they are affected by a hardware reset.
Only those registers listed below and in Table 7-3 are affected by a hardware reset.)
1. Receiver and Transmitter are disabled (CR).
2. The General Purpose timer is halted (CR).
3. All interrupts are masked out (IMR).
4. The NCRS and PTX status bits in the Transmit Control
Register (TCR) are set.
5. The End Of Byte Count (EOBC) register is set to 02F8h
(760 words).
6. Packet and buffer sequence number counters are set to
zero.
7. All CAM entries are disabled. The broadcast address is
also disabled (CAM Enable Register and the RCR).
8. Loopback operation is disabled (RCR).
9. The latched bus retry is set to the unlatched mode
(DCR).
10. All interrupt status bits are reset (ISR).
11. The Extended Bus Mode is disabled (DCR).
12. HOLD will be asserted/deasserted from the falling clock
edge (DCR2).
13. PCOMP will not be asserted (DCR2).
14. Packets will be accepted (not rejected) on CAM match
(DCR2).
7.3.8 On-Chip Memory Arbiter
For applications which share the buffer memory area with
the host system (shared-memory applications), the
SONIC-T provides a fast on-chip memory arbiter for efficiently resolving accesses between the SONIC-T and the
host system (Figure 7-23) . The host system indicates its
intentions to use the shared-memory by asserting Memory
Request (MREQ). The SONIC-T will allow the host system
to use the shared memory by acknowledging the host system’s request with Slave and Memory Acknowledge
SMACK. Once SMACK is asserted, the host system may
use the shared memory freely. The host system gives up the
shared memory by deasserting MREQ.
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MREQ is clocked in on the falling edge of bus clock and is
double synchronized internally to the rising edge. SMACK is
asserted on the falling edge of a Ts bus cycle. If the
SONIC-T is not currently accessing the memory, SMACK is
asserted immediately after MREQ was clocked in. If, however, the SONIC-T is accessing the shared memory, it finishes
its current memory transfer and then issues SMACK.
SMACK will be asserted 1 or 5 bus clocks, respectively,
after MREQ is clocked in. Since MREQ is double synchronized, it is not necessary to meet its setup time. Meeting the
setup time for MREQ will, however, guarantee that SMACK
is asserted in the next or fifth bus clock after the current bus
clock. SMACK will deassert within one bus clock after
MREQ is deasserted. The SONIC-T will then finish its master operation if it was using the bus previously.
If the host system needs to access the SONIC-T’s registers
instead of shared memory, CS would be asserted instead of
MREQ. Accessing the SONIC-T’s registers works almost
exactly the same as accessing the shared memory except
that the SONIC-T goes into a slave cycle instead of going
idle. See Section 7.3.7 for more information about how register accesses work.
Note 1: The successive assertion of CS and MREQ must be separated by
at least two bus clocks. Both CS and MREQ must not be asserted
concurrently.
TABLE 7-3. Internal Register Content after Reset
Contents after Reset
bs
Note 2: The number of bus clocks between MREQ being asserted and the
assertion of SMACK when the SONIC-T is in Master Mode is 5 bus
clocks assuming there were no wait states in the Master Mode
access. Wait states will increase the time for SMACK to go low by
the number of wait states in the cycle (the time will be 5 a the
number of wait states).
Register
O
Note 3: The way in which SMACK is asserted to due to CS is not the same
as the way in which SMACK is asserted due to MREQ. SMACK
goes low as a direct result of the assertion of MREQ, whereas, for
CS, SAS must also be driven low (BMODE e 1) or high (BMODE e
0) before SMACK will be asserted. This means that when SMACK
is asserted due to MREQ, SMACK will remain asserted until MREQ
is deasserted. Multiple memory accesses can be made to the
shared memory without SMACK ever going high. When SMACK is
asserted due to CS, however, SMACK will only remain low as long
as SAS is also low (BMODE e 1) or high (BMODE e 0). SMACK
will not remain low throughout multiple register accesses to the
SONIC-T because SAS must toggle for each register access. This
is an important difference to consider when designing shared memory designs.
7.3.9 Chip Reset
The SONIC-T has two reset modes; a hardware reset and a
software reset. The SONIC-T can be hardware reset by asserting the RESET pin or software reset by setting the RST
bit in the Command Register (Section 6.4.1). The two reset
modes are not interchangeable since each mode performs
a different function.
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Hardware
Reset
Software
Reset
Command
0094h
0094h/00A4h
Data Configuration
(DCR and DCR2)
*
unchanged
Interrupt Mask
0000h
unchanged
Interrupt Status
0000h
unchanged
Transmit Control
0101h
unchanged
Receive Control
**
unchanged
End Of Buffer Count
02F8h
unchanged
Sequence Counters
0000h
unchanged
CAM Enable
0000h
unchanged
*Bits 15 and 13 of the DCR and bits 4 through 0 of the DCR2 are reset to a 0
during a hardware reset. Bits 15–12 of the DCR2 are unknown until written
to. All other bits in these two registers are unchanged.
**Bits LB1, LB0 and BRD are reset to a 0 during hardware reset. All other
bits are unchanged.
72
7.0 Bus Interface (Continued)
allows the internal ENDEC to be disabled and the
MAC/ENDEC signals to be supplied to the user for connection to an external ENDEC. If the EXT pin is tied to ground
(EXT e 0) the internal ENDEC is selected and if EXT is tied
to VCC (EXT e 1) the external ENDEC option is selected.
Internal ENDEC: When the internal ENDEC is used
(EXT e 0) the interface signals between the ENDEC and
MAC unit are internally connected. While these signals are
used internally by the SONIC-T they are also provided as an
output to the user (Figure 8-1).
The internal ENDEC allows for a 2-chip solution for the
complete Ethernet interface. Figure 8-2 shows a typical diagram of the Thin Ethernet and AUI network interface.
A software reset immediately terminates DMA operations
and future interrupts. The chip is put into an idle state where
registers can be accessed, but the SONIC-T will not be active in any other way. The registers are affected by a software reset as shown in Table 7-3 (only the Command Register is changed).
8.0 Network Interfacing
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The SONIC-T contains an on-chip ENDEC that performs the
network interfacing between the AUI (Attachment Unit Interface) and the SONIC-T’s MAC unit. A pin selectable option
TL/F/12597 – 51
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FIGURE 8-1. MAC and Internal ENDEC Interface Signals
73
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FIGURE 8-2. Network Interface Example (EXT e 0)
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TL/F/12597 – 52
8.0 Network Interfacing (Continued)
8.0 Network Interfacing (Continued)
External ENDEC: When EXT e 1 the internal ENDEC is bypassed and the signals are provided directly to the user.
Since SONIC-T’s on-chip ENDEC is the same as National’s
DP83910 Serial Network Interface (SNI) the interface considerations discussed in this section would also apply to
using this device in the external ENDEC mode.
detects these inputs active, its Collision translator converts
the 10 MHz signal to an active collision signal to the MAC
section. This signal causes SONIC-T to abort its current
transmission and reschedule another transmission attempt.
The collision differential inputs are terminated the same way
as the differential receive inputs and a pulse transformer is
required between the collision input pair and the AUI interface. The squelch circuitry is also similar, rejecting pulses
with magnitudes less than b175 mV.
8.1 MANCHESTER ENCODER AND
DIFFERENTIAL DRIVER
The ENDEC unit’s encoder begins operation when the MAC
section begins sending the serial data stream. It converts
NRZ data from the MAC section to Manchester data for the
differential drivers (TX g ). In Manchester encoding, the first
half of the bit cell contains the complementary data and the
second half contains the true data (Figure 8-3) . A transition
always occurs at the middle of the bit cell. As long as the
MAC continues sending data, the ENDEC section remains
in operation. At the end of transmission, the last transition is
always positive, occurring at the center of the bit cell if the
last bit is a one, or at the end of the bit cell if the last bit is a
zero.
The differential transmit pair drives up to 50 meters of twisted pair AUI cable. These outputs are source followers which
require two 270X pull-down resistors to ground. In addition,
a pulse transformer is required between the transmit pair
output and the AUI interface.
The driver provides full-step mode for compatibility with
Ethernet and IEEE 802.3, so that TX a and TXb are equal
in the idle state.
8.1.3 Oscillator Inputs
The oscillator inputs to the SONIC-T (OSCIN and OSCOUT)
can be driven with a parallel resonant crystal or an external
clock. In either case the oscillator inputs must be driven with
a 20 MHz signal. The signal is divided by 2 to generate the
10 MHz transmit clock (TXC) for the MAC unit. The oscillator also provides internal clock signals for the encoding and
decoding circuits.
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8.1.3.1 External Crystal
According to the IEEE 802.3 standard, the transmit clock
(TXC) must be accurate to 0.01%. This means that the oscillator circuit, which includes the crystal and other parts
involved must be accurate to 0.01% after the clock has
been divided in half. Hence, when using a crystal, it is necessary to consider all aspects of the crystal circuit. An example of a recommended crystal circuit is shown in Figure
8-4 and suggested oscillator specifications are shown in Table 8-1. The load capacitors in Figure 8-4 , C1 and C2,
should be no greater than 36 pF each, including all stray
capacitance (see note 2). The resistor, R1, may be required
in order to minimize frequency drift due to changes in VCC. If
R1 is required, its value must be carefully selected since R1
decreases the loop gain. If R1 is made too large, the loop
gain will be greatly reduced and the crystal will not oscillate.
If R1 is made too small, normal variations in VCC may cause
the oscillation frequency to drift out of specification. As a
first rule of thumb, the value of R1 should be made equal to
five times the motional resistance of the crystal. The motional resistance of 20 MHz crystals is usually in the range
of 10X to 30X. This implies that reasonable values for R1
should be in the range of 50X to 150X. The decision of
whether or not to include R1 should be based upon measured variations of crystal frequency as each of the circuit
parameters are varied.
TL/F/12597 – 53
FIGURE 8.3. Manchester Encoded Data Stream
O
8.1.1 Manchester Decoder
The decoder consists of a differential receiver and a phase
lock loop (PLL) to separate the Manchester encoded data
stream into clock signals and NRZ data. The differential input must be externally terminated with two 39X resistors
connected in series. In addition, a pulse transformer is required between the receive input pair and the AUI interface.
To prevent noise from falsely triggering the decoder, a
squelch circuit at the input rejects signals with a magnitude
less than b175 mV. Signals more negative than b300 mV
are decoded.
Once the input exceeds the squelch requirements, the decoder begins operation. The decoder may tolerate bit jitter
up to 18 ns in the received data. The decoder detects the
end of a frame within one and a half bit times after the last
bit of data.
TL/F/12597 – 54
FIGURE 8-4. Crystal Connection to the SONIC-T
(see text)
Note 1: The OSCOUT pin is not guaranteed to provide a TTL compatible
logic output, and should not be used to drive any external logic. If
additional logic needs to be driven, then an external oscillator
should be used as described in the following section.
8.1.2 Collision Translator
When the Ethernet transceiver (DP8392 CTI) detects a collision, it generates a 10 MHz signal to the differential collision
inputs (CD a and CDb) of the SONIC-T. When SONIC-T
Note 2: The frequency marked on the crystal is usually measured with a
fixed load capacitance specified in the crystal’s data sheet. The
actual load capacitance used should be the specified value minus
the stray capacitance.
75
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8.0 Network Interfacing (Continued)
should use short traces that avoid excess capacitance and
inductance. A solid ground should be used to connect the
ground legs of the two capacitors.
TABLE 8-1. Crystal Specifications
Resonant frequency
20 MHz
g 0.01% at 25§ C
Tolerance (see text)
g 0.005% (50 ppm) at 0 to 70§ C
Accuracy
s 25X
Fundamental Mode Series Resistance
s 18 pF
Specified Load Capacitance
Type
AT cut
Circuit
Parallel Resonance
When connecting an external oscillator, the only considerations are to keep the oscillator module as close to the
SONIC-T as possible to reduce stray capacitance and inductance and to give the module a clean VCC and a solid
ground.
8.1.3.2 Clock Oscillator Module
The SONIC-T also allows an external clock oscillator to be
used. The connection configuration is shown in Figure 8-5 .
This connection requires an oscillator with the following
specifications:
1. TTL or CMOS output with a 0.01% frequency tolerance
2. 40% – 60% duty cycle
3. One CMOS load output drive
These specifications assume that no other circuitry is driven. In this configuration the OSCOUT pin must be left open.
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8.1.4 Power Supply Considerations
In general, power supply routing and design for the
SONIC-T need only follow standard practices. In some situations, however, additional care may be necessary in the
layout of the analog supply. Specifically special care may be
needed for the TXVCC, RXVCC, PLLVCC, OSCVCC, RXTVCC
and TPVCC power supplies and the TXGND, RXGND,
PLLGND, OSCGND, TPGND and ANGND. In most cases
the analog and digital power supplies can be interconnected. However, to ensure optimum performance of the
SONIC-T’s analog functions, power supply noise should be
minimized. To reduce analog supply noise, any of several
techniques can be used.
1. Route analog supplies as a separate set of traces or
planes from the digital supplies with their own decoupling
capacitors.
2. Provide noise filtering on the analog supply pins by inserting a low pass filter. Alternatively, a ferrite bead could be
used to reduce high frequency power supply noise.
3. Utilize a separate regulator to generate the analog supply.
TL/F/12597–55
8.2 TWISTED PAIR INTERFACE MODULE
Transmitter Considerations: The transmitter consists of
four signals, the true and complement Manchester encoded
data (TXO g ) and these signals delayed by 50 ns (TXOd g ).
These four signals are resistively combined (Figure 8-6) ,
TXO a with TXOdb and TXOb with TXOd a , in a configuration referred to as pre-emphasis. This digital pre-emphasis
is required to compensate for the low-pass filter effects of
the twisted pair cable, which cause greater attenuation to
the 10 MHz (50 ns) pulses of the Manchester encoded
waveform than the 5 MHz (100 ns) pulses.
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FIGURE 8-5. Oscillator Module Connection
to the SONIC-T
O
bs
8.1.3.3 PCB Layout Considerations
Care should be taken when connecting a crystal. Stray capacitance (e.g., from PC board traces and plated throughholes around the OSCIN and OSCOUT pins) can shift the
crystal’s frequency out of range, causing the transmitted frequency to exceed the 0.01% tolerance specified by IEEE.
The layout considerations for using an external crystal are
rather straightforward. The oscillator layout should locate all
components close to the OSCIN and OSCOUT pins and
TL/F/12597 – 56
FIGURE 8-6. External Circuitry to Connect the SONIC-T to Twisted Pair Cable
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76
9.0 AC and DC Specifications
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b 0.5V to 7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Storage Temperature Range (TSTG)
b 65§ C to 150§ C
Power Dissipation (PD)
Lead Temp. (TL) (Soldering, 10 sec.)
500 mW
260§ C
ESD Rating
(RZAP e 1.5k, CZAP e 120 pF)
b 0.5V to VCC a 0.5V
b 0.5V to VCC a 0.5V
1.5 kV
DC Specifications TA e 0§ C to 70§ C, VCC e 5V g 5% unless otherwise specified
Symbol
Parameter
Conditions
VOH
Minimum High Level Output Voltage
IOH e b8 mA
VOL
Maximum Low Level Output Voltage
IOL e 8 mA
VIH
Minimum High Level Input Voltage
VIL
Maximum Low Level Input Voltage
IIN
Input Current
VIN e VCC or GND
IOZ
TRI-STATE Output
Leakage Current
VOUT e VCC or GND
ICC
Average Operating Supply Current
Diff. Output Voltage (TX g )
VOB
Diff. Output Voltage Imbalance (TX g )
(Guaranteed by Design. Not Tested.)
VU
Undershoot Voltage (TX g )
(Guaranteed by Design. Not Tested.)
VDS
Diff. Squelch Threshold
(RX g and CD g )
TPI INTERFACE PINS
b 10
b 10
IOUT e 0 mA, Freq e fmax
78X Termination, and 270X
from Each to GND
g 550
V
V
0.8
V
10
mA
10
mA
140
mA
g 1200
mV
78X Termination, and 270X
from Each to GND
Typical: 40 mV
78X Termination, and 270X
from Each to GND
Typical: 80 mV
b 175
Units
V
0.5
2.0
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VOD
Max
3.0
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AUI INTERFACE PINS (TX g , RX g , and CD g )
Min
b 300
mV
TXOd g , TXO g Low Level Output
Resistance
IOL e 25 mA
15
X
RTOH
TXOd g , TXO g High Level Output
Resistance
IOL e b25 mA
15
X
VSRON1
Receive Threshold Turn-On Voltage
10BASE-T Mode
LOWSQL e 0
g 300
g 585
mV
VSRON2
Receive Threshold Turn-On Voltage
Reduce Threshold
LOWSQL e 1
g 175
g 300
mV
Differential Mode Input Voltage Range
VCC e 5.0V
(Guaranteed by Design, Not Tested)
b 3.1
a 3.1
V
2.0
O
bs
RTOL
VDIFF
OSCILLATOR PINS (OSCOUT and OSCIN)
VIH
OSCIN Input High Voltage
OSCIN is Connected to an Oscillator
and OSCOUT is Open
VIL
OSCIN Input Low Voltage
OSCIN is Connected to an Oscillator
and OSCOUT is Open
IOSC2
OSCIN Input Leakage Current
OSCIN is Connected to an Oscillator
and OSCOUT is Open
VIN e VCC or GND
77
b 100
V
0.8
V
100
mA
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9.0 AC and DC Specifications (Continued)
AC Characteristics
BUS CLOCK TIMING
TL/F/12597 – 57
Number
20 MHz
Parameter
Min
25 MHz
Max
Min
33 MHz
Max
Min
Units
Max
T1
Bus Clock Low Time
22
18
13.5
T2
Bus Clock High Time
22
18
13.5
ns
T3
Bus Clock Cycle Time
50
40
30
ns
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POWER-ON RESET
ns
T5
O
bs
NON POWER-ON RESET
TL/F/12597 – 58
Number
T4
TL/F/12597 – 59
20 MHz
Parameter
Min
Max
25 MHz
Min
Max
33 MHz
Min
Units
Max
USRk1:0l Setup to RST
7
6
5
USRk1:0l Hold from RST
9
8
7
ns
ns
T6
Power-On Reset Low (Notes 1, 2)
10
10
10
TXC
T8
Reset Pulse Width (Notes 1, 2)
10
10
10
TXC
Note 1: The reset time is determined by the slower of BSCK or TXC. If BSCK l TXC, T6 and T8 equal 10 TXCs. If BSCK k TXC, T6 and T8 equal 10 BSCKs (T3).
Note 2: These specifications are not tested.
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9.0 AC and DC Specifications (Continued)
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MEMORY WRITE, BMODE e 0, SYNCHRONOUS MODE (one wait-state shown)
TL/F/12597 – 60
Number
Parameter
20 MHz
25 MHz
Max
Min
26
3
Min
24
3
Units
Max
T9
BSCK to Address Valid/Hold Time
T11
BSCK to ADS Low
T11b
BSCK to ECS Low
T12
BSCK to ADS High
T12b
BSCK to ECS High
T15
ADS High Width
45
35
25
ns
T32
RDYi Setup to BSCK
19
17
15
ns
T33
RDYi Hold from BSCK
5
3
3
ns
T36
BSCK to Memory Write Data Valid/Hold Time
(Note 2)
3
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bs
3
33 MHz
Max
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Min
T37
BSCK to MWR (Write) Valid (Note 1)
22
ns
26
24
22
ns
19
17
15
ns
24
22
20
ns
29
27
25
50
24
3
48
22
3
ns
46
ns
20
ns
Note 1: For successive read operations, MWR remains high.
Note 2: One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation. Note that the data bus will
become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing).
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9.0 AC and DC Specifications (Continued)
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MEMORY READ, BMODE e 0, SYNCHRONOUS MODE (one wait-state shown)
TL/F/12597 – 61
Number
20 MHz
Parameter
Min
Max
Min
26
3
33 MHz
Max
Min
Max
24
3
22
Units
T9
BSCK to Address Valid/Hold Time
T11
BSCK to ADS Low
T11b
BSCK to ECS Low
T12
BSCK to ADS High
T12b
BSCK to ECS High
T15
ADS High Width
45
35
25
ns
T23
Read Data Setup Time to BSCK
6
5
4
ns
T24
Read Data Hold Time from BSCK
5
5
5
ns
T28
BSCK to MWR (Ready) Valid (Note 1)
T32
RDYi Setup Time to BSCK
19
17
15
ns
T33
RDYi Hold Time to BSCK
5
3
3
ns
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3
25 MHz
24
22
ns
19
17
15
ns
24
22
20
ns
25
ns
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29
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27
26
Note 1: For successive read operations, MWR remains low.
80
ns
26
24
22
ns
9.0 AC and DC Specifications (Continued)
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MEMORY WRITE, BMODE e 0, ASYNCHRONOUS MODE
TL/F/12597 – 62
Number
Parameter
20 MHz
Min
3
25 MHz
Max
Min
26
3
33 MHz
Max
Min
24
3
Units
Max
T9
BSCK to Address Valid/Hold Time
T11
BSCK to ADS Low
T11b
BSCK to ECS Low
T11d
BSCK to DS Low
T12
BSCK to ADS High
T12b
BSCK to ECS High
T12d
BSCK to DS High
T15
ADS High Width
45
35
25
T18
Write Data Strobe Low Width (Note 2)
40
30
20
ns
T32a
RDYi Asynchronous Setup to BSCK (Note 3)
5
4
3
ns
T33a
RDYi Asynchronous Hold from BSCK
5
5
5
ns
T36
BSCK to Memory Write Data Valid/Hold Time
(Note 4)
3
T37
BSCK to MWR (Write) Valid (Note 1)
T39
Write Data Valid to DS Low
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26
22
ns
22
ns
19
17
15
ns
17
15
13
ns
24
22
20
ns
29
27
25
ns
17
15
13
ns
50
3
24
34
24
48
3
22
21
ns
46
20
7
ns
ns
ns
Note 1: For successive read operations, MWR remains high.
Note 2: DS will only be asserted if the bus cycle has at least one wait state inserted.
Note 3: This setup time assures that the SONIC-T terminates the memory cycle on the next bus clock (BSCK). RDYi does not need to be synchronized to the bus
clock, though, since it is an asynchronous input in this case. RDYi is sampled during the falling edge of BSCK. If the SONIC-T samples RDYi low during the T1
cycle, the SONIC-T will finish the current access in a total of two bus clocks instead of three, which would be the case if RDYi had been sampled low during
T2 (wait). (This is assuming that programmable wait states are set to 0.)
Note 4: One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation. Note that the data bus will
become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing).
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9.0 AC and DC Specifications (Continued)
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MEMORY READ, BMODE e 0, ASYNCHRONOUS MODE
Number
Parameter
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TL/F/12597 – 63
20 MHz
Min
3
25 MHz
Max
Min
26
3
33 MHz
Max
Min
24
3
Units
Max
T9
BSCK to Address Valid/Hold Time
T11
BSCK to ADS Low
T11b
BSCK to ECS Low
19
17
15
ns
T11d
BSCK to DS Low
17
15
13
ns
T12
BSCK to ADS High
24
22
20
ns
T12b
BSCK to ECS High
29
27
25
ns
T12d
BSCK to DS High
13
ns
T15
ADS High Width
45
35
25
ns
Read Data Strobe High Width
45
35
25
ns
Read Data Strobe Low Width
40
30
20
ns
Read Data Setup Time to BSCK
6
5
4
ns
Read Data Hold Time from BSCK
5
5
5
bs
26
24
15
ns
ns
T24
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17
22
22
T28
BSCK to MWR (Read) Valid (Note 1)
T32a
RDYi Asynchronous Setup Time to BSCK (Note 2)
5
4
3
ns
T33a
RDYi Asynchronous Hold Time to BSCK
5
5
5
ns
T16
T17
T23
26
24
ns
22
ns
Note 1: For successive read operations, MWR remains low.
Note 2: This setup time assures that the SONIC-T terminates the memory cycle on the next bus clock (BSCK). RDYi does not need to be synchronized to the bus
clock, though, since it is an asynchronous input in this case. RDYi is sampled during the falling edge of BSCK. If the SONIC-T samples RDYi low during the T1
cycle, the SONIC-T will finish the current access in a total of two bus clocks instead of three, which would be the case if RDYi had been sampled low during
T2 (wait). (This is assuming that programmable wait states are set to 0.)
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9.0 AC and DC Specifications (Continued)
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MEMORY WRITE, BMODE e 1, SYNCHRONOUS MODE (one wait-state shown)
TL/F/12597 – 64
Number
Parameter
20 MHz
Min
Min
26
3
33 MHz
Max
Min
24
3
Units
Max
T9
BSCK to Address Valid/Hold Time
T11a
BSCK to AS Low
T11c
BSCK to ECS Low
T12a
BSCK to AS High
T12c
BSCK to ECS High
T13a
BSCK to DS High (Note 1)
T13b
BSCK to DS High (Note 1)
T14
AS Low Width
44
34
24
ns
T15a
AS High Width
45
35
25
ns
T18
Write Data Strobe Width (Note 1)
40
30
20
ns
T19
Address Hold Time from AS
18
14
10
ns
ol
3
25 MHz
Max
O
bs
17
15
22
ns
13
ns
19
17
15
ns
17
15
13
ns
19
17
15
ns
16
14
12
ns
16
14
12
ns
T20
Data Hold Time from AS
20
16
12
ns
T22
Address Valid to AS (Note 3)
9
6
2
ns
T30
DSACK0,1 Setup to BSCK (Note 3)
5
4
3
ns
T31
DSACK0,1 Hold from BSCK
9
8
7
ns
T36
BSCK to Memory Write Data Valid/Hold
Time (Note 4)
3
T37a
BSCK to MRW (Write) Valid (Note 2)
T39
Write Data Valid to Data Strobe Low
50
3
26
34
48
3
24
21
7
46
ns
22
ns
ns
Note 1: DS will only be asserted if the bus cycle has at least one wait state inserted.
Note 2: For successive write operations, MRW remains low.
Note 3: DSACK0,1 must be synchronized to the bus clock (BSCK) during synchronous mode.
Note 4: One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation. Note that the data bus will
become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing).
83
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9.0 AC and DC Specifications (Continued)
et
e
MEMORY READ, BMODE e 1, SYNCHRONOUS MODE (one wait-state shown)
TL/F/12597 – 65
Parameter
20 MHz
Min
T9
BSCK to Address Valid
T11a
BSCK to AS Low
T11c
BSCK to ECS Low
T12a
BSCK to AS High
T12c
T13a
25 MHz
33 MHz
ol
Number
3
Max
Min
26
3
17
Max
Min
24
3
15
Units
Max
22
ns
13
ns
17
15
ns
15
13
ns
BSCK to ECS High
19
17
15
ns
BSCK to DS Low (Note 3)
16
14
12
ns
T13b
BSCK to DS High (Note 3)
16
14
12
T14
AS Low Width
44
34
24
ns
T15a
AS High Width
bs
19
17
ns
35
25
ns
45
35
25
ns
Read Data Strobe Low Width
40
30
20
ns
Address Hold Time from AS
14
10
ns
Address Valid to AS
9
6
2
ns
ns
T23a
O
45
Read Data Strobe High Width
18
Read Data Setup Time to BSCK
5
4
3
T24a
Read Data Hold Time from BSCK
5
5
5
T28
BSCK to MRW (Read) Valid (Note 1)
T30
DSACK0,1 Setup to BSCK (Note 2)
5
4
3
ns
T31
DSACK0,1 Hold from BSCK
9
8
7
ns
T16
T17
T19
T22
26
Note 1: For successive read operations, MRW remains high.
Note 2: DSACK0,1 must be synchronized to the bus clock (BSCK) during synchronous mode.
Note 3: DS will only be asserted if the bus cycle has at least one wait state inserted.
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84
24
ns
22
ns
9.0 AC and DC Specifications (Continued)
TL/F/12597 – 66
O
bs
ol
et
e
MEMORY WRITE, BMODE e 1, ASYNCHRONOUS MODE
85
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9.0 AC and DC Specifications (Continued)
Number
20 MHz
Parameter
Min
3
25 MHz
Max
Min
26
3
33 MHz
Max
Min
24
2
Units
Max
T9
BSCK to Address Valid
T11a
BSCK to AS Low
T11c
BSCK to ECS Low
19
17
15
ns
T12a
BSCK to AS High
17
15
13
ns
T12c
BSCK to ECS High
19
17
15
ns
T13a
BSCK to DS Low
16
14
12
ns
T13b
BSCK to DS High
12
ns
T14
AS Low Width
44
34
24
ns
T15a
AS High Width
45
35
25
ns
T18
Write Data Strobe Low Width (Note 3)
40
30
20
ns
T19
Address Hold Time from AS
18
14
10
ns
T20
Data Hold Time from AS
20
16
12
ns
T22
Address Valid to AS
9
6
2
ns
T30
DSACK0,1 Setup to BSCK (Note 2)
5
4
3
ns
T30a
STERM Setup to BSCK (Note 2)
5
T31
DSACK0,1 Hold from BSCK
9
T31a
STERM Hold from BSCK
8
T36
BSCK to Memory Write Data Valid (Note 4)
3
T37a
BSCK to MRW (Write) Valid (Note 1)
T39
Write Data Valid to Data Strobe Low
17
15
14
4
3
ns
8
7
ns
7
50
3
26
34
Note 1: For successive write operations, MRW remains low.
ns
ns
et
e
16
22
13
6
48
3
24
21
7
ns
46
ns
22
ns
ns
ol
Note 2: Meeting the setup time for DSACK0,1 or STERM guarantees that the SONIC-T will terminate the memory cycle 11/2 bus clocks after DSACK0,1 were
sampled, or 1 cycle after STERM was sampled. T2 states will be repeated until DSACK0,1 or STERM are sampled properly in a low state. If the SONIC-T samples
DSACK0,1 or STERM low during the T1 or first T2 state respectively, the SONIC-T will finish the current access in a total of two bus clocks instead of three
(assuming that programmable wait states are set to 0). DSACK0,1 are asynchronously sampled and STERM is synchronously sampled.
Note 3: DS will only be asserted if the bus cycle has at least one wait state inserted.
O
bs
Note 4: One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation. Note that the data bus will
become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing).
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86
9.0 AC and DC Specifications (Continued)
et
e
MEMORY READ, BMODE e 1, ASYNCHRONOUS MODE
TL/F/12597 – 67
Number
Parameter
20 MHz
BSCK to Address Valid
T11a
BSCK to AS Low
T11c
BSCK to ECS Low
T12a
BSCK to AS High
T12c
BSCK to ECS High
Min
26
3
33 MHz
Max
Min
3
24
2
Units
Max
22
ns
17
15
13
ns
19
17
15
ns
17
15
13
ns
19
17
15
ns
BSCK to DS Low
16
14
12
ns
BSCK to DS High
16
14
12
bs
T9
25 MHz
Max
ol
Min
34
T19
Address Hold Time from AS
18
14
10
ns
T22
Address Valid to AS
9
6
2
ns
T23a
Read Data Setup Time to BSCK
6
5
3
ns
T24a
Read Data Hold Time from BSCK
5
5
5
T28
BSCK to MRW (Read) Valid (Note 1)
T30
DSACK0,1 Setup to BSCK (Note 2)
5
4
3
T30a
STERM Setup to BSCK (Note 2)
5
4
3
ns
T31
DSACK0,1 Hold from BSCK
9
8
7
ns
T31a
STERM Hold from BSCK
8
7
6
ns
T13a
T13b
T14
T15a
T16
44
24
ns
AS High Width
45
35
25
ns
Read Data Strobe High Width
45
35
25
ns
Read Data Strobe Low Width
40
30
20
ns
O
T17
ns
AS Low Width
26
24
ns
22
ns
ns
Note 1: For successive read operations, MRW remains high.
Note 2: Meeting the setup time for DSACK0,1 or STERM guarantees that the SONIC-T will terminate the memory cycle 1.5 bus clocks after DSACK0,1 were
sampled, or 1 cycle after STERM was sampled. T2 states will be repeated until DSACK0,1 or STERM are sampled properly in a low state. If the SONIC-T samples
DSACK0,1 or STERM low during the T1 or first T2 state respectively, the SONIC-T will finish the current access in a total of two bus clocks instead of three
(assuming that programmable wait states are set to 0). DSACK0,1 are asynchronously sampled and STERM is synchronously sampled.
87
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9.0 AC and DC Specifications (Continued)
et
e
BUS REQUEST TIMING, BMODE e 0
TL/F/12597 – 68
Number
20 MHz
Parameter
Min
T43
BSCK to HOLD High (Note 2)
T44
BSCK to HOLD Low (Note 2)
T45
HLDA Asynchronous Setup Time to BSCK (Note 5)
T46
HLDA Synchronous Deassert Setup Time
(Note 1)
T51
BSCK to Address, ADS, MWR, DS, ECS,
USRk1:0l and EXUSRk3:0lTRI-STATE (Note 4)
T52
BSCK to Data TRI-STATE
T53
BSCK to USRk1:0l or EXUSRk3:0l Valid
T55
BSCK to Bus Status Valid
T55b
Sk2:0l Hold from BSCK
Max
25 MHz
Min
18
17
ol
6
7
6
37
bs
39
29
14
ns
15
ns
ns
5
ns
33
ns
37
30
ns
32
30
ns
27
3
Units
Max
5
35
34
3
33 MHz
Min
16
19
7
Max
25
3
ns
ns
Note 1: A block transfer by the SONIC-T can be pre-empted from the bus by deasserting HLDA provided HLDA is asserted T46 before the rising edge of the last T2
in the current access.
O
Note 2: The assertion edge for HOLD is dependent upon the PH bit in the DCR2. The default situation is shown wih a solid line in the timing diagram. T43 and T44
apply for both modes. Also, if HLDA is asserted when the SONIC-T wants to acquire the bus, HOLD will not be asserted until HLDA has been deasserted first.
Note 3: S k 2:0 l will indicate IDLE at the end of T2 if the last operation is a read operation, or at the end of Th if the last operation is a write operation.
Note 4: This timing value includes an RC delay inherent in the test measurement. These signals typically TRI-STATE 7 ns earlier, enabling other devices to drive
these lines without contention.
Note 5: The HLDA signal is sampled by the SONIC-T on each rising edge of BSCK. The maximum set-up time is ((BSCKÐperiod b T45ÐminÐspec) b 5 ns). HDLA
max set-up time is for information only, and is not tested.
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88
9.0 AC and DC Specifications (Continued)
et
e
BUS REQUEST TIMING, BMODE e 1
TL/F/12597 – 69
Number
Parameter
20 MHz
Max
Min
ol
Min
25 MHz
Max
33 MHz
Min
Units
Max
T45a
BG AS, BGACK, DSACK0,1, and STERM Asynchronous
Setup Time to BSCK (Note 1)
T51a
BSCK to Address, AS, MRW, DS, ECS,
USRk1:0l and EXUSRk3:0l TRI-STATE
37
35
33
ns
T52
BSCK to Data TRI-STATE
34
32
30
ns
T53
BSCK to Address, AS, MRW, DS, ECS,
USRk1:0l and EXUSRk3:0l Active (Note 1)
34
32
30
ns
T54
BSCK Low to BR Low/TRI-STATE
26
24
22
ns
T54a
BSCK High to BGACK Low/High
24
22
20
ns
T54b
High to BGACK TRI-STATE
19
17
15
ns
T55
BSCK to Bus Status Valid
T55b
Sk2:0l Hold from BSCK
O
bs
7
6
29
3
5
27
3
ns
25
3
ns
ns
Note 1: BGACK is asserted one bus clock after all the signals (AS, DSACK0,1, BGACK, STERM (Extended bus mode), and BG) meet the T45a setup time (see
Section 5.4.1 for more information). The address bus, AS, DS, ECS, MRW, USR k 1:0 l , and EXUSR k 3:0 l will also be driven active on the same clock.
Note 2: S k 2:0 l will indicate IDLE at the end of T2 if the last operation is a read operation, or at the end of Th if the last operation is a write operation.
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9.0 AC and DC Specifications (Continued)
et
e
BUS RETRY
TL/F/12597 – 70
Number
20 MHz
Parameter
Min
T41
Bus Retry Synchronous Setup Time to BSCK
(Note 3)
T41a
Bus Retry Asynchronous Setup Time
to BSCK (Note 3)
6
T42
Bus Retry Hold Time from BSCK (Note 2)
7
Max
Max
4
33 MHz
Min
Units
Max
3
ns
5
4
ns
6
5
ns
ol
5
25 MHz
Min
Note 1: Depending upon the mode, the SONIC-T will assert and deassert HOLD from the rising or falling edge of BSCK.
bs
Note 2: Unless Latched Bus Retry mode is set (LBR in the Data Configuration Register, Section 4.3.2), BRT must remain asserted until after the Th state. If
Latched Bus Retry mode is used, BRT does not need to satisfy T42.
O
Note 3: T41 is for synchronous bus retry and T41a is for asynchronous bus retry (see Section 4.3.2, bit 15, Extended Bus Mode). Since T41a is an asynchronous
setup time, it is not necessary to meet it, but doing so will guarantee that the bus exception occurs in the current memory transfer, not the next.
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90
9.0 AC and DC Specifications (Continued)
et
e
MEMORY ARBITRATION/SLAVE ACCESS
TL/F/12597 – 71
Parameter
20 MHz
25 MHz
33 MHz
ol
Number
Min
Max
Min
Max
Min
Units
Max
CS Low Asynchronous Setup to BSCK
(Note 2)
8
7
6
ns
T58
MREQ Low Asynchronous Setup to BSCK
(Note 2)
8
7
6
ns
T60
MREQ or CS Valid to SMACK Low
(Notes 3, 4)
1
T80
MREQ to SMACK High
18
T81
BSCK to SMACK Low
22
bs
T56
5
1
5
1
5
bcyc
16
14
ns
20
18
ns
O
Note 1: Both CS and MREQ must not be asserted concurrently. If these signals are successively asserted, there must be at least two bus clocks between the
deasserting and asserting edges of these signals.
Note 2: It is not necessary to meet the setup times for MREQ or CS since these signals are asynchronously sampled. Meeting the setup time for these signals,
however, makes it possible to use T60 to determine exactly when SMACK will be asserted.
Note 3: T60 could range from 1 bus clock minimum to 5 bus clock maximum depending on what state machine the SONIC-T is when the CS or MREQ signal is
asserted. This timing is not tested, but is guaranteed by design. This specification assumes that CS or MREQ is asserted before the falling edge that these signals
are asynchronously clocked in on (see T56 and T58). SAS must have been asserted for this timing to be correct. See SAS and CS timing in the Register Read, and
Register Write timing specificaitons.
Note 4: bcyc e bus clock cycle time (T3).
Note 5: The way in which SMACK is asserted due to CS is not the same as the way in which SMACK is asserted due to MREQ. SMACK goes low as a direct result
of the assertion of MREQ, whereas, for CS, SAS must also be driven low (BMODE e 1) or high (BMODE e 0) before SMACK will be asserted. This means that
when SMACK is asserted due to MREQ, SMACK will remain asserted until MREQ is deasserted. Multiple memory accesses can be made to the shared memory
without SMACK ever going high. When SMACK is asserted due to CS, however, SMACK will only remain low as long as SAS is also low (BMODE e 1) or high
(BMODE e 0). SMACK will not remain low throughout multiple register accesses to the SONIC-T because SAS must toggle for each register access. This is an
important difference to consider when designing shared memory designs.
91
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9.0 AC and DC Specifications (Continued)
et
e
REGISTER READ, BMODE e 0 (Note 1)
TL/F/12597 – 72
Number
20 MHz
Parameter
Min
25 MHz
Max
Min
4
0
T56
CS Asynchronous Setup to BSCK (Notes 4, 6)
T60a
CS and SAS to SMACK Low (Notes 3, 5, 6)
8
T62
SAS Asynchronous Setup to BSCK (Notes 4, 6)
T63
Register Address Setup Time to SAS
T64
Register Address Hold Time from SAS
8
T65
SAS Minimum Low Width (Notes 4, 6)
20
T68
SWR (Read) Hold from SAS
8
7
T73
SWR (Read) Setup to SAS
T75
BSCK to RDYo Low
T76
SAS or CS to RDYo High (Note 2)
T79
0
33 MHz
Max
Min
4
0
7
Units
Max
6
ns
4
bcyc
6
5
ns
6
5
ns
7
6
ns
17
15
ns
6
ns
ol
7
7
6
5
ns
20
18
16
ns
34
32
30
ns
SAS or CS to SMACK High (Note 2)
18
16
14
ns
T81
BSCK to SMACK Low
22
20
18
ns
T82
BSCK to Register Data Valid
44
42
40
ns
T85
SAS or CS to Data TRI-STATE (Notes 2, 7)
34
32
30
ns
T85a
bs
7
Minimum CS Deassert Time (Note 3)
1
1
1
bcyc
O
Note 1: This figure shows a slave access to the SONIC-T. The BSCK states (T1, T2, etc.) are the equivalent processor states during a slave access.
Note 2: If CS is deasserted before the falling edge of SAS, T76, T79 and T85 are referenced from the rising edge of CS.
Note 3: bcyc e bus clock cycle time (T3).
Note 4: It is not necessary to meet the setup time for CS (T56) and the setup time for SAS (T62) since these signals are asynchronously sampled. Meeting these
setup times for these signals, however, makes it possible to use T60a to determine exactly when SMACK will be asserted. For multiple register accesses, CS can
be held low and SAS can be used to delimit the slave cycle. In this case, SMACK will be driven low by the SONIC-T after T60a when T62 is met. T85a must be met
to ensure proper slave operation once CS is deasserted.
Note 5: The smaller value for T60a refers to when the SONIC-T is accessed during an Idle condition and the other value refers to when the SONIC-T is accessed
during non-idle conditions. These values are not tested, but are guaranteed by design.
Note 6: SAS may be asserted low anytime before or simultaneous to the falling edge of CS. Register address and slave read/write signals are latched on the rising
edge of the SAS, and if T62 is met, SMACK will be asserted by the SONIC-T after T60a. If T62 is not met, SONIC-T will sample SAS again on the next falling edge
of the clock, and SMACK will not be asserted until SAS is deasserted.
Note 7: This timing value includes an RC delay inherent in the test measurement. These signals typically TRI-STATE 7 ns earlier, enabling other devices to drive
these lines without contention.
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92
9.0 AC and DC Specifications (Continued)
et
e
REGISTER WRITE, BMODE e 0 (Note 1)
TL/F/12597 – 73
Number
Parameter
20 MHz
Min
25 MHz
Max
Min
4
0
33 MHz
Min
6
ns
4
0
bcyc
T56
CS Asynchronous Setup to BSCK (Notes 4, 6)
8
T60a
CS and SAS to SMACK Low (Notes 3, 5, 6)
0
T62
SAS Asynchronous Setup to BSCK (Notes 4, 6)
7
6
5
ns
T63
Register Address Setup Time to SAS
7
6
5
ns
T64
Register Address Hold Time from SAS
8
7
6
ns
T65
Minimum SAS Low Width (Notes 4, 6)
20
17
15
ns
T70
SWR (Write) Setup to SAS
7
6
5
ns
T71
SWR (Write) Hold from SAS
8
T75
BSCK to RDYo Low
T76
ol
7
Max
Units
Max
7
6
ns
18
16
SAS or CS to RDYo High (Note 2)
34
32
30
ns
T79
SAS or CS to SMACK High (Note 2)
18
16
14
ns
T81
BSCK to SMACK Low
18
ns
T83
Register Write Data Setup to BSCK
8
7
6
T84
Register Write Data Hold from BSCK
14
12
10
ns
T85a
Minimum CS Deassert Time (Note 3)
1
1
1
bcyc
bs
20
22
20
ns
ns
O
Note 1: This figure shows a slave access to the SONIC-T. The BSCK states (T1, T2, etc.) are the equivalent processor states during a slave access.
Note 2: If CS is deasserted before the falling edge of SAS, T76, T79 and T85 are referenced from the rising edge of CS.
Note 3: bcyc e bus clock cycle time (T3).
Note 4: It is not necessary to meet the setup time for CS (T56) and the setup time for SAS (T62) since these signals are asynchronously sampled. Meeting these
setup times for these signals, however, makes it possible to use T60a to determine exactly when SMACK will be asserted. For multiple register accesses, CS can
be held low and SAS can be used to delimit the slave cycle. In this case, SMACK will be driven low by the SONIC-T after T60a when T62 is met. T85a must be met
to ensure proper slave operation once CS is deasserted.
Note 5: The smaller value for T60a refers to when the SONIC-T is accessed during an Idle condition and the other value refers to when the SONIC-T is accessed
during non-idle conditions. These values are not tested, but are guaranteed by design.
Note 6: SAS may be asserted low anytime before or simultaneous to the falling edge of CS. Register address and slave read/write signals are latched on the rising
edge of the SAS, and if T62 is met, SMACK will be asserted by the SONIC-T after T60a. If T62 is not met, SONIC-T will sample SAS again on the next falling edge
of the clock, and SMACK will not be asserted until SAS is deasserted.
93
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9.0 AC and DC Specifications (Continued)
O
bs
ol
et
e
REGISTER READ, BMODE e 1 (Note 1)
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94
TL/F/12597 – 74
9.0 AC and DC Specifications (Continued)
Number
20 MHz
Parameter
Min
25 MHz
Max
Min
5
1
33 MHz
Min
6
ns
5
1
bcyc
T56
CS Asynchronous Setup to BSCK (Notes 3, 4)
8
T60
CS Valid to SMACK Low (Notes 2, 3, 4)
1
T63
Register Address Setup to SAS
6
5
4
ns
T64
Register Address Hold from SAS
8
7
6
ns
T67
SRW (Read) Setup to SAS
4
3
2
ns
T69
SAS Asynchronous Setup to BSCK (Notes 3, 4)
7
6
5
ns
T69a
SAS Asynchronous Setup to BSCK (Notes 3, 5)
5
4
3
ns
T74
SRW (Read) Hold from SAS
8
7
6
ns
T75a
BSCK to DSACK0,1 Low
20
18
16
ns
T77
CS to DSACK0,1 High (Note 5)
20
18
16
ns
T77a
SAS to DSACK0,1 High (Note 5)
31
29
27
ns
T77b
BSCK to DSACK0,1 TRI-STATE (Note 5)
19
17
15
ns
T78
Skew between DSACK0,1
3
3
2
ns
T79a
BSCK to SMACK High (Note 5)
19
17
15
T81
BSCK to SMACK Low
T82
BSCK to Register Data Valid
T85a
Minimum CS Deassert Time (Notes 2, 3)
T86
SAS to Register Data TRI-STATE (Note 6)
et
e
7
Max
Units
Max
22
20
44
1
18
42
1
42
40
1
40
38
ns
ns
ns
bcyc
ns
Note 1: This figure shows a slave access to the SONIC-T when the SONIC-T is idle, or rather not in master mode. If the SONIC-T is a bus master, there will be
some differences as noted in the Memory Arbitration/Slave Access diagram. The BSCK states (T1, T2, etc.) are the equivalent processor states during a slave
access.
Note 2: bcyc e bus clock cycle time (T3).
ol
Note 3: It is not necessary to meet the setup time for CS and SAS (T56 and T69) since these signals are asynchronously sampled. Meeting the setup time for these
signals, however, makes it possible to use T60 to determine when SMACK will be asserted. SAS may be asserted anytime before the next falling edge of the clock
that the CS is sampled on (as shown by specification T69). For multiple register accesses, CS can be held low and SAS can be used to delimit the slave cycle
(T69a must be met in order to terminate and start another cycle). In this case, SMACK will be asserted as soon as T69 timing is met.
Note 4: T60 could range from 1 bus clock minimum to 5 bus clock maximum depending on what state machine the SONIC-T is in when the CS signal is asserted.
This timing is not tested, but is guaranteed by design. This specification assumes that both T56 is met for CS and T69 is met for SAS. T60 specification also
assumes that there were no wait states in the current master mode access (if CS is asserted when SONIC-T is in Master Mode). If there were wait states, then it
would increase to T60 futher.
bs
Note 5: It is not necessary to meet the setup time for SAS (T69a) since this signal is asynchronously sampled. Meeting the setup time for this signal, however, will
ensure DSACK0,1 becomes TRI-STATE (T77b) and SMACK goes high (T79) at the falling edge of T1. Both CS and SAS could cause DSACK0,1 to deassert but
only SAS could cause DSACK0,1 to become TRI-STATE.
O
Note 6: The timing value includes an RC delay inherent in the test measurement. These signals typically TRI-STATE 7 ns earlier, enabling other devices to drive
these lines without contention.
95
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9.0 AC and DC Specifications (Continued)
et
e
REGISTER WRITE, BMODE e 1 (Note 1)
TL/F/12597 – 75
Number
20 MHz
Parameter
Min
T56
CS Asynchronous Setup to BSCK (Notes 3, 4)
T60
CS Valid to SMACK Low (Notes 2, 3, 4)
T63
Register Address Setup to SAS
T64
Register Address Hold from SAS
T69
25 MHz
Max
Min
5
1
8
1
33 MHz
Units
Max
Min
6
ns
5
1
bcyc
7
Max
5
4
ns
8
7
6
ns
SAS Asynchronous Setup to BSCK (Notes 3, 4)
7
6
5
ns
T69a
SAS Asynchronous Setup to BSCK (Notes 3, 5)
5
4
3
ns
T70a
SRW (Write) Setup to SAS
4
3
2
ns
ol
6
SRW (Write) Hold from SAS
T75b
BSCK to DSACK0,1 Low
22
20
18
ns
T77
CS to DSACK0,1 High (Note 5)
20
18
16
ns
T77a
SAS to DSACK0,1 High (Note 5)
31
29
27
ns
T77b
BSCK to DSACK0,1 TRI-STATE (Note 5)
19
17
15
ns
T78
Skew between DSACK0,1
3
3
2
ns
T79a
BSCK to SMACK High (Note 5)
19
17
15
ns
T81
BSCK to SMACK Low
22
20
18
ns
T84
T85a
O
T83
8
7
bs
T71a
6
ns
Register Write Data Setup to BSCK
8
7
6
Register Write Data Hold from BSCK
14
12
10
ns
ns
Minimum CS Deassert Time (Notes 2, 3)
1
1
1
bcyc
Note 1: This figure shows a slave access to the SONIC-T when the SONIC-T is idle, or rather not in master mode. If the SONIC-T is a bus master, there will be
some differences as noted in the Memory Arbitration/Slave Access diagram. The BSCK states (T1, T2, etc.) are the equivalent processor states during a slave
access.
Note 2: bcyc e bus clock cycle time (T3).
Note 3: It is not necessary to meet the setup time for CS and SAS (T56 and T69) since these signals are asynchronously sampled. Meeting the setup time for these
signals, however, makes it possible to use T60 to determine when SMACK will be asserted. SAS may be asserted anytime before the next falling edge of the clock
that the CS is sampled on (as shown by specification T69). For multiple register accesses, CS can be held low and SAS can be used to delimit the slave cycle
(T69a must be met in order to terminate and start another cycle). In this case, SMACK will be asserted as soon as T69 timing is met.
Note 4: T60 could range from 1 bus clock minimum to 5 bus clock maximum depending on what state machine the SONIC-T is in when the CS signal is asserted.
This timing is not tested, but is guaranteed by design. This specification assumes that both T56 is met for CS and T69 is met for SAS. T60 specification also
assumes that there were no wait states in the current master mode access (if CS is asserted when SONIC-T is in Master Mode). If there were wait states, then it
would increase the T60 futher.
Note 5: It is not necessary to meet the setup time for SAS (T69a) since this signal is asynchronously sampled. Meeting the setup time for this signal, however, will
ensure DSACK0,1 becomes TRI-STATE (77b) and SMACK goes high (T79) at the falling edge of T1. Both CS and SAS could cause DSACK0,1 to deassert but only
SAS could cause DSACK0,1 to become TRI-STATE.
http://www.national.com
96
9.0 AC and DC Specifications (Continued)
ENDEC TRANSMIT TIMING
TL/F/12597 – 76
Number
Parameter
Min
Max
Units
T87
Transmit Clock High Time (Note 1)
40
ns
T88
Transmit Clock Low Time (Note 1)
40
ns
T89
Transmit Clock Cycle Time (Note 1)
100.01
ns
T95
Transmit Output Delay (Note 1)
55
ns
T96
Transmit Output Fall Time (80% to 20%, Note 1)
7
ns
T97
Transmit Output Rise Time (20% to 80%, Note 1)
T98
Transmit Output Jitter (Not Shown)
T100
Transmit Output High before Idle (Half Step)
T101
Transmit Output Idle Time (Half Step)
et
e
99.99
7
0.5 Typ
200
8000
ns
ns
ns
ns
O
bs
ol
Note 1: This specification is provided for information only and is not tested.
97
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9.0 AC and DC Specifications (Continued)
ENDEC RECEIVE TIMING (INTERNAL ENDEC MODE)
TL/F/12597 – 77
et
e
ENDEC COLLISION TIMING
TL/F/12597 – 78
Number
Parameter
Min
Max
Receive Clock Duty Cycle Time (Note 1)
T105
Carrier Sense on Time
60
ns
70
ns
T106
Data Acquisition Time
T107
Receive Data Output Delay
700
ns
150
T108
Receive Data Valid from RXC
ns
10
ns
T109
Receive Data Stable Valid Time
T112
Carrier Sense Off Delay)
T113
Minimum Number of RXCs after CRS Low (Note 3)
T114
Collision Turn On Time
55
ns
T115
Collision Turn Off Time
250
ns
ol
T102
bs
90
Note 1: This parameter is measured at the 50% point of each clock edge.
Note 2: When CRSi goes low, it remains low for a minimum of 2 receive clocks (RXCs).
O
Note 3: rcyc e receive clocks.
http://www.national.com
40
Units
98
ns
250
5
ns
rcyc
9.0 AC and DC Specifications (Continued)
ENDEC-MAC SERIAL TIMING FOR RECEPTION (EXTERNAL ENDEC MODE)
TL/F/12597 – 79
Parameter
Min
T118
Receive Clock High Time
40
T119
Receive Clock Low Time
40
T120
Receive Clock Cycle Time
90
T121
RXD Setup to RXC
20
T122
RXD Hold from RXC
15
T124
Maximum Allowed Dribble Bits
T125
Receive Recovery Time (Note 2)
T126
RXC to Carrier Sense Low (Notes 1, 3)
Note 1: tcyc e transmit clocks, rcyc e receive clocks, bcyc e T3.
Max
Units
ns
ns
110
ns
ns
et
e
Number
ns
6
Bits
1
rcyc
Note 2: This parameter refers to longest time (not including wait-states) the SONIC TM requires to perform its end of receive processing and be ready for the next
start of frame delimiter. This time is 4 a 36 ccyc bcyc. This is guaranteed by design and is not tested.
Note 3: To ensure proper receive operation, a minimum of 5 RXCs after CRS low are required.
O
bs
ol
ENDEC-MAC SERIAL TIMING FOR TRANSMIT (NO COLLISION)
Number
Parameter
TL/F/12597 – 80
Min
Max
Units
T127
Transmit Clock High Time
40
T128
Transmit Clock Low Time
40
ns
T129
Transmit Clock Cycle Time
90
T130
TXC to TXE High
40
ns
T131
TXC to TXD Valid
40
ns
T132
TXD Hold Time from TXC
T133
TXC to TXE Low
40
ns
T134
TXE Low to Start of CD Heartbeat (Note 1)
T135
Collision Detect Width (Note 1)
ns
110
0
ns
64
2
ns
tcyc
tcyc
Note 1: tcyc e transmit clock.
99
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9.0 AC and DC Specifications (Continued)
ENDEC-MAC SERIAL TIMING FOR TRANSMISSION (COLLISION)
TL/F/12597 – 81
Parameter
Min
T135
Collision Detect Width (Note 1)
2
Max
T136
Delay from Collision
8
tcyc
T137
JAM Period
32
tcyc
tcyc
O
bs
ol
Note 1: tcyc e transmit clock.
http://www.national.com
Units
et
e
Number
100
9.0 AC and DC Specifications (Continued)
TL/F/12597 – 82
Symbol
Parameter
Min
Max
Units
Transmit Output High before Idle
200
ns
tTOi
Transmit Output Idle Time
8000
ns
Symbol
teop1
TL/F/12597 – 83
Parameter
Min
Transmit End of Packet Hold Time after Logic ‘‘1’’ (Note 1)
225
ns
Transmit End of Packet Hold Time after Logic ‘‘0’’ (Note 1)
225
ns
O
teop0
bs
ol
et
e
tTOh
Max
Units
Note 1: This parameter is guaranteed by design and is not tested.
101
http://www.national.com
9.0 AC and DC Specifications (Continued)
LINK PULSE TIMING
TL/F/12597 – 84
Parameter
Min
Max
Units
tlp
Symbol
Time between Link Output Pulses
8
24
ms
tlpw
Link Integrity Output Pulse Width
80
130
ns
O
bs
ol
et
e
TPI TRANSMIT TIMING (End of Packet)
TL/F/12597 – 85
Parameter
Min
Max
tdel
Symbol
Pre-Emphasis Output Delay (TXO g to TXO g ) (Note 1)
46
54
tOff
Transmit Hold Time at End of Packet (TXO g ) (Note 1)
250
ns
tOffd
Transmit Hold Time at End of Packet (TXOd g ) (Note 1)
200
ns
Note 1: This parameter is guaranteed by design and is not tested.
http://www.national.com
102
Units
ns
10.0 AC Timing Test Conditions
Pin Capacitance TA e 25§ C, f e 1 MHz
All specifications are valid only if the mandatory isolation is
employed and all differential signals are taken to be at the
AUI side of the pulse transformer.
Symbol
Input Pulse Levels (TTL/CMOS)
GND to 3.0V
Input Rise and Fall Times (TTL/CMOS)
5 ns
Input and Output Reference
Levels (TTL/CMOS)
1.5V
b 350 mV to b 1315 mV
Input Pulse Levels (Diff.)
Input and Output
Reference Levels (Diff.)
TRI-STATE Reference Levels
Typ
Units
CIN
Input Capacitance
Parameter
7
pF
COUT
Output Capacitance
7
pF
DERATING FACTOR
Output timing is measured with a purely capacitive load of
50 pF. The following correction factor can be used for other
loads: CL t 50 pF e 0.05 ns/pF.
50% Point of
the Differential
Float (DV) g 0.5V
AUI Transmit Test Load
OUTPUT LOAD (See Figure below)
TL/F/12597 – 87
et
e
Note: In the above diagram, the TX a and TX b signals are taken from the
AUI side of the isolation (pulse transformer). The pulse transformer
used for all testing is a 100 mH g 0.1% Pulse Engineering PE64103.
TL/F/12597 – 86
Note 1: 50 pF, includes scope and jig capacitance.
Note 2: S1 e Open for timing test for push pull outputs.
S1 e VCC for VOL test.
S1 e GND for VOH test.
S1 e VCC for High Impedance to active low and active low to High
Impedance measurements.
O
bs
ol
S1 e GND for High Impedance to active high and active High to
High Impedance measurements.
103
http://www.national.com
et
e
ol
bs
160-Lead Plastic Chip Carrier (VF)
Order Number DP83936AVF
NS Package Number VF160A
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O
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