Maxim MAX8791 Single-phase, synchronous mosfet driver Datasheet

19-0628; Rev 2; 1/10
Single-Phase, Synchronous MOSFET Drivers
The MAX8791/MAX8791B are single-phase, synchronous, noninverting MOSFET drivers. The MAX8791/
MAX8791B are intended to work with controller ICs like
the MAX8736 or MAX8786, in multiphase notebook
CPU core regulators.
The regulators can either step down directly from the
battery voltage to create the core voltage, or step down
from the main system supply. The single-stage conversion method allows the highest possible efficiency, while
the 2-stage conversion at higher switching frequency
provides the minimum possible physical size.
The low-side drivers are optimized to drive 3nF capacitive loads with 4ns/8ns typical fall/rise times, and the
high-side driver with 8ns/10ns typical fall/rise times.
Adaptive dead-time control prevents shoot-through currents and maximizes converter efficiency.
Features
o Single-Phase, Synchronous MOSFET Drivers
o 0.5Ω Low-Side On-Resistance
o 0.7Ω High-Side On-Resistance
o 8ns Propagation Delay
o 15ns Minimum Guaranteed Dead Time
o Integrated Boost “Diode”
o 2V to 24V Input Voltage Range
o Selectable Pulse-Skipping Mode
o Low-Profile TQFN Package
The MAX8791/MAX8791B are available in a small, leadfree, 8-pin, 3mm x 3mm TQFN package.
Ordering Information
Applications
Notebooks/Desktops/Servers
CPU Core Power Supplies
MAX8791GTA+
-40oC to +105oC
8 TQFN-EP*
Multiphase Step-Down Converters
MAX8791BGTA+
-40oC to +105oC
8 TQFN-EP*
PART
TEMP RANGE
PIN-PACKAGE
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
Pin Configuration
TOP VIEW
DH
MAX8791
MAX8791B
BST
SKIP
LX
5
LX 7
VOUT (1.45V
AT 20A)
4 DL
MAX8791
MAX8791B
DH 8
3 GND
+
VDD
DL
GND
PAD
1
2
PWM
+5V BIAS
SUPPLY
6
BST
PWM SKIP
VDD
PWM
SKIP
INPUT (VIN)*
5V TO 24V
TQFN
3mm × 3mm
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX8791/MAX8791B
General Description
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
VDD to GND...............…………………….………….. -0.3V to +6V
SKIP to GND..................………………………………-0.3V to +6V
PWM to GND ................……………………………….-0.3V to +6V
DL to GND ..................................................-0.3V to (VDD + 0.3V)
BST to GND ............................................................-0.3V to +36V
DH to LX ....................................................-0.3V to (VBST + 0.3V)
BST to VDD .............................................................-0.3V to +30V
BST to LX ................…………………………………...-0.3V to +6V
Continuous Power Dissipation (TA = +70°C)
8-Pin 3mm x 3mm TQFN
(derate 23.8mW/°C above +70°C) .............................1904mW
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDD = V SKIP = 5V, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
Input Voltage Range
VDD Undervoltage
Lockout Threshold
Quiescent Supply
Current (VDD)
SYMBOL
CONDITIONS
VDD
VUVLO(VDD)
IDD
MIN
TYP
4.20
Rising edge, PWM disabled below this level
Falling edge, PWM disabled below this level
MAX
UNITS
5.50
V
3.7
3.0
3.5
4.0
PWM = open; after the shutdown hold time has expired
0.08
0.2
SKIP = GND, PWM = GND,
LX = GND (after zero crossing)
0.25
0.5
SKIP = GND or VDD, PWM = VDD, VBST = 5V
0.6
1.5
V
mA
DRIVERS
tON(MIN)
Minimum on-time
50
tOFF(MIN)
Minimum off-time
300
DL Propagation Delay
tPWM-DL
PWM high to DL low
10
ns
DH Propagation Delay
tPWM-DH
PWM low to DH low
14
ns
PWM Pulse Width
DL-to-DH Dead Time
tDL-DH
DL falling to DH rising
DH-to-DL Dead Time
tDH-DL
DH falling to DL rising
DL Transition Time
DH Transition Time
TA = -40°C to +105°C
15
TA = 0°C to +85°C
15
TA = -40°C to +105°C
15
12
Rising, 3.0nF load
14
tF_DH
Falling, 3.0nF load
8
tR_DH
Rising, 3.0nF load
10
RON(DL)
Boost On-Resistance
2
IDL_SINK
VZX
RON(BST)
ns
ns
DH, high state (pullup)
0.9
2.5
0.7
2.3
DL, high state (pullup)
0.7
1.8
DL, low state (pulldown)
0.5
1.2
DH forced to 2.5V, BST - LX forced to 5V
DL Driver Source Current IDL_SOURCE DL forced to 2.5V
Zero-Crossing Threshold
ns
DH, low state (pulldown)
BST-LX forced to 5V
IDH_SOURCE DH forced to 2.5V, BST - LX forced to 5V
IDH_SINK
ns
30
Falling, 3.0nF load
DL Driver On-Resistance
DL Driver Sink Current
30
tF_DL
RON(DH)
DH Driver Sink Current
15
tR_DL
DH Driver On-Resistance
DH Driver Source Current
TA = 0°C to +85°C
ns
2.2
Ω
Ω
A
2.7
A
2.7
A
DL forced to 2.5V
8
A
GND - LX, SKIP = GND
3
mV
VDD = 5V, DH = LX = GND (pulldown state), IBST = 10mA
5
_______________________________________________________________________________________
12
Ω
Single-Phase, Synchronous MOSFET Drivers
(Circuit of Figure 1, VDD = V SKIP = 5V, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
VDD/2
- 0.4
Midlevel
Low (DH = low; DL = high)
PWM Input Current
IPWM
Midlevel Shutdown Hold
Time
tMID
ISKIP
Thermal-Shutdown
Threshold
TSHDN
VDD/2
+ 0.4
V
-400
-200
-80
80
+200
400
120
300
600
1.7
2.4
Falling edge
0.8
1.5
Sink; SKIP forced to 0.8V to VDD, TA = +25°C
-4
-2
Source; PWM forced to GND
Rising edge
SKIP Input Current
UNITS
0.4
Sink; PWM forced to VDD
SKIP Input Threshold
MAX
VDD 0.4
High (DH = high; DL = low)
PWM Input Levels
TYP
Hysteresis = 20°C
µA
ns
V
-0.5
µA
+160
°C
Note 1: Limits are 100% production tested at TA = +25°C. Maximum and minimum limits over temperature are guaranteed through
correlation using statistical-quality-control (SQC) methods.
Typical Operating Characteristics
(Circuit of Figure 1, VDD = 5V, CDH = 3nF, CDL = 3nF, TA = +25°C, unless otherwise noted.)
PACKAGE-POWER DISSIPATION
vs. CAPACITIVE LOAD ON DH AND DL
350
A
150
100
PD (mW)
200
PD (mW)
C
400
B
300
B
250
200
150
A
100
50
A: CDH = 3.3nF; CDL = 3.3nF
B: CDH = 1.5nF; CDL = 6.8nF
0
0
200
400
600
800 1000
PWM FREQUENCY (kHz)
A: 300kHz
B: 600kHz
C: 1MHz
50
0
1200
1000
2500
4000 5500 7000
CAPACITANCE (pF)
30
8500 10,000
MAX8791 toc03
250
450
25
RISE AND FALL TIME (ns)
500
MAX8791 toc01
300
DL RISE AND FALL TIMES
vs. CAPACITIVE LOAD
MAX8791 toc02
PACKAGE-POWER DISSIPATION
vs. PWM FREQUENCY
RISE TIME
20
15
10
FALL TIME
5
CDL = CDH
0
1000
2500
4000 5500 7000
CAPACITANCE (pF)
8500 10,000
_______________________________________________________________________________________
3
MAX8791/MAX8791B
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDD = 5V, CDH = 3nF, CDL = 3nF, TA = +25°C, unless otherwise noted.)
DH AND DL RISE AND FALL TIMES
vs. TEMPERATURE
25
20
FALL TIME
15
10
35
A
30
40
DH RISE
25
DH FALL
20
20
DL IS DRIVING 2 SI7336ADP
DH IS DRIVING 1 SI7892ADP
CDL = CDH
10
0
1000
2500
4000 5500 7000
CAPACITANCE (pF)
-40
8500 10,000
-15
A: CDH = 3.3nF; CDL = 3.3nF
B: CDH = 1.5nF; CDL = 6.8nF
10
35
60
TEMPERATURE (°C)
85
110
0
200
400
600
800 1000
PWM FREQUENCY (kHz)
TYPICAL APPLICATION CIRCUIT
SWITCHING WAVEFORMS
MAX8791 toc07
16
PROPOGATION DELAY TIME (ns)
10
0
PROPAGATION DELAY TIME
vs. TEMPERATURE
PWM FALL TO DH FALL
15
30
DL FALL
15
5
B
50
IDD (mW)
RISE TIME
30
DL RISE
RISE AND FALL TIME (ns)
35
60
MAX8791 toc05
40
MAX8791 toc04
40
PACKAGE-POWER DISSIPATION
vs. PWM FREQUENCY
14
MAX8791 toc08
5V/div
VPWM
13
12
VLX
10V/div
VDL
5V/div
VDH
20V/div
11
PWM RISE TO DL FALL
10
9
8
-40
-15
10
35
60
TEMPERATURE (°C)
85
110
100ns/div
DH RISE AND DL FALL WAVEFORMS
DH FALL AND DL RISE WAVEFORMS
MAX8791 toc10
MAX8791 toc09
5V/div
VPWM
VLX
VDL
20ns/div
4
5V/div
VPWM
10V/div
VLX
5V/div
VDL
10V/div
VDH
MAX8791 toc06
DH RISE AND FALL TIMES
vs. CAPACITIVE LOAD
RISE AND FALL TIME (ns)
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
10V/div
5V/div
10V/div
VDH
20ns/div
_______________________________________________________________________________________
1200
Single-Phase, Synchronous MOSFET Drivers
(Circuit of Figure 1, VDD = 5V, CDH = 3nF, CDL = 3nF, TA = +25°C, unless otherwise noted.)
SWITCHING WAVEFORMS
(PWM = HIGH TO MID TO HIGH)
SWITCHING WAVEFORMS
(PWM = MID TO LOW TO MID)
MAX8791 toc12
MAX8791 toc11
VPWM
5V
5V/div
0
VDL
5V
5V/div
0
VLX
0
10V/div
VDH
0
10V/div
5V
5V/div
0
VPWM
VDL
0
5V/div
10V
10V/div
0
VLX
15V
VDH
10V/div
0
Pin Description
PIN
NAME
FUNCTION
1
BST
Boost Flying-Capacitor Connection. Gate-drive power supply for DH high-side gate driver. Connect a 0.1µF or
0.22µF capacitor between BST and LX.
2
PWM
PWM Input Pin. Noninverting DH control input from the controller IC:
Logic high: DH = high (BST), DL = low (PGND).
Midlevel: After the midlevel hold time expires, the controller enters standby mode. DH and DL pulled low.
Logic low: DH = low (LX), DL = high (VDD) when SKIP = high.
Internal pullup and pulldown resistors create the midlevel and prevent the controller from triggering an on-time if
this input is left unconnected (not soldered properly) or driven by a high impedance.
3
GND
Power Ground for the DL Gate Drivers and Analog Ground. Connect exposed pad to GND.
4
DL
PWM Low-Side Gate-Driver Output. Swings between GND and VDD. DL forced high in shutdown.
5
VDD
Supply Voltage Input for the DL Gate Drivers. Connect to 4.2V to 5.5V supply and bypass to GND with a 1µF
ceramic capacitor.
6
SKIP
Pulse-Skipping Mode Pin. Enable pulse-skipping mode (zero-crossing comparator enabled) when the driver is
operating in SKIP mode:
SKIP = VDD PWM mode
SKIP = GND SKIP mode
An internal pulldown current pulls the controller into the low-power pulse-skipping state if this input is left
unconnected (not soldered properly) or driven by a high impedance.
7
LX
Switching Node and Inductor Connection. Low-power supply for the DH high-side gate driver. LX connects to
the skip-mode zero-crossing comparator.
8
DH
External High-Side nMOSFET Gate-Driver Output. Swings between LX and BST.
—
EP
Exposed Pad. Connect to ground through multiple vias to reduce the thermal impedance.
_______________________________________________________________________________________
5
MAX8791/MAX8791B
Typical Operating Characteristics (continued)
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
PWM
DH
BST
PWM
SKIP
SKIP
MAX8791
MAX8791B
LX
DL
+5V BIAS
SUPPLY
VDD
CDH
3nF
CBST
0.1µF
CDL
3nF
GND
C1
1.0µF
PAD
Figure 1. Test Circuit
tPWM-DH
tPWM-DL
tMID
tPWM-DL
tMID
PWM
tF_DL
tR_DL
tF_DL
tR_DL
DL
tDH-DL
tDL-DH
DH
tR_DH
tR_DH
tR_DH
tR_DH
tPWM-DH
Figure 2. Timing Diagram
6
_______________________________________________________________________________________
Single-Phase, Synchronous MOSFET Drivers
MAX8791/MAX8791B
INPUT (VIN)
CIN
PWM
SKIP
+5V BIAS
SUPPLY
PWM
DH
SKIP
BST
VDD
MAX8791
MAX8791B
NH
2x 10µF
L1
0.36µH
CBST
0.22µF
LX
CVDD
1.0µF
DL
NL
OUTPUT (VOUT)
COUT
2x 330µF
6mΩ
DL
GND
PAD
Figure 3. Typical MOSFET-Driver Application Circuit
Table 1. Typical Components
DESIGNATION
QTY
COMPONENT SUPPLIERS
NH
1 per phase
Siliconix Si4860DY
NL
1–2 per phase
Siliconix Si4336DY
BST Capacitor (CBST)
Schottky Diode
1 per phase
Optional
Inductor (L1)
1 per phase
0.1µF or 0.22µF ceramic capacitor
3A, 40V Schottky diode
0.36µH, 26A, 0.9mΩ power inductor
Output Capacitors (COUT)
1–2 per phase
330µF, 6mΩ per phase
Input Capacitors (CIN)
1–2 per phase
10µF, 25V X5R ceramic capacitors
Detail Description
The MAX8791/MAX8791B single-phase gate drivers,
along with the MAX8736 or MAX8786 multiphase controllers, provide flexible multiphase CPU core-voltage
supplies. The low driver resistance allows up to 7A output peak current. Each MOSFET driver in the
MAX8791/MAX8791B is capable of driving 3nF capacitive loads with only 9ns propagation delay and 4ns/8ns
(typ) fall/rise times, allowing operation up to 3MHz per
phase. Larger capacitive loads are allowable but result
in longer propagation and transition times. Adaptive
dead-time control prevents shoot-through currents and
maximizes converter efficiency while allowing operation
with a variety of MOSFETs and PWM controllers. An
input undervoltage lockout (UVLO) circuit allows proper
power-on sequencing.
PWM Input
The drivers for the MAX8791/MAX8791B are disabled—
DH and DL pulled low—if the PWM input remains in the
midlevel window for at least 300ns (typ). Once the
PWM signal is driven high or low, the MAX8791/
MAX8791B immediately exit the low-current shutdown
state and resume active operation. Outside the shutdown state, the drivers are enabled based on the rising
and falling thresholds specified in the Electrical
Characteristics.
MOSFET Gate Drivers (DH, DL)
The high-side driver (DH) has a 0.9Ω sourcing resistance and 0.7Ω sinking resistance, resulting in 2.2A
peak sourcing current and 2.7A peak sinking current
with a 5V supply voltage. The low-side driver (DL) has a
typical 0.7Ω sourcing resistance and 0.3Ω sinking
resistance, yielding 2.7A peak sourcing current and 8A
peak sinking current. This reduces switching losses,
making the MAX8791/MAX8791B ideal for both highfrequency and high output-current applications.
_______________________________________________________________________________________
7
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
VDD
BST
PWM
DRV
DH
DRIVER LOGIC
AND
DEAD-TIME
CONTROL
THERMAL SHUTDOWN
LX
UVLO
DRV#
VDD
SKIP
DL
LX
GND
ZX DETECTION
PAD
Figure 4. Overview Block Diagram
Adaptive Shoot-Through Protection
The DH and DL drivers are optimized for driving moderately sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VIN - VOUT differential exists. Two adaptive dead-time
circuits monitor the DH and DL outputs and prevent the
opposite-side FET from turning on until the other is fully
off. The MAX8791/MAX8791B constantly monitor the
low-side driver output (DL) voltage, and only allow the
high-side driver to turn on when DL drops below the
adaptive threshold. Similarly, the controller monitors the
high-side driver output (DH), and prevents the low side
from turning on until DH falls below the adaptive threshold before allowing DL to turn on.
The adaptive driver dead time allows operation without
shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a
low-resistance, low-inductance path from the DL and
DH drivers to the MOSFET gates for the adaptive deadtime circuits to work properly; otherwise, the sense circuitry in the MAX8791/MAX8791B interprets the
8
MOSFET gates as off while charge actually remains.
Use very short, wide traces (50 mils to 100 mils wide if
the MOSFET is 1in from the driver).
Internal Boost Switch
The MAX8791/MAX8791B use a bootstrap circuit to
generate the necessary drive voltage to fully enhance
the high-side n-channel MOSFET. The internal p-channel MOSFET creates an ideal diode, providing a low
voltage drop between VDD and BST.
The selected high-side MOSFET determines appropriate
boost capacitance values (CBST in Figure 1), according
to the following equation:
CBST = QGATE ∆VBST
where QGATE is the total gate charge of the high-side
MOSFET and ∆VBST is the voltage variation allowed on
the high-side MOSFET driver. Choose ∆VBST = 0.1V to
0.2V when determining CBST. The boost flying capacitor
should be a low equivalent-series resistance (ESR)
ceramic capacitor.
_______________________________________________________________________________________
Single-Phase, Synchronous MOSFET Drivers
Input Undervoltage Lockout
When VDD is below the UVLO threshold, DH and DL
are held low. Once VDD is above the UVLO threshold
and while PWM is low, DL is driven high and DH is
driven low. This prevents the output of the converter
from rising before a valid PWM signal is applied.
Low-Power Pulse Skipping
The MAX8791/MAX8791B enter into low-power pulseskipping mode when SKIP is pulled low. In skip mode,
an inherent automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. A zerocrossing comparator truncates the low-side switch ontime at the inductor current’s zero crossing. The
comparator senses the voltage across LX and GND.
Once VLX - VGND drops below the zero-crossing comparator threshold (see the Electrical Characteristics),
the comparator forces DL low. This mechanism causes
the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when
the load current of each phase is equal to 1/2 the peakto-peak ripple current, which is a function of the inductor value. For a battery input range of 7V to 20V, this
threshold is relatively constant, with only a minor
dependence on the input voltage due to the typically
low duty cycles. The switching waveforms may appear
noisy and asynchronous when light loading activates
the pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency.
Applications Information
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The
high-side MOSFET (NH) must be able to dissipate the
resistive losses plus the switching losses at both
V IN(MIN) and V IN(MAX) . Calculate both these sums.
Ideally, the losses at VIN(MIN) should be roughly equal
to losses at VIN(MAX), with lower losses in between. If
the losses at VIN(MIN) are significantly higher than the
losses at VIN(MAX), consider increasing the size of NH
(reducing RDS(ON) but increasing CGATE). Conversely,
if the losses at VIN(MAX) are significantly higher than the
losses at VIN(MIN), consider reducing the size of NH
(increasing RDS(ON) but reducing CGATE). If VIN does
not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the
switching losses. Choose a low-side MOSFET that has
the lowest possible on-resistance (RDS(ON)), comes in
a moderate-sized package (i.e., one or two 8-pin SOs,
DPAK, or D2PAK), and is reasonably priced. Ensure
that the DL gate driver can supply sufficient current to
support the gate charge and the current injected into
the parasitic gate-to-drain capacitor caused by the
high-side MOSFET turning on; otherwise, cross-conduction problems can occur.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the
minimum input voltage:
2
⎛V
⎞⎛ I
⎞
PD (NH RESISTIVE) = ⎜ OUT ⎟ ⎜ LOAD ⎟ RDS(ON)
⎝ VIN ⎠ ⎝ η TOTAL ⎠
where ηTOTAL is the total number of phases. Generally,
a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON)
required to stay within package-power dissipation often
limits how small the MOSFETs can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses
do not usually become an issue until the input is
greater than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (NH) due to switching losses is difficult since
it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics.
The following switching-loss calculation provides only a
very rough estimate and is no substitute for prototype
evaluation, preferably including verification using a
thermocouple mounted on NH:
⎛ VIN(MAX)ILOADfSW ⎞ ⎛ QG(SW) ⎞
PD (NH SWITCHING) = ⎜
⎟⎜
⎟+
nTOTAL
⎝
⎠ ⎝ IGATE ⎠
COSSVIN2fSW
2
where COSS is the NH MOSFET’s output capacitance,
QG(SW) is the charge needed to turn on the high-side
MOSFET, and IGATE is the peak gate-drive source/sink
current (5A typ).
_______________________________________________________________________________________
9
MAX8791/MAX8791B
5V Bias Supply (VDD)
VDD provides the supply voltage for the internal logic circuits. Bypass VDD with a 1µF or larger ceramic capacitor to GND to limit noise to the internal circuitry. Connect
these bypass capacitors as close as possible to the IC.
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the
switching-loss equation above. If the high-side MOSFET
chosen for adequate RDS(ON) at low battery voltages
becomes extraordinarily hot when biased from VIN(MAX),
consider choosing another MOSFET with lower parasitic
capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at the maximum input voltage:
2
⎡ ⎛ V
⎞⎤ ⎛ I
⎞
PD (NL RESISTIVE) = ⎢1 − ⎜ OUT ⎟ ⎥ ⎜ LOAD ⎟ RDS(ON)
⎢⎣ ⎝ VIN(MAX) ⎠ ⎥⎦ ⎝ ηTOTAL ⎠
The worst case for MOSFET power dissipation occurs
under heavy load conditions that are greater than
ILOAD(MAX), but are not quite high enough to exceed the
current limit and cause the fault latch to trip. The
MOSFETs must have a good-sized heatsink to handle the
overload power dissipation. The heat sink can be a large
copper field on the PCB or an externally mounted device.
An optional Schottky diode only conducts during the
dead time when both the high-side and low-side
MOSFETs are off. Choose a Schottky diode with a
forward voltage low enough to prevent the low-side
MOSFET body diode from turning on during the dead
time, and a peak current rating higher than the peak
inductor current. The Schottky diode must be rated to
handle the average power dissipation per switching
cycle. This diode is optional and can be removed if efficiency is not critical.
IC Power Dissipation and
Thermal Considerations
Power dissipation in the IC package comes mainly from
driving the MOSFETs. Therefore, it is a function of both
switching frequency and the total gate charge of the
selected MOSFETs. The total power dissipation when
both drivers are switching is given by:
where PD(IC) is the power dissipated by the device,
and ΘJA is the package’s thermal resistance. The typical thermal resistance is 42°C/W for the 3mm x 3mm
TQFN package.
Avoiding dV/dt Turning on the
Low-Side MOSFET
At high input voltages, fast turn-on of the high-side
MOSFET can momentarily turn on the low-side MOSFET
due to the high dV/dt appearing at the drain of the lowside MOSFET. The high dV/dt causes a current flow
through the Miller capacitance (CRSS) and the input
capacitance (CISS) of the low-side MOSFET. Improper
selection of the low-side MOSFET that results in a high
ratio of CRSS/CISS makes the problem more severe. To
avoid this problem, minimize the ratio of CRSS/CISS
when selecting the low-side MOSFET. Adding a 1Ω to
4.7Ω resistor between BST and C BST can slow the
high-side MOSFET turn-on. Similarly, adding a small
capacitor from the gate to the source of the high-side
MOSFET has the same effect. However, both methods
work at the expense of increased switching losses.
Layout Guidelines
The MAX8791/MAX8791B MOSFET driver sources and
sinks large currents to drive MOSFETs at high switching speeds. The high di/dt can cause unacceptable
ringing if the trace lengths and impedances are not well
controlled. The following PCB layout guidelines are recommended when designing with the MAX8791/
MAX8791B:
1) Place all decoupling capacitors as close as possible to their respective IC pins.
2) Minimize the length of the high-current loop from
the input capacitor, the upper switching MOSFET,
and the low-side MOSFET back to the input-capacitor
negative terminal.
3) Provide enough copper area at and around the
switching MOSFETs and inductors to aid in thermal
dissipation.
PD(IC) = IBIAS × 5V
4) Connect GND of the MAX8791/MAX8791B as close
as possible to the source of the low-side MOSFETs.
where IBIAS is the bias current of the 5V supply calculated in the 5V Bias Supply (VDD) section. The rise in
die temperature due to self-heating is given by the
following formula:
A sample layout is available in the MAX8786 evaluation kit.
∆TJ = Θ JA × PD(IC)
10
______________________________________________________________________________________
Single-Phase, Synchronous MOSFET Drivers
PROCESS: BiCMOS
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 TDFN-EP
TQ833+1
21-0136
______________________________________________________________________________________
11
MAX8791/MAX8791B
Package Information
Chip Information
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0
8/06
Initial release
1
11/06
Updated Electrical Characteristics and PWM Input section.
3, 7
—
2
1/10
Added the MAX8791B to entire data sheet.
1–12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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