ON NTD25P03L Power mosfet Datasheet

NTD25P03L
Power MOSFET
−25 A, −30 V, Logic Level P−Channel
DPAK
Designed for low voltage, high speed switching applications and to
withstand high energy in the avalanche and commutation modes. The
source−to−drain diode recovery time is comparable to a discrete fast
recovery diode.
Typical Applications
•
•
•
•
•
PWM Motor Controls
Power Supplies
Converters
Bridge Circuits
Pb−Free Package is Available
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V(BR)DSS
RDS(on) TYP
ID MAX
−30 V
51 m @ 5.0 V
−25 A
D
P−Channel
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Unit
Drain−to−Source Voltage
VDSS
−30
V
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 ms)
VGS
VGSM
15
20
V
Vpk
Drain Current
− Continuous @ TA = 25°C
− Single Pulse (tp ≤ 10 s)
ID
IDM
−25
−75
A
Apk
Total Power Dissipation @ TA = 25°C
PD
75
Watts
Operating and Storage Temperature
Range
TJ, Tstg
−55 to
+150
°C
EAS
200
mJ
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc,
Peak IL = 20 Apk, L = 1.0 mH,
RG = 25 )
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
S
4
RJC
RJA
RJA
1.65
67
120
TL
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
4
Drain
1 2
3
DPAK
CASE 369C
(Surface Mount)
Style 2
2
1
3
Drain
Gate
Source
4
4
Drain
1
°C/W
MARKING DIAGRAMS
YWW
25P
03L
Value
YWW
25P
03L
Symbol
Rating
2
3
DPAK
CASE 369D
(Straight Lead)
Style 2
25P03L
Device Code
Y
= Year
WW
= Work Week
1 2 3
Gate Drain Source
ORDERING INFORMATION
Package
Shipping†
DPAK
75 Units/Rail
NTD25P03LG
DPAK
(Pb−Free)
75 Units/Rail
NTD25P03L1
DPAK
Straight Lead
75 Units/Rail
NTD25P03LT4
DPAK
2500/Tape & Reel
Device
NTD25P03L
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. 1
1
Publication Order Number:
NTD25P03L/D
NTD25P03L
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = −250 A)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = −30 Vdc, VGS = 0 Vdc, TJ = 25°C)
(VDS = −30 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current
(VGS = ±15 Vdc, VDS = 0 Vdc)
IGSS
V
−30
mV/°C
−24
A
−1.0
−100
nA
−100
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(VDS = VGS, ID = −250 Adc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = −5.0 Vdc, ID = −12.5 Adc)
(VGS = −5.0 Vdc, ID = −25 Adc)
(VGS = −4.0 Vdc, ID = −10 Adc)
RDS(on)
V
−1.0
Forward Transconductance
(VDS = −8.0 Vdc, ID = −12.5 Adc)
−1.6
4.0
−2.0
0.051
0.056
0.065
0.072
0.080
0.090
mV/°C
gFS
Mhos
13
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = −25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance
pF
Ciss
900
1260
Coss
290
410
Crss
105
210
td(on)
9.0
20
tr
37
75
td(off)
15
30
tf
16
55
QT
15
20
nC
Q1
3.0
Q2
9.0
Q3
7.0
VSD
−1.0
−0.9
−1.5
V
trr
35
ta
20
tb
14
QRR
0.035
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = −15 Vdc, ID = −25 A,
VGS = −5.0
50V
V,
RG = 1.3 ))
Fall Time
Gate Charge
(VDS = −24 Vdc,
VGS = −5.0
5 0 Vdc
Vdc,
ID = −25 A))
ns
BODY−DRAIN DIODE RATINGS (Note 3)
Diode Forward On−Voltage
(IS = −25 Adc, VGS = 0 V)
(IS = −25 Adc, VGS = 0 V, TJ = 125°C)
Reverse Recovery Time
(IS = −25 A, VGS = 0 V,
dIS/dt = 100 A/s)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
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2
ns
C
NTD25P03L
TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
50
8V
7V
30
4.5 V
4V
20
3.5 V
10
3V
2.5 V
0
0
1
3
2
TJ = 25°C
40
TJ = 125°C
30
20
10
0
1
2
4
3
5
6
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
VGS = −5 V
0.25
0.2
0.15
T = 125°C
0.1
T = 25°C
0.05
T = −40°C
0
TJ = −40°C
VDS ≥ −5 V
5
4
0.3
0
10
5
15
20
25
30
35
40
45
50
0.01
TJ = 25°C
0.075
VGS = −5 V
0.05
VGS = −10 V
0.025
0
0
5
10
15
20
25
30
35
40
45
50
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10,000
1.6
1.4
VGS = 0 V
ID = −12.5
VGS = −5 V
−IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
−ID, DRAIN CURRENT (AMPS)
5V
6V
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
−ID, DRAIN CURRENT (AMPS)
9V
40
50
TJ = 25°C
VGS = 10 V
1.2
1
TJ = 150°C
1000
TJ = 125°C
100
0.8
0.6
−50
10
−25
0
25
50
75
100
125
150
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
30
NTD25P03L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
2200
Ciss
C, CAPACITANCE (pF)
2000
TJ = 25°C
1800
1600
1400
1200
Crss
Ciss
1000
800
600
Coss
400
200
0
VDS = 0 V
10
Crss
VGS = 0 V
5
0
5
10
15
20
−VGS
−VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
25
QT
−VDS
8
25
20
6
−VGS
Q2
Q1
4
15
10
2
0
ID = −25 A
TJ = 25°C
5
Q3
0
2.5
0
5
7.5
10
12.5
15
Qg, TOTAL GATE CHARGE (nC)
1000
VDD = −15 V
ID = −25 A
VGS = −5.0 V
TJ = 25°C
t, TIME (ns)
30
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTD25P03L
tr
100
tf
td(off)
td(on)
10
1
1
10
100
RG, GATE RESISTANCE ()
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
−IS, SOURCE CURRENT (AMPS)
25
VGS = 0 V
TJ = 25°C
20
15
10
5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1.1
Figure 10. Diode Forward Voltage versus Current
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NTD25P03L
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 s. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
VGS = −20 V
SINGLE PULSE
TC = 25°C
100 s
10
1 ms
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
−ID, DRAIN CURRENT (AMPS)
100
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
200
180
ID = −20 A
160
140
120
100
80
60
40
20
0
25
50
75
100
125
150
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
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NTD25P03L
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
TYPICAL ELECTRICAL CHARACTERISTICS
1
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
RJC(t) = r(t) RJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RJC(t)
0.02
0.01
t1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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1.0E+00
1.0E+01
NTD25P03L
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
−T−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
C
B
V
SEATING
PLANE
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
NTD25P03L
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE O
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
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MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
NTD25P03L
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NTD25P03L/D