TI1 M38510/65705B2A Octal buffers and line drivers with 3-state output Datasheet

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SN54HC244, SN74HC244
SCLS130E – DECEMBER 1982 – REVISED MAY 2016
SNx4HC244 Octal Buffers and Line Drivers With 3-State Outputs
1 Features
3 Description
•
•
The SNx4HC244 octal buffers and line drivers are
designed specifically to improve both the
performance and density of 3-state memory address
drivers, clock drivers, and bus-oriented receivers and
transmitters. The SNx4HC244 devices are organized
as two 4-bit buffers and drivers with separate outputenable (OE) inputs. When OE is low, the device
passes noninverted data from the A inputs to the Y
outputs. When OE is high, the outputs are in the
high-impedance state.
1
•
•
•
•
•
•
Wide Operating Voltage Range of 2 V to 6 V
High-Current Outputs Drive Up to 15 LSTTL
Loads
3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
Low Power Consumption: ICC, 80-µA (Maximum)
Typical tpd = 11 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA (Maximum)
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
2 Applications
•
•
•
•
•
•
Servers
LED Displays
Network Switches
Telecom Infrastructure
Motor Drivers
I/O Expanders
Device Information(1)
PART NUMBER
PACKAGE (PINS)
BODY SIZE (NOM)
CDIP (20)
6.92 mm × 24.38 mm
CFP (20)
6.92 mm × 13.72 mm
LCCC (20)
8.89 mm × 8.89 mm
SN74HC244DB
SSOP (20)
5.30 mm × 7.25 mm
SN74HC244DW
SOIC (20)
7.50 mm × 12.80 mm
SN74HC244N
PDIP (20)
6.30 mm × 25.40 mm
SN74HC244NS
SOP (20)
5.30 mm × 12.60 mm
SN74HC244PW
TSSOP (20)
4.40 mm × 6.50 mm
SN54HC244
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2OE 19
1OE 1
2
18 1Y1
2A1
4
16 1Y1
2A2
6
14 1Y1
2A3
8
12 1Y4
2A4
1A1
1A2
1A3
1A4
11
9 1Y1
13
7 1Y1
15
5 1Y1
17
3 1Y4
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC244, SN74HC244
SCLS130E – DECEMBER 1982 – REVISED MAY 2016
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
4
4
4
5
5
5
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Electrical Characteristics – SN54HC244 ..................
Electrical Characteristics – SN74HC244 ..................
Switching Characteristics ..........................................
Switching Characteristics – CL = 50 pF ....................
Switching Characteristics – CL = 150 pF ................
Typical Characteristic..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview ................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes .......................................
11
11
11
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2003) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added Military Disclaimer to Features section ....................................................................................................................... 1
•
Added Applications section .................................................................................................................................................... 1
•
Removed Ordering Information table ..................................................................................................................................... 1
•
Added Device Information table ............................................................................................................................................. 1
2
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SCLS130E – DECEMBER 1982 – REVISED MAY 2016
5 Pin Configuration and Functions
DB, DW, J, N, NS, PW, W Package
20-Pin SSOP, SOIC, CDIP, PDIP, SOP, TSSOP, or CFP
Top View
1Y2
1A3
6
15
2A3
2Y2
7
14
1Y3
1A4
8
13
2A2
2Y1
9
12
1Y4
GND
10
11
2A1
2OE
16
19
5
4
18
1Y1
2Y3
5
17
2A4
1A3
6
16
1Y2
2Y2
7
15
2A3
1A4
8
14
1Y3
13
2Y3
1A2
2A2
2A4
VCC
17
20
4
12
1A2
1Y4
1Y1
1OE
18
1
3
11
2Y4
2A1
2OE
1A1
19
2
2
10
1A1
GND
VCC
2Y4
20
9
1
2Y1
1OE
3
FK Package
20-Pin LCCC
Top View
Pin Functions
PIN
NO.
NAME
1
1OE
2
3
I/O
DESCRIPTION
I
Output Enable
1A1
I
Input
2Y4
O
Output
4
1A2
I
Input
5
2Y3
O
Output
6
1A3
I
Input
7
2Y2
O
Output
8
1A4
I
Input
9
2Y1
O
Output
10
GND
—
Ground
11
2A1
I
Input
12
1Y4
O
Output
13
2A2
I
Input
14
1Y3
O
Output
15
2A3
I
Input
16
1Y2
O
Output
17
2A4
I
Input
18
1Y1
O
Output
19
2OE
I
Output Enable
20
VCC
—
Power Pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range, VCC
MIN
MAX
UNIT
–0.5
7
V
(2)
Input clamp current, IIK
VI < 0 or VI > VCC
±20
mA
Output clamp current, IOK
VO < 0 or VO > VCC (2)
±20
mA
Continuous output current, IO
VO = 0 or VCC
±35
mA
Continuous current through VCC or GND
±70
mA
Junction Temperature, TJ
150
°C
150
°C
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
SN74HC244
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
NOM
MAX
2
5
6
VCC = 4.5 V
3.15
V
4.2
VCC = 2 V
Low-level input voltage
0.5
VCC = 4.5 V
1.35
VCC = 6 V
VI
Input voltage
VO
Output voltage
Cpd
TA
(1)
4
Input transition rise and fall time
0
0
VCC
V
VCC
V
1000
VCC = 4.5 V
500
VCC = 6 V
400
Power dissipation capacitance per buffer or driver (no load)
Operating free-air temperature
V
1.8
VCC = 2 V
Δt/Δv
V
1.5
VCC = 6 V
VIL
UNIT
35
ns/V
pF
SN54HC244
–55
125
SN74HC244
–40
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the Texas Instruments application
report, Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN54HC244, SN74HC244
THERMAL METRIC (1)
DB (SSOP)
DW (SOIC)
N (PDIP)
NS (SOP)
PW (TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal
resistance
89.5
76.8
44.9
71.9
97.5
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
50.9
42.2
30.9
38.2
32.6
°C/W
RθJB
Junction-to-board thermal resistance
44.6
44.6
25.8
39.3
48.4
°C/W
ψJT
Junction-to-top characterization
parameter
17
15.6
16.4
14.9
1.7
°C/W
ψJB
Junction-to-board characterization
parameter
44.2
44.1
25.7
39
47.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
TYP
1.9
1.998
VCC = 4.5 V
4.4
4.499
5.9
5.999
IOH = –6 mA, VCC = 4.5 V
VCC = 6 V
3.98
4.3
IOH = –7.8 mA, VCC = 6 V
5.48
5.8
MAX
UNIT
V
VCC = 2 V
0.002
0.1
VCC = 4.5 V
0.001
0.1
VCC = 6 V
0.001
0.1
IOL = 6 mA, VCC = 4.5 V
0.17
0.26
IOL = 7.8 mA, VCC = 6 V
0.15
0.26
±0.1
±100
nA
±0.01
±0.5
µA
8
µA
3
10
pF
TYP
MAX
IOL = 20 µA
VOL
MIN
VCC = 2 V
VI = VIH or VIL
II
VI = VCC or 0, VCC = 6 V
IOZ
VO = VCC or 0, VI = VIH or VIL, VCC = 6 V
ICC
VI = VCC or 0, IO = 0, VCC = 6 V
Ci
VCC = 2 V to 6 V
V
6.6 Electrical Characteristics – SN54HC244
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
MIN
VCC = 2 V
1.9
VCC = 4.5 V
4.4
VCC = 6 V
5.9
IOH = –6 mA, VCC = 4.5 V
IOL = 20 µA
VI = VIH or VIL
5.2
VCC = 2 V
0.1
VCC = 4.5 V
0.1
VCC = 6 V
0.1
IOL = 6 mA, VCC = 4.5 V
IOL = 7.8 mA, VCC = 6 V
II
VI = VCC or 0, VCC = 6 V
IOZ
V
3.7
IOH = –7.8 mA, VCC = 6 V
VOL
UNIT
V
0.4
0.4
±1000
nA
VO = VCC or 0, VI = VIH or VIL, VCC = 6 V
±10
µA
ICC
VI = VCC or 0, IO = 0, VCC = 6 V
160
µA
Ci
VCC = 2 V to 6 V
10
pF
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6.7 Electrical Characteristics – SN74HC244
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
MIN
VCC = 2 V
1.9
VCC = 4.5 V
4.4
VCC = 6 V
IOH = –6 mA, VCC = 4.5 V
VOL
VI = VIH or VIL
MAX
5.9
UNIT
V
3.84
IOH = –7.8 mA, VCC = 6 V
IOL = 20 µA
TYP
5.34
VCC = 2 V
0.1
VCC = 4.5 V
0.1
VCC = 6 V
0.1
IOL = 6 mA, VCC = 4.5 V
0.33
IOL = 7.8 mA, VCC = 6 V
0.33
V
II
VI = VCC or 0, VCC = 6 V
±1000
nA
IOZ
VO = VCC or 0, VI = VIH or VIL, VCC = 6 V
±5
µA
ICC
VI = VCC or 0, IO = 0, VCC = 6 V
80
µA
Ci
VCC = 2 V to 6 V
10
pF
6.8 Switching Characteristics
TA = 25°C (unless otherwise noted; see Figure 2)
PARAMETER
TEST CONDITIONS
VCC = 2 V
tpd
From A (input) to Y (output)
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
ten
From OE (input) to Y (output)
VCC = 4.5 V
VCC = 6 V
tdis
From OE (input) to Y (output)
To Y (output)
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MAX
40
115
CL = 150 pF
56
165
CL = 50 pF
13
23
CL = 150 pF
18
33
CL = 50 pF
11
20
CL = 150 pF
15
28
CL = 50 pF
75
150
CL = 150 pF
100
200
CL = 50 pF
15
30
CL = 150 pF
20
40
CL = 50 pF
13
26
CL = 150 pF
17
34
CL = 50 pF
75
150
VCC = 4.5 V
CL = 50 pF
15
30
VCC = 6 V
CL = 50 pF
13
26
CL = 50 pF
28
60
CL = 150 pF
45
210
CL = 50 pF
8
12
CL = 150 pF
17
42
CL = 50 pF
6
10
CL = 150 pF
13
36
VCC = 4.5 V
VCC = 6 V
6
MIN
VCC = 2 V
VCC = 2 V
tt
TYP
CL = 50 pF
UNIT
ns
ns
ns
ns
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6.9 Switching Characteristics – CL = 50 pF
over recommended operating free-air temperature range (unless otherwise noted; see Figure 2)
PARAMETER
TEST CONDITIONS
VCC = 2 V
tpd
From A (input) to Y (output)
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
ten
From OE (input) to Y (output)
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
tdis
From OE (input) to Y (output)
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
tt
To Y (output)
VCC = 4.5 V
VCC = 6 V
MIN
TYP
MAX
SN54HC244
170
SN74HC244
145
SN54HC244
34
SN74HC244
29
SN54HC244
29
SN74HC244
25
SN54HC244
225
SN74HC244
190
SN54HC244
45
SN74HC244
38
SN54HC244
38
SN74HC244
32
SN54HC244
225
SN74HC244
190
SN54HC244
45
SN74HC244
38
SN54HC244
38
SN74HC244
32
SN54HC244
90
SN74HC244
75
SN54HC244
18
SN74HC244
15
SN54HC244
15
SN74HC244
13
UNIT
ns
ns
ns
ns
6.10 Switching Characteristics – CL = 150 pF
over recommended operating free-air temperature range (unless otherwise noted; see Figure 2)
PARAMETER
TEST CONDITIONS
VCC = 2 V
tpd
From A (input) to Y (output)
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
ten
From OE (input) to Y (output)
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
tt
To Y (output)
VCC = 4.5 V
VCC = 6 V
MIN
TYP
MAX
SN54HC244
245
SN74HC244
210
SN54HC244
49
SN74HC244
42
SN54HC244
42
SN74HC244
35
SN54HC244
300
SN74HC244
250
SN54HC244
60
SN74HC244
50
SN54HC244
51
SN74HC244
43
SN54HC244
315
SN74HC244
265
SN54HC244
63
SN74HC244
53
SN54HC244
53
SN74HC244
45
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UNIT
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ns
ns
ns
7
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6.11 Typical Characteristic
60
50
tpd (ns)
40
30
20
10
CL 50pF
CL 150pF
0
2
3
4
5
6
VCC (V)
C001
Figure 1. Propagation Delay
8
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7 Parameter Measurement Information
VCC
Test
Point
From Output
Under Test
S1
RL
CL
(see Note A)
S2
Figure 2. Load Circuit
VCC
Input
50%
50%
0V
tPLH
In-Phase
Output
tPHL
50%
10%
90%
VOH
50%
10% V
OL
tf
90%
tr
tPHL
tPLH
90%
Out-of-Phase
Output
50%
10%
90%
50%
10%
VOH
VOL
tf
tr
Figure 3. Propagation Delay and
Output Transition Times
Input
50%
10%
90%
90%
VCC
50%
10% 0 V
tr
tf
Figure 4. Input Rise and Fall Times
Output
Control
(Low-Level
Enabling)
VCC
50%
50%
0V
tPZL
Output
Waveform 1
(See Note B)
tPLZ
10%
tPZH
Output
Waveform 2
(See Note B)
≈VCC
≈VCC
50%
VOL
tPHZ
50%
90%
VOH
≈0 V
Figure 5. Enable and Disable Times
for 3-State Outputs
NOTE:
A. CL includes probe and test-fixture capacitance.
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Parameter Measurement Information (continued)
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by
the output control. Waveform 2 is for an output with internal conditions such that the output is high except
when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by
generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Table 1. Switching Information Table
PARAMETER
ten
tdis
RL
CL
S1
S2
tPZH
1 kΩ
50 pF or 150 pF
Open
Closed
tPZL
1 kΩ
50 pF or 150 pF
Closed
Open
tPHZ
1 kΩ
50 pF
Open
Closed
tPLZ
1 kΩ
50 pF
Closed
Open
—
50 pF or 150 pF
Open
Open
tpd or tt
10
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8 Detailed Description
8.1 Overview
The SNx4HC244 device is organized as two 4-bit buffers and line drivers with separate output-enable (OE)
inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs
are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the currentsinking capability of the driver.
8.2 Functional Block Diagram
2OE 19
1OE 1
2
18 1Y1
2A1
4
16 1Y1
2A2
6
14 1Y1
2A3
8
12 1Y4
2A4
1A1
1A2
1A3
1A4
11
9 1Y1
13
7 1Y1
15
5 1Y1
17
3 1Y4
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8.3 Feature Description
The SNx4HC244 has a wide operating voltage of 2 V to 6 V. Inputs accept voltage levels up to VCC. This device
has a low power consumption of ICC 80 µA (maximum). The SNx4HC244 device can drive ±6 mA at VCC of 5 V.
8.4 Device Functional Modes
Table 2 lists the functions of the SNx4HC244.
Table 2. Function Table
(Each Buffer or Driver)
INPUTS
OUTPUT
OE
A
Y
L
H
H
L
L
L
H
X
Z
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
SN74HC244 is a high-drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern.
9.2 Typical Application
Regulated 3V
SN74HC244
1OE
x
x
x
MCU or
System
Logic
A1
x
x
x
A4
VCC
Y1
x
x
x
Y4
MCU System
Logic LEDS
x
x
x
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 6. SN74HC244 Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads so
routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/ΔV in Recommended Operating Conditions.
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
2. Recommend output conditions:
– Load currents should not exceed IO max per output and should not exceed the continuous current through
VCC or GND total current for the part. These limits are located in Absolute Maximum Ratings.
– Outputs should not be pulled above VCC.
12
Submit Documentation Feedback
Copyright © 1982–2016, Texas Instruments Incorporated
Product Folder Links: SN54HC244 SN74HC244
SN54HC244, SN74HC244
www.ti.com
SCLS130E – DECEMBER 1982 – REVISED MAY 2016
Typical Application (continued)
9.2.3 Application Curve
100
90
80
ten (ns)
70
60
50
40
30
20
10
CL 50pF
CL 150pF
0
2
3
4
5
VCC (V)
6
C002
Figure 7. Enable Time
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recomments a 0.1-μF capacitor. If there are multiple VCC terminals, then TI recommends 0.01-μF or
0.022-μF capacitors for each power terminal. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The
bypass capacitor should be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input and gate are used, or
when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 8 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC
Input
Unused Input
Output
Unused Input
Output
Input
Figure 8. Layout Diagram
Copyright © 1982–2016, Texas Instruments Incorporated
Product Folder Links: SN54HC244 SN74HC244
Submit Documentation Feedback
13
SN54HC244, SN74HC244
SCLS130E – DECEMBER 1982 – REVISED MAY 2016
www.ti.com
12 Device and Documentation Support
12.1 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HC244
Click here
Click here
Click here
Click here
Click here
SN74HC244
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
Submit Documentation Feedback
Copyright © 1982–2016, Texas Instruments Incorporated
Product Folder Links: SN54HC244 SN74HC244
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-8409601VRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8409601VR
A
SNV54HC244J
5962-8409601VSA
ACTIVE
CFP
W
20
25
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8409601VS
A
SNV54HC244W
84096012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84096012A
SNJ54HC
244FK
8409601RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409601RA
SNJ54HC244J
8409601SA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409601SA
SNJ54HC244W
JM38510/65705B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
65705B2A
JM38510/65705BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65705BRA
JM38510/65705BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65705BSA
M38510/65705B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
65705B2A
M38510/65705BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65705BRA
M38510/65705BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65705BSA
SN54HC244J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54HC244J
SN74HC244ADBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
-40 to 85
SN74HC244APWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
-40 to 85
SN74HC244DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
-40 to 85
SN74HC244DBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244DBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HC244DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244DWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244DWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC244N
SN74HC244N3
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
-40 to 85
SN74HC244NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC244N
SN74HC244NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244NSRG4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244PWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
-40 to 85
SN74HC244PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244PWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244PWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
SN74HC244PWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC244
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HC244QDWRG4Q1
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HC244Q
SNJ54HC244FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84096012A
SNJ54HC
244FK
SNJ54HC244J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409601RA
SNJ54HC244J
SNJ54HC244W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
8409601SA
SNJ54HC244W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC244, SN54HC244-SP, SN74HC244 :
• Catalog: SN74HC244, SN54HC244
• Automotive: SN74HC244-Q1, SN74HC244-Q1
• Enhanced Product: SN74HC244-EP, SN74HC244-EP
• Military: SN54HC244
• Space: SN54HC244-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74HC244DBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
SN74HC244DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74HC244DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74HC244DWRG4
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74HC244DWRG4
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74HC244NSR
SO
NS
20
2000
330.0
24.4
9.0
13.0
2.4
4.0
24.0
Q1
SN74HC244PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74HC244PWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74HC244QDWRG4Q1
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HC244DBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74HC244DWR
SOIC
DW
20
2000
600.0
144.0
84.0
SN74HC244DWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74HC244DWRG4
SOIC
DW
20
2000
367.0
367.0
45.0
SN74HC244DWRG4
SOIC
DW
20
2000
367.0
367.0
45.0
SN74HC244NSR
SO
NS
20
2000
367.0
367.0
45.0
SN74HC244PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74HC244PWT
TSSOP
PW
20
250
367.0
367.0
38.0
SN74HC244QDWRG4Q1
SOIC
DW
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
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