D2 PA K BUK9675-100A N-channel TrenchMOS logic level FET 18 August 2015 Product data sheet 1. General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. 2. Features and benefits • • AEC Q101 compliant Low conduction losses due to low on-state resistance 3. Applications • Automotive and general purpose power switching 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 100 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - - 23 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 98 W VGS = 10 V; ID = 10 A; Tj = 25 °C; - 55 72 mΩ - 60 75 mΩ - - 100 mJ Static characteristics RDSon drain-source on-state resistance Fig. 12 VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 12 Avalanche ruggedness EDS(AL)S non-repetitive drainsource avalanche energy [1] [2] ID = 23 A; Vsup ≤ 100 V; RGS = 50 Ω; [1][2] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. Scan or click this QR code to view the latest information for this product BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D drain 3 S source mb D mounting base; connected to drain Graphic symbol mb D G mbb076 2 1 S 3 D2PAK (SOT404) 6. Ordering information Table 3. Ordering information Type number Package BUK9675-100A Name Description Version D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT404 7. Marking Table 4. Marking codes Type number Marking code BUK9675-100A BUK9675-100A 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V VDGR drain-gate voltage RGS = 20 kΩ - 100 V VGS gate-source voltage -15 15 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 98 W ID drain current Tmb = 100 °C; VGS = 5 V; Fig. 2 - 16 A Tmb = 25 °C; VGS = 5 V; Fig. 2 - 23 A Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 3 - 92 A IDM peak drain current Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C BUK9675-100A Product data sheet All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 2 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Max Unit Source-drain diode IS source current Tmb = 25 °C - 23 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 92 A - 100 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 23 A; Vsup ≤ 100 V; RGS = 50 Ω; [1][2] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 [1] [2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 03aa16 120 ID (A) Pder (%) aaa-019260 25 20 80 15 10 40 5 0 Fig. 1. 0 50 100 150 Tmb (°C) Normalized total power dissipation as a function of mounting base temperature BUK9675-100A Product data sheet 0 200 0 25 50 75 100 125 150 175 Tmb (°C) 200 VGS ≥ 5V Fig. 2. Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 3 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET 003aaf172 103 IAL (A) IDM (A) 102 RDS(on) = VDS / ID 003aaf188 102 10 (1) tp = 1 µs 10 µs 10 (3) 1 ms D.C. 1 (2) 1 100 µs 10 ms 1 102 10 VDS (V) 10-1 103 Tmb = 25 °C; IDM is single pulse Fig. 3. 10-2 10-3 Safe operating area; continuous and peak drain currents as a function of drain-source voltage 10-2 10-1 1 tAL (ms) 10 (1) Tj (init) = 25°C; (2) Tj (init) = 150°C; (3) Repetitive Avalanche Fig. 4. Avalanche rating; avalanche current as a function of avalanche time 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-mb) thermal resistance from junction to mounting base Rth(j-a) thermal resistance from junction to ambient Minimum footprint; FR4 board Min Typ Max Unit - - 1.5 K/W - 50 - K/W 003aaf173 10 Zth(j-mb) (K/W) 1 10- 1 δ = 0.5 0.2 0.1 0.05 0.02 P δ= 0 10- 2 10- 6 Fig. 5. tp 10- 5 10- 4 10- 3 10- 2 tp T t T 10- 1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration BUK9675-100A Product data sheet All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 4 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 100 - - V ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 89 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 175 °C; 0.5 - - V 1 1.5 2 V - - 2.3 V VDS = 100 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.05 10 µA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 10 A; Tj = 25 °C; - 55 72 mΩ - - 188 mΩ - 61 84 mΩ VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 12 - 60 75 mΩ Static characteristics V(BR)DSS VGS(th) Fig. 10 ID = 1 mA; VDS = VGS; Tj = 25 °C; Fig. 10; Fig. 11 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 10 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 12 VGS = 5 V; ID = 10 A; Tj = 175 °C; Fig. 13 VGS = 4.5 V; ID = 10 A; Tj = 25 °C; Fig. 12 Dynamic characteristics QG(tot) total gate charge ID = 10 A; VDS = 80 V; VGS = 5 V; - 24.3 - nC QGS gate-source charge Fig. 14; Fig. 15 - 3 - nC QGD gate-drain charge - 12.2 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 1278 1704 pF Coss output capacitance Tj = 25 °C; Fig. 16 - 129 155 pF Crss reverse transfer capacitance - 88 120 pF td(on) turn-on delay time VDS = 30 V; RL = 1.2 Ω; VGS = 5 V; - 13 20 ns tr rise time RG(ext) = 10 Ω; Tj = 25 °C - 120 168 ns td(off) turn-off delay time - 58 87 ns tf fall time - 57 86 ns LD internal drain inductance - 4.5 - nH BUK9675-100A Product data sheet from drain lead 6 mm from package to centre of die; Tj = 25 °C All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 5 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter LS internal source inductance Conditions Min Typ Max Unit from upper edge of drain tab to centre of die; Tj = 25 °C - 2.5 - nH from source lead to source bond pad; Tj = 25 °C - 7.5 - nH Source-drain diode VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 17 - 0.85 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 53.7 - ns recovered charge VDS = 30 V; Tj = 25 °C - 126 - nC Qr ID (A) 003aaf174 40 10 V 5V 4V 3.4 V 32 3.2 V 65 24 VGS = 3 V 16 2.8 V 55 2.6 V 50 8 003aaf176 75 RDS(on) (mΩ) 70 3.6 V 60 3 4 5 6 7 8 2.4 V Tj = 25 °C; ID = 25 A 2.2 V 0 0 1 2 3 VDS (V) Fig. 7. 4 Drain-source on-state resistance as a function of gate-source voltage; typical values Tj = 25 °C Fig. 6. 9 10 VGS (V) Output characteristics: drain current as a function of drain-source voltage; typical values 003aaf178 25 ID (A) 20 003aaf179 40 gfs (S) 30 15 20 10 Tj = 175 °C 5 0 0 1 2 Tj = 25 °C 3 VGS (V) 10 0 4 VDS > ID x RDSon Fig. 8. Product data sheet 20 40 VGS (V) 60 VDS > ID x RDSon Transfer characteristics: drain current as a function of gate-source voltage; typical values BUK9675-100A 0 Fig. 9. Forward transconductance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 6 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET 03aa33 2.5 VGS(th) (V) 2 1.5 03aa36 10-1 ID (A) max 10-2 typ 10-3 min max 10-4 min 1 typ 10-5 0.5 0 -60 0 60 120 Tj (° C) 10-6 180 Fig. 10. Gate-source threshold voltage as a function of junction temperature RDSon (mΩ) 2.4 V 2.6 V 2.8 V 2 VGS (V) 3 Fig. 11. Sub-threshold drain current as a function of gate-source voltage 003aaf180 3.0 3V a 2.5 120 3.2 V 3.4 V 3.6 V 3.8 V 4V 5V 100 80 2.0 1.5 1.0 0.5 - 100 60 40 1 Tj = 25 °C; VDS = 5 V 003aaf174 140 0 VGS = 10 V 0 8 16 24 32 ID (A) 40 0 100 Tmb (°C) 200 Fig. 13. Normalized drain-source on-state resistance factor as a function of junction temperature Tj = 25 °C Fig. 12. Drain-source on-state resistance as a function of drain current; typical values BUK9675-100A Product data sheet All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 7 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET VDS VGS (V) ID 003aaf184 10 8 VGS(pl) VDS = 14 V 6 VGS(th) VGS QGS2 QGS1 QGS 80 V 4 2 QGD QG(tot) 003aaa508 0 Fig. 14. Gate charge waveform definitions 0 10 20 30 40 QG (nC) 50 Tj = 25 °C; ID = 10 A Fig. 15. Gate-source voltage as a function of gate charge; typical values 003aaf183 104 C (pF) IS (A) 003aaf185 40 32 103 Ciss 24 Coss 102 16 Crss 10 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz 0 Tj = 25°C Tj = 150°C 8 0 0.2 0.4 0.6 0.8 1 VSD (V) 1.2 VGS = 0 V Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source (diode forward) current as a function of as a function of drain-source voltage; typical source-drain (diode forward) voltage; typical values values BUK9675-100A Product data sheet All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 8 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET 11. Package outline Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 b2 c b e e Q 0 5 mm scale Dimensions (mm are the original dimensions) Unit max nom min mm A A1 b b2 c 4.5 1.40 0.85 1.45 0.64 4.1 1.27 0.60 1.05 0.46 D D1 E 11 1.6 10.3 1.2 9.7 e 2.54 HD Lp Q 15.8 2.9 2.6 14.8 2.1 2.2 sot404_po Outline version References IEC JEDEC JEITA European projection Issue date 06-03-16 13-02-25 SOT404 Fig. 18. Package outline D2PAK (SOT404) BUK9675-100A Product data sheet All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 9 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. Legal information 12.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Definition Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Preview — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 12.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. BUK9675-100A Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 10 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE, MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK9675-100A Product data sheet All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 11 / 12 BUK9675-100A NXP Semiconductors N-channel TrenchMOS logic level FET 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ..................................................... 9 12 12.1 12.2 12.3 12.4 Legal information .................................................10 Data sheet status ............................................... 10 Definitions ...........................................................10 Disclaimers .........................................................10 Trademarks ........................................................ 11 © NXP Semiconductors N.V. 2015. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 18 August 2015 BUK9675-100A Product data sheet All information provided in this document is subject to legal disclaimers. 18 August 2015 © NXP Semiconductors N.V. 2015. All rights reserved 12 / 12