FAST CMOS 18-BIT REGISTER IDT54/74FCT16823AT/BT/CT/ET IDT54/74FCT162823AT/BT/CT/ET Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Common features: – 0.5 MICRON CMOS Technology – High-speed, low-power CMOS replacement for ABT functions – Typical tSK(o) (Output Skew) < 250ps – Low input and output leakage ≤1µA (max.) – ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack – Extended commercial range of -40°C to +85°C – VCC = 5V ±10% • Features for FCT16823AT/BT/CT/ET: – High drive outputs (-32mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” – Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C • Features for FCT162823AT/BT/CT/ET: – Balanced Output Drivers: ±24mA (commercial), ±16mA (military) – Reduced system switching noise – Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25°C The FCT16823AT/BT/CT/ET and FCT162823AT/BT/CT/ ET 18-bit bus interface registers are built using advanced, dual metal CMOS technology. These high-speed, low-power registers with clock enable (xCLKEN) and clear (xCLR) controls are ideal for parity bus interfacing in high-performance synchronous systems. The control inputs are organized to operate the device as two 9-bit registers or one 18-bit register. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16823AT/BT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. The FCT162823AT/BT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times – reducing the need for external series terminating resistors. The FCT162823AT/BT/CT/ET are plug-in replacements for the FCT16823AT/BT/CT/ET and ABT16823 for on-board interface applications. FUNCTIONAL BLOCK DIAGRAM 1OE 2OE 1CLR 2CLR 1CLK 2CLK 1CLKEN 2CLKEN R C D R C D 1Q1 1D1 2Q1 2D1 TO 8 OTHER CHANNELS 2772 drw 01 TO 8 OTHER CHANNELS 2772 drw 02 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. 5.16 AUGUST 1996 DSC-2772/8 1 IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS 1CLR 1 56 1CLK 1CLKEN 1OE 2 55 1CLKEN 54 1D1 1Q1 3 54 1D1 4 53 GND GND 4 53 GND 1Q2 5 52 1D2 1Q2 5 52 1D2 1Q3 6 51 1D3 1Q3 6 51 1D3 VCC 7 50 VCC VCC 7 50 VCC 1Q4 8 49 1D4 1Q4 8 49 1D4 1Q5 9 48 1D5 1Q5 9 48 1D5 1Q6 10 47 1D6 1Q6 10 47 1D6 GND 11 46 GND GND 11 46 GND 1Q7 12 45 1D7 1Q7 12 45 1D7 1Q8 13 44 1D8 1Q8 13 44 1D8 1Q9 14 1D9 1Q9 14 43 1D9 2Q1 15 SO56-1 43 SO56-2 SO56-3 42 2D1 2Q1 15 42 2D1 2Q2 16 41 2D2 2Q2 16 41 2D2 2Q3 17 40 2D3 2Q3 17 40 2D3 GND 18 39 GND GND 18 39 GND 2Q4 19 38 2D4 2Q4 19 38 2D4 2Q5 20 37 2D5 2Q5 20 37 2D5 2Q6 21 36 2D6 2Q6 21 36 2D6 VCC 22 35 VCC VCC 22 35 VCC 2Q7 23 34 2D7 2Q7 23 34 2D7 2Q8 24 33 2D8 2Q8 24 33 2D8 GND 25 32 GND GND 25 32 GND 2Q9 26 31 2D9 2Q9 26 31 2D9 2OE 27 30 2CLKEN 2OE 27 30 2CLKEN 2CLR 28 29 2CLK 2CLR 28 29 2CLK 1CLR 1 56 1CLK 1OE 2 55 1Q1 3 GND SSOP/ TSSOP/TVSOP TOP VIEW E56-1 CERPACK TOP VIEW 2772 drw 03 2772 drw 04 5.16 2 IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTION TABLE(1) PIN DESCRIPTION Data inputs xOE xCLR Inputs xCLKEN xCLK xDx Clock Inputs H X X X X Clock Enable Inputs (Active LOW) L L X X H H X H H L xOE Asynchronous clear Inputs (Active LOW) Output Enable Inputs (Active LOW) L H H xQx 3-State Outputs L H L H Pin Names xDx xCLK xCLKEN xCLR Description 2772 tbl 01 (1) Unit V I OUT mA DC Output Current –60 to +120 Z High Z X L Clear X Q(2) Hold ↑ L Z Load L ↑ H Z L ↑ L L L ↑ H H NOTES: 2772 tbl 02 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 2. Output level before indicated steady-state input conditions were established. ABSOLUTE MAXIMUM RATINGS Symbol Description Max. VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0 GND VTERM(3) Terminal Voltage with Respect to –0.5 to GND VCC +0.5 TSTG Storage Temperature –65 to +150 Outputs xQx Function V °C CAPACITANCE (TA = +25°C, f = 1.0MHz) 2772 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT. Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V Typ. 3.5 VOUT = 0V 3.5 Max. Unit 6.0 pF 8.0 pF 2772 lnk 04 NOTE: 1. This parameter is measured at characterization but not tested. 5.16 3 IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, V CC = 5.0V ± 10% Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level VIL Input LOW Level II H Input HIGH Current (Input pins)(5) Symbol VIH Min. 2.0 Typ.(2) — Max. Guaranteed Logic LOW Level — — 0.8 V VCC = Max. — — ±1 µA — — ±1 — — ±1 — — ±1 — — ±1 VI = VCC Input HIGH Current (I/O pins)(5) II L Input LOW Current (Input pins)(5) VI = GND Input LOW Current (I/O pins)(5) I OZH High Impedance Output Current VCC = Max. VO = 2.7V pins) (5) I OZL (3-State Output VIK Clamp Diode Voltage I OS Short Circuit Current VH Input Hysteresis I CCL I CCH I CCZ Quiescent Power Supply Current VO = 0.5V VCC = Min., IIN = –18mA VCC = Max., VO = GND (3) — VCC = Max., VIN = GND or VCC — Unit V µA — — ±1 — –0.7 –1.2 V –80 –140 –225 mA — 100 — mV — 5 500 µA 2772 lnk 05 OUTPUT DRIVE CHARACTERISTICS FOR FCT16823T Symbol IO Parameter Output Drive Current Test Conditions(1) VCC = Max., VO = 2.5V(3) Min. –50 Typ.(2) Max. — –180 Unit mA VOH Output HIGH Voltage VCC = Min. 2.5 3.5 — V 2.4 3.5 — V 2.0 3.0 — V — 0.2 0.55 V — — ±1 µA I OH = –3mA VIN = VIH or V IL VOL Output LOW Voltage I OFF Input/Output Power Off Leakage(5) VCC = Min. VIN = VIH or V IL VCC = 0V, VIN or V O I OH = –12mA MIL. I OH = –15mA COM'L. I OH = –24mA MIL. I OH = –32mA COM'L.(4) I OL = 48mA MIL. I OL = 64mA COM'L. ≤ 4.5V 2772 lnk 06 OUTPUT DRIVE CHARACTERISTICS FOR FCT162823T Symbol I ODL Parameter Output LOW Current Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) Min. 60 Typ.(2) 115 Max. 200 Unit mA I ODH Output HIGH Current VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) –60 –115 –200 mA VOH Output HIGH Voltage 2.4 3.3 — V VOL Output LOW Voltage VCC = Min. VIN = VIH or V IL VCC = Min. VIN = VIH or V IL — 0.3 0.55 V I OH = –16mA MIL. I OH = –24mA COM'L. I OL = 16mA MIL. I OL = 24mA COM'L. NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is ± 5µA at TA = –55°C. 5.16 2772 lnk 07 4 IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Test Conditions(1) Min. — Typ.(2) 0.5 Max. 1.5 Unit mA VIN = VCC VIN = GND — 75 120 µA/ MHz VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle VIN = VCC VIN = GND — 0.8 1.7 mA xOE = xCLKEN = GND at fi = 5MHz 50% Duty Cycle One Bit Toggling VIN = 3.4V VIN = GND — 1.3 3.2 VCC = Max. Outputs Open fCP= 10MHz 50% Duty Cycle VIN = VCC VIN = GND — 4.2 7.1 (5) xOE = xCLKEN = GND at fi = 2.5MHz 50% Duty Cycle Eighteen Bits Toggling VIN = 3.4V VIN = GND — 9.2 22.1 (5) Symbol ∆ICC Parameter Quiescent Power Supply Current TTL Inputs HIGH ICCD Dynamic Power Supply Current (4) VCC = Max. Outputs Open xOE = xCLKEN = GND One Input Toggling 50% Duty Cycle IC Total Power Supply Current (6) VCC = Max. VIN = 3.4V(3) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 5.16 2772 tbl 08 5 IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT16823AT/162823AT Com'l. Symbol tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tSU Parameter Propagation Delay xCLK to xQx Propagation Delay xCLR to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx tW Set-up Time HIGH or LOW xDx to xCLK Hold Time HIGH or LOW xDx to xCLK Set-up Time HIGH or LOW xCLKEN to xCLK Hold Time HIGH or LOW xCLKEN to xCLK xCLK Pulse Width HIGH or LOW xCLR Pulse Width LOW tREM Recovery Time xCLR to xCLK tH tSU tH tW tSK(o) Output Skew (3) FCT16823BT/162823BT Mil. Com'l. Mil. Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit CL = 50pF RL = 500Ω CL = 300pF(5) RL = 500Ω CL = 50pF RL = 500Ω CL = 50pF RL = 500Ω CL = 300pF(5) RL = 500Ω CL = 5pF(5) RL = 500Ω CL = 50pF RL = 500Ω CL = 50pF RL = 500Ω 1.5 10.0 1.5 11.5 1.5 7.5 1.5 8.5 ns 1.5 20.0 1.5 20.0 1.5 15.0 1.5 16.0 1.5 14.0 1.5 15.0 1.5 9.0 1.5 9.5 ns 1.5 12.0 1.5 13.0 1.5 8.0 1.5 9.0 ns 1.5 23.0 1.5 25.0 1.5 15.0 1.5 16.0 1.5 7.0 1.5 8.0 1.5 6.5 1.5 7.0 1.5 8.0 1.5 9.0 1.5 7.5 1.5 8.0 4.0 — 4.0 — 3.0 — 3.0 — ns 2.0 — 2.0 — 1.5 — 1.5 — ns 4.0 — 4.0 — 3.0 — 3.0 — ns 2.0 — 2.0 — 0 — 0 — ns 7.0 — 7.0 — 6.0 — 6.0 — ns 6.0 — 7.0 — 6.0 — 6.0 — ns 6.0 — 7.0 — 6.0 — 6.0 — ns — 0.5 — 0.5 — 0.5 — 0.5 ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested. 5. This condition is guaranteed but not tested. 5.16 ns 2772 tbl 09 6 IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT16823CT/162823CT Com'l. Symbol tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tSU Parameter Propagation Delay xCLK to xQx Propagation Delay xCLR to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx tW Set-up Time HIGH or LOW xDx to xCLK Hold Time HIGH or LOW xDx to xCLK Set-up Time HIGH or LOW xCLKEN to xCLK Hold Time HIGH or LOW xCLKEN to xCLK xCLK Pulse Width HIGH or LOW xCLR Pulse Width LOW tREM Recovery Time xCLR to xCLK tH tSU tH tW tSK(o) Output Skew (3) Condition(1) Min.(2) CL = 50pF RL = 500Ω CL = 300pF(5) RL = 500Ω CL = 50pF RL = 500Ω CL = 50pF RL = 500Ω CL = 300pF(5) RL = 500Ω CL = 5pF(5) RL = 500Ω CL = 50pF RL = 500Ω CL = 50pF RL = 500Ω 1.5 FCT16823ET/162823ET Mil. Max. Min.(2) 6.0 1.5 1.5 12.5 1.5 Com'l. Max. Min.(2) 7.0 1.5 1.5 13.5 8.0 1.5 1.5 7.0 1.5 Mil. Max. Min.(2) Max. Unit 4.4 — — ns 1.5 8.0 — — 8.5 1.5 4.4 — — ns 1.5 8.0 1.5 4.4 — — ns 12.5 1.5 13.5 1.5 9.0 — — 1.5 6.2 1.5 6.2 1.5 3.6 — — 1.5 6.5 1.5 6.5 1.5 3.6 — — 3.0 — 3.0 — 1.5 — — — ns 1.5 — 1.5 — 0.0 — — — ns 3.0 — 3.0 — 2.5 — — — ns 0 — 0 — 0.0 — — — ns 6.0 — 6.0 — 3.0 (4) — — — ns 6.0 — 6.0 — 3.0 (4) — — — ns 6.0 — 6.0 — 3.0 — — — ns — 0.5 — 0.5 — 0.5 — — ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested. 5. This condition is guaranteed but not tested. 5.16 ns 2772 tbl 10 7 IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS V CC 7.0V 500Ω VIN Open Drain Disable Low Closed Open All Other Tests D.U.T. 50pF RT Switch Enable Low V OUT Pulse Generator Test 2772 lnk 10 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 2772 drw 05 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 2772 drw 07 3V 1.5V 0V tH 2772 drw 06 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V 1.5V CONTROL INPUT tPZL VOH 1.5V VOL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 2772 drw 08 SWITCH OPEN 0V tPLZ 3.5V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V 2772 drw 09 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 5.16 8 IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT FCT XX XXXX Temp. Range Device Type X Package X Process Blank B Commercial MIL-STD-883, Class B PV PA PF E Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1) 16823AT Non-Inverting 18-Bit Register 16823BT 16823CT 16823ET 162823AT 162823BT 162823CT 162823ET 54 74 –55°C to +125°C –40°C to +85°C 2772 drw 10 5.16 9