SILABS C8051F015 25 mips, 32 kb flash, 10-bit adc, 64-pin mixed-signal mcu Datasheet

C8051F015
25 MIPS, 32 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
-
10-Bit ADC
-
±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
-
Memory
-
Two 12-Bit DACs
-
Voltage output
10 µsec settling time
-
16 programmable hysteresis values
Configurable to generate interrupts or reset
-
Internal Voltage Reference
VDD Monitor/Brown-out Detector
-
On-Chip JTAG Debug
-
On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Fully compliant with IEEE 1149.1 specification
32 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
Programmable 16-bit counter/timer array with five capture/compare
modules
4 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Clock Sources
-
Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Package
-
64-pin TQFP (standard lead and lead-free packages)
Ordering Part Numbers
Supply Voltage: 2.7 to 3.6 V
-
2304 bytes data RAM
32 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
Digital Peripherals
Two Comparators
-
Pipelined instruction architecture; executes 70% of Instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler; up to 21 interrupt sources
-
Typical operating current: 12.5 mA at 25 MHz
Multiple power saving sleep and shutdown modes
Lead-free package: C8051F015-GQ
Standard package: C8051F015
Temperature Range: –40 to +85 °C
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
UART
Digital Power
SMBus
SPI Bus
Analog Power
TCK
TMS
TDI
TDO
5-Chnl
PCA
Boundary Scan
JTAG
Logic
Debug HW
Reset
RST
VDD
Monitor
External
Oscillator
Circuit
XTAL1
XTAL2
WDT
System Clock
Internal
Oscillator
VREF
DAC1
(12-Bit)
DAC0
DAC0
(12-Bit)
CP0+
CP0CP1+
CP1-
C
o
r
e
Timers
0,1,2
256 Byte
RAM
Timer 3
2048 Byte
XRAM
Port 0
Latch
Port 1
Latch
Port 2
Latch
SFR Bus
Port 3
Latch
A
M
U
X
Prog
Gain
S
W
I
T
C
H
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
P
3
D
r
v
VREF
DAC1
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
8
0
5
1
32 kB
FLASH
C
R
O
S
S
B
A
R
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
ADC
100 ksps
(10-Bit)
TEMP
SENSOR
CP0
CP1
Precision Mixed Signal
Copyright © 2005 by Silicon Laboratories
5.5.2005
C8051F015
25 MIPS, 32 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)
PARAMETER
CONDITIONS
GLOBAL CHARACTERISTICS
Analog Supply Voltage
Analog Supply Current
Internal REF, ADC, DAC, Comparators all
active
Analog Supply Current with
Internal REF, ADC, DAC, Comparators all
analog sub-systems inactive
disabled
Digital Supply Voltage
Digital Supply Current with
Clock = 25 MHz
CPU active
Clock = 1 MHz
Clock = 32 kHz
Digital Supply Current
Oscillator not running
(shutdown mode)
VDD Data Retention Voltage
RAM remains valid
CPU & DIGITAL I/O
Clock Frequency Range
Port Output High Voltage
IOH = –3 mA, Port I/O push-pull
Port Output Low Voltage
IOL = 8.5 mA
Input High Voltage
Input Low Voltage
SMBus SCL Frequency
SYSCLK = MCU system clock
SPI Bus Clock Frequency
SYSCLK = MCU system clock
A/D CONVERTER
Resolution
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
Throughput Rate
Input Voltage Range
D/A CONVERTERS
Resolution
Integral Nonlinearity
Specified from Data Word 014h to FEBh
Differential Nonlinearity
Guaranteed Monotonic
Offset Error
Data Word = 014h
Output Settling Time
To ½ LSB of full-scale
Output Voltage Swing
COMPARATORS
Supply Current
(each Comparator)
Response Time
| (CP+) – (CP-) | = 100 mV
Input Voltage Range
Input Bias Current
Input Offset Voltage
MIN
TYP
MAX
UNITS
3.6
0.8
V
mA
5
µA
2.7
2.7
12
0.5
20
2
3.6
V
mA
mA
µA
µA
1.5
V
DC
VDD – 0.7
25
0.2 x VDD
SYSCLK/8
SYSCLK/2
MHz
V
V
V
V
MHz
MHz
±1
±1
100
VREF
bits
LSB
LSB
ksps
V
0.6
0.8 x VDD
10
0
12
VREF – 1 LSB
bits
LSB
LSB
LSB
µs
V
(AV+) +0.25
+5
+10
µA
µs
V
nA
mV
±4
±1
±3
10
0
1.5
4
–0.25
–5
–10
0.001
C8051F005DK Development Kit
Package Information
D
D1
MIN NOM MAX
(mm) (mm) (mm)
A
E1
E
-
1.20
A1 0.05
-
0.15
A2 0.95
-
1.05
b
64
PIN 1
DESIGNATOR
1
A2
e
A
b
Precision Mixed Signal
-
0.17 0.22 0.27
D
-
12.00
-
D1
-
10.00
-
e
-
0.50
-
E
-
12.00
-
E1
-
10.00
-
A1
Copyright © 2005 by Silicon Laboratories
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
5.5.2005
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