Sample & Buy Product Folder Technical Documents Support & Community Tools & Software LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 LM5109B-Q1 High Voltage 1-A Peak Half Bridge Gate Driver 1 Features 3 Description • • The LM5109B-Q1 is a cost effective, high voltage gate driver designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half bridge configuration. The floating highside driver is capable of working with rail voltages up to 90 V. The outputs are independently controlled with TTL/CMOS compatible logic input thresholds. The robust level shift technology operates at high speed while consuming low power and providing clean level transitions from the control input logic to the high-side gate driver. Under-voltage lockout is provided on both the low-side and the high-side power rails. The device is available in the thermally enhanced WSON(8) packages. 1 • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results – Device Temperature Grade 1 – Device HBM ESD Classification Level 1C – Device CDM ESD Classification Level C4A Drives Both a High-Side and Low-Side N-Channel MOSFET 1-A Peak Output Current (1.0-A Sink/1.0-A Source) Independent TTL/CMOS Compatible Inputs Bootstrap Supply Voltage to 108-V DC Fast Propagation Times (30 ns Typical) Drives 1000-pF Load with 15-ns Rise and Fall Times Excellent Propagation Delay Matching (2 ns Typical) Supply Rail Under-Voltage Lockout Low Power Consumption Thermally-Enhanced WSON-8 Package Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM5109B-Q1 WSON (8) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • Push-Pull Converters Half and Full Bridge Power Converters Solid State Motor Drives Two Switch Forward Power Converters Simplified Application Diagram DBoot RBoot VIN VCC HB VDD HI HO LM5109 LI HS LOAD LO VSS 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................... 9 7.4 HS Transient Voltages Below Ground .................... 10 7.5 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application ................................................. 11 9 Power Supply Recommendations...................... 16 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (November 2015) to Revision A • 2 Page Changed device from Product Preview to Production Data and released full data sheet...................................................... 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 LM5109B-Q1 www.ti.com SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 5 Pin Configuration and Functions NGT Package 8-Pin WSON Top View VDD 1 8 HB HI 2 7 HO WSON-8 LI 3 6 HS VSS 4 5 LO Pin Functions PIN NO. (2) NAME I/O (1) DESCRIPTION APPLICATIONS INFORMATION 1 VDD P Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor located as close to IC as possible. 2 HI I High side control input The HI input is TTL/CMOS Compatible input thresholds. Unused HI input should be tied to ground and not left open. 3 LI I Low side control input The LI input is TTL/CMOS Compatible input thresholds. Unused LI input should be tied to ground and not left open. 4 VSS G Ground reference All signals are referenced to this ground. Connect to the gate of the low-side N-MOS device. 5 LO O Low side gate driver output 6 HS P High side source connection Connect to the negative terminal of the bootstrap capacitor and to the source of the high-side N-MOS device. 7 HO O High side gate driver output Connect to the gate of the high-side N-MOS device. 8 HB P High side gate driver positive supply rail Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal of the bootstrap capacitor to HS. The bootstrap capacitor should be placed as close to IC as possible. (1) (2) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output For WSON-8 package, it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB and the ground plane should extend out from underneath the package to improve heat dissipation. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 3 LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD to VSS –0.3 18 V HB to HS –0.3 18 V LI or HI to VSS –0.3 VDD + 0.3 V LO to VSS –0.3 VDD + 0.3 V HO to VSS VHS – 0.3 VHB + 0.3 V –5 90 V 108 V HS to VSS (2) HB to VSS Junction temperature –40 150 °C Storage temperature, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the application, the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed –5 V. (2) 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) 1500 Charged-device model (CDM), per AEC Q100-011 750 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VDD HS 8 (1) HB (1) 4 MAX UNIT 14 V –1 90 V VHS+8 VHS+14 HS Slew Rate Junction Temperature NOM –40 V < 50 V/ns 125 °C In the application, the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed –1 V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15 V. For example, if VDD = 10 V, the negative transients at HS must not exceed –5 V. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 LM5109B-Q1 www.ti.com SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 6.4 Thermal Information LM5109B-Q1 THERMAL METRIC (1) NGT (WSON) UNIT 8-PINS RθJA Junction-to-ambient thermal resistance 42.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 34.0 °C/W RθJB Junction-to-board thermal resistance 19.3 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 19.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). 6.5 Electrical Characteristics TJ = 25°C (unless otherwise noted) VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Currents IDD VDD Quiescent Current LI = HI = 0V TJ = 25°C 0.3 TJ = –40°C to 125°C IDDO VDD Operating Current f = 500 kHz 0.6 TJ = 25°C 1.8 TJ = –40°C to 125°C IHB Total HB Quiescent Current LI = HI = 0V 2.9 TJ = 25°C 0.06 TJ = –40°C to 125°C IHBO Total HB Operating Current f = 500 kHz 0.2 TJ = 25°C 1.4 TJ = –40°C to 125°C IHBS HB to VSS Current, Quiescent VHS = VHB = 90V 2.8 TJ = 25°C 0.1 TJ = –40°C to 125°C IHBSO HB to VSS Current, Operating 10 f = 500 kHz 0.5 mA mA mA mA µA mA Input Pins Li and Hi VIL VIH RI Low Level Input Voltage Threshold TJ = 25°C High Level Input Voltage Threshold TJ = 25°C Input Pulldown Resistance TJ = 25°C 1.8 TJ = –40°C to 125°C V 0.8 1.8 TJ = –40°C to 125°C 2.2 200 TJ = –40°C to 125°C 100 500 V kΩ Under Voltage Protection VDDR VDD Rising Threshold VDDR = VDD - VSS TJ = 25°C 6.7 TJ = –40°C to 125°C VDDH VDD Threshold Hysteresis VHBR HB Rising Threshold 7.4 0.5 VHBR = VHB - VHS TJ = 25°C HB Threshold Hysteresis 5.7 V V 6.6 TJ = –40°C to 125°C VHBH 6.0 7.1 0.4 V V LO Gate Driver VOLL VOHL Low-Level Output Voltage High-Level Output Voltage ILO = 100 mA, VOHL = VLO – VSS TJ = 25°C 0.38 TJ = –40°C to 125°C ILO = −100 mA, VOHL = VDD– VLO TJ = 25°C 0.65 0.72 TJ = –40°C to 125°C 1.20 V V IOHL Peak Pullup Current VLO = 0V 1.0 A IOLL Peak Pulldown Current VLO = 12V 1.0 A Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 5 LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Electrical Characteristics (continued) TJ = 25°C (unless otherwise noted) VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HO Gate Driver VOLH VOHH IHO = 100 mA, VOLH = VHO– VHS Low-Level Output Voltage TJ = 25°C 0.38 TJ = –40°C to 125°C IHO = −100 mA, VOHH = VHB– VHO High-Level Output Voltage V 0.65 TJ = 25°C 0.72 TJ = –40°C to 125°C V 1.20 IOHH Peak Pullup Current VHO = 0V 1.0 A IOLH Peak Pulldown Current VHO = 12V 1.0 A 6.6 Switching Characteristics TJ = 25°C (unless otherwise noted) VDD = VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO. PARAMETER tLPHL tHPHL tLPLH tHPLH tMON tMOFF TEST CONDITIONS Lower Turn-Off Propagation Delay (LI Falling to LO Falling) TJ = 25°C Upper Turn-Off Propagation Delay (HI Falling to HO Falling) TJ = 25°C Lower Turn-On Propagation Delay (LI Rising to LO Rising) TJ = 25°C Upper Turn-On Propagation Delay (HI Rising to HO Rising) TJ = 25°C MIN TYP 30 TJ = –40°C to 125°C 56 30 TJ = –40°C to 125°C 56 32 TJ = –40°C to 125°C 56 32 TJ = –40°C to 125°C 56 Delay Matching: Lower Turn-On and Upper TJ = 25°C Turn-Off TJ = –40°C to 125°C 2 Delay Matching: Lower Turn-Off and Upper TJ = 25°C Turn-On TJ = –40°C to 125°C 2 tRC, tFC Either Output Rise/Fall Time tPW Minimum Input Pulse Width that Changes the Output MAX 15 15 CL = 1000 pF UNIT ns ns ns ns ns ns 15 ns 50 ns LI LI HI HI tHPLH tLPLH tHPHL tHPLH LO LO HO HO tMON tMOFF Figure 1. Typical Test Timing Diagram 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 LM5109B-Q1 www.ti.com SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 6.7 Typical Characteristics 100 100 VDD = VHB = 12V CL = 1000 pF VSS = VHS = 0V 10 IHBO (mA) 10 CL = 1000 pF IDDO (mA) CL = 2200 pF CL = 4400 pF CL = 2200 pF CL = 4400 pF 1 1 CL = 0 pF 0.1 CL = 0 pF CL = 470 pF CL = 470 pF 0.01 0.1 1 10 100 1 1000 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) VDD = VHB = 12 V VSS = VHS = 0 V Figure 3. HB Operating Current vs Frequency Figure 2. VDD Operating Current vs Frequency 0.45 2.2 0.40 IDDO 0.35 CL = 0 pF f = 500 kHz 1.8 IDD, IHB (mA) IDDO, IHBO (mA) 2.0 VDD = VHB = 12V 1.6 VSS = VHS = 0V 1.4 IHBO IDDO 0.30 0.25 LI = HI = 0V VDD = VHB = 12V 0.20 VSS = VHS = 0V 0.15 0.10 1.2 IHBO 0.05 0.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) TEMPERATURE (°C) Figure 5. Quiescent Current vs Temperature Figure 4. Operating Current vs Temperature 600 44 CL = 0 pF VDD = VHB VDD = VHB = 12V CURRENT (PA) VSS= VHS = 0V PROPAGATION DELAY (ns) 500 LI = HI = 0V IDD 400 300 200 IHB 100 0 8 10 12 14 16 18 40 tLPHL tHPHL VSS = VHS = 0V 36 turn off 32 tHPLH 28 24 tLPLH turn on 20 -40 -25 -10 5 20 35 50 65 80 95 110 125 VDD, VHB (V) TEMPERATURE (oC) Figure 6. Quiescent Current vs Voltage Figure 7. Propagation Delay vs Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 7 LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Typical Characteristics (continued) 0.6 1.6 Output Current : -100 mA VSS = VHS = 0V Output Current : -100 mA 1.4 VSS = VHS = 0V 0.5 1.2 VDD = VHB = 8V 1.0 VOL (V) VOH (V) VDD = VHB = 8V 0.8 0.4 VDD = VHB = 12V 0.6 VDD = VHB = 12V 0.4 0.2 0.3 VDD = VHB = 16V VDD = VHB = 16V 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. LO and HO High Level Output Voltage vs Temperature THRESHOLD (V) 6.9 0.50 VDDR = VDD - VSS 0.48 VHBR = VHB - VHS 0.46 HYSTERESIS (V) 7.0 Figure 9. LO and HO Low Level Output Voltage vs Temperature 6.8 VDDR 6.7 VHBR 6.6 VDDH 0.44 0.42 0.40 0.38 VHBH 0.36 6.5 0.34 6.4 0.32 0.30 -40 -25 -10 5 20 35 50 65 80 95 110 125 6.3 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (oC) TEMPERATURE (oC) Figure 10. Undervoltage Rising Thresholds vs Temperature Figure 11. Undervoltage Hysteresis vs Temperature 1.92 VDD = 12V 1.95 INPUT THRESHOLD VOLTAGE (V) INPUT THRESHOLD VOLTAGE (V) 2.00 VSS = 0V Rising 1.90 1.85 Falling 1.80 1.75 1.91 1.89 1.88 1.87 1.86 1.85 Falling 1.84 1.83 1.82 1.81 1.70 1.80 8 -40 -25 -10 5 20 35 50 65 80 95 110 125 9 10 11 12 13 14 15 16 VDD (V) TEMPERATURE (oC) Figure 12. Input Thresholds vs Temperature 8 Rising 1.90 Figure 13. Input Thresholds vs Supply Voltage Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 LM5109B-Q1 www.ti.com SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 7 Detailed Description 7.1 Overview The LM5109B-Q1 is a cost-effective, high voltage gate driver designed to drive both the high-side and the lowside N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with TTL/CMOS compatible input thresholds. The floating high-side driver is capable of working with HB voltage up to 108 V. An external high voltage diode must be provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Under-voltage lockout (UVLO) is provided on both the low side and the high side power rails. 7.2 Functional Block Diagram VDD HV HB UVLO Level Shift Driver HO HS HI VDD UVLO Driver LO LI VSS 7.3 Feature Description 7.3.1 Start-up and UVLO Both top and bottom drivers include UVLO protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each output until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering during supply voltage variations. When the supply voltage is applied to the VDD pin of the LM5109B-Q1, the top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.7 V. Any UVLO condition on the bootstrap capacitor (VHB–HS) will only disable the high- side output (HO). Table 1. VDD UVLO Feature Logic Operation Condition (VHB-HS>VHBR for all case below) HI LI HO LO VDD-VSS < VDDR during device start-up H L L L VDD-VSS < VDDR during device start-up L H L L VDD-VSS < VDDR during device start-up H H L L VDD-VSS < VDDR during device start-up L L L L VDD-VSS < VDDR – VDDH after device start-up H L L L VDD-VSS < VDDR – VDDH after device start-up L H L L VDD-VSS < VDDR – VDDH after device start-up H H L L VDD-VSS < VDDR – VDDH after device start-up L L L L Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 9 LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Table 2. VHB-HS UVLO Feature Logic Operation Condition (VDD>VDDR for all case below) HI LI HO LO VHB-HS < VHBR during device start-up H L L L VHB-HS < VHBR during device start-up L H L H VHB-HS < VHBR during device start-up H H L H VHB-HS < VHBR during device start-up L L L L VHB-HS < VHBR – VHBH after device start-up H L L L VHB-HS < VHBR – VHBH after device start-up L H L H VHB-HS < VHBR – VHBH after device start-up H H L H VHB-HS < VHBR – VHBH after device start-up L L L L 7.3.2 Level Shift The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and provides excellent delay matching with the low-side driver. 7.3.3 Output Stages The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The lowside output stage is referenced to VSS and the high-side is referenced to HS. 7.4 HS Transient Voltages Below Ground The HS node will always be clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided: 1. HS must always be at a lower potential than HO. Pulling HO more than –0.3 V below HS can activate parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must be placed as close to the IC pins as possible in order to be effective. 2. HB to HS operating voltage should be 15 V or less. Hence, if the HS pin transient voltage is –5 V, VDD should be ideally limited to 10 V to keep HB to HS below 15 V. 3. Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the leads of the IC which must be avoided for reliable operation. 7.5 Device Functional Modes The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold, the output stage is dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating. Table 3. INPUT/OUTPUT Logic Table LI HO (1) L L L L L H L H H L H L H H H H Floating Floating L L HI (1) (2) HO is measured with respect to the HS. LO is measured with respect to the VSS. 10 Submit Documentation Feedback LO (2) Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 LM5109B-Q1 www.ti.com SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information To operate fast switching of power MOSFETs at high switching frequencies and to reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller and the gates of the power semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching devices. With the advent of digital power, this situation is often encountered because the PWM signal from the digital controller is often a 3.3 V logic signal which cannot effectively turn on a power switch. Level shift circuit is needed to boost the 3.3 V signal to the gate-drive voltage (such as 12 V) in order to fully turn-on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise (by placing the high-current driver IC physically close to the power switch), driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver. The LM5109B-Q1 is the high voltage gate drivers designed to drive both the high-side and low-side N-Channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit. The floating high side driver is capable of operating with supply voltages up to 90V. This allows for N-Channel MOSFETs control in halfbridge, full-bridge, push-pull, two switch forward and active clamp topologies. The outputs are independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing full and independent flexibility to control ON and OFF state of the output. 8.2 Typical Application VIN VCC RBOOT Anti-parallel Diode (Optional) DBOOT HB VDD VDD Secondary Side Circuit RGATE HO CBOOT 0.1 µF PWM Controller OUT1 HI HS T1 LM5109 RGATE LI OUT2 LO 1.0 µF VSS Figure 14. LM5109B-Q1 Driving MOSFETs in a Half Bridge Converter Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 11 LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com Typical Application (continued) 8.2.1 Design Requirements Table 4. Design Example PARAMETER VALUE Gate Driver LM5109B-Q1 MOSFET CSD19534KCS VDD 10 V QG 17 nC fSW 500 kHz 8.2.2 Detailed Design Procedure 8.2.2.1 Select Bootstrap and VDD Capacitor The bootstrap capacitor must maintain the VHB-HS voltage above the UVLO threshold for normal operation. Calculate the maximum allowable drop across the bootstrap capacitor with Equation 1. 'VHB VDD VDH VHBL 10 V 1 V 6.7 V 2.3 V where • • • VDD = Supply voltage of the gate drive IC; VDH = Bootstrap diode forward voltage drop; VHBL = VHBRmax – VHBH, HB falling threshold; (1) Then, the total charge needed per switching cycle could be estimated by Equation 2. D IHB 0.95 0.2 mA QTotal QG IHBS u Max 17 nC 10 PA u 17.5 nC ¦SW ¦SW 500 kHz 500 kHz where • • • • QG: Total MOSFET gate charge IHBS: HB to VSS Leakage current DMax: Converter maximum duty cycle IHB: HB Quiescent current Therefore, the minimum CBoot should be: QTotal 17.5 nC CBoot 7.6 nF 'VHB 2.3 V (2) (3) In practice, the value of the CBoot capacitor should be greater than calculated to allow for situations where the power stage may skip pulse due to load transients. It is recommended to have enough margins and place the bootstrap capacitor as close to the HB and HS pins as possible. CBoot = 100 nF (4) As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBoot, as shown in Equation 5. CVDD = 1 µF (5) The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be twice that of the maximum VDD considering capacitance tolerances once the devices have a DC bias voltage across them and to ensure long-term reliability. 8.2.2.2 Select External Bootstrap Diode and Its Series Resistor The bootstrap capacitor is charged by the VDD through the external bootstrap diode every cycle when low side MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power dissipation in the bootstrap diode may be significant and the conduction loss also depends on its forward voltage drop. Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver circuit. 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 LM5109B-Q1 www.ti.com SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 For the selection of external bootstrap diodes, please refer to the application note SNVA083A. Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of voltage of VHB-HS during each switching cycle, especially when HS pin have excessive negative transient voltage. RBOOT recommended value is between 2 Ω and 10 Ω depending on diode selection. A current limiting resistor of 2.2 Ω is selected to limit inrush current of bootstrap diode, and the estimated peak current on the DBoot is shown in Equation 6. VDD VDH 10 V 1 V IDBoot(pk) |4A RBoot 2.2 : where • VDH is the Bootstrap diode forward voltage drop (6) 8.2.2.3 Selecting External Gate Driver Resistor External Gate Driver Resistor, RGATE, is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the current coming out of the gate driver. Peak HO pull-up current are calculated by the following equations. VDD VDH 10 V 1 V IOHH RHOH RGate RGFET_Int 1.2 V / 100 mA 4.7 : 2.2 : 0.48 A where • • • • • IOHH – Peak pull-up current; VDH – Bootstrap diode forward voltage drop; RHOH – Gate driver internal HO pull-up resistance, provide by driver datasheet directly or estimated from the testing conditions, i.e. RHOH=VOHH/IHO; RGate – External gate drive resistance; R(GFET_Int) – MOSFET internal gate resistance, provided by transistor datasheet; (7) Similarly, Peak HO pull-down current is shown in Equation 8. VDD VDH IOLH RHOL RGate RGFET_Int where • RHOL is HO pull-down resistance (8) Peak LO pullup current is shown in Equation 9. VDD IOHL RLOH RGate RGFET_Int where • RLOH is LO pull-up resistance. (9) Peak LO pulldown current is shown in Equation 10. VDD IOLL RLOL RGate RFET_Int where • RLOL is LO pull-down resistance (10) For some scenarios, if the applications require fast turn-off, an anti-paralleled diode on RGate could be used to bypass the external gate drive resistor and speed-up turn-off transition. 8.2.2.4 Estimate the Driver Power Loss The total driver IC power dissipation can be estimated through the following components. 1. Static power losses, PQC, due to quiescent current – IDD and IHB; PQC = VDD × IDD + (VDD – VDH) × IHB (11) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 13 LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com 2. Level-shifter losses, PIHBS, due high side leakage current – IHBS; PIHBS = VHB × IHBS × D where • D is high side switch duty cycle (12) 3. Dynamic losses, PQG1&2, due to the FETs gate charge – QG; RGD_R PQG1&2 2 u VDD u QG u ¦SW u RGD_R RGate RGFET_Int where • • • • • QG is total FETs gate charge; fSW is switching frequency; RGD_R is average value of pull-up and pull-down resistor; RGate is external gate drive resistor; RGFET_Int is internal FETs gate resistor; (13) 4. Level-shifter dynamic losses, PLS, during high side switching due to required level-shifter charge on each switching cycle – QP; PLS = VHB × QP × fSW (14) In this example, the estimated gate driver loss in LM5109B-Q1 is shown in Equation 15. PLM5109BQ 10 V u 0.6 mA 9 V u 0.2 mA 72 V u 10 PA u 0.95 2 u 10 u 17 nC u 500 kHz u 12 : 12 : 4.7 : 2.2 : 72 V u 0.5 nC u 500 kHz 0.134 W (15) For a given ambient temperature, the maximum allowable power loss of the IC can be defined as shown in Equation 16. TJ TA PLM5109BQ RTJA where • • • • PLM5109BQ = The total power dissipation of the driver TJ = Junction temperature TA = Ambient temperature RθJA = Junction-to-ambient thermal resistance (16) The thermal metrics for the driver package is summarized in the Thermal Information section of the datasheet. For detailed information regarding the thermal information table, please refer to the Texas Instruments application note entitled Semiconductor and IC Package Thermal Metrics (SPRA953.). 8.2.3 Application Curves Figure 15 and Figure 16 shows the rising/falling time and turn-on/off propagation delay testing waveform in room temperature, and waveform measurement data (see the bottom part of the waveform). Each channel, HI/LI/HO/LO, is labeled and displayed on the left hand of the waveforms. The testing condition: load capacitance is 1 nF, VDD = 12 V, fSW = 500 kHz. HI and LI share one same input from function generator, therefore, besides the propagation delay and rising/falling time, the difference of the propagation delay between HO and LO gives the propagation delay matching data. 14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 LM5109B-Q1 www.ti.com SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 CL = 1 nF VDD = 12 V fSW = 500 kHz Figure 15. Rising Time and Turn-On Propagation Delay CL = 1 nF VDD = 12 V fSW = 500 kHz Figure 16. Falling Time and Turn-Off Propagation Delay Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 15 LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com 9 Power Supply Recommendations The recommended bias supply voltage range for LM5109B-Q1 is from 8 V to 14 V. The lower end of this range is governed by the internal under voltage-lockout (UVLO) protection feature of the VDD supply circuit blocks. The upper-end of this range is driven by the 18-V absolute maximum voltage rating of the VDD. It is recommended to keep a 4-V margin to allow for transient voltage spikes. The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage drop do not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification, the device will shut down. Therefore, while operating at or near the 8-V range, the voltage ripple on the auxiliary power supply output should be smaller than the hysteresis specification of LM5109B-Q1 to avoid triggering device-shutdown. A local bypass capacitor should be placed between the VDD and GND pins. And this capacitor should be located as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. TI recommends using 2 capacitors across VDD and GND: a 100 nF ceramic surface-mount capacitor for high frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to 10 µF, for IC bias requirements. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore, a 22-nF to 220-nF local decoupling capacitor is recommended between the HB and HS pins. 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 LM5109B-Q1 www.ti.com SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 10 Layout 10.1 Layout Guidelines Optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. The following points are emphasized: 1. Low ESR/ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB and HS pins to support high peak currents drawn from VDD and HB during the turn-on of the external MOSFETs. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the source of the high side MOSFET and the drain of the low side MOSFET (synchronous rectifier) must be minimized. 4. Grounding considerations: – The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close as possible to the MOSFETs. – The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. 10.2 Layout Example Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 17 LM5109B-Q1 SNVSAG6A – NOVEMBER 2015 – REVISED DECEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LM5109B-Q1 PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM5109BQNGTRQ1 ACTIVE WSON NGT 8 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5109Q LM5109BQNGTTQ1 ACTIVE WSON NGT 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5109Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM5109B-Q1 : • Catalog: LM5109B NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 MECHANICAL DATA NGT0008A SDC08A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated