ATMEL AT27BV512-70RI 512k (64k x 8) unregulated battery-voltage high-speed otp eprom Datasheet

Features
• Fast Read Access Time – 70 ns
• Dual Voltage Range Operation
•
•
•
•
•
•
•
•
•
– Unregulated Battery Power Supply Range, 2.7V to 3.6V
or Standard 5V ± 10% Supply Range
Pin Compatible with JEDEC Standard AT27C512R
Low Power CMOS Operation
– 20 µA Max (Less than 1 µA Typical) Standby for VCC = 3.6V
– 29 mW Max Active at 5 MHz for VCC = 3.6V
JEDEC Standard Surface Mount Packages
– 32-lead PLCC
– 28-lead SOIC
– 28-lead TSOP
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Rapid Programming Algorithm – 100 µs/Byte (Typical)
CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL and LVBO
Integrated Product Identification Code
Industrial Temperature Range
Green (Pb/Halide-free) Packaging Option
512K (64K x 8)
Unregulated
Battery-Voltage
High-Speed
OTP EPROM
AT27BV512
1. Description
The AT27BV512 is a high-performance, low-power, low-voltage 524,288-bit one-time
programmable read-only memory (OTP EPROM) organized as 64K by 8 bits. It
requires only one supply in the range of 2.7 to 3.6V in normal read mode operation,
making it ideal for fast, portable systems using either regulated or unregulated battery
power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3V supply. At VCC = 2.7V, any byte can be
accessed in less than 70 ns. With a typical power consumption of only 18 mW at
5 MHz and VCC = 3V, the AT27BV512 consumes less than one fifth the power of a
standard 5V EPROM.
Standby mode supply current is typically less than 1 µA at 3V. The AT27BV512 simplifies system design and stretches battery lifetime even further by eliminating the need
for power supply regulation.
The AT27BV512 is available in industry-standard JEDEC-approved one-time
programmable (OTP) plastic PLCC, SOIC, and TSOP packages. All devices feature
two-line control (CE, OE) to give designers the flexibility to prevent bus contention.
The AT27BV512 operating with VCC at 3.0V produces TTL level outputs that are compatible with standard TTL logic devices operating at VCC = 5.0V. At VCC = 2.7V, the
part is compatible with JEDEC approved low voltage battery operation (LVBO) interface specifications. The device is also capable of standard 5-volt operation making it
ideally suited for dual supply range systems or card products that are pluggable in
both 3-volt and 5-volt hosts.
0602E–EPROM–12/07
Atmel’s AT27BV512 has additional features to ensure high quality and efficient production use.
The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated
Product Identification Code electronically identifies the device and manufacturer. This feature
is used by industry-standard programming equipment to select the proper programming algorithms and voltages. The AT27BV512 programs exactly the same way as a standard 5V
AT27C512R and uses the same programming equipment.
2. Pin Configurations
2.1
Function
A0 - A15
Addresses
O0 - O7
Outputs
CE
Chip Enable
OE/VPP
Output Enable/Program Supply
NC
No Connect
2.3
28-lead SOIC Top View
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A13
A8
A9
A11
OE/VPP
A10
CE
O7
O6
O5
O4
O3
28-lead TSOP ( Type 1) Top View
OE/VPP
A11
A9
A8
A13
A14
VCC
A15
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A1
A2
32-lead PLCC Top View
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
A8
A9
A11
NC
OE/VPP
A10
CE
O7
O6
O1
O2
GND
NC
O3
O4
O5
A6
A5
A4
A3
A2
A1
A0
NC
O0
4
3
2
1
32
31
30
A7
A12
A15
NC
VCC
A14
A13
2.2
Pin Name
Note:
2
PLCC package pins 1 and 17 are Don’t Connect.
AT27BV512
0602E–EPROM–12/07
AT27BV512
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high
frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the VCC and Ground terminals of the device, as close
to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the VCC and Ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature ..................................... -65°C to +125°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground ......................................-2.0V to +14.0V(1)
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Notes:
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V DC which may be exceeded if certain precautions are observed (consult application notes) and which may
overshoot to +7.0V for pulses of less than 20 ns.
3
0602E–EPROM–12/07
6. Operating Modes
Mode \ Pin
CE
OE/VPP
Ai
VCC
Outputs
Read
VIL
VIL
Ai
VCC
DOUT
Output Disable(2)
VIL
VIH
X(1)
VCC
High Z
Standby(2)
VIH
X
X
VCC
High Z
(2)
(3)
VIL
VPP
Ai
VCC
DIN
(3)
PGM Verify
VIL
VIL
Ai
VCC
DOUT
PGM Inhibit(3)
VIH
VPP
X
VCC
High Z
VCC
Identification Code
Rapid Program
(4)
Product Identification(3)(5)
Notes:
VIL
VIL
A9 = VH
A0 = VIH or VIL
A1 - A15 = VIL
1. X can be VIL or VIH.
2. Read, output disable, and standby modes require, 2.7V ≤VCC ≤3.6V, or 4.5V ≤VCC ≤5.5V.
3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V.
4. VH = 12.0 ± 0.5V.
5. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7. DC and AC Operating Conditions for Read Operation
AT27BV512-70
Operating Temperature (Case)
-40°C - 85°C
2.7V to 3.6V
VCC Power Supply
4
5V ± 10%
AT27BV512
0602E–EPROM–12/07
AT27BV512
8. DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
Min
Max
Units
VCC = 2.7V to 3.6V
ILI
ILO
IPP1
(2)
Input Load Current
VIN = 0V to VCC
±1
µA
Output Leakage Current
VOUT = 0V to VCC
±5
µA
VPP(1)
VPP = VCC
10
µA
ISB1 (CMOS), CE = VCC ± 0.3V
20
µA
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
100
µA
8
mA
Read/Standby Current
ISB
VCC(1) Standby Current
ICC
VCC Active Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
VOH
Output Low Voltage
Output High Voltage
f = 5 MHz, IOUT = 0 mA, CE = VIL, VCC = 3.6V
VCC = 3.0 to 3.6V
-0.6
0.8
V
VCC = 2.7 to 3.6V
-0.6
0.2 x VCC
V
VCC = 3.0 to 3.6V
2.0
VCC + 0.5
V
VCC = 2.7 to 3.6V
0.7 x VCC
VCC + 0.5
V
IOL = 2.0 mA
0.4
V
IOL = 100 µA
0.2
V
IOL = 20 µA
0.1
V
IOH = -2.0 mA
2.4
V
IOH = -100 µA
VCC - 0.2
V
IOH = -20 µA
VCC - 0.1
V
VCC = 4.5V to 5.5V
ILI
Input Load Current
VIN = 0V to VCC
±1
µA
ILO
Output Leakage Current
VOUT = 0V to VCC
±5
µA
IPP1(2)
VPP(1) Read/Standby Current
VPP = VCC
10
µA
VCC(1) Standby Current
ISB1 (CMOS), CE = VCC ± 0.3V
100
µA
ISB
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
1
mA
ICC
VCC Active Current
f = 5 MHz, IOUT = 0 mA, CE = VIL
20
mA
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = -400 µA
Notes:
2.4
V
1. VCC must be applied simultaneously with or before OE/VPP, and removed simultaneously with or after OE/VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
5
0602E–EPROM–12/07
9. AC Characteristics for Read Operation
VCC = 2.7V to 3.6V and 4.5V to 5.5V
AT27BV512-70
Symbol
Parameter
Condition
tACC(3)
Address to Output Delay
tCE(2)
tOE(2)(3)
tDF(4)(5)
OE/VPP or CE High to Output Float,
Whichever Occurred First
tOH
Output Hold from Address, CE or
OE/VPP, Whichever Occurred First
Min
Max
Units
CE = OE/VPP = VIL
70
ns
CE to Output Delay
OE/VPP = VIL
70
ns
OE/VPP to Output Delay
CE = VIL
50
ns
40
ns
0
ns
10. AC Waveforms for Read Operation(1)
Notes:
1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE/VPP may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE/VPP may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
6. When reading a AT27BV256, a 0.1 µF capacitor is required across VCC and ground to suppress spurious voltage transients.
6
AT27BV512
0602E–EPROM–12/07
AT27BV512
11. Input Test Waveform and Measurement Level
tR, tF < 20 ns (10% to 90%)
12. Output Test Load
Note: CL = 100 pF
including jig capacitance.
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
7
0602E–EPROM–12/07
14. Programming Waveforms(1)
Notes:
1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27BV512, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage
transients.
8
AT27BV512
0602E–EPROM–12/07
AT27BV512
15. DC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, OE/VPP = 13.0 ± 0.25V
Limits
Symbol
Parameter
Test Conditions
ILI
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
VIH
Input High Level
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
ICC2
VCC Supply Current (Program and Verify)
IPP2
OE/VPP Current
VID
A9 Product Identification Voltage
Min
Max
Units
±10
µA
-0.6
0.8
V
2.0
VCC + 0.5
V
0.4
V
2.4
V
25
mA
25
mA
12.5
V
Max
Units
CE = VIL
11.5
16. AC Programming Characteristics
TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, OE/VPP = 13.0 ± 0.25V
Limits
Test Conditions(1)
Min
Symbol
Parameter
tAS
Address Setup Time
2
µs
tOES
OE/VPP Setup Time
2
µs
tOEH
OE/VPP Hold Time
2
µs
tDS
Data Setup Time
2
µs
tAH
Address Hold Time
0
µs
tDH
Data Hold Time
2
µs
Input Rise and Fall Times:
(10% to 90) 20 ns
Input Pulse Levels:
0.45V to 2.4V
(2)
tDFP
CE High to Output Float Delay
tVCS
VCC Setup Time
tPW
CE Program Pulse Width(3)
130
Data Valid from CE
tVR
OE/VPP Recovery Time
tPRT
OE/VPP Pulse Rise Time During
Programming
ns
2
µs
95
Output Timing Reference Level:
0.8V to 2.0V
(2)
tDV
Notes:
0
Input Timing Reference Level:
0.8V to 2.0V
105
µs
1
µs
2
µs
50
ns
1. VCC must be applied simultaneously or before OE/VPP and removed simultaneously or after OE/VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 100 µsec ± 5%.
17. Atmel’s AT27BV512 Integrated Product Identification Code(1)
Pins
A0
O7
O6
O5
O4
O3
O2
O1
O0
Hex
Data
Manufacturer
0
0
0
0
1
1
1
1
0
1E
Device Type
1
0
0
0
0
1
1
0
1
0D
Codes
Note:
1. The AT27BV512 has the same Product Identification Code as the AT27C512R. Both are programming compatible.
9
0602E–EPROM–12/07
18. Rapid Programming Algorithm
A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is
raised to 6.5V and OE/VPP is raised to 13.0V. Each address is first programmed with one
100 µs CE pulse without verification. Then a verification/reprogramming loop is executed for
each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses
are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have
been applied, the part is considered failed. After the byte verifies properly, the next address is
selected until all have been checked. OE/VPP is then lowered to VIL and VCC to 5.0V. All bytes
are read again and compared with the original data to determine if the device passes or fails.
10
AT27BV512
0602E–EPROM–12/07
AT27BV512
19. Ordering Information
19.1
Standard Package
ICC (mA)
tACC
(ns)
Active
Standby
70
8
0.02
Note:
19.2
Package
32J
28R(1)
28T
Operation Range
Industrial
(-40°C to 85°C)
Not recommended for new designs. Use Green package option.
Green Package Option (Pb/Halide-free)
ICC (mA)
tACC
(ns)
Active
Standby
70
8
0.02
Note:
Ordering Code
AT27BV512-70JI
AT27BV512-70RI
AT27BV512-70TI
Ordering Code
Package
AT27BV512-70JU
AT27BV512-70RU
AT27BV512-70TU
32J
28R(1)
28T
Operation Range
Industrial
(-40°C to 85°C)
1. The 28-pin SOIC package is not recommended for new designs.
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28R
28-lead, 0.330" Wide, Plastic Gull Wing Small Package (SOIC)
28T
28-lead, Plastic Thin Small Outline Package (TSOP)
11
0602E–EPROM–12/07
20. Packaging Information
20.1
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
AT27BV512
0602E–EPROM–12/07
AT27BV512
20.2
28R – SOIC
B
E
E1
PIN 1
e
D
A
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 8º
C
L
Note: 1. Dimensions D and E1 do not include mold Flash
or protrusion. Mold Flash or protrusion shall not exceed
0.25 mm (0.010").
SYMBOL
MIN
NOM
MAX
A
2.39
–
2.79
A1
0.050
–
0.356
D
18.00
–
18.50
E
11.70
–
12.50
E1
8.59
–
8.79
B
0.356
–
0.508
C
0.203
–
0.305
L
0.94
–
1.27
e
NOTE
Note 1
Note 1
1.27 TYP
5/18/2004
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28R, 28-lead, 0.330" Body Width,
Plastic Gull Wing Small Outline (SOIC)
DRAWING NO.
REV.
28R
C
13
0602E–EPROM–12/07
20.3
28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.90
1.00
1.05
D
13.20
13.40
13.60
D1
11.70
11.80
11.90
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
NOTE
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
0.55 BASIC
12/06/02
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
28T
C
AT27BV512
0602E–EPROM–12/07
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0602E–EPROM–12/07
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