Cirrus CS5345-DQZR 104 db, 24-bit, 192 khz stereo audio adc Datasheet

CS5345
104 dB, 24-Bit, 192 kHz Stereo Audio ADC
A/D Features
General Description
 Multi-Bit Delta Sigma Modulator
The CS5345 integrates an analog multiplexer, programmable gain amplifier, and stereo audio analog-to-digital
converter. The CS5345 performs stereo analog-to-digital (A/D) conversion of up to 24-bit serial values at
sample rates up to 192 kHz.
 104 dB Dynamic Range
 -95 dB THD+N
 Stereo 6:1 Input Multiplexer
 Programmable Gain Amplifier (PGA)




– ± 12 dB Gain, 0.5 dB Step Size
– Zero Crossing, Click-Free Transitions
Stereo Microphone Inputs
– +32 dB Gain Stage
– Low-Noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
– Left-Justified up to 24-bit
– I²S up to 24-bit
High-Pass Filter or DC Offset Calibration
System Features
 Power-Down Mode
 +3.3 V to +5 V Analog Power Supply, Nominal
 +3.3 V to +5 V Digital Power Supply, Nominal
 Direct Interface with 1.8 V to 5 V Logic Levels
 Pin-Compatible with CS4245
http://www.cirrus.com
Register Configuration
PCM Serial Interface
Serial
Audio
Output
Level Translator
Reset
Level
Translator
Interrupt
Overflow
The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the
serial audio interface at rates from 4 kHz to 192 kHz in
either Slave or Master Mode.
Integrated level translators allow easy interfacing between the CS5345 and other devices operating over a
wide range of logic levels.
The CS5345 is available in a 48-pin LQFP package in
Commercial (-10° to +70° C) and Automotive (-40° to
+105° C) grade. The CDB5345 Customer Demonstration board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 41 for complete details.
3.3 V to 5 V
1.8 V to 5 V
I²C/SPI
Control Data
A 6:1 stereo input multiplexer is included for selecting
between line-level and microphone-level inputs. The
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is available for line or microphone inputs and provides
gain/attenuation of ± 12 dB in 0.5 dB steps.
High Pass
Filter
High Pass
Filter
Low-Latency
Anti-Alias Filter
Low-Latency
Anti-Alias Filter
3.3 V to 5 V
Left PGA Output
Right PGA Output
Internal Voltage
Reference
Stereo Input 1
Stereo Input 2
Stereo Input 3
Multibit
Oversampling
ADC
PGA
Multibit
Oversampling
ADC
PGA
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
MUX
+32 dB
Stereo Input 4 /
Mic Input 1 & 2
+32 dB
Stereo Input 5
Stereo Input 6
AUGUST '07
DS658F2
CS5345
TABLE OF CONTENTS
1. PIN DESCRIPTIONS
......................................................................................................................... 5
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7
SPECIFIED OPERATING CONDITIONS ............................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 7
ADC ANALOG CHARACTERISTICS ................................................................................................... 8
ADC ANALOG CHARACTERISTICS ................................................................................................. 10
ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 11
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 12
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 13
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 14
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 15
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 16
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 17
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 20
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 21
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 22
4. APPLICATIONS ................................................................................................................................... 23
4.1 Recommended Power-Up Sequence ............................................................................................. 23
4.2 System Clocking ............................................................................................................................. 23
4.2.1 Master Clock ......................................................................................................................... 23
4.2.2 Master Mode ......................................................................................................................... 24
4.2.3 Slave Mode ........................................................................................................................... 24
4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 24
4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................ 25
4.5 Input Connections ........................................................................................................................... 25
4.6 PGA Auxiliary Analog Output ......................................................................................................... 25
4.7 Control Port Description and Timing ............................................................................................... 26
4.7.1 SPI Mode ............................................................................................................................... 26
4.7.2 I²C Mode ................................................................................................................................ 26
4.8 Interrupts and Overflow .................................................................................................................. 28
4.9 Reset .............................................................................................................................................. 28
4.10 Synchronization of Multiple Devices ............................................................................................. 28
4.11 Grounding and Power Supply Decoupling .................................................................................... 28
5. REGISTER QUICK REFERENCE ........................................................................................................ 30
6. REGISTER DESCRIPTION .................................................................................................................. 31
6.1 Chip ID - Register 01h .................................................................................................................... 31
6.2 Power Control - Address 02h ......................................................................................................... 31
6.2.1 Freeze (Bit 7) ......................................................................................................................... 31
6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 31
6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 31
6.2.4 Power-Down Device (Bit 0) ................................................................................................... 31
6.3 ADC Control - Address 04h ............................................................................................................ 32
6.3.1 Functional Mode (Bits 7:6) .................................................................................................... 32
6.3.2 Digital Interface Format (Bit 4) .............................................................................................. 32
6.3.3 Mute (Bit 2) ............................................................................................................................ 32
6.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 32
6.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 32
6.4 MCLK Frequency - Address 05h .................................................................................................... 33
6.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 33
6.5 PGAOut Control - Address 06h ...................................................................................................... 33
6.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 33
6.6 Channel B PGA Control - Address 07h .......................................................................................... 33
2
DS658F2
CS5345
6.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 33
6.7 Channel A PGA Control - Address 08h .......................................................................................... 34
6.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 34
6.8 ADC Input Control - Address 09h ................................................................................................... 34
6.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 34
6.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 35
6.9 Active Level Control - Address 0Ch ................................................................................................ 35
6.9.1 Active High/Low (Bit 0) .......................................................................................................... 35
6.10 Interrupt Status - Address 0Dh ..................................................................................................... 35
6.10.1 Clock Error (Bit 3) ................................................................................................................ 36
6.10.2 Overflow (Bit 1) .................................................................................................................... 36
6.10.3 Underflow (Bit 0) .................................................................................................................. 36
6.11 Interrupt Mask - Address 0Eh ....................................................................................................... 36
6.12 Interrupt Mode MSB - Address 0Fh .............................................................................................. 36
6.13 Interrupt Mode LSB - Address 10h ............................................................................................... 36
7. PARAMETER DEFINITIONS ................................................................................................................ 37
8. FILTER PLOTS .................................................................................................................................. 38
9. PACKAGE DIMENSIONS .................................................................................................................... 40
10. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 40
11. ORDERING INFORMATION
........................................................................................................ 41
12. REVISION HISTORY .......................................................................................................................... 41
LIST OF FIGURES
Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 18
Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 18
Figure 3.Format 0, Left-Justified up to 24-Bit Data ................................................................................... 19
Figure 4.Format 1, I²S up to 24-Bit Data ................................................................................................... 19
Figure 5.Control Port Timing - I²C Format ................................................................................................. 20
Figure 6.Control Port Timing - SPI Format ................................................................................................ 21
Figure 7.Typical Connection Diagram ....................................................................................................... 22
Figure 8.Master Mode Clocking ................................................................................................................ 24
Figure 9.Analog Input Architecture ............................................................................................................ 25
Figure 10.Control Port Timing in SPI Mode .............................................................................................. 26
Figure 11.Control Port Timing, I²C Write ................................................................................................... 27
Figure 12.Control Port Timing, I²C Read ................................................................................................... 27
Figure 13.Single-Speed Stopband Rejection ............................................................................................ 38
Figure 14.Single-Speed Stopband Rejection ............................................................................................ 38
Figure 15.Single-Speed Transition Band (Detail) ...................................................................................... 38
Figure 16.Single-Speed Passband Ripple ................................................................................................ 38
Figure 17.Double-Speed Stopband Rejection ........................................................................................... 38
Figure 18.Double-Speed Stopband Rejection ........................................................................................... 38
Figure 19.Double-Speed Transition Band (Detail) .................................................................................... 39
Figure 20.Double-Speed Passband Ripple ............................................................................................... 39
Figure 21.Quad-Speed Stopband Rejection ............................................................................................. 39
Figure 22.Quad-Speed Stopband Rejection ............................................................................................. 39
Figure 23.Quad-Speed Transition Band (Detail) ....................................................................................... 39
Figure 24.Quad-Speed Passband Ripple ................................................................................................. 39
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 23
Table 2. Common Clock Frequencies ....................................................................................................... 23
Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 24
Table 4. Device Revision .......................................................................................................................... 31
DS658F2
3
CS5345
Table 5. Freeze-able Bits .......................................................................................................................... 31
Table 6. Functional Mode Selection .......................................................................................................... 32
Table 7. Digital Interface Formats ............................................................................................................. 32
Table 8. MCLK Frequency ........................................................................................................................ 33
Table 9. PGAOut Source Selection ........................................................................................................... 33
Table 10. Example Gain and Attenuation Settings ................................................................................... 34
Table 11. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 35
Table 12. Analog Input Multiplexer Selection ............................................................................................ 35
4
DS658F2
CS5345
TSTI
NC
NC
NC
SDOUT
SCLK
LRCK
MCLK
DGND
VD
INT
OVFL
1. PIN DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
SDA/CDOUT
1
36
VLS
SCL/CCLK
2
35
TSTO
AD0/CS
3
34
NC
AD1/CDIN
4
33
NC
VLC
5
32
AGND
RESET
6
31
AGND
AIN3A
7
30
VA
AIN3B
8
29
PGAOUTB
AIN2A
9
28
PGAOUTA
AIN2B
10
27
AIN6B
AIN1A
11
26
AIN6A
AIN1B
12
25
MICBIAS
CS5345
AIN5B
AIN5A
AIN4B/MICIN2
AIN4A/MICIN1
TSTO
FILT+
TSTO
VQ
AFILTB
AFILTA
VA
AGND
13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
#
Pin Description
SDA/CDOUT
1
Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode. CDOUT is the output data line for
the control port interface in SPITM Mode.
SCL/CCLK
2
Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0/CS
3
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode;
CS is the chip-select signal for SPI format.
AD1/CDIN
4
Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode;
CDIN is the input data line for the control port interface in SPI Mode.
VLC
5
Control Port Power (Input) - Determines the required signal level for the control port interface. Refer
to the Recommended Operating Conditions for appropriate voltages.
RESET
6
Reset (Input) - The device enters a low-power mode when this pin is driven low.
AIN3A
AIN3B
7
8
Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AIN2A
AIN2B
9
10
Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
DS658F2
5
CS5345
AIN1A
AIN1B
11
12
Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AGND
13
Analog Ground (Input) - Ground reference for the internal analog section.
VA
14
Analog Power (Input) - Positive power for the internal analog section.
AFILTA
15
Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input.
AFILTB
16
Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input.
VQ
17
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
TSTO
18
Test Pin (Output) - This pin must be left unconnected.
FILT+
19
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
TSTO
20
Test Pin - This pin must be left unconnected.
AIN4A/MICIN1
AIN4B/MICIN2
21
22
Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full-scale level is specified in the ADC
Analog Characteristics specification table.
AIN5A
AIN5B
23
24
Stereo Analog Input 5 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
MICBIAS
25
Microphone Bias Supply (Output) - Low-noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics specification table.
AIN6A
AIN6B
26
27
Stereo Analog Input 6 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
PGAOUTA
PGAOUTB
28
29
PGA Analog Audio Output (Output) - Either an analog output from the PGA block or high impedance.
See “PGAOut Source Select (Bit 6)” on page 33.
VA
30
Analog Power (Input) - Positive power for the internal analog section.
AGND
31
32
Analog Ground (Input) - Ground reference for the internal analog section.
NC
33
34
No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
TSTO
35
Test Pin (Output) - This pin must be left unconnected.
VLS
36
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.
TSTI
37
Test Pin (Input) - This pin must be connected to ground.
NC
38,
39,
40
No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
SDOUT
41
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK
42
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK
43
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK
44
Master Clock (Input) - Clock source for the ADC’s delta-sigma modulators.
DGND
45
Digital Ground (Input) - Ground reference for the internal digital section.
VD
46
Digital Power (Input) - Positive power for the internal digital section.
INT
47
Interrupt (Output) - Indicates an interrupt condition has occurred.
OVFL
48
Overflow (Output) - Indicates an ADC overflow condition is present.
6
DS658F2
CS5345
2. CHARACTERISTICS AND SPECIFICATIONS
SPECIFIED OPERATING CONDITIONS
AGND = DGND = 0 V; All voltages with respect to ground.
Parameters
Symbol
Min
Nom
Max
Units
Analog
Digital
Logic - Serial Port
Logic - Control Port
Ambient Operating Temperature (Power Applied)
Commercial
Automotive
VA
VD
VLS
VLC
TA
TA
3.13
3.13
1.71
1.71
-10
-40
5.0
3.3
3.3
3.3
-
5.25
(Note 1)
5.25
5.25
+70
+105
V
V
V
V
°C
°C
DC Power Supplies:
Notes:
1. Maximum of VA+0.25 V or 5.25 V, whichever is less.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V All voltages with respect to ground. (Note 2)
Parameter
DC Power Supplies:
Input Current
Analog
Digital
Logic - Serial Port
Logic - Control Port
(Note 3)
Analog Input Voltage
Symbol
Min
Max
Units
VA
VD
VLS
VLC
Iin
-0.3
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
+6.0
V
V
V
V
-
±10
mA
VINA
AGND-0.3
VA+0.3
V
VIND-S
VIND-C
-0.3
-0.3
VLS+0.3
VLC+0.3
V
V
Ambient Operating Temperature (Power Applied)
TA
-50
+125
°C
Storage Temperature
Tstg
-65
+150
°C
Digital Input Voltage
Logic - Serial Port
Logic - Control Port
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS658F2
7
CS5345
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V
or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to
+85° C for Automotive; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz;
Fs = 48/96/192 kHz.; All connections as shown in Figure 7 on page 22.
Line-Level Inputs
Commercial Grade
Parameter
Symbol
Dynamic Performance for VA = 4.75 V to 5.25 V
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
98
95
-
104
101
98
-
96
93
-
104
101
98
-
dB
dB
dB
92
89
-
98
95
92
-
90
87
-
98
95
92
-
dB
dB
dB
-
-95
-81
-41
-92
-89
-
-
-95
-81
-41
-92
-87
-
dB
dB
dB
dB
-
-92
-75
-35
-89
-86
-
-
-92
-75
-35
-89
-84
-
dB
dB
dB
dB
93
90
-
101
98
95
-
91
88
-
101
98
95
-
dB
dB
dB
89
86
-
95
92
89
-
87
84
-
95
92
89
-
dB
dB
dB
-
-92
-78
-38
-84
-86
-
-
-92
-78
-38
-84
-84
-
dB
dB
dB
dB
-
-89
-72
-32
-81
-83
-
-
-89
-72
-32
-81
-81
-
dB
dB
dB
dB
Dynamic Range
(Note 6)
(Note 6)
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 5)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 6)
40 kHz bandwidth
-1 dB THD+N
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 6)
40 kHz bandwidth
-1 dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
(Note 6)
(Note 6)
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 5)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 6)
40 kHz bandwidth
-1 dB THD+N
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 6)
40 kHz bandwidth
-1 dB
8
DS658F2
CS5345
Line-Level Inputs
Commercial Grade
Parameter
Symbol
Interchannel Isolation
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
-
90
-
-
90
-
dB
-
±100
-
±10
-
-
±100
-
±10
-
%
ppm/°C
DC Accuracy
Gain Error
Gain Drift
Line-Level Input Characteristics
Full-scale Input Voltage
Input Impedance
(Note 4)
Maximum Interchannel Input Impedance
Mismatch
0.51*VA 0.57*VA 0.63*VA 0.51*VA 0.57*VA 0.63*VA
6.12
6.8
7.48
5.44
6.8
8.16
-
5
-
-
5
-
Vpp
kΩ
%
Line-Level and Microphone-Level Inputs
Commercial Grade
Parameter
Symbol
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
-
0.1
-
-
0.1
-
dB
-
0.5
-
0.4
-
0.5
-
0.4
dB
dB
DC Accuracy
Interchannel Gain Mismatch
Programmable Gain Characteristics
Gain Step Size
Absolute Gain Step Error
4. Valid for the selected input pair.
DS658F2
9
CS5345
ADC ANALOG CHARACTERISTICS
(Continued)
Microphone-Level Inputs
Commercial Grade
Parameter
Symbol
Dynamic Performance for VA = 4.75 V to 5.25 V
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
77
74
83
80
-
75
72
83
80
-
dB
dB
65
62
71
68
-
63
60
71
68
-
dB
dB
-
-80
-60
-20
-74
-
-
-80
-60
-20
-72
-
dB
dB
dB
-
-68
-
-
-68
-
dB
77
74
83
80
-
75
72
83
80
-
dB
dB
65
62
71
68
-
63
60
71
68
-
dB
dB
-
-80
-60
-20
-74
-
-
-80
-60
-20
-72
-
dB
dB
dB
-
-68
80
-
-
-68
80
-
dB
dB
-
±300
±5
-
-
±300
±5
-
%
ppm/°C
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 5)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
THD+N
-60 dB
PGA Setting: +12 dB
-1 dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 5)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
THD+N
-60 dB
PGA Setting: +12 dB
-1 dB
Interchannel Isolation
DC Accuracy
Gain Error
Gain Drift
Microphone-Level Input Characteristics
Full-scale Input Voltage
Input Impedance
(Note 7)
0.013*VA 0.017*VA 0.021*VA 0.013*VA 0.017*VA 0.021*VA
60
60
-
Vpp
kΩ
5. Referred to the typical line-level full-scale input voltage
6. Valid for Double- and Quad-Speed Modes only.
7. Valid when the microphone-level inputs are selected.
10
DS658F2
CS5345
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Notes 8, 10)
Symbol
Min
Typ
Max
Unit
0
-
0.4896
Fs
-
-
0.035
dB
0.5688
-
-
Fs
70
-
-
dB
-
12/Fs
-
s
0
-
0.4896
Fs
-
-
0.025
dB
Single-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
Double-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
0.5604
-
-
Fs
69
-
-
dB
-
9/Fs
-
s
0
-
0.2604
Fs
-
-
0.025
dB
Quad-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
tgd
0.5000
-
-
Fs
60
-
-
dB
-
5/Fs
-
s
-
1
20
-
Hz
Hz
-
10
-
Deg
-
0
dB
High-Pass Filter Characteristics
Frequency Response
Phase Deviation
-3.0 dB
-0.13 dB
(Note 9)
@ 20 Hz
(Note 9)
Passband Ripple
Filter Settling Time
-
105/Fs
s
8. Filter response is guaranteed by design.
9. Response shown is for Fs = 48 kHz.
10. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 13 to 24) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
DS658F2
11
CS5345
PGAOUT ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V or
VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; TA = -10° to +70° C for Commercial or -40° to
+85° C for Automotive; Input test signal: 1 kHz sine wave; Measurement bandwidth: 10 Hz to 20 kHz;
Fs = 48/96/192 kHz; Synchronous mode; All connections as shown in Figure 7 on page 22.
VA = 4.75 V to 5.25 V
Commercial Grade
Parameter
Symbol Min
Typ
Dynamic Performance with PGA Line-Level Input Selected
Automotive Grade
Max
Min
Typ
Max
Unit
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 11)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
THD+N
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
98
95
104
101
-
96
93
104
101
-
dB
dB
92
89
98
95
-
90
87
98
95
-
dB
dB
-
-80
-81
-41
-74
-
-
-80
-81
-41
-72
-
dB
dB
dB
-
-80
-75
-35
-74
-
-
-80
-75
-35
-72
-
dB
dB
dB
77
74
83
80
-
75
72
83
80
-
dB
dB
65
62
71
68
-
63
60
71
68
-
dB
dB
-
-74
-60
-20
-68
-
-
-74
-60
-20
-66
-
dB
dB
dB
-
-68
-
-
-68
-
dB
Dynamic Performance with PGA Mic-Level Input Selected
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 11)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
THD+N
-60 dB
PGA Setting: +12 dB
-1 dB
11. Referred to the typical Line-Level Full-Scale Input Voltage.
12
DS658F2
CS5345
PGAOUT ANALOG CHARACTERISTICS
(Continued)
VA = 3.13 V to 3.46 V
Commercial Grade
Parameter
Symbol Min
Typ
Dynamic Performance with PGA Line-Level Input Selected
Automotive Grade
Max
Min
Typ
Max
Unit
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 11)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
THD+N
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
93
90
101
98
-
91
88
101
98
-
dB
dB
89
86
95
92
-
87
84
95
92
-
dB
dB
-
-80
-78
-38
-74
-
-
-80
-78
-38
-72
-
dB
dB
dB
-
-80
-72
-32
-74
-
-
-80
-72
-32
-72
-
dB
dB
dB
77
74
83
80
-
75
72
83
80
-
dB
dB
65
62
71
68
-
63
60
71
68
-
dB
dB
-
-74
-60
-20
-68
-
-
-74
-60
-20
-66
-
dB
dB
dB
-
-68
-
-
-68
-
dB
Dynamic Performance with PGA Mic Level-Input Selected
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 11)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
THD+N
-60 dB
PGA Setting: +12 dB
-1 dB
DS658F2
13
CS5345
PGAOUT ANALOG CHARACTERISTICS
(Continued)
VA = 3.13 V to 5.25 V
Parameter
Symbol
DC Accuracy with PGA Line Level Input Selected
Interchannel Gain Mismatch
Gain Error
Gain Drift
Commercial Grade
Automotive Grade
Min
Typ
Max
Min
Typ
Max
Unit
-
0.1
±5
±100
-
-
0.1
±5
±100
-
dB
%
ppm/°C
-
0.3
±5
±300
-
-
0.3
±5
±300
-
dB
%
ppm/°C
-0.1dB
100
-
180
-
180
-
+0.1dB
1
20
dB
deg
μA
kΩ
pF
DC Accuracy with PGA Mic Level Input Selected
Interchannel Gain Mismatch
Gain Error
Gain Drift
Analog Output
Frequency Response 10 Hz to 20 kHz
Analog In to Analog Out Phase Shift
DC Current draw from a PGAOUT pin
AC-Load Resistance
Load Capacitance
(Note 12)
IOUT
RL
CL
+0.1dB -0.1dB
1
100
20
-
12. Guaranteed by design.
14
DS658F2
CS5345
DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.
Parameter
Symbol
Min
Typ
Max
Unit
V
V
V
V
IA
IA
ID
ID
-
41
37
39
23
50
45
47
28
mA
mA
mA
mA
VA = 5 V
VLS, VLC, VD=5 V
IA
ID
-
0.50
0.54
-
mA
mA
Power Consumption
(Normal Operation)
VA, VD, VLS, VLC = 5 V
(Power-Down Mode)
VA, VD, VLS, VLC = 3.3 V
VA, VD, VLS, VLC = 5 V
-
-
400
198
4.2
485
241
-
mW
mW
mW
PSRR
-
55
-
dB
VQ
-
0.5 x VA
-
VDC
IQ
-
-
1
μA
ZQ
-
23
-
kΩ
Power Supply Current
(Normal Operation)
VA = 5
VA = 3.3
VD, VLS, VLC = 5
VD, VLS, VLC = 3.3
Power Supply Current
(Power-Down Mode) (Note 13)
Power Supply Rejection Ratio (1 kHz)
(Note 14)
VQ Characteristics
Quiescent Voltage
DC Current from VQ
VQ Output Impedance
FILT+ Nominal Voltage
Microphone Bias Voltage
Current from MICBIAS
(Note 15)
FILT+
-
VA
-
VDC
MICBIAS
-
0.8 x VA
-
VDC
IMB
-
-
2
mA
13. Power-Down Mode is defines as RESET = Low with all clock and data lines held static and no analog
input.
14. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
15. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage
through the electrolytic de-coupling capacitors.
DS658F2
15
CS5345
DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V.
Parameters (Note 16)
Symbol
Min
Typ
Max
Units
VIH
VIH
VIH
VIH
VIL
VIL
VOH
VOH
VOL
VOL
Iin
0.8xVLS
0.8xVLC
0.7xVLS
0.7xVLC
VLS-1.0
VLC-1.0
-
-
0.2xVLS
0.2xVLC
0.4
0.4
±10
1
V
V
V
V
V
V
V
V
V
V
μA
pF
-
-
μs
High-Level Input Voltage
VL = 1.71 V
VL > 2.0 V
Low-Level Input Voltage
High-Level Output Voltage at Io = 2 mA
Low-Level Output Voltage at Io = 2 mA
Input Leakage Current
Input Capacitance
Minimum OVFL Active Time
Serial Port
Control Port
Serial Port
Control Port
Serial Port
Control Port
Serial Port
Control Port
Serial Port
Control Port
(Note 17)
6
10
----------------LRCK
16. Serial Port signals include: MCLK, SCLK, LRCK, SDOUT.
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RESET, INT, OVFL.
17. Guaranteed by design.
16
DS658F2
CS5345
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, CL = 20 pF. (Note 18)
Parameter
Sample Rate
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Symbol
Min
Typ
Max
Unit
Fs
Fs
Fs
4
50
100
-
50
100
200
kHz
kHz
kHz
fmclk
tclkhl
1.024
8
-
51.200
-
MHz
ns
tslr
tsdo
-10
0
50
50
-
10
36
%
%
ns
ns
40
50
60
%
-
-
ns
-
-
ns
MCLK Specifications
MCLK Frequency
MCLK Input Pulse Width High/Low
Master Mode
LRCK Duty Cycle
SCLK Duty Cycle
SCLK falling to LRCK edge
SCLK falling to SDOUT valid
Slave Mode
LRCK Duty Cycle
SCLK Period
9
Single-Speed Mode
tsclkw
10
--------------------( 128 )Fs
Double-Speed Mode
tsclkw
10
-----------------( 64 )Fs
Quad-Speed Mode
tsclkw
10
-----------------( 64 )Fs
-
-
ns
tsclkh
tsclkl
tslr
tsdo
30
48
-10
0
-
10
36
ns
ns
ns
ns
9
9
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK falling to LRCK edge
SCLK falling to SDOUT valid
18. See Figure 1 and Figure 2 on page 18.
DS658F2
17
CS5345
LRCK
Output
t
slr
SCLK
Output
t
sdo
SDOUT
Figure 1. Master Mode Serial Audio Port Timing
LRCK
Input
t
slr
t
sclkh
t
sclkl
SCLK
Input
t
sdo
t
sclkw
SDOUT
Figure 2. Slave Mode Serial Audio Port Timing
18
DS658F2
CS5345
Channel B - Right
Channel A - Left
LRCK
SCLK
SDATA
MSB -1
-2
-3
-4
-5
+5 +4
+3 +2
+1 LSB
MSB -1
-2
-3
-4
+5
+4 +3
+2 +1 LSB
Figure 3. Format 0, Left-Justified up to 24-Bit Data
Channel A - Left
LRCK
Channel B - Right
SCLK
SDATA
MSB -1
-2
-3
-4
-5
+5 +4 +3 +2 +1 LSB
MSB -1
-2
-3
-4
+5 +4 +3 +2 +1 LSB
Figure 4. Format 1, I²S up to 24-Bit Data
DS658F2
19
CS5345
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RESET Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
-
1
µs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 19)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
(Note 20)
trc, trd
Fall Time SCL and SDA
(Note 20)
tfc, tfd
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
20. Guaranteed by design.
RST
t
irs
Stop
R e p e ate d
Sta rt
Sta rt
t rd
t fd
Stop
SDA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t ack
t sust
t rc
Figure 5. Control Port Timing - I²C Format
20
DS658F2
CS5345
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL = 30 pF.
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
-
6.0
MHz
RESET Rising Edge to CS Falling
tsrs
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
μs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
tdh
15
-
ns
CCLK Falling to CDOUT Stable
(Note 21)
tpd
-
50
ns
Rise Time of CDOUT
tr1
-
25
ns
Fall Time of CDOUT
tf1
-
25
ns
Rise Time of CCLK and CDIN
(Note 22)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 22)
tf2
-
100
ns
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For fsck <1 MHz.
t srs
RST
CS
t scl
t css
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu
t dh
t pd
CDOUT
Figure 6. Control Port Timing - SPI Format
DS658F2
21
CS5345
3. TYPICAL CONNECTION DIAGRAM
+3.3V to +5V
10 µF
0.1 µF
0.1 µF
VA
VD
+1.8V
to +5V
0.1 µF
0.1 µF
+3.3V to +5V
10 µF
VA
3.3 µF
PGAOUTA
VLS
3.3 µF
PGAOUTB
MCLK
SCLK
Digital Audio
Capture
AIN1A
LRCK
1800 pF *
SDOUT
AIN1B
INT
OVFL
CS5345
AIN2A
SCL/CCLK
AIN2B
SDA/CDOUT
AIN3A
AD1/CDIN
AD0/CS
2 kΩ
2 kΩ
See Note 1
AIN3B
VLC
AIN4A/MICIN1
0.1 µF
AIN4B/MICIN2
AIN5A
NC
NC
NC
NC
NC
Note 1: Resistors are required
for I²C control port operation
Note 2 The value of RL is
dictated by the microphone
carteridge.
AIN5B
AIN6A
TSTI
TSTO
TSTO
TSTO
AIN6B
*
1800 pF *
RESET
MicroController
+1.8V
to +5V
1800 pF
1800 pF
*
1800 pF *
1800 pF
*
1800 pF *
1800 pF
*
1800 pF *
1800 pF
*
1800 pF *
1800 pF
*
10 µF 0.1 µF
47 µF
AGND
AGND
0.1 µF
DGND
10 µF
100 kΩ
100 Ω
Right Analog Input 1
Left Analog Input 2
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 2
Left Analog Input 3
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 3
Left Analog Input 4
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 4
Left Analog Input 5
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
100 Ω
Right Analog Input 5
Left Analog Input 6
10 µF 100 Ω
100 kΩ
10 µF
100 kΩ
47 µF
*
AFILTA
AFILTB
AGND
100 kΩ
100 Ω
Right Analog Input 6
See Note 2
MICBIAS
VQ
FILT+
Left Analog Input 1
10 µF 100 Ω
RL
*
2.2nF 2.2nF
* Capacitors must be C0G or equivalent
Figure 7. Typical Connection Diagram
22
DS658F2
CS5345
4. APPLICATIONS
4.1
Recommended Power-Up Sequence
1. Hold RESET low until the power supply,MCLK, and LRCK are stable. In this state, the Control Port is
reset to its default settings.
2. Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The control port will be accessible.
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
4.2
System Clocking
The CS5345 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three
speed modes as shown in Table 1.
Mode
Sampling Frequency
Single-Speed
4-50 kHz
Double-Speed
50-100 kHz
Quad-Speed
100-200 kHz
Table 1. Speed Modes
4.2.1
Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the
frequency at which audio samples for each channel are clocked out of the device. The FM bits (See “Functional Mode (Bits 7:6)” on page 32.) and the MCLK Freq bits (See “MCLK Frequency - Address 05h” on
page 33.) configure the device to generate the proper clocks in Master Mode and receive the proper
clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and
LRCK frequencies.
LRCK
(kHz)
MCLK (MHz)
64x
96x
128x
192x
256x
384x
512x
768x
1024x
32
-
-
-
-
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
-
-
-
-
11.2896
16.9344
22.5792
33.8680
45.1584
48
-
-
-
-
12.2880
18.4320
24.5760
36.8640
49.1520
64
-
-
8.1920
12.2880
16.3840
24.5760
32.7680
-
-
88.2
-
-
11.2896
16.9344
22.5792
33.8680
45.1584
-
-
96
-
-
12.2880
18.4320
24.5760
36.8640
49.1520
-
-
128
8.1920
12.2880
16.3840
24.5760
32.7680
-
-
-
-
176.4
11.2896
16.9344
22.5792
33.8680
45.1584
-
-
-
-
192
12.2880
18.4320
24.5760
36.8640
49.1520
-
-
-
Mode
QSM
DSM
SSM
Table 2. Common Clock Frequencies
DS658F2
23
CS5345
4.2.2
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.
MCLK Freq Bits
MCLK
÷1
000
÷1.5
001
÷2
010
÷3
011
÷4
100
÷256
00
÷128
01
÷64
10
LRCK
FM Bits
÷4
00
÷2
01
÷1
10
SCLK
Figure 8. Master Mode Clocking
4.2.3
Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x, 48x or 32x Fs, depending on the desired speed mode. Refer to Table 3 for required clock ratios.
SCLK/LRCK Ratio
Single-Speed
Double-Speed
Quad-Speed
32x, 48x, 64x, 128x
32x, 48x, 64x
32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3
High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS5345, a small DC offset may be driven
into the A/D converter. The CS5345 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See “High-Pass Filter Freeze (Bit 1)” on page 32.) is set during normal operation,
the current value of the DC offset for the each channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration
by:
1. Running the CS5345 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5345.
24
DS658F2
CS5345
4.4
Analog Input Multiplexer, PGA, and Mic Gain
The CS5345 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the
PGA. Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing
them to be used for microphone-level signals without the need for any external gain. The PGA stage provides ±12 dB of gain or attenuation in 0.5 dB steps. Figure 9 shows the architecture of the input multiplexer,
PGA, and microphone gain stages.
AIN1A
AIN2A
AIN3A
AIN4A/MICIN1
MUX
PGA
Out to ADC
Channel A
+32 dB
AIN5A
AIN6A
Channel A
PGA Gain Bits
Analog Input
Selection Bits
AIN1B
AIN2B
Channel B
PGA Gain Bits
AIN3B
AIN4B/MICIN2
MUX
PGA
Out to ADC
Channel B
+32 dB
AIN5B
AIN6B
Figure 9. Analog Input Architecture
The ““Analog Input Selection (Bits 2:0)” on page 35” outlines the bit settings necessary to control the input
multiplexer and mic gain. “Channel B PGA Control - Address 07h” on page 33 and “Channel A PGA Control
- Address 08h” on page 34 outline the register settings necessary to control the PGA. By default, linelevel input 1 is selected, and the PGA is set to 0 dB.
4.5
Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are
(n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient (such as general-purpose ceramics) must be avoided since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.6
PGA Auxiliary Analog Output
The CS5345 includes an auxiliary analog output through the PGAOUT pins. These pins can be configured
to output the analog input to the ADC as selected by the input MUX and gained or attenuated with the PGA,
or alternatively, they may be set to high-impedance. See the ““PGAOut Source Select (Bit 6)” on page 33”
for information on configuring the PGA auxiliary analog output.
The PGA auxiliary analog output can source very little current. As current from the PGAOUT pins increases,
distortion will increase. For this reason, a high-input impedance buffer must be used on the PGAOUT pins
to achieve full performance. Refer to the table in “PGAOUT Analog Characteristics” on page 12 for acceptable loading conditions.
DS658F2
25
CS5345
4.7
Control Port Description and Timing
The control port is used to access the registers, allowing the CS5345 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS5345 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS pin, after the RESET pin has been brought high. I²C
Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
4.7.1
SPI Mode
In SPI Mode, CS is the CS5345 chip-select signal; CCLK is the control port bit clock (input into the CS5345
from the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data
line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 10 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 kΩ resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the
addressed register (CDOUT will leave the high-impedance state).
For both read and write cycles, the memory address pointer will automatically increment following each
data byte in order to facilitate block reads and writes of successive registers.
CS
CC LK
C H IP
ADDRESS
1001111
C D IN
MAP
MSB
R/W
C H IP
ADDRESS
DATA
b y te 1
LSB
1001111
R/W
b y te n
High Impedance
CDOUT
MSB
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 10. Control Port Timing in SPI Mode
4.7.2
I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should
26
DS658F2
CS5345
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS5345 is being reset.
The signal timings for a read and write cycle are shown in Figure 11 and Figure 12. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS5345
after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write).
The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS5345, the chip
address field, which is the first byte sent to the CS5345, should match 10011 followed by the settings of
the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is
the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a
read, the contents of the register pointed to by the MAP will be output. Following each data byte, the memory address pointer will automatically increment to facilitate block reads and writes of successive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS5345 after each
input byte is read, and is input to the CS5345 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
MAP BYTE
1 AD1 AD0 0
6
6
5
4
3
2
1
0
7
ACK
6
ACK
1
DATA +n
DATA +1
DATA
0
7
6
1
0
7
6
1
0
ACK
ACK
STOP
START
Figure 11. Control Port Timing, I²C Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
STOP
MAP BYTE
7
1 AD1 AD0 0
6
5
4
3
ACK
2
1
CHIP ADDRESS (READ)
1
0
0
0
1
ACK
START
DATA
1 AD1 AD0 1
START
7
ACK
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 12. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 12, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
DS658F2
27
CS5345
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
4.8
Interrupts and Overflow
The CS5345 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an
active low open-drain driver (see “Active High/Low (Bit 0)” on page 35). When configured as active low
open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups with
multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external
pull-up resistor must be placed on the INT pin for proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Interrupt
Status - Address 0Dh” on page 35). Each source may be masked off through mask register bits. In addition,
each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option of levelsensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer.
The CS5345 also has a dedicated overflow output. The OVFL pin functions as active low open drain and
has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR
of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register; however, these
conditions do not need to be unmasked for proper operation of the OVFL pin.
4.9
Reset
When RESET is low, the CS5345 enters a low-power mode and all internal states are reset, including the
control port and registers, the outputs are muted. When RESET is high, the control port becomes operational, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RESET pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this
voltage reference ramp delay, SDOUT will be automatically muted.
It is recommended that RESET be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
4.10
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the
CS5345s in the system. If only one master clock source is needed, one solution is to place one CS5345 in
Master Mode, and slave all of the other CS5345s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all clocks from the same external source and time the
CS5345 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
4.11
Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5345 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 7 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
28
DS658F2
CS5345
system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this
case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as
near to the CS5345 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the
modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CS5345 evaluation board demonstrates the optimum
layout and power supply arrangements. To minimize digital noise, connect the CS5345 digital outputs only
to CMOS inputs.
DS658F2
29
CS5345
5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr
Function
01h Chip ID
02h Power Control
7
6
5
4
3
2
1
0
PART3
PART2
PART1
PART0
REV3
REV2
REV1
REV0
1
1
1
0
0
0
0
1
Reserved
PDN_MIC
PDN_ADC
Reserved
PDN
0
0
0
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Freeze
0
03h Reserved
Reserved Reserved
0
0
Reserved Reserved Reserved
0
0
0
0
1
0
0
0
FM1
FM0
Reserved
DIF
Reserved
Mute
HPFFreeze
M/S
0
0
0
0
0
0
0
0
Reserved
MCLK
Freq2
MCLK
Freq1
MCLK
Freq0
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
06h PGAOut
Control
Reserved
PGAOut
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
1
07h PGA Ch B
Gain Control
Reserved Reserved
08h PGA Ch A
Gain Control
Reserved Reserved
04h ADC Control
05h MCLK
Frequency
0
0
09h Analog Input
Control
0
0
0
0
0
0
0
0
Gain5
Gain4
Gain3
Gain2
Gain1
Gain0
0
0
0
0
0
0
Gain5
Gain4
Gain3
Gain2
Gain1
Gain0
0
0
0
0
0
0
PGASoft
PGAZero
Sel2
Sel1
Sel0
1
1
0
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved Reserved Reserved
0
0
0
0Ah - Reserved
0Bh
Reserved Reserved Reserved
0Ch Active Level
Control
Reserved Reserved Reserved
0
1
0
1
0
0
0Dh Interrupt Status Reserved Reserved Reserved
0
0
0
0Eh Interrupt Mask
Reserved Reserved Reserved
0Fh Interrupt Mode
MSB
Reserved Reserved Reserved
0
0
10h Interrupt Mode
LSB
0
0
0
Reserved Reserved Reserved
0
30
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Active_H/L
0
0
0
0
0
Reserved
ClkErr
Reserved
Ovfl
Undrfl
0
0
0
0
0
Reserved
ClkErrM
Reserved
OvflM
UndrflM
0
0
0
0
0
Reserved
ClkErr1
Reserved
Ovfl1
Undrfl1
0
0
0
0
0
Reserved
ClkErr0
Reserved
Ovfl0
Undrfl0
0
0
0
0
0
DS658F2
CS5345
6. REGISTER DESCRIPTION
6.1
Chip ID - Register 01h
7
PART3
6
PART2
5
PART1
4
PART0
3
REV3
2
REV2
1
REV1
0
REV0
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1110b (0Eh), and the remaining
bits (3 through 0) indicate the device revision as shown in Table 4 below.
REV[2:0]
Revision
001
A
010
B, C0
011
C1
Table 4. Device Revision
6.2
Power Control - Address 02h
7
Freeze
6.2.1
6
Reserved
5
Reserved
4
Reserved
3
PDN_MIC
2
PDN_ADC
1
Reserved
0
PDN
Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
in Table 5.
Name
Register
Bit(s)
Mute
04h
2
Gain[5:0]
07h
5:0
Gain[5:0]
08h
5:0
Table 5. Freeze-able Bits
6.2.2
Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
6.2.3
Power-Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
6.2.4
Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
DS658F2
31
CS5345
6.3
ADC Control - Address 04h
7
6
5
4
3
2
1
0
FM1
FM0
Reserved
DIF
Reserved
Mute
HPFFreeze
M/S
6.3.1
Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates.
FM1
FM0
0
0
Single-Speed Mode: 4 to 50 kHz sample rates
Mode
0
1
Double-Speed Mode: 50 to 100 kHz sample rates
1
0
Quad-Speed Mode: 100 to 200 kHz sample rates
1
1
Reserved
Table 6. Functional Mode Selection
6.3.2
Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format
bit. The options are detailed in Table 7 and may be seen in Figure 3 and Figure 4.
DIF
Description
Format
Figure
0
Left-Justified, up to 24-bit data (default)
0
3
1
I²S, up to 24-bit data
1
4
Table 7. Digital Interface Formats
6.3.3
Mute (Bit 2)
Function:
When this bit is set, the serial audio output of the both channels is muted.
6.3.4
High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on
page 24.
6.3.5
Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
32
DS658F2
CS5345
6.4
MCLK Frequency - Address 05h
7
Reserved
6.4.1
6
MCLK
Freq2
5
MCLK
Freq1
4
MCLK
Freq0
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See Table 8 for the appropriate settings.
MCLK Divider
MCLK Freq2
MCLK Freq1
MCLK Freq0
÷1
0
0
0
÷ 1.5
0
0
1
÷2
0
1
0
÷3
0
1
1
÷4
1
0
0
Reserved
1
0
1
Reserved
1
1
x
Table 8. MCLK Frequency
6.5
PGAOut Control - Address 06h
7
6
5
4
3
2
1
0
Reserved
PGAOut
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6.5.1
PGAOut Source Select (Bit 6)
Function:
This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to
Table 9.
PGAOut
PGAOutA & PGAOutB
0
High Impedance
1
PGA Output
Table 9. PGAOut Source Selection
6.6
Channel B PGA Control - Address 07h
7
Reserved
6.6.1
6
Reserved
5
Gain5
4
Gain4
3
Gain3
2
Gain2
1
Gain1
0
Gain0
Channel B PGA Gain (Bits 5:0)
Function:
See “Channel A PGA Gain (Bits 5:0)” on page 34.
DS658F2
33
CS5345
6.7
Channel A PGA Control - Address 08h
7
Reserved
6.7.1
6
Reserved
5
Gain5
4
Gain4
3
Gain3
2
Gain2
1
Gain1
0
Gain0
Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 10 for example settings.
Gain[5:0]
Setting
101000
-12 dB
000000
0 dB
011000
+12 dB
Table 10. Example Gain and Attenuation Settings
6.8
ADC Input Control - Address 09h
7
Reserved
6.8.1
6
Reserved
5
Reserved
4
PGASoft
3
PGAZero
2
Sel2
1
Sel1
0
Sel0
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 11.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 11.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 11.
34
DS658F2
CS5345
PGASoft
0
0
1
1
PGAZeroCross
0
1
0
1
Mode
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled (default)
Table 11. PGA Soft Cross or Zero Cross Mode Selection
6.8.2
Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 12.
Sel2
Sel1
Sel0
PGA/ADC Input
0
0
0
Microphone-Level Inputs (+32 dB Gain Enabled)
0
0
1
Line-Level Input Pair 1
0
1
0
Line-Level Input Pair 2
0
1
1
Line-Level Input Pair 3
1
0
0
Line-Level Input Pair 4
1
0
1
Line-Level Input Pair 5
1
1
0
Line-Level Input Pair 6
1
1
1
Reserved
Table 12. Analog Input Multiplexer Selection
6.9
Active Level Control - Address 0Ch
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Active_H/L
Active High/Low (Bit 0)
6.9.1
Function:
When this bit is set, the INT pin functions as an active high CMOS driver.
When this bit is cleared, the INT pin functions as an active low open drain driver and will require an external pull-up resistor for proper operation.
6.10
Interrupt Status - Address 0Dh
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
ClkErr
2
Reserved
1
Ovfl
0
Undrfl
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last
reading of the register. Status bits that are masked off in the associated mask register will always be ‘0’ in
this register. This register defaults to 00h.
DS658F2
35
CS5345
6.10.1 Clock Error (Bit 3)
Function:
Indicates the occurrence of a clock error condition.
6.10.2 Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.10.3 Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
6.11
Interrupt Mask - Address 0Eh
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
ClkErrM
2
Reserved
1
OvflM
0
UndrflM
Function:
The bits of this register serve as a mask for the Status sources found in the register “Interrupt Status - Address 0Dh” on page 35. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect
the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence
will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Status register.
6.12
Interrupt Mode MSB - Address 0Fh
6.13
Interrupt Mode LSB - Address 10h
7
Reserved
Reserved
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
3
ClkErr1
ClkErr0
2
Reserved
Reserved
1
Ovfl1
Ovfl0
0
Undrfl1
Undrfl0
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are
three ways to set the INT pin active in accordance with the interrupt condition. In the Rising-Edge Active
Mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling-Edge Active Mode,
the INT pin becomes active on the removal of the interrupt condition. In Level-Active Mode, the INT pin remains active during the interrupt condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
36
DS658F2
CS5345
7. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
DS658F2
37
CS5345
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
Amplitude (dB)
Amplitude (dB)
8. FILTER PLOTS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44
Frequency (norm alized to Fs)
0
0.10
-1
0.08
-2
0.06
-3
0.04
-4
-5
-6
-7
0.58
0.60
0.00
-0.04
-0.06
-0.08
-0.10
0.46 0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0
0.55
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Figure 16. Single-Speed Passband Ripple
Amplitude (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.1
0.05
Frequency (norm alized to Fs)
Figure 15. Single-Speed Transition Band (Detail)
Amplitude (dB)
0.56
-0.02
-9
Frequency (norm alized to Fs)
0.9
Frequency (norm alized to Fs)
Figure 17. Double-Speed Stopband Rejection
38
0.54
0.02
-8
0.0
0.52
Figure 14. Single-Speed Stopband Rejection
Amplitude (dB)
Amplitude (dB)
Figure 13. Single-Speed Stopband Rejection
-10
0.45
0.46 0.48 0.50
Frequency (norm alized to Fs)
1.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Figure 18. Double-Speed Stopband Rejection
DS658F2
0
0.10
-1
0.08
-2
0.06
-3
0.04
Amplitude (dB)
Amplitude (dB)
CS5345
-4
-5
-6
-7
0.02
0.00
-0.02
-0.04
-8
-0.06
-9
-0.08
-10
0.46
0.47
0.48
0.49
0.50
0.51
-0.10
0.00 0.05
0.52
Frequency (norm alized to Fs)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.15
0.20 0.25 0.30 0.35 0.40 0.45 0.50
Figure 20. Double-Speed Passband Ripple
Amplitude (dB)
Amplitude (dB)
Figure 19. Double-Speed Transition Band (Detail)
0.0
0.10
Frequency (norm alized to Fs)
0.9
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
1.0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 21. Quad-Speed Stopband Rejection
Figure 22. Quad-Speed Stopband Rejection
0
0.10
-1
0.08
-3
0.06
-4
0.04
Amplitude (dB)
Amplitude (dB)
-2
-5
-6
-7
-8
-0.04
-0.08
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (norm alized to Fs)
Figure 23. Quad-Speed Transition Band (Detail)
DS658F2
0.00
-0.02
-0.06
-9
-10
0.10
0.02
-0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (norm alized to Fs)
Figure 24. Quad-Speed Passband Ripple
39
CS5345
9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
MAX
MIN
0.055
0.063
--0.004
0.006
0.05
0.009
0.011
0.17
0.354
0.366
8.70
0.28
0.280
6.90
0.354
0.366
8.70
0.28
0.280
6.90
0.020
0.024
0.40
0.24
0.030
0.45
4°
7.000°
0.00°
*Controlling dimension is mm.
MILLIMETERS
NOM
MAX
1.40
1.60
0.10
0.15
0.22
0.27
9.0 BSC
9.30
7.0 BSC
7.10
9.0 BSC
9.30
7.0 BSC
7.10
0.50 BSC
0.60
0.60
0.75
4°
7.00°
*JEDEC Designation: MS022
10.THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters
Package Thermal Resistance (Note 1)
Allowable Junction Temperature
48-LQFP
Symbol
Min
Typ
Max
Units
θJA
θJC
-
48
15
-
125
°C/Watt
°C/Watt
°C
1. θJA is specified according to JEDEC specifications for multi-layer PCBs.
40
DS658F2
CS5345
11.ORDERING INFORMATION
Product
CS5345
CS5345
CDB5345
Description
24-bit, 192 kHz
Stereo Audio ADC
24-bit, 192 kHz
Stereo Audio ADC
Package Pb-Free
48-LQFP
48-LQFP
CS5345 Evaluation Board
Yes
Grade
Commercial
Temp Range
-10° to +70° C
Yes
Automotive
-40° to +105° C
No
-
-
Container
Order #
Tray
CS5345-CQZ
Tape & Reel
CS5345-CQZR
Tray
CS5345-DQZ
Tape & Reel
CS5345-DQZR
-
CDB5345
12.REVISION HISTORY
Release
F1
F2
Changes
– Removed the MAP auto-increment functional description from the Control Port Description and Timing section
beginning on page 26.
– Added device revision information to the Chip ID - Register 01h description on page 31.
– Added Automotive Grade
– Changed MCLK to input only in the Pin Descriptions table on page 5.
– Updated the ADC Analog Characteristics table on page 8.
– Updated the PGAOUT Analog Characteristics table on page 12.
– Updated the DC Electrical Characteristics table on page 15.
– Updated the Digital Interface Characteristics table on page 16.
– Updated the Switching Characteristics - Serial Audio Port table on page 17.
– Updated the Switching Characteristics - Control Port - SPI Format table on page 21.
– Updated the Typical Connection Diagram on page 22.
– Switched Channel B PGA Control - Address 07h on page 33 and Channel A PGA Control - Address 08h on
page 34.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
DS658F2
41
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