ICST ICS813001AGI Dual vcxo w/3.3v, 2.5v lvpecl femtoclock-tm pll Datasheet

ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
GENERAL DESCRIPTION
FEATURES
The ICS813001I is a dual VCXO + FemtoClock™
Multiplier designed for use in Discrete PLL
HiPerClockS™ loops. Two selectable external VCXO crystals
allow the device to be used in multi-rate applications, where a given line card can be
switched, for example, between 1Gb Ethernet (125MHz
system reference clock) and 1Gb Fibre Channel
(106.25MHz system reference clock) modes. Of course,
a multitude of other applications are also possible such
as switching between 74.25MHz and 74.175824MHz
for HDTV, switching between SONET, FEC and non FEC
rates, etc.
• One 3.3V or 2.5V LVPECL output pair
ICS
• Two selectable crystal oscillator interfaces for the VCXO,
one differential clock or one LVCMOS/LVTTL clock inputs
• CLK1/nCLK1 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Crystal operating frequency range: 14MHz - 24MHz
• VCO range: 490MHz - 640MHz
• Output frequency range: 40.83MHz - 640MHz
• VCXO pull range: ±100ppm (typical)
• Supports the following applications (among others):
SONET, Ethernet, Fibre Channel, HDTV, MPEG
The ICS813001I is a two stage device – a VCXO followed
by a FemtoClock PLL. The FemtoClock PLL can multiply
the crystal frequency of the VCXO to provide an output
frequency range of 40.83MHz to 640MHz, with a random
rms phase jitter of less than 1ps (12kHz – 20MHz). This
phase jitter performance meets the requirements of 1Gb/
10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel,
and SONET up to OC48. The FemtoClock PLL can also be
bypassed if frequency multiplication is not required. For
testing/debug purposes, de-assertion of the output enable
pin will place both Q and nQ in a high impedance state.
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.84 (typical)
• Supply voltage modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
BLOCK DIAGRAM
VCO_SEL Pullup
CLK_SEL0 Pulldown
CLK_SEL1 Pullup
CLK0 Pulldown
Pulldown
CLK1
nCLK1 Pullup
00
0
01
PD
XTAL_IN0
VCO
490-640MHz
10
XTAL_OUT0
(default)
VCXO
XTAL_IN1
11
XTAL_OUT1
VC
M2
Pullup
Feedback Divider M
M2:M0
000 ÷16
001 ÷20
010 ÷22
011 ÷24
100 ÷25 (default)
101 ÷32
110 ÷40
111 MR
1
Output Divider N
N2:N0
000 ÷1
001 ÷2
010 ÷3
011 ÷4 (default)
100 ÷5
101 ÷6
110 ÷8
111 ÷12
M1 Pulldown
M0 Pulldown
N2 Pulldown
N1 Pullup
PIN ASSIGNMENT
VCO_SEL
N0
N1
N2
VCCO
Q
nQ
V EE
VCCA
VCC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK_SEL1
CLK_SEL0
OE
M2
M1
M0
CLK1
nCLK1
CLK0
VC
XTAL_IN0
XTAL_OUT0
ICS813001I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
N0 Pullup
O E Pullup
813001AGI
Q
nQ
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1
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TABLE 1. PIN DESCRIPTIONS
Νυ μ β ε ρ
Ναμ ε
1
VCO_SEL
Input
Τψπ ε
Δ ε σχριπ τιο ν
2, 3
N0, N1
Input
4
N2
Input
5
VCCO
Power
Output supply pin.
6, 7
Q, nQ
Ouput
Differential output pair. LVPECL interface levels.
8
VEE
Power
Negative supply pin.
9
VCCA
Power
Analog supply pin.
10
11
12
13
14
15
VCC
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
VC
Power
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant cr ystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
VCXO control voltage input.
Pullup
VCO select pin. LVCMOS/LVTTL interface levels.
Pullup
Output divider select pins. Default value = ÷4.
Pulldown LVCMOS/LVTTL interface levels.
Input
Input
Input
16
CLK0
Input
17
nCLK1
Input
Pulldown LVCMOS/LVTTL clock input.
18
CLK1
Input
Pulldown Non-inver ting differential clock input.
19, 20
M0, M1
Input
21
M2
Input
Pulldown Feedback divider select pins. Default value = ÷25.
LVCMOS/LVTTL interface levels.
Pullup
22
OE
Input
Pullup
23
CLK_SEL0
Input
Pulldown
24
CLK_SEL1
Input
Pullup
Pullup
Inver ting differential clock input.
Output enable. When HIGH, the output is active. When LOW, the output
is in a high impedance state. LVCMOS/LVTTL interface levels.
Clock select pin. LVCMOS/LVTTL interface levels. Refer to Table 3.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pullup Resistor
51
kΩ
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
CLK_SEL0
0
Selected Input
CLK0
0
1
CLK1, nCLK1
1
0
XTAL0
1
1
XTAL1
CLK_SEL1
0
813001AGI
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2
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
70°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
VCC
Test Conditions
Core Supply Voltage
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
130
mA
ICCA
Analog Supply Current
10
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
2.375
2.5
VCCO
Output Supply Voltage
2.625
V
IEE
Power Supply Current
130
mA
ICCA
Analog Supply Current
10
mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
Test Conditions
2.375
2.5
2.625
V
VCCA
Analog Supply Voltage
2.375
2.5
2.625
V
2.375
2.5
VCCO
Output Supply Voltage
2.625
V
IEE
Power Supply Current
125
mA
ICCA
Analog Supply Current
10
mA
813001AGI
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3
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VC
VCXO Control Voltage
IIH
IIL
IVC
Input
High Current
Input
Low Current
Test Conditions
VCC = 3.3V
N2, M0, M1,
CLK0, CLK_SEL0
N0, N1, M2,
VCO_SEL, CLK_SEL1
N2, M0, M1,
CLK0, CLK_SEL0
N0, N1, M2,
VCO_SEL, CLK_SEL1
Input Current cƒ Vc pin
Minimum Typical
2.0
Maximum
VCC + 0.3
Units
V
VCC + 0.3
V
VCC = 2.5V
1.7
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
0.7
V
0
VCC
V
150
µA
5
µA
VCC = VIN = 3.465V
or 2.625V
VCC = VIN = 3.465V
or 2.625V
VCC = 3.465V or 2.625V,
VIN = 0V
VCC = 3.465V or 2.625V,
VIN = 0V
VCC = 3.465V or 2.625V
-5
µA
-150
µA
-100
100
µA
Maximum
Units
150
µA
5
µA
TABLE 4D. DIFFERENTIAL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
Test Conditions
VIN = VCC = 3.465V
or 2.625V
VIN = VCC = 3.465V
or 2.625V
VIN = 0V, VCC = 3.465V
or 2.625V
VIN = 0V, VCC = 3.465V
or 2.625V
CLK1
nCLK1
CLK1
IIL
Input Low Current
nCLK1
VPP
Minimum
Peak-to-Peak Input Voltage
Typical
-5
µA
-150
µA
0.15
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCMR
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended appliations, the maximum input voltage for CLK1, nCLK1 is VCC + 0.3V.
1.3
V
VCC - 0.85
V
Maximum
Units
TABLE 4E. LVPECL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
813001AGI
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4
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
fVCO
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
PLL VCO Lock Range
t R / tF
Output Rise/Fall Time
t jit(Ø)
odc
Test Conditions
Minimum
VCO_SEL = 1
40.83
622.08MHz (12kHz - 20MHz)
Output Duty Cycle
Typical
Maximum
Units
64 0
MHz
0.84
ps
490
640
MHz
20% to 80%
250
500
ps
N÷1
N ≠ ÷1
43
48
57
52
%
%
Maximum
Units
64 0
MHz
NOTE 1: Phase jitter using a cr ystal interface.
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
fVCO
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
PLL VCO Lock Range
t R / tF
Output Rise/Fall Time
t jit(Ø)
odc
Test Conditions
Minimum
VCO_SEL = 1
40.83
622.08MHz (12kHz - 20MHz)
Output Duty Cycle
Typical
0.87
ps
490
640
MHz
20% to 80%
250
500
ps
N÷1
N ≠ ÷1
43
48
57
52
%
%
Maximum
Units
64 0
MHz
NOTE 1: Phase jitter using a cr ystal interface.
TABLE 5C. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
fVCO
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
PLL VCO Lock Range
t R / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tjit(Ø)
Test Conditions
Minimum
VCO_SEL = 1
40.83
622.08MHz (12kHz - 20MHz)
Typical
1.2
ps
490
640
MHz
20% to 80%
250
500
ps
N÷1
N ≠ ÷1
43
48
57
52
%
%
NOTE 1: Phase jitter using a crystal interface.
813001AGI
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5
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TYPICAL PHASE NOISE
AT
622.08MHZ @ 3.3V
➤
0
-10
OC-12 Filter
-20
-30
622.08MHz
-40
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.84ps (typical)
-60
-70
Raw Phase Noise Data
-80
-90
➤
-100
-110
-120
➤
NOISE POWER dBc
Hz
-50
-130
-140
Phase Noise Result by adding
Sonet OC-12 Filter to raw data
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
813001AGI
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6
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
PARAMETER MEASUREMENT INFORMATION
2V
2.8V±0.04V
2V
VCC,
VCCA,
VCCO
SCOPE
Qx
VCC,
VCCA
LVPECL
Qx
SCOPE
VCCO
LVPECL
VEE
nQx
nQx
VEE
-0.5V ± 0.125V
-1.3V±0.165V
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2V
VCC,
VCCA,
VCCO
Qx
V CC
SCOPE
nCLK1
V
LVPECL
V
Cross Points
PP
CMR
CLK1
nQx
VEE
VEE
-0.5V ± 0.125V
DIFFERENTIAL INPUT LEVELS
2.5V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
Q
Phase Noise Plot
Noise Power
nQ
t PW
t
PERIOD
Phase Noise Mask
odc =
t PW
x 100%
t PERIOD
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
80%
VSW I N G
Clock
Outputs
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
813001AGI
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7
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS813001I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VCCA.
3.3V or 2.5V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the
input clock swing is only 2.5V and VCC = 3.3V, V_REF should be
1.25V and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
813001AGI
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8
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
VCXO CRYSTAL SELECTION
Choosing a crystal with the correct characteristics is one of
the most critical steps in using a Voltage Controlled Crystal
Oscillator (VCXO). The crystal parameters affect the tuning
➤
VC
range and accuracy of a VCXO. Below are the key variables
and an example of using the crystal parameters to calculate
the tuning range of the VCXO.
VC
- Control voltage used to tune
frequency
Oscillator
Control Voltage
CV
➤
CV
the
➤C
V
VCXO (Internal)
XTAL
CS1
➤
CL1
- Varactor capacitance, varies due to
change in control voltage
Optional
CS2
➤
CL1, CL2 - Load tuning capacitance used for fine
tuning or centering nominal
frequency
CS1, CS2 - Stray Capacitance caused by pads,
vias, and other board parasitics
CL2
FIGURE 3. VCXO OSCILLATOR CIRCUIT
TABLE 6. EXAMPLE CRYSTAL PARAMETERS
Symbol
Parameter
fN
Nominal Frequency
fT
fS
Test Conditions
Minimum
Typical
Maximum
Units
24
MHz
Frequency Tolerance
±20
ppm
Frequency Stability
±20
ppm
70
°C
14
Operating Temperature Range
0
CL
Load Capacitance
12
pF
CO
Shunt Capacitance
4
pF
C1, C2
Pullability Ratio
ESR
Equivalent Series Resistance
220
240
20
Drive Level
1
Aging @ 25°C
±3 per year
ppm
Fundamental
Mode of Operation
813001AGI
mW
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9
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TABLE 7. VARACTOR PARAMETERS
Symbol
Parameter
CV_LOW
Low Varactor Capacitance
Test Conditions
VC = 0V
Minimum
15
pF
CV_HIGH
High Varactor Capacitance
VC = 3.3V
27.4
pF
FORMULAS
C Low =
(C
(C
L1
L1
+ C S1 + CV _ Low ) ⋅ (C L 2 + C S 2 + CV _ Low )
C High =
+ C S 1 + CV _ Low ) + (C L 2 + C S 2 + CV _ Low )
(C
(C
L1
L1
Typical
Maximum
Units
+ C S1 + CV _ High ) ⋅ (C L 2 + C S 2 + CV _ High )
+ C S1 + CV _ High ) + (C L 2 + C S 2 + CV _ High )
• CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
CLow determines the high frequency component on the TPR.
• CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
CHigh determines the low frequency component on the TPR.
⎛
⎞
⎜
⎟
1
1
⎜
⎟ ⋅ 10 6
−
Total Pull Range (TPR ) =
⎜
C Low ⎞
C High ⎞ ⎟
⎛
⎛
C
0
C
0
⎜ 2 ⋅ C 1 ⋅ ⎜1 +
C 0 ⎟⎠ 2 ⋅ C1 ⋅ ⎜⎝1 +
C 0 ⎟⎠ ⎟⎠
⎝
⎝
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were
some assumptions made. First, the stray capacitance (CS1,
C S2), which is all the excess capacitance due to board
parasitic, is 4pF. Second, the expected lifetime of the project
is 5 years; hence the inaccuracy due to aging is ±15ppm.
Third, though many boards will not require load tuning
capacitors (C L1 , C L2 ), it is recommended for long-term
consistent performance of the system that two tuning
capacitor pads be placed into every design. Typical values
for the load tuning capacitors will range from 0 to 4pF.
(0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ )
CLow =
TPR =
(0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ )
CHigh =
= 9.5pƒ
(0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ )
1
(
2· 220 · 1 + 9.5pƒ
4pƒ
)
–
= 15.7pƒ
(0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ )
⎞
⎟
6
⎟ ⋅=
1 · 10 · = 212ppm
⎞
15.7pƒ
⎟
2· 220 · 1 +
4pƒ ⎟⎠ ⎟⎠
1
(
)
TPR = ±106ppm
APR = 106ppm – (20ppm + 20ppm + 15ppm) = ±51ppm
The example above will ensure a total pull range of
±106 ppm with an APR of ±51ppm. Many times, board
designers may select their own crystal based on their
application. If the application requires a tighter APR, a crystal
813001AGI
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can vary the frequency tolerance,
temperature stability, and aging or shunt capacitance to
achieve the required pullability.
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10
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to4E show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
813001AGI
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11
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
VC input pin - do not float, must be biased.
TERMINATION
FOR
3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
outputs are designed to drive 50Ω transmission lines.
Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
VCC - 2V
Zo = 50Ω
RTT
84Ω
84Ω
FIGURE 5B. LVPECL OUTPUT TERMINATION
FIGURE 5A. LVPECL OUTPUT TERMINATION
813001AGI
FIN
50Ω
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12
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 6A and Figure 6B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very
close to ground level. The R3 in Figure 6B can be eliminated
and the termination is shown in Figure 6C.
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
-
2,5V LVPECL
Driv er
2,5V LVPECL
Driv er
R2
62.5
R1
50
R4
62.5
R2
50
R3
18
FIGURE 6A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 6B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 6C. 2.5V LVPECL TERMINATION EXAMPLE
813001AGI
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13
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813001I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813001I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450.45mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with output switching) = 450.45mW + 30mW = 480.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 70°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.481W * 65°C/W = 116.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
813001AGI
0
1
2.5
70°C/W
65°C/W
62°C/W
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14
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
For logic high, VOUT = V
OH_MAX
=V
CCO_MAX
– 0.9V
(VCCO_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = V
OL_MAX
(V
CCO_MAX
-V
=V
CCO_MAX
– 1.7V
) = 1.7V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
CCO_MAX
L
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
CCO_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
)=
OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
813001AGI
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15
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS813001I is: 3948
813001AGI
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16
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
24 LEAD TSSOP
TABLE 10. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
24
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
E
E1
7.90
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
813001AGI
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17
REV. A SEPTEMBER 2, 2005
ICS813001I
Integrated
Circuit
Systems, Inc.
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS813001AGI
ICS813001AGI
24 Lead TSSOP
tube
-40°C to 85°C
ICS813001AGIT
ICS813001AGI
24 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS813001AGILF
ICS813001AGIL
24 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS813001AGILFT
ICS813001AGIL
24 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an LF suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
813001AGI
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18
REV. A SEPTEMBER 2, 2005
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