Maxim MAX11602EEE+ 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/8-/12-channel 2-wire serial 8-bit adc Datasheet

19-4554; Rev 1; 7/09
KIT
ATION
EVALU
E
L
B
AVAILA
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
The MAX11600–MAX11605 low-power, 8-bit, multichannel, analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply and require only 350µA at
the maximum sampling rate of 188ksps. AutoShutdown™ powers down the devices between conversions, reducing supply current to less than 1µA at low
throughput rates. The MAX11600/MAX11601 provide 4
analog input channels each, the MAX11602/MAX11603
provide 8 analog input channels each while the
MAX11604/MAX11605 provide 12 analog input channels.
The analog inputs are software configurable for unipolar or
bipolar and single-ended or pseudo-differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to V DD . The MAX11601/
MAX11603/MAX11605 feature a 2.048V internal reference and the MAX11600/MAX11602/MAX11604 feature
a 4.096V internal reference.
The MAX11600/MAX11601 are available in 8-pin SOT23
packages. The MAX11602–MAX11605 are available in
16-pin QSOP packages. The MAX11600–MAX11605 are
guaranteed over the extended industrial temperature
range (-40°C to +85°C). Refer to the MAX11606–
MAX11611 for 10-bit devices and to the MAX11612–
MAX11617 for 12-bit devices.
Applications
Handheld Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
Features
o High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
o Single Supply
2.7V to 3.6V (MAX11601/MAX11603/MAX11605)
4.5V to 5.5V (MAX11600/MAX11602/MAX11604)
o Internal Reference
2.048V (MAX11601/MAX11603/MAX11605)
4.096V (MAX11600/MAX11602/MAX11604)
o External Reference: 1V to VDD
o Internal Clock
o 4-Channel Single-Ended or 2-Channel PseudoDifferential (MAX11600/MAX11601)
o 8-Channel Single-Ended or 4-Channel PseudoDifferential (MAX11602/MAX11603)
o 12-Channel Single-Ended or 6-Channel PseudoDifferential (MAX11604/MAX11605)
o Internal FIFO with Channel-Scan Mode
o Low Power
350µA at 188ksps
110µA at 75ksps
8µA at 10ksps
1µA in Power-Down Mode
o Software Configurable Unipolar/Bipolar
o Small Packages
8-Pin SOT23 (MAX11600/MAX11601)
16-Pin QSOP (MAX11602–MAX11605)
Pin Configurations and Typical Operating Circuit appear
at end of data sheet.
Ordering Information/Selector Guide
TEMP RANGE
PIN-PACKAGE
TUE
(LSB)
INPUT
CHANNELS
INTERNAL
REFERENCE (V)
MAX11600EKA+
-40°C to +85°C
8 SOT23
±2
4
4.096
AAJE
MAX11601EKA+
-40°C to +85°C
8 SOT23
±2
4
2.048
AAJG
MAX11602EEE+
-40°C to +85°C
16 QSOP
±1
8
4.096
—
MAX11603EEE+
-40°C to +85°C
16 QSOP
±1
8
2.048
—
MAX11604EEE+
-40°C to +85°C
16 QSOP
±1
12
4.096
—
MAX11605EEE+
-40°C to +85°C
16 QSOP
±1
12
2.048
—
PART
TOP
MARK
+Denotes a lead(Pb)-free/RoHS-compliant package.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1
MAX11600–MAX11605
General Description
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
AIN0–AIN11, REF to
GND ......................-0.3V to the lower of (VDD + 0.3V) and +6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SOT23 (derate 7.1mW/°C above +70°C).............567mW
16-Pin QSOP (derate 8.3mW/°C above +70°C).........666.7mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD = 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF = 2.048V (MAX11601/MAX11603/MAX11605), VREF = 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±1
LSB
DC ACCURACY (Note 1)
Resolution
8
Relative Accuracy
INL
(Note 2)
Differential Nonlinearity
DNL
No missing codes over temperature
Bits
Offset Error
Offset-Error Temperature
Coefficient
LSB
LSB
3
Gain Error
ppm/°C
±1
(Note 3)
±1
Gain Temperature Coefficient
Total Unadjusted Error
±1
±1.5
TUE
LSB
ppm/°C
MAX11600/MAX11601
±0.5
MAX11602/MAX11603
±0.5
±2
±1
MAX11604/MAX11605
±0.5
±1
LSB
Channel-to-Channel Offset
Matching
±0.1
LSB
Channel-to-Channel Gain
Matching
±0.5
LSB
75
dB
Input Common-Mode Rejection
Ratio
CMRR
Pseudo-differential input mode
DYNAMIC PERFORMANCE (fIN(sine wave) = 25kHz, VIN = VREF(P-P), fSAMPLE = 188ksps, RIN = 100Ω)
Signal-to-Noise Plus Distortion
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Channel-to-Channel Crosstalk
Up to the 5th harmonic
(Note 4)
49
dB
-69
dB
69
dB
75
dB
Full-Power Bandwidth
-3dB point
2.0
MHz
Full-Linear Bandwidth
SINAD > 49dB
200
kHz
CONVERSION RATE
Conversion Time (Note 5)
2
tCONV
Internal clock
External clock
6.1
4.7
_______________________________________________________________________________________
µs
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
(VDD = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD = 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF = 2.048V (MAX11601/MAX11603/MAX11605), VREF = 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Throughput Rate
SYMBOL
fSAMPLE
CONDITIONS
MIN
TYP
Internal clock, SCAN[1:0] = 01
(MAX11600/MAX11601)
76
SCAN[1:0] = 00 CS[3:0] = 0111
(MAX11602/MAX11603)
76
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX11604/MAX11605)
77
External clock
Track/Hold Acquisition Time
ksps
ns
2.25
tAD
UNITS
188
588
Internal Clock Frequency
Aperture Delay
MAX
External clock, fast mode
45
External clock, high-speed mode
30
MHz
ns
ANALOG INPUT (AIN0–AIN11)
Unipolar
Input Voltage Range, Single
Ended and Differential (Note 6)
VREF
±VREF/2
On/off-leakage current, VAIN_ = 0 or VDD,
no clock, fSCL = 0
Input Multiplexer Leakage Current
Input Capacitance
0
Bipolar
±0.01
CIN
±1
18
V
µA
pF
INTERNAL REFERENCE (Note 7)
Reference Voltage
VREF
Reference Temperature
Coefficient
TA = +25°C
MAX11601/MAX11603/MAX11605
1.925
2.048
2.171
MAX11600/MAX11602/MAX11604
3.850
4.096
4.342
TCREF
120
Reference Short-Circuit Current
ppm/°C
10
Reference Source Impedance
(Note 8)
V
mA
Ω
675
EXTERNAL REFERENCE
Reference Input Voltage Range
VREF
(Note 9)
REF Input Current
IREF
fSAMPLE = 188ksps
1.0
14
VDD
V
30
µA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Current
VIH
0.7 x VDD
V
VIL
0.3 x VDD
VHYST
IIN
Input Capacitance
CIN
Output Low Voltage
VOL
0.1 x VDD
V
±10
VIN = 0 to VDD
15
ISINK = 3mA
V
µA
pF
0.4
V
_______________________________________________________________________________________
3
MAX11600–MAX11605
ELECTRICAL CHARACTERISTICS (continued)
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD = 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF = 2.048V (MAX11601/MAX11603/MAX11605), VREF = 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Voltage (Note 10)
VDD
MAX11601/MAX11603/MAX11605
2.7
3.6
MAX11600/MAX11602/MAX11604
4.5
5.5
fSAMPLE =
188ksps
fSAMPLE =
75ksps
Supply Current
IDD
Internal REF, external clock
350
External REF, external clock
250
External REF, external clock
110
External REF, internal clock
150
fSAMPLE =
10ksps
External REF, external clock
8
External REF, internal clock
10
fSAMPLE =
1ksps
External REF, external clock
2
External REF, internal clock
2.5
Power-down
Power-Supply Rejection Ratio
PSRR
(Note 11)
V
650
µA
1
10
±0.25
±1
LSB/V
400
kHz
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1a and 2)
Serial-Clock Frequency
fSCL
Bus Free Time Between a STOP (P)
and a START (S) Condition
tBUF
1.3
µs
Hold Time for START Condition
tHD.STA
0.6
µs
Low Period of the SCL Clock
tLOW
1.3
µs
High Period of the SCL Clock
tHIGH
0.6
µs
Setup Time for a Repeated START
Condition (Sr)
tSU.STA
0.6
µs
Data Hold Time
tHD.DAT
Data Setup Time
tSU.DAT
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
Setup Time for STOP Condition
(Note 12)
0
150
100
ns
tR
(Note 13)
20 + 0.1CB
300
tF
(Note 13)
20 + 0.1CB
300
tSU.STO
ns
0.6
ns
ns
µs
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns
1.7
MHz
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1b and 2)
Serial-Clock Frequency
Hold Time (Repeated) START
Condition
fSCLH
(Note 14)
tHD.STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
tSU.STA
160
ns
Setup Time for a Repeated START
Condition (Sr)
4
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
(VDD = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD = 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF = 2.048V (MAX11601/MAX11603/MAX11605), VREF = 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Data Hold Time
tHD.DAT
Data Setup Time
tSU.DAT
CONDITIONS
(Note 12)
MIN
0
TYP
MAX
UNITS
150
ns
10
ns
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
(Note 13)
20
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1
(Note 13)
20
160
ns
Fall Time of SCL Signal
tFCL
(Note 13)
20
80
ns
Rise Time of SDA Signal
tRDA
(Note 13)
20
160
ns
tFDA
(Note 13)
20
160
Fall Time of SDA Signal
Setup Time for STOP Condition
tSU, STO
Capacitive Load for Each Bus Line
CB
Pulse Width of Spike Suppressed
tSP
160
0
ns
ns
400
pF
10
ns
Note 1: The MAX11600/MAX11602/MAX11604 are tested at VDD = 5V and the MAX11601/MAX11603/MAX11605 are tested at VDD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Ground on channel; sine wave applied to all off channels.
Note 5: Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7: When AIN_/REF (MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF or REF to GND with a 0.01µF capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF or REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mVP-P.
Note 10: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operation beyond this range, see the Typical
Operating Characteristics.
Note 11: Power-supply rejection ratio is measured as:
N
[VFS (3.3V) − VFS (2.7V)] × V2REF
3.3V − 2.7V
,
for the MAX11601/MAX11603/MAX11605, where N is the number of bits.
Power-supply rejection ratio is measured as:
N
[VFS (5.5V) − VFS (4.5V)] × V2REF
5.5V − 4.5V
,
for the MAX11600/MAX11602/MAX11604, where N is the number of bits.
Note 12: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of
SCL’s falling edge (Figure 1).
Note 13: CB = total capacitance of one bus line in pF. tR, tFDA, and tF measured between 0.3VDD and 0.7VDD. The minimum value is
specified at TA = +25°C with CB = 400pF.
Note 14: fSCLH must meet the minimum clock low time plus the rise/fall times.
_______________________________________________________________________________________
5
MAX11600–MAX11605
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VDD = 3.3V (MAX11601/MAX11603/MAX11605), VDD = 5V (MAX11600/MAX11602/MAX11604), fSCL = 1.7MHz, external clock (33% duty
cycle), fSAMPLE = 188ksps, single ended, unipolar, TA = +25°C, unless otherwise noted.)
A
SDA = SCL = VDD
4
INTERNAL 4.096VREF
IDD (μA)
300
C
300
INTERNAL 2.048VREF
D
200
200
3.0
3.5
4.0
4.5
5.0
0
-40
5.5
-15
10
35
60
2.5
85
3.5
4.0
4.5
5.0
5.5
VDD (V)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (INTERNAL CLOCK)
AVERAGE SUPPLY CURRENT VS.
CONVERSION RATE (EXTERNAL CLOCK)
350
300
2
VDD = 5V
A
500
400
250
B
200
C
150
100
A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF
A
450
AVERAGE IDD (μA)
AVERAGE IDD (μA)
3
A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF
MAX11600 toc05
SDA = SCL = VDD
1
MAX11600 toc06
TEMPERATURE (°C)
4
350
300
B
250
200
C
150
100
50
INTERNAL CLOCK MODE
fSCL = 1.7MHz
VDD = 3.3V
0
-15
10
35
60
85
EXTERNAL CLOCK MODE
fSCL = 1.7MHz
50
0
-40
0
0
10
20
30
40
50
60
0
50
100
150
200
TEMPERATURE (°C)
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
NORMALIZED 4.096V REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL 4.096V REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL 2.048V REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.015
1.0050
1.0075
1.0050
1.0000
0.9975
VREF NORMALIZED
VREF NORMALIZED
1.010
1.0025
1.005
1.000
0.995
1.0025
1.0000
0.9975
0.9950
0.990
0.9950
0.9925
0.985
0.9925
0.9900
0.9900
0.980
4.00
4.25
4.50
4.75
VDD (V)
5.00
5.25
5.50
MAX11600 toc09
1.0075
1.0100
MAX11600 toc08
1.020
MAX11600 toc7
1.0100
6
3.0
VDD (V)
MAX11600 toc04
5
IDD (μA)
1
EXTERNAL 2.048VREF
150
150
3
2
EXTERNAL 4.096VREF
250
250
IDD (μA)
350
B
2.5
MAX11600 toc03
400
350
IDD (μA)
5
MAX11600 toc02
400
450
MAX11600 toc01
450
A) INTERNAL 4.096VREF
B) INTERNAL 2.048VREF
C) EXTERNAL 4.096VREF
D) EXTERNAL 2.048VREF
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. VOLTAGE
VREF NORMALIZED
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
-40
-15
10
35
60
85
2.5
3.0
3.5
TEMPERATURE (°C)
_______________________________________________________________________________________
4.0
VDD (V)
4.5
5.0
5.5
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
0.3
DNL (LSB)
1.005
1.000
0.995
0.990
0.985
0.980
35
60
0.3
0.2
0.1
0.1
0
-0.1
0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
85
-0.5
0
50
TEMPERATURE (°C)
100
150
200
250
0
300
50
1.0
MAX11600 toc13
fSAMPLE = 188ksps
fIN = 25kHz
-40
-60
-80
VREF = 2.048V
0.9
0.8
OFFSET ERROR (LSB)
-20
150
200
250
300
OFFSET ERROR vs. SUPPLY VOLTAGE
FFT PLOT
0
100
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
MAX11600 toc14
10
AMPLITUDE (dBc)
0.7
0.6
0.5
0.4
0.3
0.2
-100
0.1
-120
0
40k
60k
80k
100k
2.5
3.0
3.5
FREQUENCY (Hz)
OFFSET ERROR vs. TEMPERATURE
1.0
0.9
4.0
4.5
5.0
5.5
VDD (V)
GAIN ERROR vs. SUPPLY VOLTAGE
0
VDD = 3.3V
VREF = 2.048V
0.8
0.6
0.5
0.4
0.3
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
0.2
-0.08
0.1
-0.09
0
VREF = 2.048V
-0.01
GAIN ERROR (LSB)
0.7
MAX11600 toc16
20k
0
MAX11600 toc15
-15
0.4
0.2
-0.5
-40
OFFSET ERROR (LSB)
VREF NORMALIZED
1.010
MAX11600 toc12
0.4
INL (LSB)
1.015
0.5
MAX11600 toc11
0.5
MAX11600 toc10
1.020
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
INTERNAL 2.048V REFERENCE VOLTAGE
vs. TEMPERATURE
-0.1
-40
-15
10
35
TEMPERATURE (°C)
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
_______________________________________________________________________________________
7
MAX11600–MAX11605
Typical Operating Characteristics (continued)
(VDD = 3.3V (MAX11601/MAX11603/MAX11605), VDD = 5V (MAX11600/MAX11602/MAX11604), fSCL = 1.7MHz, external clock (33% duty
cycle), fSAMPLE = 188ksps, single ended, unipolar, TA = +25°C, unless otherwise noted.)
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
MAX11600–MAX11605
Pin Description
PIN
MAX11600
MAX11601
MAX11602
MAX11603
MAX11604
MAX11605
NAME
FUNCTION
1, 2, 3
12, 11, 10
12, 11, 10
AIN0, AIN1, AIN2
—
9–5
9–5
AIN3–AIN7
—
—
4, 3, 2
AIN8–AIN10
4
—
—
AIN3/REF
Analog Input 3/Reference Input/Output. Selected in the setup register
(see Tables 1 and 6).
—
1
—
REF
Reference Input/Output. Selected in the setup register (see Tables 1
and 6).
—
—
1
AIN11/REF
5
13
13
SCL
6
14
14
SDA
Data Input/Output
7
15
15
GND
Ground
8
16
16
VDD
Positive Supply. Bypass to GND with a 0.1µF capacitor.
—
2, 3, 4
—
N.C.
No Connection
Analog Inputs
Analog Input 11/Reference Input/Output. Selected in the setup
register (see Tables 1 and 6).
Clock Input
Detailed Description
The MAX11600–MAX11605 ADCs use successiveapproximation conversion techniques and input T/H circuitry to capture and convert an analog signal to a
serial 8-bit digital output. The MAX11600/MAX11601
are 4-channel ADCs, the MAX11602/MAX11603 are
8-channel ADCs and the MAX11604/MAX11605 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 3 shows the simplified functional diagram for the MAX11604/MAX11605.
Power Supply
The MAX11600–MAX11605 operate from a single supply
and consume 350µA at sampling rates up to 188ksps.
The MAX11601/MAX11603/MAX11605 feature a 2.048V
internal reference and the MAX11600/MAX11602/
MAX11604 feature a 4.096V internal reference. All
devices can be configured for use with an external reference from 1V to VDD.
Analog Input and Track/Hold
The MAX11600–MAX11605 analog input architecture
contains an analog input multiplexer (MUX), a T/H
capacitor, T/H switches, a comparator, and a switched
capacitor digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer connects CT/H to the analog input selected by CS[3:0] (see
the Configuration/Setup Bytes (Write Cycle) section). The
8
charge on CT/H is referenced to GND when converted. In
pseudo-differential mode, the analog input multiplexer
connects CT/H to the positive analog input selected by
CS[3:0]. The charge on CT/H is referenced to the negative analog input when converted.
The MAX11600–MAX11605 input configuration is
pseudo-differential in that only the signal at the positive
analog input is sampled with the T/H circuitry. The negative analog input signal must remain stable within
±0.5 LSB (±0.1 LSB for best results) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from the negative analog input to GND.
See the Single-Ended/Pseudo-Differential Input section.
During the acquisition interval, the T/H switches are in
the track position and CT/H charges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/H as a sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 8-bit resolution. This action
requires eight conversion clock cycles and is equivalent to transferring a charge of 18pF (VIN+ - VIN-)
from CT/H to the binary weighted capacitive DAC, forming a digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance below 1.5kΩ
does not significantly degrade sampling accuracy. To
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
tR
tF
MAX11600–MAX11605
a) F/S-MODE I2C SERIAL-INTERFACE TIMING
t
SDA
tSU.DAT
tHD.DAT
tHD.STA
tLOW
tBUF
tSU.STA
tSU.STO
SCL
tHD.STA
tHIGH
tR
tF
S
A
Sr
P
b) HS-MODE I2C SERIAL-INTERFACE TIMING
S
tRDA
tFDA
SDA
tSU.DAT
tHD.DAT
tBUF
tHD.STA
tLOW
tSU.STO
tSU.STA
SCL
tHD.STA
tHIGH
tRCL
tFCL
tRCL1
S
Sr
A
S
HS MODE
F/S MODE
Figure 1. I2C Serial-Interface Timing
minimize sampling errors with higher source impedances, connect a 100pF capacitor from the analog
input to GND. This input capacitor forms an RC filter
with the source impedance limiting the analog input
bandwidth. For larger source impedances, use a buffer
amplifier to maintain analog input signal integrity.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the ninth falling clock edge
of the address byte (see the Slave Address section).
The T/H circuitry enters hold mode two internal clock
cycles later. A conversion or a series of conversions is
then internally clocked (eight clock cycles per conversion) and the MAX11600–MAX11605 hold SCL low.
When operating in external clock mode, the T/H circuitry enters track mode on the seventh falling edge of a
valid slave address byte. Hold mode is then entered on
the falling edge of the eighth clock cycle. The conversion is performed during the next eight clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of input capacitance. If the
analog input source impedance is high, the acquisition
time lengthens and more time must be allowed
between conversions. The acquisition time (tACQ) is the
minimum time needed for the signal to be acquired. It is
calculated by:
VDD
IOL = 3mA
VOUT
SDA
400pF
IOH = 0mA
Figure 2. Load Circuit
tACQ ≥ 6.25 (RSOURCE + RIN) CIN
where RSOURCE is the analog input source impedance,
RIN = 2.5kΩ, and CIN = 18pF. tACQ is 1/fSCL for external
clock mode. For internal clock mode, the acquisition
time is two internal clock cycles. To select RSOURCE,
allow 625ns for tACQ in internal clock mode to account
for clock frequency variations.
_______________________________________________________________________________________
9
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
SDA
SCL
INPUT SHIFT REGISTER
VDD
INTERNAL
OSCILLATOR
CONTROL
LOGIC
SETUP REGISTER
GND
CONFIGURATION REGISTER
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11/REF
T/H
ANALOG
INPUT
MUX
OUTPUT SHIFT
REGISTER AND
12-BYTE RAM
8-BIT
ADC
REF
REFERENCE
4.096V (MAX11604)
2.048V (MAX11605)
MAX11604
MAX11605
THE MAX11600/MAX11601/MAX11604/MAX11605
USE THE SAME PIN FOR AIN_ AND REF, WHILE THE
MAX11602/MAX11603 USE DIFFERENT PINS.
SEE THE PIN DESCRIPTION SECTION.
Figure 3. MAX11604/MAX11605 Simplified Functional Diagram
ANALOG INPUT MUX
REF
CT/H
AIN2
AIN3/REF
GND
HOLD
HOLD
SINGLE ENDED
CAPACITIVE
DAC
TRACK
TRACK
AIN1
DIFFERENTIAL
AIN0
MAX11600
MAX11601
Figure 4. Equivalent Input Circuit
Analog Input Bandwidth
Analog Input Range and Protection
The MAX11600–MAX11605 feature input tracking circuitry with a 2MHz small signal bandwidth. The 2MHz
input bandwidth makes it possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Internal protection diodes clamp the analog input to
VDD and GND. These diodes allow the analog inputs to
swing from (GND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above VDD. If the analog input exceeds VDD by more
than 50mV, the input current should be limited to 2mA.
10
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SEL2
SEL1
SEL0
CLK
BIP/UNI
RST
X
BIT
NAME
DESCRIPTION
7
REG
Register bit. 1 = setup byte, 0 = configuration byte (Table 2).
6
SEL2
5
SEL1
4
SEL0
Three bits select the reference voltage and the state of AIN_/REF
(MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) (Table 6).
Default to 000 at power-up.
3
CLK
1 = external clock, 0 = internal clock. Defaulted to zero at power-up.
2
BIP/UNI
1
RST
0
X
1 = bipolar, 0 = unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section).
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t care; can be set to 1 or 0.
Single-Ended/Pseudo-Differential Input
Digital Interface
The SGL/DIF bit of the configuration byte configures the
MAX11600–MAX11605 analog input circuitry for singleended or pseudo-differential inputs (Table 2). In singleended mode (SGL/DIF = 1), the digital conversion results
are the difference between the analog input selected by
CS[3:0] and GND (Table 3). In pseudo-differential mode
(SGL/DIF = 0), the digital conversion results are the difference between the positive and the negative analog inputs
selected by CS[3:0] (Table 4). The negative analog input
signal must remain stable within ±0.5 LSB (±0.1 LSB for
best results) with respect to GND during a conversion.
The MAX11600–MAX11605 feature a 2-wire interface
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate bidirectional communication between the MAX11600–MAX11605 and the master at rates up to 1.7MHz. The MAX11600–MAX11605 are
slaves that transmit and receive data. The master (typically a microcontroller) initiates data transfer on the bus and
generates SCL to permit that transfer.
Unipolar/Bipolar
When operating in pseudo-differential mode, the BIP/
UNI bit of the setup byte (Table 1) selects unipolar or
bipolar operation. Unipolar mode sets the differential
analog input range from zero to VREF. A negative differential analog input in unipolar mode causes the digital
output code to be zero. Selecting bipolar mode sets the
differential input range to ±VREF/2, with respect to the
negative input. The digital output code is binary in
unipolar mode and two’s complement binary in bipolar
mode (see the Transfer Functions section).
In single-ended mode, the MAX11600–MAX11605
always operate in unipolar mode regardless of the
BIP/UNI setting, and the analog inputs are internally referenced to GND with a full-scale input range from zero
to VREF.
SDA and SCL must be pulled high. This is typically
done with pullup resistors (500Ω or greater) (see
Typical Operating Circuit ). Series resistors (RS) are
optional. They protect the input architecture of the
MAX11600–MAX11605 from high-voltage spikes on the
bus lines and minimize crosstalk and undershoot of the
bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data in or out of the MAX11600–MAX11605. The data
on SDA must remain stable during the high period of
the SCL clock pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). Both SDA and SCL idle high when
the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condition (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP
condition (P), a low-to-high transition on SDA, while
______________________________________________________________________________________
11
MAX11600–MAX11605
Table 1. Setup Byte Format
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
SCL is high (Figure 5). A repeated START condition (Sr)
can be used in place of a STOP condition to leave the
bus active and in its current timing mode (see the HS
Mode section).
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX11600–MAX11605 (slave) generate acknowledge bits. To generate an acknowledge bit,
the receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the clock
pulse (Figure 6). To generate a not acknowledge bit, the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge-related clock pulse and leaves
it high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt
communication at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address. When idle, the MAX11600–MAX11605
continuously wait for a START condition followed by
their slave address. When the MAX11600–MAX11605
recognize their slave address, they are ready to accept
or send data. The slave address has been factory programmed and is always 1100100 for the MAX11600/
MAX11601, 1101101 for MAX11602/MAX11603, and
1100101 for MAX11604/MAX11605 (Figure 7). The least
significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from
the MAX11600–MAX11605 (R/W = zero selects a write
condition. R/W = 1 selects a read condition). After
receiving the address, the MAX11600–MAX11605
(slave) issue an acknowledge by pulling SDA low for
one clock cycle.
Bus Timing
At power-up, the MAX11600–MAX11605 bus timing
defaults to fast mode (F/S mode), allowing conversion
rates up to 44ksps. The MAX11600–MAX11605 must
operate in high-speed mode (HS mode) to achieve
conversion rates up to 188ksps. Figure 1 shows the bus
timing for the MAX11600–MAX11605 2-wire interface.
HS Mode
At power-up, the MAX11600–MAX11605 bus timing is
set for F/S mode. The master selects HS mode by
12
S
P
Sr
SDA
SCL
Figure 5. START and STOP Conditions
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
SCL
1
2
8
9
Figure 6. Acknowledge Bits
addressing all devices on the bus with the HS mode
master code 0000 1XXX (X = don’t care). After successfully receiving the HS-mode master code, the
MAX11600–MAX11605 issues a not acknowledge,
allowing SDA to be pulled high for one clock cycle
(Figure 8). After the not acknowledge, the
MAX11600–MAX11605 are in HS mode. The master must
then send a repeated START followed by a slave
address to initiate HS mode communication. If the master generates a STOP condition, the MAX11600–
MAX11605 return to F/S mode.
Configuration/Setup Bytes (Write Cycle)
Write cycles begin with the master issuing a START
condition followed by 7 address bits (Figure 7) and 1
write bit (R/W = zero). If the address byte is successfully received, the MAX11600–MAX11605 (slave) issue an
acknowledge. The master then writes to the slave. The
slave recognizes the received byte as the setup byte
(Table 1) if the most significant bit (MSB) is 1. If the
MSB is zero, the slave recognizes that byte as the configuration byte (Table 2). The master can write either 1
or 2 bytes to the slave in any order (setup byte then
configuration byte; configuration byte then setup byte;
setup byte only; configuration byte only; Figure 9). If the
slave receives bytes successfully, it issues an acknowledge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS mode, a STOP condition returns the
bus to F/S mode (see the HS Mode section).
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
MAX11600–MAX11605
DEVICE
SLAVE ADDRESS
MAX11600/MAX11601
1100100
MAX11602/MAX11603
1101101
MAX11604/MAX11605
1100101
SLAVE ADDRESS
S
1
1
0
0
1
0
0
R/W
A
SDA
1
SCL
2
3
4
5
6
7
8
9
Figure 7. Slave Address Byte
HS MODE MASTER CODE
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
F/S MODE
HS MODE
Figure 8. F/S Mode to HS Mode Transfer
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by 7 address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX11600–MAX11605 (slave) issue an
acknowledge. The master then reads from the slave.
After the master has received the results, it can issue
an acknowledge if it wants to continue reading or a not
acknowledge if it no longer wishes to read. If the
MAX11600–MAX11605 receive a not acknowledge,
they release SDA, allowing the master to generate a
STOP or repeated START. See the Clock Mode and
Scan Mode sections for detailed information on how
data is obtained and converted.
Clock Mode
The clock mode determines the conversion clock, the
acquisition time, and the conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s CLK bit determines the clock mode (Table
1). At power-up, the MAX11600–MAX11605 default to
internal clock mode (CLK = zero).
Internal Clock
When configured for internal clock mode (CLK = zero),
the MAX11600–MAX11605 use their internal oscillator
as the conversion clock. In internal clock mode, the
MAX11600–MAX11605 begin tracking analog input on
the ninth falling clock edge of a valid slave address
byte. Two internal clock cycles later, the analog signal
is acquired and the conversion begins. While tracking
and converting the analog input signal, the
MAX11600–MAX11605 hold SCL low (clock stretching).
After the conversion completes, the results are stored in
______________________________________________________________________________________
13
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. 1-BYTE WRITE CYCLE
1
7
1 1
S
SLAVE ADDRESS
W A
8
1
1
NUMBER OF BITS
SETUP OR
A P OR Sr
CONFIGURATION BYTE
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. 2-BYTE WRITE CYCLE
7
1 1
1
S
SLAVE ADDRESS
W A
8
1
SETUP OR
CONFIGURATION BYTE
A
8
1
1
NUMBER OF BITS
SETUP OR
A P OR Sr
CONFIGURATION BYTE
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
random access memory (RAM). If the scan mode is set
for multiple conversions, they all happen in succession
with each additional result being stored in RAM. The
MAX11600/MAX11601 contain 8 bytes of RAM, the
MAX11602/MAX11603 contain 8 bytes of RAM, and the
MAX11604/MAX11605 contain 12 bytes of RAM. Once
all conversions are complete, the MAX11600–
MAX11605 release SCL, allowing it to be pulled high.
The master can now clock the results out of the output
shift register at a clock rate of up to 1.7MHz. SCL is
stretched for a maximum acquisition and conversion
time of 7.6µs per channel (Figure 10).
The device RAM contains all of the conversion results
when the MAX11600–MAX11605 release SCL. The converted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from
a multichannel scan. This does not apply to the
MAX11602/MAX11603 as each provides separate pins
for AIN7 and REF. RAM contents can be read continuously. If reading continues past the last result stored in
RAM, the pointer wraps around and points to the first
result. Note that only the current conversion results are
read from memory. The device must be addressed with
a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during conversion. Using the internal clock also frees the master
(typically a microcontroller) from the burden of running
the conversion clock.
14
External Clock
When configured for external clock mode (CLK = 1),
the MAX11600–MAX11605 use SCL as the conversion
clock. In external clock mode, the MAX11600–
MAX11605 begin tracking the analog input on the seventh falling clock edge of a valid slave address byte.
One SCL clock cycle later, the analog signal is
acquired and the conversion begins. Unlike internal
clock mode, converted data is available immediately
after the slave-address acknowledge bit. The device
continuously converts input channels dictated by the
scan mode until given a not acknowledge. There is no
need to re-address the device with a read command to
obtain new conversion results (Figure 11).
The conversion must complete in 9ms or droop on the
T/H capacitor degrades conversion results. Use internal
clock mode if the SCL clock period exceeds 1ms.
The MAX11600–MAX11605 must operate in external
clock mode for conversion rates up to 188ksps.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan-mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference input
or output (SEL1 = 1, Table 6), AIN_/REF is excluded
from a multichannel scan. This does not apply to the
MAX11602/MAX11603 as each provides separate pins
for AIN7 and REF.
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
REG
SCAN1
SCAN0
CS3
CS2
CS1
CS0
SGL/DIF
BIT
7
6
5
4
3
2
1
NAME
REG
SCAN1
SCAN0
CS3
CS2
CS1
CS0
0
SGL/DIF
DESCRIPTION
Register bit. 1 = setup byte (Table 1), 0 = configuration byte.
Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at
power-up.
Channel select bits. Four bits select which analog input channels are to be used for conversion
(Tables 3 and 4). Default to 0000 at power-up. For the MAX11600/MAX11601, CS3 and CS2 are
internally set to 0. For the MAX11602/MAX11603, CS3 is internally set to zero.
1 = single-ended, 0 = pseudo-differential (Tables 3 and 4). Default to 1 at power-up (see the
Single-Ended/Pseudo-Differential Input section).
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the
reference and AIN_/REF (MAX11600/MAX11601/
MAX11604/MAX11605) configured as an analog input.
For the MAX11602/MAX11603, the REF pin is floating
after power-up. The RAM contents are unknown after
power-up.
Automatic Shutdown
SEL[2:0] of the setup byte (Tables 1 and 6) controls the
state of the reference and AIN_/REF (MAX11600/
MAX11601/MAX11604/MAX11605) or REF (MAX11602/
MAX11603). If automatic shutdown is selected (SEL[2:0] =
100), shutdown occurs between conversions when the
MAX11600–MAX11605 are idle. When operating in external clock mode, a STOP condition must be issued to place
the devices in idle mode and benefit from automatic shutdown. A STOP condition is not necessary in internal clock
mode to benefit from automatic shutdown because powerdown occurs once all contents are written to memory
(Figure 10). All analog circuitry is inactive in shutdown and
supply current is less than 1µA. The digital conversion
results are maintained in RAM during shutdown and are
available for access through the serial interface at any
time prior to a STOP or repeated START condition.
When idle, the MAX11600–MAX11605 wait for a START
condition followed by their slave address (see the
Slave Address section). Upon reading a valid address
byte, the MAX11600–MAX11605 power up. The analog
circuits do not require any wakeup time from shutdown,
whether using external or internal reference.
Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates. For example, at a
conversion rate of 10ksps, the average supply current
for the MAX1036 is 8µA and drops to 2µA at 1ksps.
At 0.1ksps the average supply current is just 1µA (see
Average Supply Current vs. Conversion Rate in the
Typical Operating Characteristics section).
Reference Voltage
SEL[2:0] of the setup byte (Table 1) controls the reference and the AIN_/REF (MAX11600/MAX11601/
MAX11604/MAX11605) or REF (MAX11602/MAX11603)
configuration (Table 6). When AIN_/REF (MAX11600/
MAX11601/MAX11604/MAX11605) is configured to be
a reference input or reference output (SEL1 = 1), conversions on AIN_/REF appear as if AIN_/REF is connected to GND (see note 2 of Tables 3 and 4).
Internal Reference
The internal reference is 4.096V for the MAX11600/
MAX11602/MAX11604 and 2.048V for the MAX11601/
MAX11603/MAX11605. SEL1 of the setup byte controls
whether AIN_/REF (MAX11600/MAX11601/MAX11604/
MAX11605) is used for an analog input or a reference
(Table 6). When AIN_/REF (MAX11600/MAX11601/
MAX11604/MAX11605) or REF (MAX11602/MAX11603) is
configured to be an internal reference output (SEL[2:1] =
11), decouple AIN_/REF (MAX11600/MAX11601/
MAX11604/MAX11605) or REF (MAX11602/MAX11603)
to GND with a 0.01µF capacitor. Due to the decoupling
capacitor and the 675Ω reference source impedance,
allow 80µs for the reference to stabilize during initial
power-up. Once powered up, the reference always
remains on until reconfigured. The reference should not
be used to supply current for external circuitry. When the
MAX11602/MAX11603 is in shutdown, the internal reference output is in a high-impedance state.
______________________________________________________________________________________
15
MAX11600–MAX11605
Table 2. Configuration Byte Format
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
1 1
S SLAVE ADDRESS R A
1
8
tACQ
NUMBER OF BITS
A P or Sr
RESULT
CLOCK STRETCH
1
tCONV
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
7
1
1
1
8
S SLAVE ADDRESS R A
CLOCK STRETCH
CLOCK STRETCH
tACQ1
tACQ2
tCONV2
tCONV1
1
8
1
8
RESULT 1 A RESULT 2 A
1
1
NUMBER OF BITS
RESULT N A P OR Sr
tACQN
tCONVN
NOTE: tACQ + tCONV ≤ 7.6μs PER CHANNEL.
Figure 10. Internal Clock Mode Read Cycles
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
1 1
8
1
1
S
SLAVE ADDRESS
R A
RESULT
A
P OR Sr
tACQ
NUMBER OF BITS
tCONV
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
7
1 1
8
1
8
1
8
S
SLAVE ADDRESS
R A
RESULT 1
A
RESULT 2
A
RESULT N
tACQ1
tCONV1
tACQ2
tCONV2
1
1
NUMBER OF BITS
A P OR Sr
tACQN
tCONVN
Figure 11. External Clock Mode Read Cycles
16
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
1
2
CS31
CS21
CS1
CS0
AIN0
0
0
0
0
+
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
AIN1
AIN2
AIN32
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10 AIN112 GND
-
+
+
+
+
+
+
+
+
+
+
+
-
For the MAX11600/MAX11601, CS3 and CS2 are internally set to zero. For the MAX11602/MAX11603, CS3 is internally set to zero.
When SEL1 = 1, a single-ended read of AIN3/REF (MAX11600/MAX11601) or AIN11/REF (MAX11604/MAX11605) returns GND. This
does not apply to the MAX11602/MAX11603 as each provides separate pins for AIN7 and REF.
______________________________________________________________________________________
17
MAX11600–MAX11605
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
Table 4. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)1
1
2
3
CS32
CS22
CS1
CS0
AIN0
AIN1
AIN2
AIN32
0
0
0
0
+
-
0
0
0
1
-
+
0
0
1
0
+
-
0
0
0
1
1
1
-
+
0
0
0
+
-
1
0
1
-
+
0
1
1
0
+
-
0
1
1
1
-
+
1
0
0
1
0
1
0
1
AIN4
AIN5
AIN6
AIN7
AIN10 AIN113
AIN8
AIN9
0
+
-
0
1
-
+
1
0
+
-
0
1
1
-
+
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
When scanning multiple channels (SCAN0 = 0), CS0 = 0 causes the even-numbered channel-select bits to be scanned, while CS0 = 1
causes the odd-numbered channel-select bits to be scanned. For example, if the MAX11604/MAX11605 SCAN[1:0] = 00 and CS[3:0] =
1010, a pseudo-differential read returns AIN0–AIN1, AIN2–AIN3, AIN4–AIN5, AIN6–AIN7, AIN8–AIN9, and AIN10–AIN11. If the
MAX11604/MAX11605 SCAN[1:0] = 00 and CS[3:0] = 1011, a pseudo-differential read returns AIN1–AIN0, AIN3–AIN2, AIN5–AIN4,
AIN7–AIN6, AIN9–AIN8, and AIN11–AIN10.
For the MAX11600/MAX11601, CS3 and CS2 are internally set to zero. For the MAX11602/MAX11603, CS3 is internally set to zero.
When SEL1 = 1, a pseudo-differential read between AIN2 and AIN3/REF (MAX11600/MAX11601) or AIN10 and AIN11/REF
(MAX11604/MAX11605) returns the difference between GND and AIN2 or AIN10, respectively. For example, a pseudo-differential
read of 1011 returns the negative difference between AIN10 and GND. This does not apply to the MAX11602/MAX11603 as each provides separate pins for AIN7 and REF.
18
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
SCAN1
SCAN0
0
0
Scans up from AIN0 to the input selected by CS3–CS0 (default setting).
SCANNING CONFIGURATION
0
1
Converts the input selected by CS3–CS0 eight times.*
MAX11600/MAX11601: Scans upper half of channels.
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0, AIN1, and
AIN2, the scanning stops at AIN2 (MAX11600/MAX11601).
1
0
MAX11602/MAX11603: Scans upper quartile of channels.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the scanning
stops at AIN6 (MAX11602/MAX11603).
MAX11604/MAX11605: Scans upper half of channels.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the scanning
stops at AIN6 (MAX11604/MAX11605).
1
1
Converts the channel selected by CS3–CS0.*
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting continues
until a not acknowledge occurs.
Table 6. Reference Voltage, AIN_/REF, and REF Format
SEL2
SEL1
SEL0
REFERENCE
VOLTAGE
0
0
X
VDD
AIN_/REF
(MAX11600/
MAX11601/
MAX11604/
MAX11605)
Analog input
0
1
X
External reference
Reference input
Reference input
Always off
1
0
0
Internal reference
Analog input
Not connected
AutoShutdown
1
0
1
Internal reference
Analog input
Not connected
Always on
1
1
X
Internal reference
Reference output
Reference output
Always on
REF
(MAX11602/
MAX11603)
INTERNAL
REFERENCE STATE
Not connected
Always off
X = Don’t care.
External Reference
The external reference can range from 1.0V to VDD. For
maximum conversion accuracy, the reference must be
able to deliver up to 30µA and have an output impedance
of 1kΩ or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close as possible to
AIN_/REF (MAX11600/MAX11601/MAX11604/MAX11605)
or REF (MAX11602/MAX11603) with a 0.1µF capacitor.
Transfer Functions
Output data coding for the MAX11600–MAX11605 is
binary in unipolar mode and two’s complement binary in
bipolar mode with 1 LSB = VREF/2N where N is the number of bits (8). Code transitions occur halfway between
successive-integer LSB values. Figures 12 and 13 show
the input/output (I/O) transfer functions for unipolar and
bipolar operations, respectively.
______________________________________________________________________________________
19
MAX11600–MAX11605
Table 5. Scanning Configuration
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
OUTPUT CODE
1 LSB =
VREF
256
REF
1...111
1...110
1...101
1...100
OUTPUT CODE
(TWO'S COMPLEMENT)
1 LSB =
VREF
256
REF
0...111
0...110
0...101
0...100
0...001
0...000
1...111
1...011
1...010
1...001
1...000
0...011
0...010
0...001
0...000
0
1
2
3
252 253 254 255 256
-128 -127 -126 -125
-1
0
+1
+124 +125 +126 +127 +128
NEGATIVE INPUT
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 12. Unipolar Transfer Function
Figure 13. Bipolar Transfer Function
Layout, Grounding, and Bypassing
SUPPLIES
3V/5V
VLOGIC = 3V/5V
GND
R* = 5Ω
0.1μF
VDD
GND
MAX11600–
MAX11605
3V/5V
DGND
DIGITAL
CIRCUITRY
*OPTIONAL
For best performance, use PC boards. Wire-wrap configurations are not recommended since the layout should
ensure proper separation of analog and digital traces. Do
not run analog and digital lines parallel to each other, and
do not lay out digital signal paths underneath the ADC
package. Use separate analog and digital PCB ground
sections with only one star point (Figure 14) connecting
the two ground systems (analog and digital). For lowest
noise operation, ensure the ground return to the star
ground’s power supply is low impedance and as short as
possible. Route digital signals far away from sensitive
analog and reference inputs.
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast
comparator. Bypass V DD to the star ground with a
0.1µF capacitor located as close as possible to the
MAX11600–MAX11605 power-supply pin. Minimize
capacitor lead length for best supply-noise rejection,
and add an attenuation resistor (5Ω) if the power supply is extremely noisy.
Figure 14. Power-Supply and Grounding Connections
20
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The INL
is measured using the end point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (t AD ) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = (6.02 N + 1.76)dB
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20 log (SignalRMS/NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fundamental itself. This is expressed as:
⎛
⎞
THD = 20 × log ⎜ ⎛⎝ V2 2 + V3 2 + V4 2 + V5 2 ⎞⎠ / V1 ⎟
⎝
⎠
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion
component.
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________
21
MAX11600–MAX11605
Definitions
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
MAX11600–MAX11605
Pin Configurations
Typical Operating Circuit
5V
TOP VIEW
VDD
+
AIN0 1
8
VDD
AIN1 2
7
GND
6
SDA
5
SCL
AIN2
MAX11600
MAX11601
3
AIN3/REF 4
AIN0
AIN1
AIN2
AIN3/REF
ANALOG
INPUTS
*RS
MAX11600–
MAX11605
SDA
SCL
*RS
GND
5V
SOT23
RP
5V
+
(REF) AIN11/REF 1
16 VDD
(N.C.) AIN10 2
15 GND
(N.C.) AIN9 3
14 SDA
(N.C.) AIN8 4
AIN7 5
MAX11602–
MAX11605
μC
SDA
SCL
13 SCL
12 AIN0
AIN6 6
11 AIN1
AIN5 7
10 AIN2
AIN4 8
9
QSOP
RP
*OPTIONAL
Package Information
AIN3
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
( ) INDICATES PINS ON THE MAX11602/MAX11603.
22
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 SOT23
K8CN+2
21-0078
16 QSOP
E16+4
21-0055
______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
PAGES
CHANGED
REVISION
NUMBER
REVISION
DATE
0
4/09
Introduction of the MAX11600/MAX11601/MAX11603
—
1
7/09
Introduction of the MAX11602/MAX11604/MAX11605
1
DESCRIPTION
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX11600–MAX11605
Revision History