Electrical Specifications Subject to Change LTC2175-14/ LTC2174-14/LTC2173-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Quad ADCs FEATURES DESCRIPTION n The LTC®2175-14/2174-14/2173-14 are 4-channel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.4dB SNR and 88dB spurious free dynamic range (SFDR). Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. n n n n n n n n n n n 4-Channel Simultaneous Sampling ADC 73.4dB SNR 88dB SFDR Low Power: 558mW/450mW/376mW Single 1.8V Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 52-Pin (7mm × 8mm) QFN Package DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2 LSBRMS. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. APPLICATIONS n n n n n n Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multichannel Data Acquisition Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. TYPICAL APPLICATION 1.8V VDD CHANNEL 1 ANALOG INPUT S/H LTC2175-14, 125Msps, 2-Tone FFT, fIN = 70MHz and 75MHz 1.8V OVDD 14-BIT ADC CORE OUT1A 0 OUT1B –10 14-BIT ADC CORE OUT2A –20 CHANNEL 3 ANALOG INPUT CHANNEL 4 ANALOG INPUT ENCODE INPUT S/H DATA SERIALIZER S/H 14-BIT ADC CORE OUT3A OUT4A S/H 14-BIT ADC CORE OUT3B OUT4B DATA CLOCK OUT PLL –30 OUT2B FRAME SERIALIZED LVDS OUTPUTS AMPLITUDE (dBFS) CHANNEL 2 ANALOG INPUT –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 TA01b GND OGND 217514 TA01 21754314p 1 LTC2175-14/ LTC2174-14/LTC2173-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATIONS (Notes 1, 2) OUT1B– OUT1B+ OUT1A– OUT1A+ GND SDO PAR/SER VREF GND SENSE VDD TOP VIEW VDD Supply Voltages VDD, OVDD................................................ –0.3V to 2V Analog Input Voltage (AIN+, AIN–, PAR/SER, SENSE) (Note 3) ...........–0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4) .................................... –0.3V to 3.9V SDO (Note 4) ............................................ –0.3V to 3.9V Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2175C, 2174C, 2173C ........................ 0°C to 70°C LTC2175I, 2174I, 2173I ....................... –40°C to 85°C Storage Temperature Range................... –65°C to 150°C 52 51 50 49 48 47 46 45 44 43 42 41 AIN1+ 1 40 OUT2A+ – 2 39 OUT2A– VCM12 3 38 OUT2B+ AIN1 + 4 37 OUT2B– – 5 36 DCO+ REFH 6 35 DCO– AIN2 AIN2 REFH 7 34 OVDD 53 REFL 8 33 OGND REFL 9 32 FR+ + 31 FR– – AIN3 11 30 OUT3A+ VCM34 12 29 OUT3A– AIN3 10 + 28 OUT3B+ AIN4 13 AIN4– 14 27 OUT3B– OUT4A+ OUT4A– OUT4B+ OUT4B– GND SDI SCK CS ENC– ENC+ VDD VDD 15 16 17 18 19 20 21 22 23 24 25 26 UKG PACKAGE 52-LEAD (7mm × 8mm) PLASTIC QFN TJMAX = 150°C, θJA = 28°C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2175CUKG-14#PBF LTC2175CUKG-14#TRPBF LTC2175UKG-14 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C LTC2175IUKG-14#PBF LTC2175IUKG-14#TRPBF LTC2175UKG-14 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C LTC2174CUKG-14#PBF LTC2174CUKG-14#TRPBF LTC2174UKG-14 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C LTC2174IUKG-14#PBF LTC2174IUKG-14#TRPBF LTC2174UKG-14 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C LTC2173CUKG-14#PBF LTC2173CUKG-14#TRPBF LTC2173UKG-14 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C LTC2173IUKG-14#PBF LTC2173IUKG-14#TRPBF LTC2173UKG-14 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 21754314p 2 LTC2175-14/ LTC2174-14/LTC2173-14 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2175-14 PARAMETER CONDITIONS MIN l Resolution (No Missing Codes) MAX MIN ±1 3.75 ±0.3 MAX MIN TYP MAX –3.75 ±1 3.75 –3.5 ±1 3.5 LSB 0.9 –0.9 ±0.3 0.9 –0.9 ±0.3 0.9 LSB 15 –15 ±3 –1.5 ±1.5 ±0.4 15 –15 ±3 15 mV –1.5 ±1.5 ±0.4 1.5 %FS %FS 14 Differential Analog Input (Note 6) l –3.75 Differential Linearity Error Differential Analog Input l –0.9 Offset Error (Note 7) l –15 ±3 Gain Error Internal Reference External Reference –1.5 ±1.5 ±0.4 Offset Drift LTC2173-14 TYP 14 Integral Linearity Error l LTC2174-14 TYP 1.5 UNITS 14 1.5 Bits ±20 ±20 ±20 μV/°C Full-Scale Drift Internal Reference External Reference ±35 ±25 ±35 ±25 ±35 ±25 ppm/°C ppm/°C Gain Matching External Reference ±0.2 ±0.2 ±0.2 %FS ±3 ±3 ±3 mV External Reference 1.2 1.2 1.2 LSBRMS Offset Matching Transition Noise ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(CM) Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ + AIN–)/2 VSENSE External Voltage Reference Applied to SENSE External Reference Mode IINCM Analog Input Common Mode Current Per Pin, 125Msps Per Pin, 105Msps Per Pin, 80Msps IIN1 Analog Input Leakage Current No Encode 0 < AIN+, AIN– < VDD, l –1 1 μA IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –3 3 μA IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –6 6 μA tAP Sample-and-Hold Acquisition Delay Time 0 tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 VIN CMRR Analog Input Common Mode Rejection Ratio BW-3B Full-Power Bandwidth 1.7V < VDD < 1.9V l Differential Analog Input (Note 8) l VCM – 100mV VCM VCM + 100mV V l 0.625 1.250 1.300 V Figure 6 Test Circuit 1 to 2 VP-P 155 130 100 μA μA μA ns psRMS 80 dB 800 MHz 21754314p 3 LTC2175-14/ LTC2174-14/LTC2173-14 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) LTC2175-14 SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input 70MHz Input 140MHz Input SFDR S/(N+D) MAX LTC2174-14 MAX LTC2173-14 MIN TYP MIN TYP MIN TYP l 71.3 73.4 73.2 72.7 71.3 73.4 73.2 72.7 70.9 73.1 72.9 72.4 MAX UNITS dBFS dBFS dBFS Spurious Free Dynamic Range 5MHz Input 2nd or 3rd Harmonic 70MHz Input 140MHz Input l 76 88 85 82 76 88 85 82 79 88 85 82 dBFS dBFS dBFS Spurious Free Dynamic Range 5MHz Input 4th Harmonic or Higher 70MHz Input 140MHz Input l 85 90 90 90 83 90 90 90 85 90 90 90 dBFS dBFS dBFS l 70.2 73 72.6 72 70.2 73 72.6 72 70.4 72.9 72.6 72 dBFS dBFS dBFS Signal-to-Noise Plus Distortion Ratio 5MHz Input 70MHz Input 140MHz Input Crosstalk, Near Channel 10MHz Input (Note 12) –90 –90 –90 dBc Crosstalk, Far Channel 10MHz Input (Note 12) –105 –105 –105 dBc INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) PARAMETER CONDITIONS VCM Output Voltage IOUT = 0 MIN TYP MAX 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV VCM Output Temperature Drift ±25 VCM Output Resistance –600μA < IOUT < 1mA VREF Output Voltage IOUT = 0 VREF Output Temperature Drift 1.250 ±25 VREF Output Resistance –400μA < IOUT < 1mA VREF Line Regulation 1.7V < VDD < 1.9V 7 0.6 V ppm/°C 4 1.225 UNITS Ω 1.275 V ppm/°C Ω mV/V 21754314p 4 LTC2175-14/ LTC2174-14/LTC2173-14 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 1.6 V V l 0.2 3.6 V VIN Input Voltage Range ENC+, ENC– to GND RIN Input Resistance (See Figure 10) CIN Input Capacitance V 1.2 10 kΩ 3.5 pF Single-Ended Encode Mode (ENC– Tied to GND) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l VIN Input Voltage Range ENC+ to GND l RIN Input Resistance (See Figure 11) CIN Input Capacitance 1.2 V 0.6 0 3.6 V V 30 kΩ 3.5 pF DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l VIN = 0V to 3.6V l IIN Input Current CIN Input Capacitance 1.3 V –10 0.6 V 10 μA 3 pF 200 Ω SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used) ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V IOH Logic High Output Leakage Current SDO = 0V to 3.6V COUT Output Capacitance l –10 10 3 μA pF DIGITAL DATA OUTPUTS VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 247 125 350 175 454 250 VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 1.125 1.125 1.250 1.250 1.375 1.375 RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 mV mV V V Ω 21754314p 5 LTC2175-14/ LTC2174-14/LTC2173-14 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2175-14 SYMBOL PARAMETER CONDITIONS LTC2174-14 LTC2173-14 MIN TYP MAX MIN TYP MAX MIN TYP VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 MAX UNITS OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 283 TBD 224 TBD 184 TBD mA IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 27 49 TBD TBD 26 48 TBD TBD 25 47 TBD TBD mA mA PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 558 598 TBD TBD 450 490 TBD TBD 376 416 TBD TBD mW mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 85 85 85 mW PDIFFCLK Power Increase With Differential Encode Mode Enabled (No Increase for Sleep Mode) 20 20 20 mW 1.9 V TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2175-14 SYMBOL PARAMETER CONDITIONS fS Sampling Frequency (Notes 10,11) l MIN 5 tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 tAP Sample-and-Hold Acquisition Delay Time SYMBOL PARAMETER TYP LTC2174-14 MAX MIN 125 5 4 4 100 100 4.52 2 4 4 100 100 4.52 2 0 TYP LTC2173-14 MAX MIN 105 5 4.76 4.76 100 100 5.93 2 4.76 4.76 100 100 5.93 2 0 CONDITIONS MIN TYP MAX MHz 6.25 6.25 100 100 ns ns 6.25 6.25 100 100 ns ns 0 TYP UNITS 80 ns MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output) 1/(8 • fS) 1/(7 • fS) 1/(6 • fS) 1/(16 • fS) 1/(14 • fS) 1/(12 • fS) s s s s s s tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tPD Propagation Delay (Note 8) l tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns Pipeline Latency 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s 60 psP-P 6 Cycles 21754314p 6 LTC2175-14/ LTC2174-14/LTC2173-14 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SPI Port Timing (Note 8) l l 40 250 ns ns CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid tSCK SCK Period tS Write Mode Readback Mode, CSDO = 20pF, RPULLUP = 2k Readback Mode, CSDO = 20pF, RPULLUP = 2k Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2175), 105MHz (LTC2174), or 80MHz (LTC2173), 2-lane output mode, differential ENC+/ ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. l 125 ns Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2175), 105MHz (LTC2174), or 80MHz (LTC2173), 2-lane output mode, ENC+ = singleended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential drive, unless otherwise noted. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so tSER must be greater than or equal to 1ns. Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4. Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and Ch.2 to Ch.4. 21754314p 7 LTC2175-14/ LTC2174-14/LTC2173-14 TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization* tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– tDATA tSER FR+ tPD OUT#A– OUT#A+ OUT#B– OUT#B+ tSER D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217514 TD01 *SEE THE DIGITAL OUTPUTS SECTION 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+2 N tENCH ENC– N+1 tENCL ENC+ tSER DCO– DCO+ tFRAME FR– tDATA tSER FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ tPD tSER D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 217514 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 21754314p 8 LTC2175-14/ LTC2174-14/LTC2173-14 TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N N+1 tENCH ENC– tENCL ENC+ tSER DCO– DCO+ FR+ tFRAME tDATA tPD tSER tSER FR– OUT#A– OUT#A+ OUT#B– OUT#B+ D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217514 TD03 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– tDATA tSER FR+ OUT#A– OUT#A+ tPD D1 D0 SAMPLE N-6 0 tSER 0 D13 D12 D11 D10 D9 SAMPLE N-5 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D13 D12 D11 D10 SAMPLE N-4 217514 TD05 OUT#B+, OUT#B– ARE DISABLED 21754314p 9 LTC2175-14/ LTC2174-14/LTC2173-14 TIMING DIAGRAMS One-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– tDATA tSER FR+ OUT#A– OUT#A+ tPD D3 D2 tSER D1 D0 D13 D12 D11 D10 D9 SAMPLE N-6 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 SAMPLE N-5 SAMPLE N-4 217514 TD06 OUT#B+, OUT#B– ARE DISABLED One-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC– tENCL ENC+ tSER DCO– DCO+ tFRAME FR– tDATA tSER FR+ OUT#A– OUT#A+ tPD D5 D4 D3 tSER D2 D13 D12 D11 D10 D9 SAMPLE N-6 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11 SAMPLE N-5 SAMPLE N-4 217514 TD07 OUT#B+, OUT#B– ARE DISABLED SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI R/W A6 A5 A4 A3 A2 A1 A0 SDO XX D7 HIGH IMPEDANCE XX D6 XX D5 XX D4 XX D3 XX D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI R/W SDO HIGH IMPEDANCE A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 217514 TD04 21754314p 10 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2175-14: Integral Nonlinearity (INL) LTC2175-14: Differential Nonlinearity (DNL) 2.0 1.0 0 1.5 0.8 –10 –20 0.6 0.5 0 –0.5 –1.0 –30 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) 1.0 INL ERROR (LSB) LTC2175-14: 8k Point FFT, fIN = 5MHz –1dBFS, 125Msps 0.2 0 –0.2 –0.4 –2.0 –0.8 0 4096 8192 12288 OUTPUT CODE –1.0 16384 –70 –80 –110 –120 0 4096 8192 12288 OUTPUT CODE 217514 G01 0 16384 LTC2175-14: 8k Point FFT, fIN = 70MHz –1dBFS, 125Msps –20 –20 –20 –30 –30 –30 –70 –80 AMPLITUDE (dBFS) 0 –10 AMPLITUDE (dBFS) 0 –10 –60 –40 –50 –60 –70 –80 –40 –60 –70 –80 –90 –100 –90 –100 –110 –120 –110 –120 –110 –120 10 20 30 40 FREQUENCY (MHz) 50 0 60 10 20 30 40 FREQUENCY (MHz) 50 0 60 LTC2175-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 125Msps 60 74 73 5000 72 –30 –50 SNR (dBFS) 4000 –40 COUNT AMPLITUDE (dBFS) 50 LTC2175-14: SNR vs Input Frequency, –1dB, 2V Range, 125Msps LTC2175-14: Shorted Input Histogram –10 –20 20 30 40 FREQUENCY (MHz) 217514 G06 6000 0 10 217514 G05 217514 G04 60 –50 –90 –100 0 50 LTC2175-14: 8k Point FFT, fIN = 140MHz –1dBFS, 125Msps 0 –50 20 30 40 FREQUENCY (MHz) 217514 G03 –10 –40 10 217514 G02 LTC2175-14: 8k Point FFT, fIN = 30MHz –1dBFS, 125Msps AMPLITUDE (dBFS) –60 –90 –100 –0.6 –1.5 –40 –50 –60 3000 –70 –80 2000 –90 –100 1000 71 70 69 68 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G07 0 8178 67 8180 8182 8184 OUTPUT CODE 8186 217514 G08 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 217514 G09 21754314p 11 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2175-14: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps 110 95 80 90 70 80 75 80 70 dBc 60 60 SNR (dBc AND dBFS) SFDR (dBc AND dBFS) 90 85 50 40 30 dBc 50 40 30 20 20 70 10 10 65 dBFS dBFS 100 SFDR (dBFS) LTC2175-14: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps LTC2175-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 350 217514 G10 0 –60 0 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 217514 G11 LTC2175-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 217514 G50 LTC2175-14: SNR vs SENSE, fIN = 5MHz, –1dB IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 50 290 0 74 2-LANE, 3.5mA 280 73 40 72 250 240 230 1-LANE, 3.5mA 30 71 SNR (dBFS) 260 IOVDD (mA) IVDD (mA) 270 2-LANE, 1.75mA 20 70 69 1-LANE, 1.75mA 10 68 220 210 67 0 0 25 50 75 100 SAMPLE RATE (Msps) 125 0 25 50 75 100 SAMPLE RATE (Msps) 0.6 LTC2174-14: Integral Nonlinearity (INL) 0 1.5 0.8 –10 0.4 0.2 0 –0.2 –0.4 –2.0 –0.8 0 4096 8192 12288 OUTPUT CODE 16384 217514 G14 –1.0 –40 –50 –60 –70 –80 –90 –100 –0.6 –1.5 1.3 –30 AMPLITUDE (dBFS) DNL ERROR (LSB) –1.0 1.2 –20 0.6 1.0 –0.5 0.9 1 1.1 SENSE PIN (V) LTC2174-14: 8k Point FFT, fIN = 5MHz –1dBFS, 105Msps LTC2174-14: Differential Nonlinearity (DNL) 1.0 0 0.8 217514 G12 2.0 0.5 0.7 217514 G51 217514 G53 INL ERROR (LSB) 66 125 –110 –120 0 4096 8192 12288 OUTPUT CODE 16384 217514 G15 0 10 20 30 40 FREQUENCY (MHz) 50 217514 G16 21754314p 12 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2174-14: 8k Point FFT, fIN = 70MHz –1dBFS, 105Msps LTC2174-14: 8k Point FFT, fIN = 140MHz –1dBFS, 105Msps 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) 0 –10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2174-14: 8k Point FFT, fIN = 30MHz –1dBFS, 105Msps –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –100 –90 –100 –90 –100 –110 –120 –110 –120 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 0 50 10 20 30 40 FREQUENCY (MHz) 50 0 217514 G19 LTC2174-14: Shorted Input Histogram 6000 0 74 73 5000 –20 72 –30 –50 SNR (dBFS) 4000 –40 COUNT 3000 –60 –70 –80 2000 –90 –100 1000 71 70 69 68 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 67 0 8195 50 8197 8199 8201 OUTPUT CODE 66 8203 95 100 90 230 220 SFDR (dBc AND dBFS) 80 70 60 210 dBc 50 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 217514 G23 190 180 30 170 10 0 200 40 20 70 350 dBFS 90 75 100 150 200 250 300 INPUT FREQUENCY (MHz) LTC2174-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 110 80 50 217514 G22 LTC2174-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps 85 0 217514 G21 226114 G20 LTC2174-14: SFDR vs Input Frequency, –1dB, 2V Range, 105Msps IVDD (mA) AMPLITUDE (dBFS) 50 LTC2174-14: SNR vs Input Frequency, –1dB, 2V Range, 105Msps –10 SFDR (dBFS) 20 30 40 FREQUENCY (MHz) 217514 G18 217517 G24 LTC2174-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 105Msps 65 10 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 217514 G24 160 0 25 50 75 SAMPLE RATE (Msps) 100 217514 G54 21754314p 13 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2174-14: SNR vs SENSE, fIN = 5MHz, –1dB LTC2173-14: Integral Nonlinearity (INL) 2.0 1.0 73 1.5 0.8 72 1.0 SNR (dBFS) 70 69 0.6 0.5 0 –0.5 68 –1.0 67 –1.5 66 –2.0 0.4 DNL ERROR (LSB) INL ERROR (LSB) 74 71 0.2 0 –0.2 –0.4 –0.6 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 –0.8 –1.0 0 4096 8192 12288 OUTPUT CODE 217514 G25 16384 LTC2173-14: 8k Point FFT, fIN = 30MHz –1dBFS, 80Msps –20 –20 –20 –30 –30 –30 –70 –80 AMPLITUDE (dBFS) 0 –10 AMPLITUDE (dBFS) 0 –10 –60 –40 –50 –60 –70 –80 –40 –60 –70 –80 –90 –100 –90 –100 –110 –120 –110 –120 –110 –120 10 20 30 FREQUENCY (MHz) 0 40 10 20 30 FREQUENCY (MHz) 0 –10 –20 –20 –30 –30 –60 –70 6000 5000 –40 4000 –50 –60 3000 –70 2000 –90 –100 1000 –110 –120 –110 –120 10 20 30 FREQUENCY (MHz) 40 217514 G31 40 LTC2173-14: Shorted Input Histogram –80 0 20 30 FREQUENCY (MHz) 217514 G30 –90 –100 –80 10 COUNT AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 –10 –40 0 LTC2173-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 80Msps LTC2173-14: 8k Point FFT, fIN = 140MHz –1dBFS, 80Msps –50 40 217514 G29 217514 G28 16384 –50 –90 –100 0 8192 12288 OUTPUT CODE LTC2173-14: 8k Point FFT, fIN = 70MHz –1dBFS, 80Msps 0 –50 4096 217514 G27 –10 –40 0 217514 G26 LTC2173-14: 8k Point FFT, fIN = 5MHz –1dBFS, 80Msps AMPLITUDE (dBFS) LTC2173-14: Differential Nonlinearity (DNL) 0 10 20 30 FREQUENCY (MHz) 40 217514 G32 0 8184 8186 8188 8190 OUTPUT CODE 8192 217514 G33 21754314p 14 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2173-14: SNR vs Input Frequency, –1dB, 2V Range, 80Msps LTC2173-14: SFDR vs Input Frequency, –1dB, 2V Range, 80Msps LTC2173-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 80Msps 95 74 110 100 73 90 70 69 SFDR (dBc AND dBFS) SFDR (dBFS) SNR (dBFS) 72 71 85 80 75 68 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 dBc 60 50 40 30 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) DCO Cycle-Cycle Jitter vs Serial Data Rate 74 350 73 300 PEAK-TO-PEAK JITTER (ps) 180 SNR (dBFS) 72 160 71 70 69 68 150 20 40 60 SAMPLE RATE (Msps) 80 217514 G55 66 250 200 150 100 50 67 0 0 217514 G36 LTC2173-14: SNR vs SENSE, fIN = 5MHz, –1dB 190 170 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 350 217514 G35 LTC2173-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB IVDD (mA) 70 10 65 217514 G34 140 80 20 70 67 dBFS 90 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 217514 G37 0 0 200 400 600 800 SERIAL DATA RATE (Mbps) 1000 217514 G52 21754314p 15 LTC2175-14/ LTC2174-14/LTC2173-14 PIN FUNCTIONS AIN1+ (Pin 1): Channel 1 Positive Differential Analog Input. AIN1– (Pin 2): Channel 1 Negative Differential Analog Input. VCM12 (Pin 3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 1 and 2. Bypass to ground with a 0.1μF ceramic capacitor. AIN2+ (Pin 4): Channel 2 Positive Differential Analog Input. AIN2– (Pin 5): Channel 2 Negative Differential Analog Input. REFH (Pins 6,7): ADC High Reference. Bypass to pins 8, 9 with a 2.2μF ceramic capacitor and to ground with a 0.1μF ceramic capacitor. REFL (Pins 8,9): ADC Low Reference. Bypass to pins 6, 7 with a 2.2μF ceramic capacitor and to ground with a 0.1μF ceramic capacitor. CS (Pin 19): In serial programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. SCK (Pin 20): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER = VDD), SCK selects 3.5mA or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 21): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. GND (Pins 22, 45, 49): ADC Power Ground. OGND (Pin 33): Output Driver Ground. AIN3+ (Pin 10): Channel 3 Positive Differential Analog Input. OVDD (Pin 34): Output Driver Supply. Bypass to ground with a 0.1μF ceramic capacitor. AIN3 – (Pin 11): Channel 3 Negative Differential Analog Input. SDO (Pin 46): In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V – 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO is an input that enables internal 100Ω termination resistors on the digital outputs. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. VCM34 (Pin 12): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 3 and 4. Bypass to ground with a 0.1μF ceramic capacitor. AIN4 + (Pin 13): Channel 4 Positive Differential Analog Input. AIN4 – (Pin 14): Channel 4 Negative Differential Analog Input. VDD (Pins 15, 16, 51, 52): 1.8V Analog Power Supply. Bypass to ground with 0.1μF ceramic capacitors. Adjacent pins can share a bypass capacitor. ENC+ (Pin 17): Encode Input. Conversion starts on the rising edge. ENC – (Pin 18): Encode Complement Input. Conversion starts on the falling edge. PAR/SER (Pin 47): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. 21754314p 16 LTC2175-14/ LTC2174-14/LTC2173-14 PIN FUNCTIONS VREF (Pin 48): Reference Voltage Output. Bypass to ground with a 1μF ceramic capacitor, nominally 1.25V. SENSE (Pin 50): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. Exposed Pad (Pin 53): Ground. The Exposed Pad must be soldered to the PCB ground. LVDS Outputs OUT3B –/OUT3B+, OUT3A–/OUT3A+ (Pins 27/28, 29/30): Serial data outputs for Channel 3. In 1-lane output mode only OUT3A–/OUT3A+ are used. FR–/FR+ (Pins 31/32): Frame Start Outputs. DCO –/DCO+ (Pins 35/36): Data Clock Outputs. OUT2B –/OUT2B+, OUT2A–/OUT2A+ (Pins 37/38, 39/40): Serial data outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used. OUT1B –/OUT1B+, OUT1A–/OUT1A+ (Pins 41/42, 43/44): Serial data outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used. All pins in this section are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OUT4B –/OUT4B+, OUT4A–/OUT4A+ (Pins 23/24, 25/26): Serial data outputs for Channel 4. In 1-lane output mode only OUT4A–/OUT4A+ are used. 21754314p 17 LTC2175-14/ LTC2174-14/LTC2173-14 FUNCTIONAL BLOCK DIAGRAM 1.8V ENC+ ENC– VDD CH 1 ANALOG INPUT 1.8V OVDD OUT1A 14-BIT ADC CORE S/H OUT1B PLL OUT2A CH 2 ANALOG INPUT DATA SERIALIZER 14-BIT ADC CORE S/H OUT2B OUT3A OUT3B CH 3 ANALOG INPUT 14-BIT ADC CORE S/H OUT4A OUT4B DATA CLOCK OUT CH 4 ANALOG INPUT VREF 14-BIT ADC CORE S/H FRAME 1.25V REFERENCE OGND 1μF RANGE SELECT SENSE REFH REF BUF REFL VDD/2 DIFF REF AMP GND MODE CONTROL REGISTERS REFH 0.1μF REFL 0.1μF 2.2μF 0.1μF VCM12 217514 F01 VCM34 0.1μF PAR/SER CS SCK SDI SDO 0.1μF Figure 1. Functional Block Diagram 21754314p 18 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2175-14/LTC2174-14/LTC2173-14 are low power, 4-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single ended for lower power consumption. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port. ANALOG INPUT The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM12 or VCM34 output pins, which are nominally VDD/2. For the LTC2175-14 VDD AIN+ RON 25Ω 10Ω AIN– INPUT DRIVE CIRCUITS Input Filtering If possible, there should be an RC low pass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application’s input frequency. Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center 50Ω VCM 0.1μF 0.1μF RON 25Ω 10Ω The four channels are simultaneously sampled by a shared encode circuit (Figure 2). CSAMPLE 3.5pF CPARASITIC 1.8pF VDD 2V input range, the inputs should swing from VCM – 0.5V to VCM + 0.5V. There should be 180° phase difference between the inputs. CSAMPLE 3.5pF ANALOG INPUT T1 1:1 25Ω 25Ω AIN+ LTC2175-14 0.1μF 12pF CPARASITIC 1.8pF 25Ω VDD 25Ω T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 217514 F03 1.2V Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz. 10k ENC+ ENC– 10k 1.2V 217514 F02 Figure 2. Equivalent Input Circuit. Only One of the Four Analog Channels is Shown. 21754314p 19 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion. At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the A/D. Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. 50Ω Reference The LTC2175-14/LTC2174-14/LTC2173-14 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to 50Ω VCM VCM 0.1μF 0.1μF 0.1μF 0.1μF ANALOG INPUT AIN+ T2 T1 25Ω LTC2175-14 0.1μF 2.7nH ANALOG INPUT T1 0.1μF 25Ω T1: MA/COM MABA-007159-000000 T2: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE T1 HIGH SPEED DIFFERENTIAL 0.1μF AMPLIFIER AIN+ 25Ω LTC2175-14 0.1μF 25Ω ANALOG INPUT 200Ω 200Ω 25Ω 0.1μF AIN+ LTC2175-14 + + – – 12pF 1.8pF 0.1μF 217514 F06 VCM VCM 0.1μF T2 AIN– Figure 6. Recommended Front End Circuit for Input Frequencies Above 300MHz Figure 4. Recommended Front End Circuit for Input Frequencies from 70MHz to 170MHz 0.1μF 2.7nH T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 217514 F04 ANALOG INPUT 25Ω AIN– 50Ω LTC2175-14 0.1μF 25Ω 4.7pF 0.1μF AIN+ AIN– 0.1μF 25Ω AIN– 217514 F07 217514 F05 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1LB RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 7. Front End Circuit Using a High Speed Differential Amplifier Figure 5. Recommended Front End Circuit for Input Frequencies from 170MHz to 300MHz 21754314p 20 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). and REFL should be as close to the pins as possible (not on the backside of the circuit board). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE. Encode Input The reference is shared by all four ADC channels, so it is not possible to independently adjust the input range of individual channels. The VREF, REFH and REFL pins should be bypassed as shown in Figure 8. The 0.1μF capacitor between REFH The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). LTC2175-14 LTC2175-14 VREF 1.25V 5Ω 1.25V BANDGAP REFERENCE VDD DIFFERENTIAL COMPARATOR VDD 1μF 0.625V 15k TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 • VSENSE FOR 0.65V < VSENSE < 1.300V RANGE DETECT AND CONTROL ENC+ ENC– SENSE 30k BUFFER INTERNAL ADC HIGH REFERENCE 0.1μF 217514 F10 REFH Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode 2.2μF 0.1μF 0.8x DIFF AMP 0.1μF REFL LTC2175-14 INTERNAL ADC LOW REFERENCE 1.8V TO 3.3V 0V 217514 F08 Figure 8. Reference Circuit ENC+ ENC– 30k CMOS LOGIC BUFFER 217514 F11 Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode VREF 1μF LTC2175-14 1.25V EXTERNAL REFERENCE SENSE 1μF 217514 F09 Figure 9. Using an External 1.25V Reference 21754314p 21 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC – is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. Clock PLL and Duty Cycle Stabilizer The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25μs to lock onto the input clock. A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled. 0.1μF 0.1μF ENC+ T1 PECL OR LVDS CLOCK 50Ω 100Ω 0.1μF ENC+ LTC2175-14 50Ω LTC2175-14 0.1μF ENC– 217514 F13 0.1μF ENC– 217514 F12 Figure 13. PECL or LVDS Encode Drive T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 12. Sinusoidal Encode Drive 21754314p 22 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION DIGITAL OUTPUTS The digital outputs of the LTC2175-14/LTC2174-14/ LTC2173-14 are serialized LVDS signals. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The data can be serialized with 16, 14, or 12-bit serialization (see timing diagrams for details). Note that with 12-bit serialization the two LSBs are not available—this mode is included for compatibility with the 12-bit versions of these parts. The output data should be latched on the rising and falling edges of the data clock out (DCO). A data frame output (FR) can be used to determine when the data from a new conversion result begins. In the 2-lane, 14-bit serialization mode, the frequency of the FR output is halved. The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade of the ADC (see Table 1). The minimum sample rate for all serialization modes is 5Msps. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by control register A2 in the serial programming mode. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the parallel programming mode the SCK pin can select either 3.5mA or 1.75mA. Optional LVDS Driver Internal Termination In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. In the parallel programming mode the SDO pin enables internal termination. Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2175-14. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTC2174-14) or 80MHz (LTC2173-14). SERIALIZATION MODE MAXIMUM SAMPLING FREQUENCY, fS (MHz) DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE 2-Lane 16-Bit Serialization 125 4 • fS fS 8 • fS 2-Lane 14-Bit Serialization 125 3.5 • fS 0.5 • fS 7 • fS 2-Lane 12-Bit Serialization 125 3 • fS fS 6 • fS 1-Lane 16-Bit Serialization 62.5 8 • fS fS 16 • fS 1-Lane 14-Bit Serialization 71.4 7 • fS fS 14 • fS 1-Lane 12-Bit Serialization 83.3 6 • fS fS 12 • fS 21754314p 23 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION DATA FORMAT Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A1. Table 2. Output Codes vs Input Voltage and all other bits. The FR and DCO outputs are not affected. The output randomizer is enabled by serially programming mode control register A1. Digital Output Test Pattern To allow in-circuit testing of the digital interface to the A/D, there is a test mode that forces the A/D data outputs (D13-D0) of all channels to known values. The digital output test patterns are enabled by serially programming mode control registers A3 and A4. When enabled, the test patterns override all other formatting modes: 2’s complement and randomizer. AIN+ – AIN– (2V RANGE) D13-D0 (OFFSET BINARY) D13-D0 (2’s COMPLEMENT) >1.000000V 11 1111 1111 1111 01 1111 1111 1111 +0.999878V 11 1111 1111 1111 01 1111 1111 1111 +0.999756V 11 1111 1111 1110 01 1111 1111 1110 +0.000122V 10 0000 0000 0001 00 0000 0000 0001 Output Disable +0.000000V 10 0000 0000 0000 00 0000 0000 0000 –0.000122V 01 1111 1111 1111 11 1111 1111 1111 –0.000244V 01 1111 1111 1110 11 1111 1111 1110 –0.999878V 00 0000 0000 0001 10 0000 0000 0001 –1.000000V 00 0000 0000 0000 10 0000 0000 0000 <–1.000000V 00 0000 0000 0000 10 0000 0000 0000 The digital outputs may be disabled by serially programming mode control register A2. The current drive for all digital outputs including DCO and FR are disabled to save power or enable in-circuit testing. When disabled the common mode of each output pair becomes high impedance, but the differential impedance may remain low. Digital Output Randomizer Sleep and Nap Modes Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire chip is powered down, resulting in 1mW power consumption. Sleep mode is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode). The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF, REFH, and REFL. For the suggested values in Figure 8, the A/D will stabilize after 2ms. The digital output is randomized by applying an exclusiveOR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied —an exclusive-OR operation is applied between the LSB In nap mode any combination of A/D channels can be powered down while the internal reference circuits and the PLL stay active, allowing faster wakeup than from sleep 21754314p 24 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands very accurate DC settling then an additional 50μs should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Nap mode is enabled by mode control register A1 in the serial programming mode. DEVICE PROGRAMMING MODES The operating modes of the LTC2175-14/LTC2174-14/ LTC2173-14 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1k series resistor. Table 3 shows the modes set by CS, SCK, SDI and SDO. Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the Timing Diagrams sections). During a read back command the register is not updated and data on SDI is ignored. The SDO pin is an open-drain output that pulls to ground with a 200Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD) Pin DESCRIPTION CS 2-Lane / 1-Lane Selection Bit 0 = 2-Lane, 16-Bit Serialization Output Mode 1 = 1-Lane, 14-Bit Serialization Output Mode SCK LVDS Current Selection Bit 0 = 3.5mA LVDS Current Mode 1 = 1.75mA LVDS Current Mode SDI Power Down Control Bit 0 = Normal Operation 1 = Sleep Mode SDO Internal Termination Selection Bit 0 = Internal Termination Disabled 1 = Internal Termination Enabled 21754314p 25 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 4 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset is complete, bit D7 is automatically set back to zero. GROUNDING AND BYPASSING The LTC2175-14/LTC2174-14/LTC2173-14 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1μF capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The larger 2.2μF capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC2175-14/LTC2174-14/ LTC2173-14 is transferred from the die through the bottom-side Exposed Pad and package leads onto the printed circuit board. For good electrical and thermal performance, the Exposed Pad must be soldered to a large grounded pad on the PC board. Table 4. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 D6 RESET Bit 7 X RESET D5 D4 D3 D2 D1 D0 X X X X X X Software Reset Bit 0 = Not Used 1 = Software Reset. All Mode Control Registers are Reset to 00h. The ADC is Momentarily Placed in SLEEP Mode. This Bit is Automatically Set Back to Zero After the Reset is Complete Bits 6-0 Unused, Don’t Care Bits. REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h) D7 D6 D5 D4 D3 D2 D1 D0 DCSOFF RAND TWOSCOMP SLEEP NAP_4 NAP_3 NAP_2 NAP_1 Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended. Bit 6 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On 21754314p 26 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION Bit 5 TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format Bits 4-0 SLEEP: NAP_4:NAP_1 Sleep/Nap Mode Control Bits 00000 = Normal Operation 0XXX1 = Channel 1 in Nap Mode 0XX1X = Channel 2 in Nap Mode 0X1XX = Channel 3 in Nap Mode 01XXX = Channel 4 in Nap Mode 1XXXX = Sleep Mode. All Channels are Disabled Note: Any Combination of Channels Can Be Placed in Nap Mode. REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0 Bits 7-5 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 4 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0 Bit 3 OUTOFF Output Disable Bit 0 = Digital Outputs are Enabled. 1 = Digital Outputs are Disabled. Bits 2-0 OUTMODE2:OUTMODE0 Digital Output Mode Control Bits 000 = 2-Lanes, 16-Bit Serialization 001 = 2-Lanes, 14-Bit Serialization 010 = 2-Lanes, 12-Bit Serialization 011 = Not Used 100 = Not Used 101 = 1-Lane, 14-Bit Serialization 110 = 1-Lane, 12-Bit Serialization 111 = 1-Lane, 16-Bit Serialization REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 OUTTEST X TP13 TP12 TP11 TP10 TP9 TP8 Bit 7 OUTTEST Digital Output Test Pattern Control Bit 0 = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On Bit 6 Unused, Don’t Care Bit. Bit 5-0 TP13:TP8 Test Pattern Data Bits (MSB) TP13:TP8 Set the Test Pattern for Data Bit 13(MSB) Through Data Bit 8. REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h) Bit 7-0 D7 D6 D5 D4 D3 D2 D1 D0 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 TP7:TP0 Test Pattern Data Bits (LSB) TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0(LSB). 21754314p 27 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL APPLICATIONS Silkscreen Top Top Side Inner Layer 2 GND Inner Layer 3 21754314p 28 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Power Bottom Side Silkscreen Bottom 21754314p 29 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL APPLICATIONS LTC2175 Schematic SENSE PAR/SER C4 1μF SDO R14 1k C17 1μF C5 1μF 37 5 AIN2– DCO+ 36 DCO– 35 32 10 AIN3+ FR– 31 11 AIN3 – OUT3A+ 30 VCM34 OUT3A– 29 13 AIN4+ OUT3B+ 28 14 AIN4– OUT3B– 27 AIN4 OVDD 33 C16 0.1μF DIGITAL OUTPUTS OUT4A+ R94 100 OUT4A– FR+ OUT4B+ REFL OUT4B– OGND GND REFL SDI AIN4 DIGITAL OUTPUTS 34 OVDD SCK C59 0.1μF LTC2175 REFH 12 AIN3 REFH CS AIN3 OUT1B– OUT2B– 9 R93 100 OUT1B+ AIN2+ 8 C3 0.1μF OUT1A– 38 VCM12 4 VDD C2 0.1μF OUT1A+ 39 OUT2B+ 7 C30 0.1μF SDO OUT2A– 6 C1 2.2μF GND AIN1– ENC– AIN2 PAR/SER 2 ENC+ R92 100 GND AIN1+ 40 OUT2A+ 3 AIN2 VREF 1 VDD C29 0.1μF AIN1 VDD VDD R8 100 SENSE 52 51 50 49 48 47 46 45 44 43 42 41 AIN1 15 16 17 18 19 20 21 22 23 24 25 26 VDD C7 0.1μF C47 0.1μF ENCODE CLOCK C46 0.1μF ENCODE CLOCK SPI BUS 217514 TA02 21754314p 30 LTC2175-14/ LTC2174-14/LTC2173-14 PACKAGE DESCRIPTION UKG Package 52-Lead Plastic QFN (7mm × 8mm) (Reference LTC DWG # 05-08-1729 Rev Ø) 7.50 ±0.05 6.10 ±0.05 5.50 REF (2 SIDES) 0.70 ±0.05 6.45 ±0.05 6.50 REF 7.10 ±0.05 8.50 ±0.05 (2 SIDES) 5.41 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 0.00 – 0.05 R = 0.115 TYP 5.50 REF (2 SIDES) 51 52 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45°C CHAMFER 6.45 ±0.10 8.00 ± 0.10 (2 SIDES) 6.50 REF (2 SIDES) 5.41 ±0.10 R = 0.10 TYP TOP VIEW 0.200 REF 0.00 – 0.05 0.75 ± 0.05 (UKG52) QFN REV Ø 0306 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD SIDE VIEW NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 21754314p Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC2175-14/ LTC2174-14/LTC2173-14 RELATED PARTS PART NUMBER ADCs LTC2170-14/LTC2171-14/ LTC2172-14 LTC2170-12/LTC2171-12/ LTC2172-12 LTC2173-12/LTC2174-12/ LTC2175-12 LTC2202/LTC2203 LTC2204/LTC2205 LTC2205-14/LTC2206-14/ LTC2207-14 LTC2206/LTC2207 LTC2208 LTC2208-14 LTC2209 LTC2215/LTC2216/ LTC2217 LTC2240-12/LTC2241-12/ LTC2242-12 LTC2256-14/LTC2257-14/ LTC2258-14 LTC2259-14/LTC2260-14/ LTC2261-14 LTC2262-14 DESCRIPTION COMMENTS 14-Bit, 25Msps/40Msps/65Msps 1.8V Quad ADCs, Ultralow Power 12-Bit, 25Msps/40Msps/65Msps 1.8V Quad ADCs, Ultralow Power 12-Bit, 80Msps/105Msps/125Msps 1.8V Quad ADCs, Ultralow Power 16-Bit, 10Msps/25Msps, 3.3V ADCs 16-Bit, 40Msps/65Msps 3.3V ADCs 14-Bit, 65Msps/80Msps/105Msps 3.3V ADCs 16-Bit, 80Msps/105Msps 3.3V ADCs 16-Bit, 130Msps 3.3V ADC 14-Bit, 130Msps 3.3V ADC 16-Bit, 160Msps 3.3V ADC 16-Bit, 65Msps/80Msps/105Msps 3.3V Low Noise ADCs 12-Bit, 170Msps/210Msps/250Msps 2.5V ADCs 14-Bit, 25Msps/40Msps/65Msps Msps1.8V ADCs, Ultralow Power 14-Bit, 80Msps/105Msps/125Msps 1.8V ADCs, Ultralow Power 14-Bit, 150Msps 1.8V ADC, Ultralow Power LTC2263-14/LTC2264-14/ LTC2265-14 LTC2263-12/LTC2264-12/ LTC2265-12 LTC2266-14/LTC2267-14/ LTC2268-14 LTC2266-12/LTC2267-12/ LTC2268-12 LTC2284/LTC2285 LTC2295/LTC2296/ LTC2297 LTC2298/LTC2299 RF Mixers/Demodulators LTC5517 14-Bit, 25Msps/40Msps/65Msps 1.8V Dual ADCs, Ultralow Power 12-Bit, 25Msps/40Msps/65Msps 1.8V Dual ADCs, Ultralow Power 14-Bit, 80Msps/105Msps/125Msps 1.8V Dual ADCs, Ultralow Power 12-Bit, 80Msps/105Msps/125Msps 1.8V Dual ADCs, Ultralow Power 14-Bit, 105Msps/125Msps 3V Dual ADCs 14-Bit, 10Msps/25Msps/40Msps 3V Dual ADCs 14-Bit, 65Msps/80Msps 3V Dual ADCs 178mW/234mW/360mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 178mW/234mW/360mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 412mW/481mW/567mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 140mW/220mW, 81.6dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 480mW/590mW, 79dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 597mW/762mW/947mW, 78.3dB/77.3dB/77.3dB SNR, 98dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 725mW/900mW, 77.9dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 1250mW, 77.7dB SNR, 100dB SFDR, LVDS Outputs, 9mm × 9mm QFN-64 1320mW, 77.1dB SNR, 98dB SFDR, LVDS Outputs, 9mm × 9mm QFN-64 1450mW, 77.1dB SNR, 100dB SFDR, LVDS Outputs, 9mm × 9mm QFN-64 700mW/970mW/1190mW, 81.5dB/81.3dB/81.2dB SNR, 100dB SFDR, LVDS Outputs, 9mm × 9mm QFN-64 445mW/585mW/740mW, 65.5dB SNR, 80dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64 35mW/49mW/81mW, 74dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 99mW/126mW/191mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 99mW/126mW/191mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 540mW/790mW, 72.4dB SNR, 88dB SFDR, CMOS Outputs, 9mm × 9mm QFN-64 120mW/150mW/235mW, 74.4dB SNR, 90dB SFDR, CMOS Outputs, 9mm × 9mm QFN-64 400mW/444mW, 74.3dB/73.0dB SNR, 90dB SFDR, CMOS Outputs, 9mm × 9mm QFN-64 LTC5527 LTC5557 LTC5575 Amplifiers/Filters LTC6416 LTC6420-20 LTC6421-20 LTC6605-7/ LTC6605-10/ LTC6605-14 40MHz to 900MHz Direct Conversion Quadrature Demodulator 400MHz to 3.7GHz High Linearity Downconverting Mixer 400MHz to 3.8GHz High Linearity Downconverting Mixer 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF 1.3GHz Dual Low Noise, Low Distortion Differential ADC Drivers Dual Matched 7MHz/10MHz/14MHz Filters with ADC Drivers Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm × 4mm QFN-24 Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier, 3mm × 4mm QFN-20 Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier, 3mm × 4mm QFN-20 Dual Matched 2nd Order Lowpass Filters with Differential Drivers, Pin-Programmable Gain, 6mm × 3mm DFN-22 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports 23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply Operation, Integrated Transformer High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF and LO Transformer 21754314p 32 Linear Technology Corporation LT 0709 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009