Triple, 180° Out-of-Phase, Synchronous Step-Down PWM Controller ISL9443 Features The ISL9443 is a triple-output synchronous buck controller that integrates three PWM controllers which are fully featured and designed to provide multi-rail power for use in products such as cable and satellite set-top boxes, VoIP gateways, cable modems, and other home connectivity products as well as a variety of industrial and general purpose applications. Each output is adjustable down to 0.7V. The PWMs are synchronized at 180° out-of-phase, thus reducing the input RMS current and ripple voltage. • Three Integrated Synchronous Buck PWM Controllers - Internal Bootstrap Diodes - Independent Programmable Output Voltage - Independent Soft-Starting and Tracking • Power-Good Indicator • Light Load Efficiency Enhancement - Low Ripple Diode Emulation Mode with Pulse Skipping • Supports Pre-Biased Output The ISL9443 offers programmable soft-start and tracking functions for ease of supply rail sequencing and integrated UV/OV/OC/OT protections in a space conscious 5mmx5mm QFN package. • Programmable Frequency: 200kHz to 1200kHz • Adaptive Shoot-Through Protection • Out-of-Phase Switching (0°/180°/0°) Switching frequency can be set between 200kHz and 1200kHz using a resistor. The ISL9443 can be synchronized to an external clock to reduce beat frequencies. • No External Current Sense Resistor - Uses Lower MOSFET’s rDS(ON) • Complete Protection - Overcurrent, Overvoltage, Over-Temperature The ISL9443 utilizes internal loop compensation to keep minimum peripheral components for a compact design and a low total solution cost. The controller is implemented with current mode control with feed forward to cover various applications even with fixed internal compensation. • Wide Input Voltage Range: 4.5V to 28V • Pb-Free (RoHS Compliant) Applications Related Literature • VoX Gateway Devices • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages” • NAS/SAN Devices • ATX power supplies +12V + Q1 Q2 CIN2 0.1µF C1 4.7µF R5 100kΩ R6 200kΩ LGATE2 PHASE2 R7 200kΩ LGATE3 FB3 TK/SS2,3 MODE/SYNC OCSET2 OCSET1 CSS 10nF SGND EN/SS1 OCSET2 FB1 RT ISEN3 CO2 100µF Q3 BOOT3 PHASE3 R9 11.5kΩ R8 3.09kΩ FB2 UGATE3 EN23 RT 49.9kΩ ISEN2 +12V ISL9443 R4 15.8kΩ R3 31.6kΩ BOOT2 VIN VCC_5V UGATE2 ISEN1 +12V PGND CO1 100µF VOUT2 +3.3V,6A + RESN2 1.3kΩ CB2 CB1 BOOT1 1.0µH L2 2.2µH 0.1µF UGATE1 + RESN1 1.3kΩ PHASE1 L1 LGATE1 VOUT1 +1.0V, 6A PGOOD CIN1 CB3 0.1µF L3 3.3µH VOUT3 +5.0V,6A + RESN3 1.3kΩ CO3 100µF R4 10.7kΩ R3 1.74kΩ FIGURE 1. TYPICAL APPLICATION February 24, 2012 FN7663.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL9443 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL9443IRZ PART MARKING TEMP. RANGE (°C) ISL9443 IRZ PACKAGE (Pb-Free) -40 to +85 32 Ld 5x5 QFN PKG. DWG. # L32.5X5B NOTES: 1. Add “-T*” for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9443. For more information on MSL please see techbrief TB363. Pin Configuration PHASE1 BOOT1 UGATE1 LGATE1 LGATE2 UGATE2 BOOT2 PHASE2 ISL9443 (32 LD 5x5 QFN) TOP VIEW 32 31 30 29 28 27 26 25 PGND VIN 3 22 LGATE3 EN/SS1 4 21 UGATE3 FB1 5 20 BOOT3 OCSET1 6 19 PHASE3 RT 7 18 ISEN3 8 17 MODE/SYNC 9 10 11 12 13 14 15 16 TK/SS3 PGOOD FB3 23 TK/SS2 2 OCSET3 VCC_5V FB2 ISEN2 OCSET2 24 SGND 1 EN23 ISEN1 Pin Descriptions PIN NAME FUNCTION 1 ISEN1 2 VCC_5V Output of the internal 5V linear regulator. This output supplies bias for the IC, the low side gate drivers, and the external boot circuitry for the high-side gate drivers. The VCC_5V pin must be always decoupled to power ground with a minimum of 4.7µF ceramic capacitor, placed very close to the pin. Do not allow the voltage at VCC_5V to exceed VIN at any time. 3 VIN This pin should be tied to the input rail. It provides power to the internal linear drive circuitry and is also used by the feedforward controller to adjust the amplitude of each PWM sawtooth. Decouple this pin with a small ceramic capacitor (0.1µF to 1µF) to ground. 4 EN/SS1 This pin provides an enable/disable function and soft-starting for PWM1 output. The output is disabled when the pin is pulled to GND. During start-up, a regulated 1.55µA soft-start current charges an external capacitor connected at this pin. When the voltage on the EN/SS1 pin reaches 1.3V, the PWM1 output becomes active. From 1.3V to 2.0V, the reference voltage of the PWM1 is clamped to the voltage at EN/SS1 minus 1.3V. The capacitance of the soft-start capacitors sets the soft-starting time and enable delay time. Setting the soft-starting time too short might create undesirable overshoot at the output during start-up. VCC_5V UVLO discharges the EN/SS1 via an internal MOSFET. Current signal input for PWM1. This pin is used to monitor the voltage drop across the lower MOSFET for current loop feedback and overcurrent protection. 2 FN7663.1 February 24, 2012 ISL9443 Pin Descriptions (Continued) PIN NAME FUNCTION 5 FB1 PWM1 feedback input. Connect FB1 to a resistive voltage divider from the output of PWM1 to GND to adjust the output voltage. 6 OCSET1 7 RT A resistor from this pin to ground adjusts the overcurrent threshold for PWM1. A resistor from this pin to ground adjusts the switching frequency from 200kHz to 1.2MHz. R T = ( 23.36 × ( 1.5 × t SW – 0.36 ) ) ⋅ kΩ (EQ. 1) Where tSW is the switching period in µs. 8 PGOOD Open drain logic output used to indicate the status of the PWM output voltages. This pin is pulled LOW when any of the outputs is not within ±11% of the nominal voltage. 9 EN23 Enable/Disable input for PWM2 and PWM3. The outputs of PWM2 and PWM3 are enabled when this pin is pulled HIGH, and disabled when this pin is pulled LOW. Do not float this pin. 10 SGND This is the small-signal ground common to all 3 controllers. It is suggested to route this separately from the high current ground (PGND). SGND and PGND can be tied together if there is one solid ground plane with no noisy currents around the chip. All voltage levels are measured with respect to this pin. 11 OCSET2 12 FB2 PWM2 feedback input. Connect FB2 to a resistive voltage divider from the output of PWM2 to GND to adjust the output voltage. 13 TK/SS2 Dual function pin. The reference voltage of PWM2 is clamped to the voltage at TK/SS2 during start-up. When this pin is used for tracking, another channel is configured as the master and the output voltage of the master channel is applied to this pin via a resistor divider. When used for soft-starting control, a soft-start capacitor is connected from this pin to GND. A regulated 1.55µA soft-starting current charges up the soft-start capacitor. Value of the soft-start capacitor sets the PWM2 output voltage ramp. 14 OCSET3 A resistor from this pin to ground adjusts the overcurrent threshold for PWM3. 15 FB3 PWM3 feedback input. Connect FB3 to a resistive voltage divider from the output of PWM3 to GND to adjust the output voltage. 16 TK/SS3 Dual function pin. The reference voltage of PWM3 is clamped to the voltage at TK/SS3 during start-up. When this pin is used for tracking, another channel is configured as the master and the output voltage of the master channel is applied to this pin via a resistor divider. When used for soft-starting control, a soft-start capacitor is connected from this pin to GND. A regulated 1.55µA soft-starting current charges up the soft-start capacitor. Value of the soft-start capacitor sets the PWM3 output voltage ramp. 17 MODE/SYNC Dual function pin. Tie this pin to ground or VCC_5V for DEM or CCM operation mode selection. Connect this pin to ground to select Diode Emulation Mode with pulse skipping at light load. While connected to VCC_5V, the controllers operate in PWM Mode at light load. Connect this pin to an external clock for synchronization. The controller operates in PWM mode at light load when synchronized with an external clock. 18 ISEN3 19 PHASE3 Phase node connection for PWM3. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor, and lower MOSFET’s drain. PHASE3 is the internal lower supply rail for UGATE3. 20 BOOT3 Bootstrap pin to provide bias for PWM3 high-side driver. The positive terminal of the bootstrap capacitor connects to this pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity. 21 UGATE3 High-side MOSFET gate driver output for PWM3. 22 LGATE3 Low-side MOSFET gate driver output for PWM3. 23 PGND Power ground connection for all three PWM channels. This pin should be connected to the sources of the lower MOSFETs and the (-) terminals of the external input capacitors 24 ISEN2 Current signal input for PWM2. This pin is used to monitor the voltage drop across the lower MOSFET for current loop feedback and overcurrent protection. 25 PHASE2 A resistor from this pin to ground adjusts the overcurrent threshold for PWM2. Current signal input for PWM3. This pin is used to monitor the voltage drop across the lower MOSFET for current loop feedback and overcurrent protection. Phase node connection for PWM2. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor, and lower MOSFET’s drain. PHASE2 is the internal lower supply rail for UGATE2. 3 FN7663.1 February 24, 2012 ISL9443 Pin Descriptions (Continued) PIN NAME FUNCTION 26 BOOT2 Bootstrap pin to provide bias for PWM2 high-side driver. The positive terminal of the bootstrap capacitor connects to this pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity. 27 UGATE2 High-side MOSFET gate driver output for PWM2. 28 LGATE2 Low-side MOSFET gate driver output for PWM2. 29 LGATE1 Low-side MOSFET gate driver output for PWM1. 30 UGATE1 High-side MOSFET gate driver output for PWM1. 31 BOOT1 Bootstrap pin to provide bias for PWM1 high-side driver. The positive terminal of the bootstrap capacitor connects to this pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity. 32 PHASE1 Phase node connection for PWM1. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor, and lower MOSFET’s drain. PHASE1 is the internal lower supply rail for UGATE1. - EPAD EPAD at ground potential. Solder it directly to GND plane for better thermal performance. 4 FN7663.1 February 24, 2012 Block Diagram PGOOD BOOT1 VIN VCC_5V EN23 BOOT2 VCC_5V VCC_5V UGATE1 UGATE2 PHASE1 PHASE2 ADAPTIVE DEAD-TIME ADAPTIVE DEAD-TIME V/I SAMPLE TIMING V/I SAMPLE TIMING VCC_5V VCC_5V LGATE1 LGATE2 5 PGND POR PGND ENABLE PGND BOOT3 BIAS SUPPLIES EN/SS1 VCC_5V REFERENCE UGATE3 FAULT LATCH PHASE3 EN23 SOFT-START ADAPTIVE DEAD-TIME V/I SAMPLE TIMING (Note 6) FB1 180kΩ 1000kΩ VCC_5V LGATE3 15pF OCP + + 0.7V REF EN/SS1 ERROR AMP 1 _ PWM1 OC1 OC2 OC3 UV/OV + PWM3 FB1 FB2 FB3 0.7V REF TK/SS3 ERROR AMP 3 OC3 EN/SS1 1.3V VIN ISEN1 FB3 _ + 1.55µA + PGND 16kΩ VCC_5V ISEN3 MINIMUM SOFT-START OCSET3 _ CURRENT SAMPLE + DUTY CYCLE RAMP GENERATOR CURRENT SAMPLE CHANNEL 3 PWM CHANNEL PHASE CONTROL OCSET1 FB2 PWM2 + 1.75V REFERENCE TK/SS2 CHANNEL 1 SAME STATE FOR 2 CLOCK CYCLES REQUIRED TO LATCH OVERCURRENT FAULT ISEN2 OC2 RT FN7663.1 February 24, 2012 + OC1 MODE/SYNC - CHANNEL 2 SGND OCSET2 ISL9443 _ ISL9443 Typical Application +12V + C1 1µF C2 4.7µF 3 VIN C3 CIN1 100µF C4 10µF 2 VCC_5V 10µF 31 C5 0.1µF VOUT1 +3.3V, 6A CO1 47µF R1 115k L1 R3 1.5µH 1.3k BOOT1 30 UGATE1 32 PHASE1 1 29 BOOT2 UGATE2 PHASE2 ISEN1 ISEN2 LGATE1 LGATE2 26 C6 0.1µF 27 25 24 R4 L2 1.1k 1.5µH 28 5 FB1 FB2 C8 1000pF 12 V VOUT1 R2 30.9k R13 100k +12V 8 PGOOD 9 BOOT3 EN23 UGATE3 R7 100k 6 R8 100k 11 R9 100k 14 CSS1 10nF VOUT2 R14 V 25.5k 6 PHASE3 OCSET1 ISEN3 OCSET2 CSS2 10nF 13 R15 49.9k 17 21 C11 0.1µF 19 VOUT3 L3 R10 1.0µH 1.3K OCSET3 LGATE3 Q3 IRF7907 22 R11 15.8k EN/SS1 FB3 16 C10 10µF 20 18 R5 16.5k R6 10.5k ISL9443 PGOOD CO2 47µF Q2 IRF7907 Q1 IRF7907 C7 47pF VOUT2 +1.8V, 6A 15 +1.05V, 6A CO3 100µF C12 470pF TK/SS3 R12 31.6k TK/SS2 RT MODE/SYNC 7 RT 49.9k 6 PGND SGND 23 10 FN7663.1 February 24, 2012 ISL9443 Typical Application +12V C10 0.1µF + CIN3 + CIN2 + 150µF 150µF CIN1 150µF C2 4.7µF CIN5 10µF CIN4 10µF 3 VIN 31 30 BSC057N03LS 32 C5 C6 L1 + BOOT2 BOOT1 Q2 C3 0.22µF VOUT1 +0.9V, 25A 2 R4 230nH Q9 Q2 1 UGATE2 UGATE1 PHASE2 ISEN2 29 3x100µF 3x270µF C4 0.22µF Q3 BSC057N03LS 27 25 24 LGATE2 LGATE1 28 VOUT2 + 1.0V, 25A L2 R5 2k 2k 230nH Q8 CFF1 2200pF CFF2 BSZ019N03LS FB2 5 R2 35.7k + C8 BSZ019N03LS Q4 2200pF R1 10.2k 10µF 26 PHASE1 ISEN1 CIN6 CIN7 10µF VCC_5V C7 3x270µF 3x100µF R8 10.7k 12 CP2 ISL9443 5600pF FB1 R11 24.9k +12V CP1 5600pF 17 V +12V R14 64.9k MODE/SYNC BOOT3 21 TK/SS3 UGATE3 R15 10k VOUT1 9 PHASE3 EN23 ISEN3 13 CSS2 47nF 4 CSS1 47nF 21 LGATE3 19 18 22 VOUT3 +0.9V,25A L3 R8 230nH Q6 BSZ019N03LS EN/SS1 C9 0.22µF Q5 909 TK/SS2 CIN8 10µF CIN9 10µF 20 BSC057N03LS + C10 C11 3x270µF 3x100µF Q10 CFF3 2200pF R3 10.2k FB3 15 CP3 5600pF R6 35.7k VCC_5V V R11 100k 6 R12 100k 11 R13 100k 14 OCSET3 RPG 100k OCSET1 OCSET2 PGOOD PGND SGND 23 10 8 PGOOD RT 7 RT 78.7k (Fsw = 400kHz) 7 FN7663.1 February 24, 2012 ISL9443 Table of Contents Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Internal 5V Linear Regulator (VCC_5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Enable Signals and Soft-Start Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Tracking Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Light Load Efficiency Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pre-biased Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Out-of-Phase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Gate Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Gate Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Adaptive Dead-Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal Bootstrap Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-Good Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Protection Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18 18 18 Feedback Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General PowerPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Component Selection Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MOSFET Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 21 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 FN7663.1 February 24, 2012 ISL9443 Absolute Maximum Ratings Thermal Information VCC_5V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.2V VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +30V BOOT1,2,3/UGATE1,2,3 to PHASE1,2,3 . . . . . . . . . -0.3V to VCC_5V+0.3V PHASE1,2,3 and ISEN1,2,3, to GND . . . . . . . . . . . -5V (<100ns, 10µJ)/-0.3V (DC) to +30V EN/SS1,EN23, FB1, FB2, FB3, to GND . . . . . . . . . . -0.3V to VCC_5V+0.3V OCSET1, OCSET2, OCSET3, TKSS2, TKSS3 LGATE1, LGATE2, LGATE3, to GND . . . . . . . . . . . . -0.3V to VCC_5V+0.3V RT, MODE/SYNC to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC_5V+0.3V PGOOD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VCC_5V + 0.3V VCC_5V Short Circuit to GND Duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1s ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 3000V Machine Model (Tested per JESD22-115-C) . . . . . . . . . . . . . . . . . . . 200V Charge Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . 2000V Latch Up (Tested per JESD78C; Class II, Level A, +85°C) . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 32 Ld QFN Package (Notes 4, 5) . . . . . . . . 31 2.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Maximum Operating Temperature . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 28V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. VIN = 5.0V to 28V, or VCC_5V = 5V ±10%, C_VCC_5V = 4.7µF, TA = -40°C to +85°C (Note 9), Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C SYMBOL PARAMETER TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS 4.5 12.0 28.0 V VIN SUPPLY VIN Input Voltage Range VIN SUPPLY CURRENT IVINQ Shutdown Current (Note 7) EN/SS1 = EN23 = 0V, PGOOD is floating 30 38 µA IVINOP Operating Current (Note 8) EN/SS1, EN23, PGOOD are floating 5 6 mA 5.7 V VCC_5V SUPPLY (Note 6) VCC IVCC_MAX Operation Voltage VIN = 12V, IL = 0mA 5.1 5.4 Internal LDO Output Voltage VIN = 4.5V, IL = 30mA 4.05 4.35 V Internal LDO Output Voltage VIN > 5.6V, IL = 75mA 4.5 5.4 V Maximum Supply Current of Internal LDO VVCC_5V = 0V, VIN = 12V 150 250 mA UNDERVOLTAGE LOCKOUT VUVLOTHR Undervoltage Lockout, Rising VCC_5V Voltage 3.4 3.95 4.45 V VUVLOTHF Undervoltage Lockout, Falling VCC_5V Voltage 3.05 3.60 4.15 V EN/SS1, EN23 THRESHOLD VENSS_TH EN/SS1 Threshold 1.1 1.3 1.5 V VEN_THR EN23 Logic Threshold, Rising 1.4 1.7 2.0 V VEN_THF EN23 Logic Threshold, Falling 1.1 1.25 1.4 V 1.05 1.55 2.05 µA SOFT-START CURRENT ISS EN/SS1, TK/SSx Soft-Start Charge Current 9 VEN/SS1 = VTK/SSx = 0V FN7663.1 February 24, 2012 ISL9443 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. VIN = 5.0V to 28V, or VCC_5V = 5V ±10%, C_VCC_5V = 4.7µF, TA = -40°C to +85°C (Note 9), Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS 1.3 2.1 2.9 ms DEFAULT INTERNAL MINIMUM SOFT-STARTING FOR PWM2 AND PWM3 tSS_MIN Default Internal Output Ramping Time POWER-GOOD MONITORS VPGOV PGOOD Upper Threshold, PWM 1, 2 and 3 105.5 111 115.5 % VPGUV PGOOD Lower Threshold, PWM 1, 2 and 3 85 89 94 % VPGLOW PGOOD Low Level Voltage I_SINK = 2mA 0.3 V IPGLKG PGOOD Leakage Current PGOOD = 5V 150 nA PGOOD Rise Time RPULLUP = 10k to 3.3V 0.05 µs PGOOD Fall Time RPULLUP = 10k to 3.3V 0.05 µs 1 PGOOD TIMING tPGR VOUT Rising Threshold to PGOOD Rising 0.7 1.1 1.5 ms tPGF VOUT Falling Threshold to PGOOD Falling 40 75 110 µs REFERENCE SECTION VREF IFBLKG Internal Reference Voltage Across specified temperature range Reference Voltage Accuracy TA = 0°C to +85°C -1.0 0.7 +1.0 % TA = -40°C to +85°C -1.15 +1.0 % 100 nA FB Bias Current (Note 10) V PWM CONTROLLER ERROR AMPLIFIERS DC Gain (Note 10) 88 dB GBW Gain-BW Product (Note 10) 15 MHz SR Slew Rate (Note 10) 2.0 V/µs PWM REGULATOR tOFF_MIN Minimum Off Time RFS = 169kΩ 95 ΔVRAMP Peak-to-Peak Saw-tooth Amplitude (Note 9) VIN = 12V 1.2 V VIN = 5.0V 0.55 V 1 V Ramp Offset 125 155 ns SWITCHING FREQUENCY (Note 10) FSW VRT Switching Frequency RT = 20.5kΩ 1080 1200 1320 kHz Switching Frequency RT = 169kΩ 168 198 228 kHz Switching Frequency RT = 49.9kΩ 540 600 660 kHz RT Voltage RT = 49.9kΩ 485 500 515 mV RT = 49.9kΩ 1020 1380 kHz SYNCHRONIZATION FSYNC SYNC Synchronization Range LIGHT LOAD EFFICIENCY MODE VMODETHH MODE/SYNC Threshold High 1.3 1.6 1.9 V VMODETHL MODE/SYNC Threshold Low 1.1 1.4 1.7 V VCROSS Diode Emulation Phase Threshold (Note 11) 10 VIN = 12V -3 mV FN7663.1 February 24, 2012 ISL9443 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. VIN = 5.0V to 28V, or VCC_5V = 5V ±10%, C_VCC_5V = 4.7µF, TA = -40°C to +85°C (Note 9), Typical values are at TA = +25°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS PWM GATE DRIVER (Note 10) IGSRC Source Current 800 mA IGSNK Sink Current 2000 mA RUG_UP Upper Drive Pull-Up VCC_5V = 5.0V 1.5 3 Ω RUG_DN Upper Drive Pull-Down VCC_5V = 5.0V 1.1 2.5 Ω RLG_UP Lower Drive Pull-Up VCC_5V = 5.0V 1.5 3 Ω RLG_DN Lower Drive Pull-Down VCC_5V = 5.0V 0.6 1.5 Ω tGR Rise Time COUT = 1000pF 8 ns tGF Fall Time COUT = 1000pF 10 ns OVERVOLTAGE PROTECTION VOVTH OV Trip Point 114.5 118.5 123.5 % OVERCURRENT PROTECTION IOCSET Overcurrent Threshold (OCSET_) (Note 11) ROCSET = 55kΩ Full Scale Input Current (ISEN_) (Note 11) VOCSET Overcurrent Set Voltage (OCSET_) 1.67 32 µA 15 µA 1.74 1.81 V OVER-TEMPERATURE (Note 9) TOT-TH Over-Temperature Shutdown 150 °C TOT-HYS Over-Temperature Hysteresis 15 °C NOTES: 6. In normal operation, where the device is supplied with voltage on the VIN pin, the VCC_5V pin provides a 5V output capable of 75mA (min). When the VCC_5V pin is connected to external 5V supply, the internal LDO regulator is disabled. The voltage at VCC_5V should not exceed the voltage at VIN at any time. (Refer to the “Pin Descriptions” on page 2 for more details.) 7. This is the total shutdown current with VIN = 5.6V and 28V. 8. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current. 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. Check Note 6 for VCC_5V and VIN configurations. 11. Threshold voltage at PHASE1, PHASE2, PHASE3 pins for turning off the bottom MOSFET during DEM. 11 FN7663.1 February 24, 2012 ISL9443 Typical Performance Curves Oscilloscope plots are taken using the ISL9443EVAL1Z Evaluation Board, VIN = 12V, VOUT1 = 0.9V, VOUT2 = 1.0V, VOUT3 = 0.9V unless otherwise noted. 5.3 OPERATING CURRENT (mA) SHUTDOWN CURRENT (µA) 33.0 32.5 32.0 31.5 31.0 30.5 30.0 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 3 2 1 150 200 250 VCC5V LOAD CURRENT (mA) NORMALIZED OUTPUT VOLTAGE (%) 4.5 -20 0 20 40 60 80 100 1.6 CHANNELS 1 AND 3 1.2 CHANNEL 2 0.8 0.4 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SOFT-START PIN VOLTAGE (V) FIGURE 4. VCC5V LOAD REGULATION 120 SOFT-START CHARGING CURRENT (µA) VCC5 VOLTAGE (V) 4 100 VIN = 4.5V FIGURE 3. QUIESCENT CURRENT vs TEMPERATURE 5 50 4.7 TEMPERATURE (°C) 6 0 4.9 4.3 -40 100 FIGURE 2. SHUTDOWN CURRENT vs TEMPERATURE 0 VIN = 28V 5.1 FIGURE 5. SOFT-START PIN CHARGING CURRENT vs VOLTAGE ON SOFT-START PIN CHANNELS 2 AND 3 PWM1 100 80 PWM2 60 CHANNEL 1 PWM3 40 20 TIME AT 1µs/DIV 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SOFT-START PIN VOLTAGE (V) FIGURE 6. NORMALIZED OUTPUT VOLTAGE VS VOLTAGE ON SOFT-START PIN 12 FIGURE 7. PHASE NODE WAVEFORMS FN7663.1 February 24, 2012 ISL9443 Typical Performance Curves Oscilloscope plots are taken using the ISL9443EVAL1Z Evaluation Board, VIN = 12V, VOUT1 = 0.9V, VOUT2 = 1.0V, VOUT3 = 0.9V unless otherwise noted. (Continued) 720 REFERENCE VOLTAGE (mV) SWITCHING FREQUENCY (kHz) 650 630 610 590 570 550 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 VOUT1 0.898 40 30 20 0.894 10 0 0 5 10 15 20 0.890 25 INPUT CURRENT (A) EFFICIENCY (%) 0.902 PWM1 OUTPUT VOLTAGE (V) 0.906 70 50 -20 0 20 40 60 TEMPERATURE (°C) 80 100 10 0.910 80 60 690 FIGURE 9. REFERENCE VOLTAGE vs TEMPERATURE EFFICIENCY @ CCM (%) 90 700 680 -40 100 FIGURE 8. SWITCHING FREQUENCY vs TEMPERATURE (RT = 49.9 kΩ) 100 710 1 CCM DEM 0.1 0.01 0.001 0.01 0.1 1 10 LOAD CURRENT (A) LOAD CURRENT (A) FIGURE 10. PWM1 EFFICIENCY AND LOAD REGULATION VOUT1 AT 500mV/DIV FIGURE 11. PWM1 INPUT CURRENT COMPARISON WITH MODE = CCM/DEM VOUT2 AT 1V/DIV TKSS2 AT 2V/DIV ENSS1 AT 1V/DIV VOUT2 AT 1V/DIV TKSS3 AT 2V/DIV TIME AT 10ms/DIV FIGURE 12. PWM1 START-UP WAVEFORM 13 TIME AT 10ms/DIV FIGURE 13. PWM2 AND PWM3 START-UP WAVEFORMS FN7663.1 February 24, 2012 ISL9443 Typical Performance Curves Oscilloscope plots are taken using the ISL9443EVAL1Z Evaluation Board, VIN = 12V, VOUT1 = 0.9V, VOUT2 = 1.0V, VOUT3 = 0.9V unless otherwise noted. (Continued) VOUT1 AT 500mV/DIV VOUT1 AT 500mV/DIV VOUT2 AT 500mV/DIV VOUT2 AT 500mV/DIV VOUT3 AT 500mV/DIV VOUT3 AT 500mV/DIV PGOOD AT 5V/DIV TIME AT 10ms/DIV FIGURE 14. PGOOD RISING WAVEFORM PGOOD AT 5V/DIV TIME AT 10ms/DIV FIGURE 15. PRE-BIASED START-UP WAVEFORM VOUT1 AT 20mV/DIV, LOAD = 0mA VOUT1 AT 20mV/DIV, LOAD = 0mA TIME AT 10ms/DIV TIME AT 2µs/DIV VOUT1 AT 20mV/DIV, LOAD = 100mA VOUT1 AT 20mV/DIV, LOAD = 100mA TIME AT 10µs/DIV TIME AT 2µs/DIV VOUT1 AT 20mV/DIV, LOAD = 10A VOUT1 AT 20mV/DIV, LOAD = 10A TIME AT 2µs/DIV TIME AT 2µs/DIV FIGURE 16. PWM1 OUTPUT RIPPLE. MODE = 0V (DEM) VOUT1 AT 100mV/DIV FIGURE 17. PWM1 OUTPUT RIPPLE. MODE = 5V (CCM) VOUT1 AT 1V/DIV VOUT2 AT 100mV/DIV ENSS1 AT 5V/DIV VOUT3 AT 100mV/DIV OUTPUT CURRENT AT 10A/DIV 15A 5A 5A TIME AT 20µs/DIV FIGURE 18. PWM1 LOAD TRANSIENT RESPONSE 14 PGOOD AT 5V/DIV TIME AT 50ms/DIV FIGURE 19. PWM1 OCP RESPONSE, OUTPUT SHORT CIRCUITED TO GROUND FN7663.1 February 24, 2012 ISL9443 Functional Description The internal LDO has an overcurrent limit of typically 150mA. For better efficiency, connect VCC_5V to VIN for 5V ±10% input applications. General Description The ISL9443 integrates control circuits for three synchronous buck converters. The three synchronous bucks operate out-of-phase to substantially reduce the input ripple and thus reduce the input filter requirements. Each part has separate enable/disable control lines (EN/SS1, EN23), which provide flexible power-up sequencing. The soft-start time is programmable individually by adjusting the soft-start capacitors connected from EN/SS1, TK/SS2 and TK/SS3 respectively. The valley current mode control scheme with input voltage feed-forward ramp simplifies loop compensation and provides excellent rejection to input voltage variation. Input Voltage Range The ISL9443 is designed to operate from input supplies ranging from 4.5V to 28V. The input voltage range can be effectively limited by the available minimum PWM off time. V OUT + V d1 ⎛ ⎞ V IN ( min ) = ⎜ -----------------------------------------------------------------------⎟ + V d2 – V d1 1 – t ⎝ OFF ( min ) × Frequency⎠ (EQ. 2) Where, Vd1 = sum of the parasitic voltage drops in the inductor discharge path, including the lower FET, inductor and PC board. Vd2 = sum of the voltage drops in the charging path, including the upper FET, inductor and PC board resistances. The maximum input voltage and minimum output voltage is limited by the minimum on-time tON(min). V OUT ⎛ ⎞ V IN ( max ) ≤ V OUT x ⎜ ------------------------------------------------------------⎟ t × Frequency ⎝ ON ( min ) ⎠ (EQ. 3) Where tON(min) = 100ns Internal 5V Linear Regulator (VCC_5V) All ISL9443 functions are internally powered from an on-chip, low dropout 5V regulator. Bypass the linear regulator’s output (VCC_5V) with a 4.7µF capacitor to the power ground. The ISL9443 also employs an undervoltage lockout circuit that disables all regulators when VCC_5V falls below 3.6V. The internal LDO can source over 75mA to supply the IC, power the low side gate drivers and charge the boot capacitors. When driving large FETs at high switching frequency, little or no regulator current may be available for external loads. For example, a single large FET with 15nC total gate charge requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA). Also, at higher input voltages with larger FETs, the power dissipation across the internal 5V will increase. Excessive dissipation across this regulator must be avoided to prevent junction temperature rise. Thermal protection may be triggered if die temperature increases above +150°C due to excessive power dissipation. Enable Signals and Soft-Start Operation Typical applications for the ISL9443 use programmable analog soft-start or the TK/SSx pins for tracking. The soft-start time can be set by the value of the soft-start capacitors connected from the EN/SS1 for PWM1 to ground and from TK/SSx pins to ground for PWM2 and PWM3. Inrush current during start-up can be alleviated by adjusting the soft-start time. After the VCC_5V pin reaches the UVLO threshold, the ISL9443 PWM1 soft-start circuitry becomes active. The internal 1.55µA charge current begins charging up the soft-start capacitor connected from the EN/SS1 pin to GND. The PWM1 output remains inactive until voltage on the EN/SS1 pin reaches 1.3V. As the voltage on the EN/SS1 pin rises from 1.3V to 2V, the PWM1 reference voltage is clamped to the voltage on the EN/SS1 pin minus 1.3V. PWM1 output voltage thus rises from 0V to regulation as EN/SS1 rises from 1.3V to 2V. Charging of the soft-start capacitor continues until the voltage on the EN/SS1 pin reaches 3.5V. Power sequencing can be achieved by using the EN23 and TK/SSx pins. When the EN23 pin is pulled high, the internal 1.55µA charge current begins charging up the soft-start capacitor connected from the TK/SSx pin to GND. The respective reference voltage is clamped to the voltage on the TK/SSx pin. Thus, PWM2 and PWM3 output voltages ramp from 0V to regulation as voltage on TK/SS2 and TK/SS3 goes up from 0V to 0.7V. Charging of the soft-start capacitors continues until the voltage on the TK/SSx reaches 3.5V. The typical soft-start time is set according to Equation 4: C SSx t SSx = 0.7V ⎛ --------------------⎞ ⎝ 1.55μA⎠ (EQ. 4) For PWM2 and PWM3, when the soft-start time set by external CSS or tracking is less than 2ms, an internal soft-start circuit of 2ms takes over the soft-start. There is no internal soft-start for PWM1. PGOOD will toggle to high when all the outputs are up and in regulation. Pulling the EN23 low disables the PWM2 and PWM3 channels. The TK/SSx pin will also be discharged to GND by internal MOSFETs. Output Voltage Programming The ISL9443 provides a precision internal reference voltage to set the output voltage. Based on this internal reference, the output voltage can thus be set from 0.7V up to a level determined by the input voltage, the maximum duty cycle, and the conversion efficiency of the circuit. A resistive divider from the output to ground sets the output voltage of any PWM channel. The center point of the divider shall be connected to the FBx pin. The output voltage value is 15 FN7663.1 February 24, 2012 ISL9443 determined by Equation 5. R1 + R2 V OUTx = 0.7V ⎛ ----------------------⎞ ⎝ R2 ⎠ (EQ. 5) where R1 is the top resistor of the feedback divider network and R2 is the bottom resistor connected from FBx to ground. set by a resistor connected from the RT pin to GND according to Equation 1. Frequency setting curve shown in Figure 20 assists in selecting the correct value for RT. 1250 Tracking Operation To minimize the impact of the 1.55µA soft-start current on the tracking function, it is recommended to use resistors of less than 10kΩ for the tracking resistive dividers. When overcurrent-protection (OCP) is triggered for the slave PWM channel, the internal minimum soft-start circuit determines the OCP soft-start hiccup. Light Load Efficiency Enhancement When MODE/SYNC pin is tied to GND, the ISL9443 operates in high efficiency diode emulation mode and pulse skipping mode in light load condition. The inductor current is not allowed to reverse (discontinuous operation). At very light loads, the converter goes into diode emulation and triggers the pulse skipping function. Here, the upper MOSFET remains off until the output voltage drops to the point the error amplifier output goes above the pulse skipping mode threshold. The minimum tON in the pulse skipping mode is 80ns, please select the switching frequency so the PWM tON is greater than 80ns at maximum VIN at no load. Pre-biased Power-Up The ISL9443 has the ability to soft-start with a pre-biased output. The output voltage would not be yanked down during pre-biased start-up. The PWM is not active until the soft-start ramp reaches the output voltage times the resistive divider ratio. Overvoltage protection is alive during soft-starting. Frequency Selection Switching frequency selection is a trade-off between efficiency and component size. Low switching frequency improves efficiency by reducing MOSFET switching loss. To meet output ripple and load transient requirements, operation at a low switching frequency would require larger inductance and output capacitance. The switching frequency of the ISL9443 is 16 1000 FREQUENCY (kHz) The PWM2 and PWM3 of the ISL9443 can be independently set up to track the output of another PWM or an external supply. In the following discussion, we refer to the voltage rail to be tracked as the master rail while we refer to the voltage rail that follows the master as the slave rail. To implement tracking, an additional resistive divider is connected between the master rail and ground. The center point of the divider shall be connected to the TK/SSx pin of the slave PWM. The resistive divider ratio sets the ramping ratio between the two voltage rails. To implement coincident tracking, set the tracking resistive divider ratio exactly the same as the slave rail output resistive divider given by Equation 5. Make sure that the voltage at TK/SSx is greater than 0.7V when the master rail reaches regulation. 750 500 250 0 0 20 40 60 80 100 RT (kΩ) 120 140 160 180 FIGURE 20. RT vs SWITCHING FREQUENCY Frequency Synchronization The MODE/SYNC pin may be used to synchronize the ISL9443 with an external clock. When the MODE/SYNC pin is connected to an external clock, the ISL9443 will synchronize to this external clock at half of the clock frequency. For proper operation, the frequency setting resistor, RT, should be set according to Equation 1. When frequency synchronization is in action, the controllers will enter forced continuous current mode at light load. Out-of-Phase Operation To reduce input ripple current, the three PWM channels operate 180° out-of-phase. This reduces the input capacitor ripple current requirements, reduces power supply-induced noise, and improves EMI. This effectively helps to lower component cost, save board space and reduce EMI. Triple PWMs traditionally operate in-phase and turn on all three upper FETs at the same time. The input capacitor must then support the instantaneous current requirements of the three switching regulators simultaneously, resulting in increased ripple voltage and current. The higher RMS ripple current lowers the efficiency due to the power loss associated with the ESR of the input capacitor. This typically requires more low-ESR capacitors in parallel to minimize the input voltage ripple and ESR-related losses, or to meet the required ripple current specification. With synchronized out-of-phase operation, the high-side MOSFETs turn off 180° out-of-phase. The instantaneous input current peaks of both regulators no longer overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the required input capacitor ripple current rating, allowing fewer or less expensive capacitors, and reducing the shielding requirements for EMI. The typical operating curves show the synchronized 180° out-of-phase operation. FN7663.1 February 24, 2012 ISL9443 Gate Control Logic Adaptive Dead-Time The gate control logic translates generated PWM signals into gate drive signals providing amplification, level shifting and shoot-through protection. The gate drivers have circuitry that helps optimize the IC performance over a wide range of operational conditions. As MOSFET switching times can vary dramatically from type to type and with input voltage, the gate control logic provides adaptive dead-time by monitoring real gate waveforms of both the upper and lower MOSFETs. Shoot-through control logic provides a 16ns dead-time to ensure that both the upper and lower MOSFETs will not turn on simultaneously causing a shoot-through condition. The ISL9443 incorporates an adaptive dead-time algorithm on the synchronous buck PWM controllers that optimizes operation with varying MOSFET conditions. This algorithm provides approximately 16ns of dead-time between switching the upper and lower MOSFET’s. This dead-time is adaptive and allows operation with different MOSFET’s without having to externally adjust the dead-time using a resistor or capacitor. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a threshold of 1V, at which time the UGATE is released to rise. Adaptive dead-time circuitry monitors the upper MOSFET gate voltage during UGATE turn-off. Once the upper MOSFET gate-to-source voltage has dropped below a threshold of 1V, the LGATE is allowed to rise. Gate Drivers The low-side gate drivers are supplied from VCC_5V and provide a peak sink current of 2A and source current of 800mA for each PWM channel. The high-side gate drivers are also capable of delivering the same currents as the low-side gate drivers. Gate-drive voltage for the upper N-Channel MOSFETs are generated by flying capacitor boot circuits. A boot capacitor connected from the BOOT pin to the PHASE node provides power to the high-side MOSFET driver. To limit the peak current in the IC, an external resistor may be placed between the BOOT pin and the boot capacitor. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET’s input capacitance. At start-up, the low-side MOSFET turns on first and forces PHASE to ground in order to charge the BOOT capacitor to 5V. After the low-side MOSFET turns off, the high-side MOSFET is turned on by closing an internal switch between BOOT and UGATE. This provides the necessary gate-to-source voltage to turn on the upper MOSFET, an action that boosts the 5V gate drive signal above VIN. The current required to drive the upper MOSFET is drawn from the internal 5V regulator. For optimal EMI performance or reducing phase node ringing, a small resistor might be placed between these pins to the positive terminal of the bootstrap capacitors. VCC_5V BOOT OPTIONAL EXTERNAL SCHOTTKY VIN The ISL9443 has integrated bootstrap diodes to help reduce total cost and reduce layout complexity. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap capacitor must have a maximum voltage rating above the maximum input voltage plus 5V. The bootstrap capacitor can be chosen from Equation 6. Q GATE C BOOT ≥ --------------------ΔV BOOT (EQ. 6) Where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The ΔVBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose an upper MOSFET has a gate charge (QGATE) of 25nC at 5V and also assume the droop in the drive voltage over a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125µF is required. The next larger standard value capacitance of 0.22µF should be used. A good quality ceramic capacitor is recommended. The internal bootstrap Schottky diodes have a resistance of 1.5Ω (typ) at 800mA. Combined with the resistance RBOOT, this could lead to the boot capacitor charging insufficiently in cases where the bottom MOSFET is turned on for a very short time. If such circumstances are expected, an additional external Schottky diode may be added from VCC_5V to the positive of the boot capacitor. RBOOT may still be necessary to lower EMI due to fast turn-on of the upper MOSFET. Power-Good Indicator RBOOT CB UGATE Internal Bootstrap Diode PHASE The PGOOD pin can be used to indicate the status of the outputs. PGOOD will be true (open drain) when all three FB pins are within ±11% of the internal voltage reference. Protection Circuits The converter outputs are monitored and protected against overload, short circuit and undervoltage conditions. ISL9443 FIGURE 21. UPPER GATE DRIVER CIRCUIT Undervoltage Lockout The ISL9443 includes UVLO protection which keeps the device in a reset condition until a proper operating voltage is applied. It also shuts down the ISL9443 if the operating voltage drops below a pre-defined value. All controllers are disabled when UVLO 17 FN7663.1 February 24, 2012 ISL9443 is asserted. When UVLO is asserted, PGOOD is valid and will be de-asserted. Overcurrent Protection All the PWM controllers use the lower MOSFET's on-resistance, rDS(ON) , to monitor the current in the converter. The sensed voltage drop is compared with a threshold set by a resistor connected from the OCSETx pin to ground. ( 7 ) ( R CS ) R OCSET = --------------------------------------( I OC ) ( r DS ( ON ) ) (EQ. 7) Where IOC is the desired overcurrent protection threshold, and RCS is a value of the current sense resistor connected to the ISENx pin. If an overcurrent is detected for 2 consecutive clock cycles, the IC enters a hiccup mode by turning off the gate drivers and entering soft-start. The IC will cycle 5 times through soft-start before trying to restart. The IC will continue to cycle through soft-start until the overcurrent condition is removed. Hiccup mode is active during soft-start so care must be taken to ensure that the peak inductor current does not exceed the overcurrent threshold during soft-start. Because of the nature of this current sensing technique, and to accommodate a wide range of rDS(ON) variations, the value of the overcurrent threshold should represent an overload current about 150% to 180% of the maximum operating current. If more accurate current protection is desired, place a current sense resistor in series with the lower MOSFET source. When OCP is triggered the EN/SS1 or TK/SSx pins are pulled to ground by internal MOSFET. For PWM rails configured to track another voltage rail the TK/SSx pin rises up much faster than the internal minimum soft-start ramp. The voltage reference will then be clamped to the internal minimum soft-start ramp. Thus, smooth soft-start hiccup is achieved even with the tracking function. Overvoltage Protection All switching controllers within the ISL9443 have fixed overvoltage set points. The overvoltage set point is set at 118% of the nominal output voltage, the output voltage set by the feedback resistors. In the case of an overvoltage event, the IC will attempt to bring the output voltage back into regulation by keeping the upper MOSFET turned off and modulating the lower MOSFET for 2 consecutive PWM cycles. If the overvoltage condition has not been corrected in 2 cycles and the output voltage is above 118% of the nominal output voltage, the ISL9443 will turn off both the upper MOSFET and the lower MOSFET. The ISL9443 will enter hiccup mode until the output voltage return to 110% of the nominal output voltage. Over-Temperature Protection The IC incorporates an over-temperature protection circuit that shuts the IC down when a die temperature of +150°C is reached. Normal operation resumes when the die temperatures drops below +130°C through the initiation of a full soft-start cycle. When all the three channels are disabled, thermal protection is inactive. This helps achieve a very low shutdown current of 33µA. 18 Feedback Loop Compensation To reduce the number of external components and to simplify the process of determining compensation components, all PWM controllers have internally compensated error amplifiers. To make internal compensation possible, several design measures were taken. Firstly, the ramp signal applied to the PWM comparator is proportional to the input voltage provided at the VIN pin. This keeps the modulator gain constant with varying input voltages. Secondly, the load current proportional signal is derived from the voltage drop across the lower MOSFET during the PWM time interval and is subtracted from the amplified error signal on the comparator input. This creates an internal current control loop. The resistor connected to the ISEN pin sets the gain in the current feedback loop. The following expression estimates the required value of the current sense resistor depending on the maximum operating load current and the value of the MOSFET’s rDS(ON). ( I MAX ) ( r DS ( ON ) ) R CS ≥ -------------------------------------------30μA (EQ. 8) Choosing RCS to provide 30µA of current to the current sample and hold circuitry is recommended but values down to 2µA and up to 100µA can be used. A higher sampling current will help to stabilize the loop. Due to the current loop feedback, the modulator has a single pole response with -20dB slope at a frequency determined by the load. 1 F PO = -----------------------------2π ⋅ R O ⋅ C O (EQ. 9) Where RO is load resistance and CO is load capacitance. For this type of modulator, a Type 2 compensation circuit is usually sufficient. Figure 22 shows a Type 2 amplifier and its response along with the responses of the current mode modulator and the converter. The Type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. 1 F Z = ------------------------------ = 10kHz 2π ⋅ R 2 ⋅ C 1 (EQ. 10) 1 F P = ------------------------------ = 600kHz 2π ⋅ R 1 ⋅ C 2 (EQ. 11) Zero frequency, amplifier high-frequency gain and modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation, plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. FN7663.1 February 24, 2012 ISL9443 Layout Considerations C2 R2 1. The input capacitors, upper FET, lower FET, inductor and output capacitor should be placed first. Isolate these power components on the topside of the board with their ground terminals adjacent to one another. Place the input high frequency decoupling ceramic capacitors very close to the MOSFETs. C1 CONVERTER R1 EA TYPE 2 EA GM = 17.5dB GEA = 18dB MODULATOR FZ FPO FP FC 2. Use separate ground planes for power ground and small signal ground. Connect the SGND and PGND together close to the IC. Do not connect them together anywhere else. 3. The loop formed by the input capacitor, the top FET and the bottom FET must be kept as small as possible. 4. Ensure the current paths from the input capacitor to the MOSFET, to the output inductor and output capacitor are as short as possible with maximum allowable trace widths. FIGURE 22. FEEDBACK LOOP COMPENSATION Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 1.2kHz to 30kHz range gives some additional phase ‘boost’. Some phase boost can also be achieved by connecting capacitor CZ in parallel with the upper resistor R1 of the divider that sets the output voltage value. Please refer to “Input Capacitor Selection” on page 21 for further details. Layout Guidelines Careful attention to layout requirements is necessary for successful implementation of an ISL9443 based DC/DC converter. The ISL9443s switch at a very high frequency and therefore the switching times are very short. At these switching frequencies, even the shortest trace has significant impedance. Also, the peak gate drive current rises significantly in an extremely short time. Transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, generate EMI, increase device overvoltage stress and ringing. Careful component selection and proper PC board layout minimizes the magnitude of these voltage spikes. There are three sets of critical components in a DC/DC converter using the ISL9443: The controller, the switching power components and the small signal components. The switching power components are the most critical from a layout point of view because they switch a large amount of energy, so they tend to generate a large amount of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. A multi-layer printed circuit board is recommended. 19 5. Place The PWM controller IC close to the lower FET. The LGATE connection should be short and wide. The IC can be best placed over a quiet ground area. Avoid switching ground loop currents in this area. 6. Place the VCC_5V bypass capacitor very close to the VCC_5V pin of the IC and connect its ground to the PGND plane. 7. Place the gate drive components - optional BOOT diode and BOOT capacitors - together near the controller IC. 8. The output capacitors should be placed as close to the load as possible. Use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. 9. Use copper filled polygons or wide but short trace to connect the junction of the upper FET, Lower FET and output inductor. Also, keep the PHASE node connection to the IC short. Do not unnecessarily oversize the copper islands for PHASE node. Since the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. 10. Route all high speed switching nodes away from the control circuitry. 11. Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. All small signal grounding paths including feedback resistors, current limit setting resistors, soft-starting capacitors and ENx pull-down resistors should be connected to this SGND plane. 12. Separate current sensing traces from PHASE node connections. 13. Ensure the feedback connection to the output capacitor is short and direct. FN7663.1 February 24, 2012 ISL9443 General PowerPAD Design Considerations Output Inductor Selection The following is an example of how to use vias to remove heat form the IC. The PWM converters require output inductors. The output inductor is selected to meet the output voltage ripple requirements. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current and the output capacitor(s) ESR. The ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by Equation 14: ( V IN – V OUT ) ( V OUT ) ΔI L = --------------------------------------------------( f S ) ( L ) ( V IN ) (EQ. 14) Output Capacitor Selection FIGURE 23. PCB VIA PATTERN It is recommended to fill the thermal pad area with vias. A typical via array fills the thermal pad foot print such that their centers are 3x the radius apart from each other. Keep the vias small but not so small that their inside diameter prevents solder wicking through during reflow. Connect all vias to the ground plane. It is important the vias have a low thermal resistance for efficient heat transfer. It is important to have a complete connection of the plated-through hole to each plane. Component Selection Guideline MOSFET Considerations The logic level MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements. Two N-Channel MOSFETs are used in each of the synchronous-rectified buck converters for the 3 PWM outputs. These MOSFETs should be selected based upon rDS(ON), gate supply requirements, and thermal management considerations. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty cycle (see the following equations). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. The equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower MOSFET’s body diode. 2 ( I O ) ( r DS ( ON ) ) ( V OUT ) ( I O ) ( V IN ) ( t SW ) ( F SW ) P UPPER = ---------------------------------------------------------- + -------------------------------------------------------V IN 2 (EQ. 12) 2 ( I O ) ( r DS ( ON ) ) ( V IN – V OUT ) P LOWER = -----------------------------------------------------------------------V IN (EQ. 13) A large gate-charge increases the switching time, tSW, which increases the upper MOSFETs’ switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. 20 The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. Selection of output capacitors is also dependent on the output inductor, so some inductor analysis is required to select the output capacitors. One of the parameters limiting the converter’s response to a load transient is the time required for the inductor current to slew to its new level. The ISL9443 will provide either 0% or maximum duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. Also, if the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, it reduces the requirement on the output capacitor. The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is: 2 ( L O ) ( I TRAN ) C OUT = ----------------------------------------------------2 ( V IN – V O ) ( DV OUT ) (EQ. 15) Where COUT is the output capacitor(s) required, LO is the output inductor, ITRAN is the transient load current step, VIN is the input voltage, VO is output voltage, and DVOUT is the drop in output voltage allowed during the load transient. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Equivalent Series Resistance) and voltage rating requirements as well as actual capacitance requirements. The output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by: V RIPPLE = ΔI L ( ESR ) (EQ. 16) Where IL is calculated in the “Output Inductor Selection” on page 20. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load circuitry for specific decoupling requirements. FN7663.1 February 24, 2012 ISL9443 Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. In most cases, multiple small-case electrolytic capacitors perform better than a single large-case capacitor. 1 C OUT = ---------------------------------2π ( ESR ) ( f Z ) (EQ. 17) 1. They must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient. 2. The ESR must be sufficiently low to meet the desired output voltage ripple due to the output inductor current. 3. The ESR zero should be placed, in a rather large range, to provide additional phase margin. The recommended output capacitor value for the ISL9443 is between 100µF to 680µF, to meet stability criteria with external compensation. Use of aluminum electrolytic (POSCAP) or tantalum type capacitors is recommended. Use of low ESR ceramic capacitors is possible but would take more rigorous loop analysis to ensure stability. Input Capacitor Selection The important parameters for the bulk input capacitor(s) are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. The AC RMS Input current varies with the load. The total RMS current supplied by the input capacitance is: 2 4.0 IN PHASE 3.5 3.0 2.5 OUT-OF-PHASE 2.0 1.5 5V 3.3V 1.0 0.5 In conclusion, the output capacitors must meet three criteria: I RMS = 4.5 INPUT RMS CURRENT The stability requirement on the selection of the output capacitor is that the ‘ESR zero’ (f Z) be between 2kHz and 60kHz. This range is set by an internal, single compensation zero at 8.8kHz. The ESR zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the control loop. Therefore: 5.0 2 I RMS1 + I RMS2 (EQ. 18) 0 0 1 2 3 3.3V AND 5V LOAD CURRENT 4 5 FIGURE 24. INPUT RMS CURRENT vs LOAD Depending on the specifics of the input power and its impedance, most (or all) of this current is supplied by the input capacitor(s). Figure 24 shows the advantage of having the PWM converters operating out-of-phase. If the converters were operating in-phase, the combined RMS current would be the algebraic sum, which is a much larger value as shown. The combined out-of-phase current is the square root of the sum of the square of the individual reflected currents and is significantly less than the combined in-phase current. Use a mix of input bypass capacitors to control the voltage ripple across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For board designs that allow through-hole components, the Sanyo OS-CON™ series offers low ESR and good temperature performance. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX is surge current tested. Where DC is duty cycle of the respective PWM. I RMSx = 2 DC – DC ⋅ I O (EQ. 19) 21 FN7663.1 February 24, 2012 ISL9443 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE February 13, 2012 June 20, 2011 REVISION CHANGE FN7663.1 Changed Input Voltage Range from “4.5V to 26V” to “4.5V to 28V” throughout datasheet. Page 3 - Pin Description table, Pin 17/MODE/SYNC: Update 2nd sentence from “Tie this pin to ground or VCC_5V for light load operation mode selection.” to “Tie this pin to ground or VCC_5V for DEM or CCM operation mode selection.” FN7663.0 Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL9443 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 FN7663.1 February 24, 2012 ISL9443 Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 5/10 4X 3.5 5.00 28X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 32 25 1 5.00 24 3 .30 ± 0 . 15 17 (4X) 8 0.15 9 16 TOP VIEW 0.10 M C A B + 0.07 32X 0.40 ± 0.10 4 32X 0.23 - 0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( ( 28X 0 . 5 ) SIDE VIEW 3. 30 ) (32X 0 . 23 ) C 0 . 2 REF 5 ( 32X 0 . 60) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 23 FN7663.1 February 24, 2012