AD AD14060LBF-4 Quad-sharc dsp multiprocessor family Datasheet

a
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer.
The AD14060/AD14060L modules have the highest performance —density and lowest cost—performance ratios of any in
their class. They are ideal for applications requiring higher levels
of performance and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in multiprocessing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The onchip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
IRQ2-0
FLAG2,0
CPA
SPORT 1
SPORT 0
TCK, TMS, TRST
FLAG1
FLAG3
TDO
RESET
IRQ2-0
CS
TIMEXP
LINK 1
LINK 3
LINK 4
(ID2-0 = 2)
EBOOT,
LBOOT, BMS
EMU
CLKIN
FLAG3
SHARC_B
SPORT 0
TCK, TMS, TRST
FLAG1
FLAG3
TDI
LINK 4
LINK 3
LINK 1
(ID2-0 = 3)
IRQ2-0
SHARC_C
CPA
SPORT 1
FLAG2,0
RESET
EMU
CLKIN
EBOOT,
LBOOT, BMS
LINK 0
LINK 2
LINK 5
TDO
TIMEXP
LINK 0
LINK 2
LINK 5
TDI
CS
FLAG2,0
(ID2-0 = 4)
IRQ2-0
SHARC_D
FLAG3
SPORT 0
TCK, TMS, TRST
FLAG1
RESET
SBTS, HBR, HBG, REDY, BR6-1, RPBA, DMAR1.2, DMAG1.2)
EMU
CLKIN
EBOOT,
LBOOT, BMS
LINK 0
LINK 2
LINK 5
TDI
SHARC BUS (ADDR31-0, DATA47-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK,
CPA
SPORT 1
TDO
SPORT 0
TCK, TMS, TRST
FLAG1
RESET
(ID2-0 = 1)
AD14060/
AD14060L
PACKAGING FEATURES
308-Lead Ceramic Quad Flatpack (CQFP)
2.05" (52 mm) Body Size
Cavity Up or Down, Configurable
Low Profile, 0.160" Height
Hermetic
25 Mil (0.65 mm) Lead Pitch
29 Grams (typical)
u JC = 0.368C/W
LINK 0
LINK 2
LINK 5
TDO
SHARC_A
EBOOT,
LBOOT, BMS
EMU
CLKIN
CPA
SPORT 1
TDI
FLAG2,0
CS
TIMEXP
LINK 1
LINK 3
LINK 4
FUNCTIONAL BLOCK DIAGRAM
CS
TIMEXP
LINK 1
LINK 3
LINK 4
PERFORMANCE FEATURES
ADSP-21060 Core Processor (. . . 34)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Twelve 40 Mbyte/s Link Ports (Three per SHARC)
Four 40 Mbit/s Independent Serial Ports (One from
Each SHARC)
One 40 Mbit/s Common Serial Port
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
Quad-SHARC®
DSP Multiprocessor Family
AD14060/AD14060L
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, each SHARC has a direct
link port connection. Externally, each SHARC has a total of
120 Mbytes/s link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and optimized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
SHARC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
AD14060/AD14060L
DETAILED DESCRIPTION
Architectural Features
ADSP-21060 Core
The SHARCs contain 4 Mbits of on-chip SRAM each, organized as two blocks of 2 Mbits, which can be configured for
different combinations of code and data storage. The memory
can be configured as a maximum of 128K words of 32-bit data,
256K words of 16-bit data, 80K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA controller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
The AD14060/AD14060L is based on the powerful ADSP-21060
(SHARC) DSP chip. The ADSP-21060 SHARC combines a
high performance floating-point DSP core with integrated, onchip system features including a 4 Mbit SRAM memory, host
processor interface, DMA controller, serial ports, and both link
port and parallel bus connectivity for glueless DSP multiprocessing, (see Figure 1). It is fabricated in a high speed, low power
CMOS process, and has a 25 ns instruction cycle time. The arithmetic/ logic unit (ALU), multiplier and shifter all perform singlecycle instructions, and the three units are arranged in parallel,
maximizing computational throughput.
The SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the program memory (PM) bus transfers both instructions and data.
There is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
PM bus data accesses. This combines with the separate program
and data memory buses to enable three-bus operation for fetching an instruction and two operands, all in a single cycle. The
SHARC also contains a general purpose data register file, which
is a 10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For example, the ADSP-21060 can conditionally execute a multiply, an
add, a subtract, and a branch, all in a single instruction.
The AD14060/AD14060L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs are
connected to maximize the performance of this cluster-of-four
architecture, and still allow for off-module expansion. The
AD14060/AD14060L in itself is a complete shared memory
multiprocessing system, as shown in Figure 3. The unified address space of the SHARCs allows direct interprocessor accesses of each SHARCs’ internal memory. In other words, each
SHARC can directly access the internal memory and IOP registers
of each of the other SHARCs by simply reading or writing to the
appropriate address in multiprocessor memory space (see Figure
2)—this is called a direct read or direct write.
TWO INDEPENDENT
DUAL-PORTED BLOCKS
32 x 48-BIT
PROCESSOR PORT
ADDR
DATA
ADDR
DAG1
DAG2
8 x 4 x 32
8 x 4 x 24
I/O PORT
DATA
7
TEST AND
EMULATION
ADDR
DATA
DATA
JTAG
BLOCK 1
INSTRUCTION
CACHE
BLOCK 0
DUAL-PORTED SRAM
CORE PROCESSOR
TIMER
Shared Memory Multiprocessing
ADDR
PROGRAM
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
IOD
48
24
EXTERNAL
PORT
IOA
17
ADDR BUS
MUX
32
32
MULTIPROCESSOR
INTERFACE
BUS
CONNECT
(PX)
PM DATA BUS
48
DM DATA BUS
40/32
DATA BUS
MUX
48
HOST PORT
DATA
REGISTER
FILE
MULTIPLIER
16 x 40-BIT
IOP
REGISTERS
(MEMORY MAPPED)
BARREL
SHIFTER
ALU
CONTROL,
STATUS, AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
36
I/O PROCESSOR
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14060)
–2–
REV. A
AD14060/AD14060L
0x0000 0000
0x0040 0000
IOP REGISTERS
INTERNAL
MEMORY
SPACE
(INDIVIDUAL
SHARCs)
0x0002 0000
BANK 0
0x0004 0000
DRAM
(OPTIONAL)
NORMAL WORD ADDRESSING
MS0
SHORT WORD ADDRESSING
0x0008 0000
INTERNAL MEMORY SPACE
OF SHARC_A
ID=001
BANK 1
MS1
BANK 2
MS2
BANK 3
MS3
0x0010 0000
INTERNAL MEMORY SPACE
OF SHARC_B
ID=010
INTERNAL
TO AD14060
0x0018 0000
INTERNAL MEMORY SPACE
OF SHARC_C
ID=011
0x0020 0000
INTERNAL MEMORY SPACE
OF SHARC_D
ID=100
MULTIPROCESSOR
MEMORY SPACE
EXTERNAL
MEMORY
SPACE
0x0028 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=101
EXTERNAL
TO AD14060
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.
0x0030 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=110
0x0038 0000
BROADCAST WRITE
TO ALL
ADSP-2106xs
NONBANKED
0x003F FFFF
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
0xFFFF FFFF
Figure 2. AD14060/AD14060L Memory Map
SYSTEM EXPANSION
1X CLOCK
CLKIN
RESET
RPBA
CPA
SHARC_A
SHARC_B
LINKS 1, 3, & 4;
IRQ2-0;
FLAGS 2 & 0;
TIMEXP,
SPORT1
LINKS 1, 3, & 4;
IRQ2-0;
FLAGS 2 & 0;
TIMEXP,
SPORT1
ADDR31-0
DATA47-0
RD
WR
ACK
BOOTSELECT A
MS3-0
BOOTSELECT BCD
PAGE
DMAR1,2
DMAG1,2
SPORT0
FLAG1
JTAG
AD14060/AD14060L
(QUAD PROCESSOR
CLUSTER)
SHARC_D
SHARC_C
LINKS 1, 3, & 4;
IRQ2-0;
FLAGS 2 & 0;
TIMEXP,
SPORT1
LINKS 1, 3, & 4;
IRQ2-0;
FLAGS 2 & 0;
TIMEXP,
SPORT1
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
BR1-6
Figure 3. Complete Shared Memory Multiprocessing System
REV. A
–3–
AD14060/AD14060L
Bus arbitration is accomplished with the on-SHARC arbitration
logic. Each SHARC has a unique ID, and drives the Bus-Request
(BR) line corresponding to its ID, while monitoring all others.
BR1–BR4 are used within the AD14060/AD14060L, while BR5
and BR6 can be used for expansion. All bus requests (BR1–BR6)
are included in the module I/O.
Two different priority schemes, fixed and rotating, are available
to resolve competing bus requests. The RPBA pin selects which
scheme is used: when RPBA is high, rotating priority bus arbitration is selected, and when RPBA is low, fixed priority is selected.
Table I. Rotating Priority Arbitration Example
Cycle
ID1
Hardware Processor IDs
ID2
ID3
ID4 ID5 ID6
1
2
3
4
5
M
4
4
5 BR
1 BR
1
5 BR
5 BR
M
2
2 BR
M-BR
M
1
3
3
1
1
2
4
4
2
2
3
5
5
Initial Priority Assignments
3
3
4 BR
M
Final Priority Assignments
NOTES
1–5 = Assigned Priority.
M = Bus Mastership (in that cycle).
BR = Requesting Bus Mastership with BRx.
Bus mastership is passed from one SHARC to another during a
bus transition cycle. A bus transition cycle only occurs when the
current bus master deasserts its BR line and one of the slave
SHARCs asserts its BR line. The bus master can therefore retain bus mastership by keeping its BR line asserted. When the
bus master deasserts its BR line, and no other BR line is asserted, then the master will not lose any bus cycles. When more
than one SHARC asserts its BR line, the SHARC with the
highest priority request becomes bus master on the following
cycle. Each SHARC observes all of the BR lines, and therefore
tracks when a bus transition cycle has occurred, and which
processor has become the new bus master. Master processor
changeover incurs only one cycle of overhead. An example bus
transition sequence is shown in Table I.
Bus locking is possible, allowing indivisible read-modify-write
sequences for semaphores. In either the fixed or rotating priority
scheme, it is also possible to limit the number of cycles the
master can control the bus. The AD14060/AD14060L also
provides the option of using the Core Priority Access (CPA)
mode of the SHARC. Using the CPA signal allows external bus
accesses by the core processor of a slave SHARC to take priority
over ongoing DMA transfers. Also, each SHARC can broadcast
write to all other SHARCs simultaneously, allowing the implementation of reflective semaphores.
The bus master can communicate with slave SHARCs by writing messages to their internal IOP registers. The MSRG0–
MSRG7 registers are general-purpose registers that can be used
for convenient message passing, semaphores and resource sharing between the SHARCs. For message passing, the master
communicates with a slave by writing and/or reading any of the
eight message registers on the slave. For vector interrupts, the
master can issue a vector interrupt to a slave by writing the
address of an interrupt service routine to the slave’s VIRPT
register. This causes an immediate high priority interrupt on the
slave which, when serviced, will cause it to branch to the specified service routine.
off-module memory and peripherals (see Figure 5). This port
consists of the complete external port bus of the SHARC, bused
together in common among the four SHARCs.
The 4-gigaword off-module address space is included in the
ADSP-14060’s unified address space. Addressing of external
memory devices is facilitated by each SHARC internally decoding the high order address lines to generate memory bank
select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The AD14060/
AD14060L also supports programmable memory wait states and
external memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold and disable
time requirements.
Link Port I/O
Each individual SHARC features six 4-bit link ports that facilitate SHARC-to-SHARC communication and external I/O interfacing. Each link port can be configured for either 1× or 2×
operation, allowing each to transfer either 4 or 8 bits per cycle.
The link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.
The AD14060/AD14060L optimizes the link port connections
internally, and brings a total of twelve of the link ports off-module for user-defined system connections. Internally, each SHARC
has a connection to the other three SHARCs with a dedicated
link port interface. Thus, each SHARC can directly interface
with its nearest and next-nearest neighbor. The remaining three
link ports from each SHARC are brought out independently
from each SHARC. A maximum of 480 MBytes/s link port
bandwidth is then available off of the AD14060/AD14060L.
The link port connections are detailed in Figure 4.
1
3
1
SHARC_A
5
5
2
2
SHARC_B
4
4
0
0
0
0
1
3
4
3
2
2
5
5
SHARC_D
1
SHARC_C
3
4
Figure 4. Link Port Connections
Link port 4, the boot link port, is brought off independently
from each SHARC. Individual booting is then allowed, or
chained link port booting is possible as described under “Link
Port Booting.”
Link port data is packed into 32-bit or 48-bit words, and can
be directly read by the SHARC core processor or DMAtransferred to on-SHARC memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
Off-Module Memory and Peripherals Interface
transfers. Transfers are programmable as either transmit or
The AD14060/AD14060L’s external port provides the interface to
receive.
REV. A
–4–
AD14060/AD14060L
AD14060/
AD14060L
1x
CLOCK
CLKIN
RESET
RESET
ADDR31–0
ADDR
DATA47–0
DATA
RD
WR
RPBA
OE
WE
ACK
CS
ACK
MS3–0
CONTROL
CS
BMS
PAGE
SBTS
SW
ADRCLK
ADDR
DATA
CS
HBR
HBG
REDY
SERIALS
LINKS
DISCRETES
CPA
BR2–6
BR1
ADDR
5
DATA
ADSP-2106x #5
(OPTIONAL)
ADDR31–0
CLKIN
RESET
DATA47–0
RPBA
101
3
ID 2–0
CONTROL
CPA
BR1, 2, 3, 4, 6
BR5
5
ADSP-2106x #6
(OPTIONAL)
CLKIN
ADDR31–0
RESET
DATA47–0
RPBA
110
3
ID 2–0
CONTROL
CPA
BR1–5
BR6
5
Figure 5. Optional System Interconnections
REV. A
–5–
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
AD14060/AD14060L
Serial Ports
Multiprocessor Link Port Booting
The SHARC serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices. Each
SHARC has two serial ports. The AD14060/AD14060L provides
direct access to Serial Port 1 of each SHARC. Serial Port 0
is bused together in common to each SHARC, and brought
off-module.
Booting can also be accomplished from a single source through
the link ports. Link Buffer 4 must always be used for booting.
To simultaneously boot all of the ADSP-21060s, a parallel
common connection is available through Link Port 4 on each of
the processors. Or, using the daisy chain connection that exists
between the processors’ link ports, each ADSP-21060 can boot
the next one in turn. In this case, the Link Assignment Register
(LAR) must be programmed to configure the internal link ports
with Link Buffer 4.
The serial ports can operate at the full clock rate of the module,
providing each with a maximum data rate of 40 Mbit/s. Independent transmit and receive functions provide more flexible
communications. Serial port data can be automatically transferred to and from on-SHARC memory via DMA, and each of
the serial ports offers time division multiplexed (TDM) multichannel mode.
Multiprocessor Booting From External Memory
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit modes
as well as optional µ-law or A-law companding. Serial port clocks
and frame syncs can be internally or externally generated.
If external memory contains a program after reset, then
SHARC_A should be set up for no boot mode; it will begin executing from address 0x0040 0004 in external memory. When
booting has completed, the other ADSP-21060s may be booted
by SHARC_A if they are set up for host booting, or they can
begin executing out of external memory if they are set up for no
boot mode. Multiprocessor bus arbitration will allow this booting
to occur in an orderly manner.
Program Booting
Host Processor Interface
The AD14060/AD14060L’s host interface allows for easy connection to standard microprocessor buses, both 16-bit and 32bit, with little additional hardware required. Asynchronous
transfers at speeds up to the full clock rate of the module are
supported. The host interface is accessed through the AD14060/
AD14060L external port and is memory-mapped into the unified address space. Four channels of DMA are available for the
host interface; code and data transfers are accomplished with
low software overhead.
The AD14060/AD14060L supports automatic downloading of
programs following power-up or a software reset. The SHARC
offers four options for program booting: 1) from an 8-bit
EPROM; 2) from a host processor; 3) through the link ports;
and 4) no-boot. In no-boot mode, the SHARC starts executing
instructions from address 0x0040 0004 in external memory.
The boot mode is selected by the state of the following signals:
BMS, EBOOT, and LBOOT.
On the AD14060/AD14060L, SHARC_A’s boot mode is separately controlled, while SHARCs B, C, and D are controlled as
a group. With this flexibility, the AD14060/AD14060L can be
configured to boot in any of the following methods.
The host processor requests the AD14060/AD14060L’s external
bus with the host bus request (HBR), host bus grant (HBG),
and ready (REDY) signals. The host can directly read and write
the internal memory of the SHARCs, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
Multiprocessor Host Booting
To boot multiple ADSP-21060 processors from a host, each
ADSP-21060 must have its EBOOT, LBOOT and BMS pins
configured for host booting: EBOOT = 0, LBOOT = 0, and
BMS = 1. After system power-up, each ADSP-21060 will be in
the idle state and the BRx bus request lines will be deasserted.
The host must assert the HBR input and boot each ADSP-21060
by asserting its CS pin and downloading instructions.
Direct Memory Access (DMA) Controller
The SHARCs on-chip DMA control logic allows zero-overhead
data transfers without processor intervention. The DMA controller operates independently and invisibly to each SHARCs
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions.
Multiprocessor EPROM Booting
DMA transfers can occur between SHARC internal memory
and either external memory, external peripherals, or a host
processor. DMA transfers can also occur between the SHARC’s
internal memory and its serial ports or link ports. DMA transfers between external memory and external peripheral devices are
another option. External bus packing to 16-, 32- or 48-bit words
is performed during DMA transfers.
There are two methods of booting the multiprocessor system
from an EPROM.
SHARC_A Is Booted, Which Then Boots the Others. The
EBOOT pin on the SHARC_A must be set high for EPROM
booting. All other ADSP-21060s should be configured for host
booting (EBOOT = 0, LBOOT = 0, and BMS = 1), which
leaves them in the idle state at start-up and allows SHARC_A
to become bus master and boot itself. Only the BMS pin of
SHARC_A is connected to the chip select of the EPROM.
When SHARC_A has finished booting, it can boot the remaining ADSP-21060s by writing to their external port DMA
buffer 0 (EPB0) via multiprocessor memory space.
Ten channels of DMA are available on the SHARCs—two via
the link ports, four via the serial ports, and four via the processor’s
external port (for either host processor, other SHARCs, memory,
or I/O transfers). Four additional link port DMA channels are
shared with serial port 1 and the external port. Programs can be
downloaded to the SHARCs using DMA transfers. Asynchronous
off-module peripherals can control two DMA channels using
DMA Request/Grant lines (DMAR1-2, DMAG1-2). Other
DMA features include interrupt generation upon completion of
DMA transfers and DMA chaining for automatic linked DMA
transfers.
All ADSP-21060s Boot in Turn From a Single EPROM.
The BMS signals from each ADSP-21060 may be wire-ORed
together to drive the chip select pin of the EPROM. Each
ADSP-21060 can boot in turn, according to its priority. When
the last one has finished booting, it must inform the others
(which may be in the idle state) that program execution can begin.
–6–
REV. A
AD14060/AD14060L
Development Tools
The ADSP-14060 is supported with a complete set of software
and hardware development tools, including an EZ-LAB® InCircuit Emulator, and development software.
Analog Devices’ ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
an Assembly Library/Librarian, a Linker, an Instruction-Level
Simulator, an ANSI C optimizing Compiler, the CBug™ C
Source-Level Debugger, and a C Runtime Library including
DSP and mathematical functions. The Optimizing Compiler
includes Numerical C extensions based on the work of the ANSI
Numerical C Extensions Group. Numerical C provides extensions to the C language for array selection, vector math operations, complex data types, circular pointers and variably
dimensioned arrays. The ADSP-21000 Family Development
Software is available for both the PC and Sun platforms.
The SHARC EZ-KIT combines the ADSP-21000 Family Development Software for the PC and the EZ-LAB Development
Board in one package.
The ADSP-2106x EZ-ICE® Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x processor to monitor
and control the target board processor during emulation. The
EZ-ICE provides full-speed emulation, allowing inspection and
modification of memory, registers and processor stacks.
Nonintrusive in-circuit emulation is assured by the use of the
processor’s JTAG interface—the emulator does not affect target
system loading or timing.
Further details and ordering information are available in the
ADSP-21000 Family Hardware & Software Development Tools
data sheet (ADDS-2100xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office or distributor,
or from the Literature Center.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hardware tools include SHARC PC plug-in cards, multiprocessor
SHARC VME boards, and daughter card modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC module specification. Third party software
tools include an Ada compiler, DSP libraries, operating systems
and block diagram design tools.
Quad-SHARC Development Board
The BlackTip-MCM, AD14060 development board and software, is available from Bittware Research Systems, Inc. This
board has one AD14060 BITSI interface, PROM and SRAM
expansion options on an ISA card. It is supported by Bittware’s
SHARC software development package. Bittware can be contacted at 1-800-848-0436.
Other Package Details
The AD14060/AD14060L contains 16 on-module 0.018 microfarad bypass capacitors. It is recommended that in the target
system at least four additional capacitors, of 0.018 microfarad
value, be placed around the module—one near each of the four
corners.
The top surface, lid, of the AD14060/AD14060L is electrically
connected to GND on the industrial and military grade parts.
Additional Information
This data sheet provides a general overview of the AD14060/
AD14060L architecture and functionality. For detailed information on the ADSP-2106x SHARC and the ADSP-21000
Family core architecture and instruction set, refer to the ADSP2106x SHARC User’s Manual.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
CBug is a trademark of Analog Devices, Inc.
REV. A
–7–
AD14060/AD14060L
TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS and
TDI)—these pins can be left floating. These pins have a logiclevel hold circuit that prevents the input from floating internally.
PIN FUNCTION DESCRIPTIONS
AD14060/AD14060L pin definitions are listed below. Inputs
identified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to TCK for TMS,
TDI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLKIN (or to TCK for TRST).
I = Input
P = Power Supply (A/D) = Active Drive
O = Output
S = Synchronous
(O/D) = Open Drain
G = Ground
A = Asynchronous
T = Three-State (when SBTS is asserted, or when the AD14060/
AD14060L is a bus slave)
Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31-0, DATA47-0, FLAG2-0, SW, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
Pin
Type
Function
ADDR31-0
I/O/T
DATA47-0
I/O/T
MS3-0
O/T
RD
I/O/T
WR
I/O/T
PAGE
O/T
ADRCLK
O/T
SW
I/O/T
ACK
I/O/S
External Bus Address. (Common to all SHARCs) The AD14060/AD14060L outputs addresses for
external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs
addresses for read/writes on the internal memory or IOP registers of slave ADSP-2106xs. The AD14060/
AD14060L inputs addresses when a host processor or multiprocessing bus master is reading or writing
the internal memory or IOP registers of internal ADSP-21060s.
External Bus Data. (Common to all SHARCs) The AD14060/AD14060L inputs and outputs data and
instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47-16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 478 of the bus. 16-bit short word data is transferred over bits 31-16 of the bus. In PROM boot mode, 8-bit
data is transferred over bits 23-16. Pull-up resistors on unused DATA pins are not necessary.
Memory Select Lines. (Common to all SHARCs) These lines are asserted (low) as chip selects for the
corresponding banks of external memory. Memory bank size must be defined in the individual ADSP21060’s system control registers (SYSCON). The MS3-0 lines are decoded memory address lines that
change at the same time as the other address lines. When no external memory access is occurring the MS3-0
lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether
or not the condition is true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory
(Bank 0). In a multiprocessing system, the MS3-0 lines are output by the bus master.
Memory Read Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14060/
AD14060L reads from external devices or when the internal memory of internal ADSP-2106xs is being
accessed. External devices (including other ADSP-2106xs) must assert RD to read from the AD14060/
AD14060L’s internal memory. In a multiprocessing system, RD is output by the bus master and is input
by all other ADSP-2106xs.
Memory Write Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14060/
AD14060L writes to external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices (including other ADSP-2106xs) must assert WR to write to the AD14060/
AD14060L’s internal memory. In a multiprocessing system WR is output by the bus master and is input by
all other ADSP-2106xs.
DRAM Page Boundary. (Common to all SHARCs) The AD14060/AD14060L asserts this pin to signal
that an external DRAM page boundary has been crossed. DRAM page size must be defined in the individual ADSP-21060’s memory control register (WAIT). DRAM can only be implemented in external
memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system,
PAGE is output by the bus master.
Clock Output Reference. (Common to all SHARCs) In a multiprocessing system, ADRCLK is output
by the bus master.
Synchronous Write Select. (Common to all SHARCs) This signal is used to interface the AD14060/
AD14060L to synchronous memory devices (including other ADSP-2106xs). The AD14060/AD14060L
asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR
is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output
by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory
access is a read or write. SW is asserted at the same time as the address output. A host processor using
synchronous writes must assert this pin when writing to the AD14060/AD14060L.
Memory Acknowledge. (Common to all SHARCs) External devices can deassert ACK (low) to add
wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The AD14060/AD14060L deasserts
ACK, as an output, to add wait states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-2106x deasserts the bus master’s ACK input to add wait state(s) to an access
of its internal memory. The bus master has a keeper latch on its ACK pin that maintains the input at the
level it was last driven to.
–8–
REV. A
AD14060/AD14060L
Pin
Type
Function
SBTS
I/S
Suspend Bus Three-State. (Common to all SHARCs) External devices can assert SBTS (low) to
place the external bus address, data, selects, and strobes in a high impedance state for the following cycle.
If the AD14060/AD14060L attempts to access external memory while SBTS is asserted, the processor
will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be
used to recover from host processor/AD14060/AD14060L deadlock, or used with a DRAM controller.
HBR
I/A
Host Bus Request. (Common to all SHARCs) Must be asserted by a host processor to request control
of the AD14060/AD14060L’s external bus. When HBR is asserted in a multiprocessing system, the
ADSP-2106x that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the
ADSP-2106x places the address, data, select, and strobe lines in a high impedance state. HBR has priority
over all ADSP-2106x bus requests (BR6-1) in a multiprocessing system.
HBG
I/O
Host Bus Grant. (Common to all SHARCs) Acknowledges an HBR bus request, indicating that the
host processor may take control of the external bus. HBG is asserted (held low) by the AD14060/AD14060L
until HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus master and is
monitored by all others.
CSA
I/A
Chip Select. Asserted by host processor to select SHARC_A.
CSB
I/A
Chip Select. Asserted by host processor to select SHARC_B.
CSC
I/A
Chip Select. Asserted by host processor to select SHARC_C.
CSD
I/A
Chip Select. Asserted by host processor to select SHARC_D.
REDY (O/D)
O
Host Bus Acknowledge. (Common to all SHARCs) The AD14060/AD14060L deasserts REDY (low)
to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain
output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP21060s to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted.
BR6-1
I/O/S
Multiprocessing Bus Requests. (Common to all SHARCs) Used by multiprocessing ADSP-2106xs to
arbitrate for bus mastership. An ADSP-2106x only drives its own BRx line (corresponding to the value of
its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the
unused BRx pins should be pulled high; BR4-1 must not be pulled high or low because they are outputs.
RPBA
I/S
Rotating Priority Bus Arbitration Select. (Common to all SHARCs) When RPBA is high, rotating
priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This
signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the
value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on
every ADSP-2106x.
CPAy (O/D)
I/O
Core Priority Access. (y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an
ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus.
CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is
required. The CPA pin of each internal ADSP-21060 is brought out individually. The CPA pin has
an internal 5 kΩ pull-up resistor. If core access priority is not required in a system, the CPA pin
should be left unconnected.
DT0
O/T
Data Transmit (Common Serial Ports 0 to all SHARCs, TDM). DT pin has a 50 kΩ internal pull-up
resistor.
DR0
I
Data Receive (Common Serial Ports 0 to all SHARCs, TDM). DR pin has a 50 kΩ internal pull-up
resistor.
TCLK0
I/O
Transmit Clock (Common Serial Ports 0 to all SHARCs, TDM). TCLK pin has a 50 kΩ internal
pull-up resistor.
RCLK0
I/O
Receive Clock (Common Serial Ports 0 to all SHARCs, TDM). RCLK pin has a 50 kΩ internal pull-up
resistor.
TFS0
I/O
Transmit Frame Sync (Common Serial Ports 0 to all SHARCs, TDM).
RFS0
I/O
Receive Frame Sync (Common Serial Ports 0 to all SHARCs, TDM).
DTy1
O/T
Data Transmit (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin
has a 50 kΩ internal pull-up resistor.
DRy1
I
Data Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin
has a 50 kΩ internal pull-up resistor.
REV. A
–9–
AD14060/AD14060L
Pin
Type
Function
TCLKy1
I/O
Transmit Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) TCLK
pin has a 50 kΩ internal pull-up resistor.
RCLKy1
I/O
Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK
pin has a 50 kΩ internal pull-up resistor.
TFSy1
I/O
Transmit Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
RFSy1
I/O
Receive Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
FLAGy0
I/O/A
Flag Pins. (FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals.
FLAG1
I/O/A
Flag Pins. (FLAG1 common to all SHARCs) Configured via control bits internal to individual ADSP21060s as either an input or output. As an input, it can be tested as a condition. As an output, it can be
used to signal external peripherals.
FLAGy2
I/O/A
Flag Pins. (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals.
IRQy2-0
I/A
Interrupt Request Lines. (Individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D)
May be either edge-triggered or level-sensitive.
DMAR1
I/A
DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAR2
I/A
DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG1
O/T
DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG2
O/T
DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
LyxCLK
I/O
Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)1. Each LyxCLK pin has a 50 kΩ
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the
ADSP-20160.
LyxDAT3-0
I/O
Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)1. Each LyxDAT pin has a
50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
LyxACK
I/O
Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)1. Each LyxACK pin has a
50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
EBOOTA
I
EPROM Boot Select. (SHARC_A) When EBOOTA is high, SHARC_A is configured for booting from
an 8-bit EPROM. When EBOOTA is low, the LBOOTA and BMSA inputs determine booting mode
for SHARC_A. See the following table. This signal is a system configuration selection which should
be hardwired.
LBOOTA
I
Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is
low, SHARC_A is configured for host processor booting or no booting. See the following table. This
signal is a system configuration selection which should be hardwired.
BMSA
I/O/T2
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTA = 1,
LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates
that no booting will occur and that SHARC_A will begin executing instructions from external memory.
See the following table. This input is a system configuration selection which should be hardwired.
EBOOTBCD
I
EPROM Boot Select. (Common to SHARC_B, SHARC_C, SHARC_D) When EBOOTBCD is high,
SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the
LBOOTBCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following
table. This signal is a system configuration selection which should be hardwired.
LBOOTBCD
I
LINK Boot. (Common to SHARC_B, SHARC_C, SHARC_D) When LBOOTBCD is high, SHARC_B, C,
D are configured for link port booting. When LBOOTBCD is low, SHARC_B, C, D are configured for
host processor booting or no booting. See the following table. This signal is a system configuration selection which should be hardwired.
–10–
REV. A
AD14060/AD14060L
Pin
BMSBCD
Type
Function
2
I/O/T
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTBCD = 1,
LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low,
indicates that no booting will occur and that SHARC_B, C, D will begin executing instructions from
external memory. See table below. This input is a system configuration selection which should be
hardwired.
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
EPROM (Connect BMS to EPROM chip select)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
TIMEXPy
O
Timer Expired. (Individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Asserted
for four cycles when the timer is enabled and TCOUNT decrements to zero.
CLKIN
I
Clock In. (Common to all SHARCs) External clock input to the AD14060/AD14060L. The instruction
cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified
frequency.
RESET
I/A
Module Reset. (Common to all SHARCs) Resets the AD14060/AD14060L to a known state. This input
must be asserted (low) at power-up.
TCK
I
Test Clock (JTAG). (Common to all SHARCs) Provides an asynchronous clock for JTAG boundary
scan.
TMS
I/S
Test Mode Select (JTAG). (Common to all SHARCs) Used to control the test state machine. TMS has
a 20 kΩ internal pull-up resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A.
TDI has a 20 kΩ internal pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.
TRST
I/A
Test Reset (JTAG). (Common to all SHARCs) Resets the test state machine. TRST must be asserted
(pulsed low) after power-up or held low for proper operation of the AD14060/AD14060L. TRST has a
20 kΩ internal pull-up resistor.
EMU (O/D)
O
Emulation Status. (Common to all SHARCs) Must be connected to the ADSP-2106x EZ-ICE target
board connector only.
VDD
P
Power Supply. Nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices (26 pins).
GND
G
Power Supply Return. (28 pins).
NOTES
FLAG3 is connected internally, common to SHARC_A, B, C, and D.
ID pins are hardwired internally as depicted in the block diagram.
1
LINK PORTS 0, 2 and 5 are connected internally as described earlier in Link Port I/O.
2
Three-statable only in EPROM boot mode (when BMS is an output).
REV. A
–11–
AD14060/AD14060L
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location;
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG
test access port of the ADSP-2106x to monitor and control the
target board processor during emulation. The EZ-ICE probe
requires that the AD14060/AD14060L’s CLKIN (optional),
TMS, TCK, TRST, TDI, TDO, EMU and GND signals be
made accessible on the target system via a 14-pin connector (a
pin strip header) such as that shown in Figure 6. The EZ-ICE
probe plugs directly onto this connector for chip-on-board emulation. You must add this connector to your target board design
if you intend to use the ADSP-2106x EZ-ICE. The length of
the traces between the connector and the AD14060/
AD14060L’s JTAG pins should be as short as possible.
1
2
3
4
5
6
GND
KEY (NO PIN)
BTMS
7
8
9
10
BTCK
BTRST
EMU
The JTAG signals are terminated on the EZ-ICE probe as follows:
CLKIN (OPTIONAL)
Signal
Termination
TMS
TMS
TCK
TCK
TRST
Driven through 22 Ω Resistor (16 µA–3.2 µA Driver)
Driven at 10 MHz through 22 Ω Resistor (16 µA–
3.2 µA Driver)
Driven by Open-Drain Driver* (Pulled Up by On-Chip
20 kΩ resistor)
Driven by 16 µA–3.2 µA Driver
One TTL Load, No Termination
One TTL Load, No Termination (Optional Signal)
4.7 kΩ Pull-Up Resistor, One TTL Load (Open-Drain
Output from ADSP-2106x)
TRST
9
11
The BTMS, BTCK, BTRST and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 6. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
VDD. The TRST pin must be asserted after power-up (through
BTRST on the connector) or held low for proper operation of
the AD14060/AD14060L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the EZ-ICE probe.
TDI
TDO
CLKIN
EMU
12
BTDI
TDI
13
14
GND
TDO
*TRST is driven low until the EZ-ICE probe is turned on by the EZ-ICE
software (after the invocation command).
TOP VIEW
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE
Emulator (Jumpers in Place)
Figure 7 shows JTAG scan path connections for the multiprocessor system.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform
OTHER
JTAG
CONTROLLER
TRST
TDO
EMU
TDI
TMS
TRST
TDO
TMS
TDI
ADSP-2106x
#n
TCK
JTAG DEVICE
(OPTIONAL)
TCK
TRST
TDO
EMU
TDI
TMS
TRST
EMU
TDO
TMS
TDI
SHARC_D
TCK
SHARC_C
TCK
TRST
TDO
EMU
TDI
TMS
TRST
EMU
TDO
TMS
TDI
TCK
TDI
EZ-ICE
JTAG
CONNECTOR
SHARC_B
TCK
SHARC_A
TCK
TMS
EMU
TRST
TDO
CLKIN
OPTIONAL
Figure 7. JTAG Scan Path Connections for the AD14060/AD14060L
–12–
REV. A
AD14060/AD14060L
operations such as starting, stopping and single-stepping multiple ADSP-2106xs in a synchronous manner. If you do not
need these operations to occur synchronously on the multiple
processors, simply tie Pin 4 of the EZ-ICE header to ground.
as possible on your board. If TCK, TMS and CLKIN are driving a large number of ADSP-2106xs (more than eight) in your
system, then treat them as a “clock tree” using multiple drivers
to minimize skew. (See Figure 8 JTAG Clock Tree and Clock
Distribution in the “High Frequency Design Considerations”
section of the ADSP-2106x User’s Manual).
If synchronous multiprocessor operations are needed and CLKIN
is connected, clock skew between the AD14060/AD14060L and
the CLKIN pin on the EZ-ICE header must be minimal. If the
skew is too large, synchronous operations may be off by one
cycle between processors. For synchronous multiprocessor
operation TCK, TMS, CLKIN and EMU should be treated as
critical signals in terms of skew, and should be laid out as short
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
5kV
*
TDI
EMU
5kV
*
TCK
TMS
TRST
TDO
CLKIN
EMU
*OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
Figure 8. JTAG Clocktree for Multiple ADSP-2106x Systems
REV. A
–13–
SYSTEM
CLKIN
AD14060/AD14060L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
VDD
Supply Voltage (5 V)
Supply Voltage (3.3 V)
Case Operating Temperature
TCASE
B Grade
Min
Max
K Grade
Min
Max
Units
4.75
3.15
–40
4.75
3.15
0
V
V
°C
5.25
3.6
+100
5.25
3.6
+85
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Case Test
Temp Level Test Condition
Parameter
1
VIH1
VIH2
VIL
VOH
VOL
IIH
IIL
IILP
IILPX4
IOZH
IOZL
IOZHP
IOZLC
IOZLA
High Level Input Voltage
High Level Input Voltage2
Low Level Input Voltage1, 2
High Level Output Voltage3, 4
Low Level Output Voltage3, 4
High Level Input Current5, 6, 7
Low Level Input Current5
Low Level Input Current6
Low Level Input Current7
Three-State Leakage Current8, 9, 10, 14
Three-State Leakage Current8, 11
Three-State Leakage Current11
Three-State Leakage Current12
Three-State Leakage Current13
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IOZLAR
IOZLS
IOZLSX4
IDDIN
IDDIDLE
CIN
Three-State Leakage Current10
Three-State Leakage Current9
Three-State Leakage Current14
Supply Current (Internal)15
Supply Current (Idle)16
Input Capacitance17, 18
Full
Full
Full
Full
Full
+25°C
I
I
I
IV
I
V
5V
Min Typ Max
@ VDD = max
2.0
@ VDD = max
2.2
@ VDD = min
@ VDD = min, IOH = –2.0 mA4
4.1
@ VDD = min, IOL = 4.0 mA4
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V (5 V),
2 V (3.3 V)
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
tCK = 25 ns, VDD = max
VDD = max
1.4
15
3.3 V
Min Typ Max
Units
VDD + 0.5 2.0
VDD + 0.5 2.2
0.8
2.4
0.4
10
10
150
600
10
10
350
1.5
VDD + 0.5
VDD + 0.5
0.8
0.4
10
10
150
600
10
10
350
1.5
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
350
4.2
150
600
3.4
800
350
4.2
150
600
2.2
760
µA
mA
µA
µA
A
mA
1.0
15
pF
EXPLANATION OF TEST LEVELS
Test Level
I
100% Production Tested19.
II
100% Production Tested at +25°C, and Sample Tested at Specified Temperatures.
III
Sample Tested Only.
IV
Parameter is guaranteed by design and analysis, and characterization testing on discrete SHARCs.
V
Parameter is typical value only.
VI
All devices are 100% production tested at +25°C; sample tested at temperature extremes.
NOTES
1
Applies to input and bidirectional pins: DATA 47-0, ADDR 31-0, RD, WR, SW, ACK, SBTS, IRQy2-0, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2,
BR6-1, RPBA, CPAy, TFS0, TFSy1, RFS0, RFSy1, LyxDAT 3-0, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS,
TDI, TCK, HBR, DR0, DRy1, TCLK0, TCLKy1, RCLK0, RCLKy1.
2
Applies to input pins: CLKIN, RESET, TRST.
3
Applies to output and bidirectional pins: DATA 47-0, ADDR31-0, MS3-0 RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy, HBG,
REDY, DMAG1, DMAG2, BR6-1, CPAy, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1 LyxDAT 3-0, LyxCLK, LyxACK,
BMSA, BMSBCD, TDO, EMU.
4
See Output Drive Currents for typical drive current capabilities.
5
Applies to input pins: SBTS, IRQy2-0, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.
6
Applies to input pins with internal pull-ups: DR0, DRy1, TDI.
7
Applies to bussed input pins with internal pull-ups: TRST, TMS.
8
Applies to three-statable pins: DATA 47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2,
BMSA, BMSBCD, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another ADSP2106x is not requesting bus mastership. HBG AND EMU are not tested for leakage current.)
9
Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.
10
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k Ω during reset in a multiprocessor system, when ID 2-0 = 001 and another
ADSP-2106x is not requesting bus mastership.)
11
Applies to three-statable pins with internal pull-downs: LyxDAT3-0, LyxCLK, LyxACK.
12
Applies to CPAy pin.
13
Applies to ACK pin when keeper latch enabled.
14
Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.
15
Applies to V DD pins. Conditions of operation: each processor executing radix-2 FFT butterfly with instruction in cache, one data operand fetched from each internal
memory block, and one DMA transfer occurring from/to internal memory at t CK = 25 ns.
16
Applies to V DD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17
Applies to all signal pins.
18
Guaranteed but not tested.
19
Link and Serial Ports: All are 100% tested at die level prior to assembly. All are 100% ac tested at module level; Link-4 and Serial-0 are also dc tested at the module
level. See Timing Specifications.
Specifications subject to change without notice.
–14–
REV. A
AD14060/AD14060L
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (5 V) . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Supply Voltage (3.3 V) . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ESD SENSITIVITY
The AD14060/AD14060L modules are ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without
detection. Permanent damage may occur to devices subjected to high energy electrostatic
discharges.
The ADSP-21060 processors include proprietary ESD protection circuitry to dissipate high
energy discharges. Per method 3015 of MIL-STD-883, the ADSP-21060 processors have been
classified as a Class 2 device.
WARNING!
ESD SENSITIVE DEVICE
Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination socket before devices are removed.
TIMING SPECIFICATIONS
GENERAL NOTES
This data sheet represents production released specifications for
the AD14060 (5 V), and for the AD14060L (3.3 V). The
ADSP-21060 die components are 100% tested, and the assembled
AD14060/AD14060L units are again extensively tested atspeed, and across-temperature. Parametric limits were established from the ADSP-21060 characterization followed by
further design/analysis of the AD14060/AD14060L package
characteristics. The specifications shown are based on a CLKIN
frequency of 40 MHz (tCK = 25 ns). The DT derating allows
specifications at other CLKIN frequencies (within the min-max
range of the tCK specification; see “Clock Input” below). DT is the
difference between the actual CLKIN period and a CLKIN period
of 25 ns:
DT = tCK – 25 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
REV. A
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drain
–15–
AD14060/AD14060L
Parameter
Min
40 MHz–5 V
Max
40 MHz–3.3 V
Min
Max
Units
Clock Input
Timing Requirements:
CLKIN Period
tCK
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
25
7
5
100
25
8.75
5
100
3
3
ns
ns
ns
ns
tCK
CLKIN
tCKH
tCKL
Figure 9. Clock Input
5V
Parameter
3.3 V
Min
Max
Min
Max
Units
4tCK
14 + DT/2
tCK
4tCK
14 + DT/2
tCK
ns
ns
Reset
Timing Requirements:
RESET Pulsewidth Low1
tWRST
tSRST
RESET Setup Before CLKIN High2
NOTES
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable V DD and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
tSRST
tWRST
RESET
Figure 10. Reset
5V
Parameter
Min
Interrupts
Timing Requirements:
tSIR
IRQ2-0 Setup Before CLKIN High1
tHIR
IRQ2-0 Hold Before CLKIN High1
tIPW
IRQ2-0 Pulsewidth2
18 + 3DT/4
3.3 V
Max
Min
Max
Units
11.5 + 3DT/4
ns
ns
ns
18 + 3DT/4
11.5 + 3DT/4
2 + tCK
2 + tCK
NOTES
1
Only required for IRQx recognition in the following cycle.
2
Applies only if t SIR and t HIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ2-0
tIPW
Figure 11. Interrupts
–16–
REV. A
AD14060/AD14060L
5V
Parameter
3.3 V
Min
Max
Timer
Switching Characteristic:
tDTEX
CLKIN High to TIMEXP
Min
16
Max
Units
16
ns
CLKIN
tDTEX
tDTEX
TIMEXP
Figure 12. Timer
5V
Parameter
Min
Flags
Timing Requirements:
tSFI
FLAG2-0IN Setup Before CLKIN High1
tHFI
FLAG2-0IN Hold After CLKIN High1
tDWRFI
FLAG2-0IN Delay After RD/WR Low1
tHFIWR
FLAG2-0IN Hold After RD/WR Deasserted1
8 + 5DT/16
0.5 – 5DT/16
3.3 V
Max
Min
8 + 5DT/16
0.5 – 5DT/16
4.5 + 7DT/16
0.5
Switching Characteristics:
FLAG2-0OUT Delay After CLKIN High
tDFO
tHFO
FLAG2-0OUT Hold After CLKIN High
tDFOE
CLKIN High to FLAG2-0OUT Enable
tDFOD
CLKIN High to FLAG2-0OUT Disable
Max
4.5 + 7DT/16
0.5
17
17
4
3
4
3
15
15
NOTE
1
Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
CLKIN
tDFOE
tDFO
tHFO
FLAG2–0OUT
FLAG OUTPUT
CLKIN
tSFI
tHFI
FLAG2–0IN
tDWRFI
tHFIWR
RD, WR
FLAG INPUT
Figure 13. Flags
REV. A
–17–
tDFO
tDFOD
Units
ns
ns
ns
ns
ns
ns
ns
ns
AD14060/AD14060L
These switching characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write – Bus
Master below). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the AD14060/
AD14060L is the bus master accessing external memory space.
5V
Parameter
Timing Requirements:
Address, Delay to Data Valid 1, 4
tDAD
RD Low to Data Valid1
tDRLD
Data Hold from Address2
tHDA
tHDRH
Data Hold from RD High2
ACK Delay from Address 3, 4
tDAAK
ACK Delay from RD Low3
tDSAK
Max
Min
17.5 + DT + W
11.5 + 5DT/8 + W
1
2.5
Address Setup Before ADRCLK High4
Max
Units
17.5 + DT + W
11.5 + 5DT/8 + W
ns
ns
ns
ns
ns
ns
1
2.5
13.5 + 7DT/8 + W
7.5 + DT/2 + W
Switching Characteristics:
Address Hold After RD High
tDRHA
tDARL
Address to RD Low4
RD Pulsewidth
tRW
RD High to WR, RD, DMAGx Low
tRWR
tSADADC
3.3 V
Min
13.5 + 7DT/8 + W
7.5 + DT/2 + W
–0.5 + H
1.5 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
–0.5 + H
1.5 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
ns
ns
ns
ns
–0.5 + DT/4
–0.5 + DT/4
ns
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
Data Delay/Setup: User must meet t DAD or tDRLD or synchronous spec t SSDATI.
2
Data Hold: User must meet t HDA or tHDRH or synchronous spec t HDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.
3
ACK Delay/Setup: User must meet tDSAK or tDAAK or synchronous specification t SACKC.
4
For MSx, SW, BMS, the falling edge is referenced.
1
ADDRESS
MSx, SW
BMS
tDARL
tRW
tDRHA
RD
tHDA
tDRLD
tDAD
tHDRH
DATA
tDSAK
tRWR
tDAAK
ACK
WR, DMAG
tSADADC
ADRCLK
(OUT)
Figure 14. Memory Read—Bus Master
–18–
REV. A
AD14060/AD14060L
Memory Write—Bus Master
These switching characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write–Bus
Master). If these timing requirements are met, the synchronous
read/write timing can be ignored (and vice versa).
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the AD14060/
AD14060L is the bus master accessing external memory space.
5V
Parameter
3.3 V
Min
Max
Timing Requirements:
tDAAK
ACK Delay from Address, Selects 1, 2
ACK Delay from WR Low1
tDSAK
Switching Characteristics:
Address, Selects to WR Deasserted2
tDAWH
tDAWL
Address, Selects to WR Low2
WR Pulsewidth
tWW
Data Setup before WR High
tDDWH
tDWHA
Address Hold after WR Deasserted
tDATRWH Data Disable after WR Deasserted3
WR High to WR, RD, DMAGx Low
tWWR
tDDWR
Data Disable before WR or RD Low
WR Low to Data Enabled
tWDE
tSADADC
Address, Selects to ADRCLK High 2
Min
13.5 + 7DT/8 + W
7.5 + DT/2 + W
16.5 + 15DT/16 + W
2.5 + 3DT/8
12 + 9DT/16 + W
6.5 + DT/2 + W
–1 + DT/16 + H
0.5 + DT/16 + H
6.5 + DT/16 + H
7.5 + 7DT/16 + H
4.5 + 3DT/8 + I
–1.5 + DT/16
–0.5 + DT/4
Max
Units
13.5 + 7DT/8 + W
7.5 + DT/2 + W
ns
ns
16.5 + 15DT/16 + W
2.5 + 3DT/8
12 + 9DT/16 + W
6.5 + DT/2 + W
–1 + DT/16 + H
0.5 + DT/16 + H 6.5 + DT/16 + H
7.5 + 7DT/16 + H
4.5 + 3DT/8 + I
–1.5 + DT/16
–0.5 + DT/4
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
1
ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification t SACKC.
2
For MSx, SW, BMS, the falling edge is referenced.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
ADDRESS
MSx , SW
BMS
tDWHA
tDAWH
tWW
tDAWL
WR
tWWR
tDDWH
tWDE
tDATRWH
DATA
tDSAK
tDAAK
ACK
RD , DMAG
tSADADC
ADRCLK
(OUT)
Figure 15. Memory Write—Bus Master
REV. A
–19–
tDDWR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD14060/AD14060L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asynchronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
Parameter
Timing Requirements:
tSSDATI
Data Setup Before CLKIN
Data Hold After CLKIN
tHSDATI
ACK Delay After Address, MSx, SW, BMS1, 2
tDAAK
tSACKC
ACK Setup Before CLKIN2
ACK Hold After CLKIN
tHACKC
Switching Characteristics:
Address, MSx, BMS, SW Delay After CLKIN1
tDADRO
Address, MSx, BMS, SW Hold After CLKIN
tHADRO
tDPGC
PAGE Delay After CLKIN
RD High Delay After CLKIN
tDRDO
WR High Delay After CLKIN
tDWRO
tDRWL
RD/WR Low Delay After CLKIN
tSDDATO Data Delay After CLKIN
Data Disable After CLKIN 3
tDATTR
tDADCCK ADRCLK Delay After CLKIN
ADRCLK Period
tADRCK
tADRCKH ADRCLK Width High
tADRCKL ADRCLK Width Low
When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
5V
Max
Min
3 + DT/8
4 – DT/8
Min
3.3 V
Max
3 + DT/8
4 – DT/8
13.5 + 7 DT/8 + W
6.5 + DT/4
–0.5 – DT/4
13.5 + 7 DT/8 + W
6.5 + DT/4
–0.5 – DT/4
8 – DT/8
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
Units
17 + DT/8
5 – DT/8
5 – 3DT/16
13.5 + DT/4
20 + 5DT/16
8 – DT/8
11 + DT/8
8 – DT/8
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
17 + DT/8
5 – DT/8
5 – 3DT/16
13.5 + DT/4
20 + 5DT/16
8 – DT/8
11 + DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = (number of Wait states specified in WAIT register) × tCK.
NOTES
For MSx, SW, BMS, the falling edge is referenced.
2
ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification t SACKC.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
1
–20–
REV. A
AD14060/AD14060L
CLKIN
tADRCK
tADRCKL
tADRCKH
tDADCCK
ADRCLK
tHADRO
tDAAK
tDADRO
ADDRESS
SW
tDPGC
PAGE
tHACKC
tSACKC
ACK
(IN)
READ CYCLE
tDRWL
tDRDO
RD
tHSDATI
tSSDATI
DATA
(IN)
WRITE CYCLE
tDWRO
tDRWL
WR
tDATTR
tSDDATO
DATA
(OUT)
Figure 16. Synchronous Read/Write—Bus Master
REV. A
–21–
AD14060/AD14060L
The bus master must meet these (bus slave) timing requirements.
Synchronous Read/Write—Bus Slave
Use these specifications for bus master accesses of a slave’s IOP
registers or internal memory (in multiprocessor memory space).
5V
Parameter
Min
Timing Requirements:
Address, SW Setup Before CLKIN
tSADRI
tHADRI
Address, SW Hold Before CLKIN
tSRWLI
RD/WR Low Setup Before CLKIN1
tHRWLI
RD/WR Low Hold After CLKIN
tRWHPI
RD/WR Pulse High
tSDATWH
Data Setup Before WR High
tHDATWH
Data Hold After WR High
Switching Characteristics:
Data Delay After CLKIN
tSDDATO
tDATTR
Data Disable After CLKIN2
tDACKAD
ACK Delay After Address, SW3
tACKTR
ACK Disable After CLKIN3
3.3 V
Max
Min
15.5 + DT/2
Max
15.5 + DT/2
4.5 + DT/2
9.5 + 5DT/16
–3.5 – 5DT/16
3
5.5
1.5
0 – DT/8
–1 – DT/8
8 + 7DT/16
20 + 5DT/16
8 – DT/8
10
7 – DT/8
8 + 7DT/16
ns
ns
ns
ns
ns
ns
ns
20 + 5DT/16
8 – DT/8
10
7 – DT/8
ns
ns
ns
ns
4.5 + DT/2
9.5 + 5DT/16
–3.5 – 5DT/16
3
5.5
1.5
0 – DT/8
–1 – DT/8
Units
NOTES
1
tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled,
tSRWLI (min) = 4 + DT/8.
2
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
3
tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 18.5 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT/4, then ACK is valid 15 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t ACKTR.
CLKIN
tSADRI
tHADRI
ADDRESS
SW
tDACKAD
tACKTR
ACK
READ ACCESS
tSRWLI
tHRWLI
tRWHPI
RD
tSDDATO
tDATTR
DATA
(OUT)
WRITE ACCESS
tSRWLI
tHRWLI
tRWHPI
WR
tHDATWH
tSDATWH
DATA
(IN)
Figure 17. Synchronous Read/Write—Bus Slave
–22–
REV. A
AD14060/AD14060L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106x’s (BRx) or a host processor
(HBR, HBG).
5V
Parameter
Timing Requirements:
tHBGRCSV HBG Low to RD/WR/CS Valid1
HBR Setup Before CLKIN2
tSHBRI
HBR Hold Before CLKIN2
tHHBRI
tSHBGI
HBG Setup Before CLKIN
HBG Hold Before CLKIN High
tHHBGI
BRx, CPA Setup Before CLKIN3
tSBRI
tHBRI
BRx, CPA Hold Before CLKIN High
RPBA Setup Before CLKIN
tSRPBAI
RPBA Hold Before CLKIN
tHRPBAI
Switching Characteristics:
HBG Delay After CLKIN
tDHBGO
tHHBGO
HBG Hold After CLKIN
BRx Delay After CLKIN
tDBRO
BRx Hold After CLKIN
tHBRO
tDCPAO
CPA Low Delay After CLKIN
CPA Disable After CLKIN
tTRCPA
REDY (O/D) or (A/D) Low from CS and HBR Low4
tDRDYCS
tTRDYHG REDY (O/D) Disable or REDY (A/D) High from HBG4
tARDYTR
REDY (A/D) Disable from CS or HBR High4
Min
3.3 V
Max
Min
19.5 + 5DT/4
20 + 3DT/4
Units
19.5 + 5DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
20 + 3DT/4
13.5 + 3DT/4
13 + DT/2
13.5 + 3DT/4
13 + DT/2
5.5 + DT/2
13 + DT/2
5.5 + DT/2
13 + DT/2
5.5 + DT/2
20 + 3DT/4
5.5 + DT/2
20 + 3DT/4
11.5 + 3DT/4
11.5 + 3DT/4
8 – DT/8
–2 – DT/8
8 – DT/8
–2 – DT/8
8 – DT/8
–2 – DT/8
–2 – DT/8
Max
8 – DT/8
–2 – DT/8
9 – DT/8
5.5 – DT/8
9.5
44 + 27DT/16
–2 – DT/8
9 – DT/8
5.5 – DT/8
10.25
44 + 27DT/16
11
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
For first asynchronous access after HBR and CS asserted, ADDR31–0 must be a non-MMS value 1/2 t CK before RD or WR goes low or by t HBGRCSV after HBG goes
low. This is easily accomplished by driving an upper address signal high when HBG is asserted.
2
Only required for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
(O/D) = open drain, (A/D) = active drive.
REV. A
–23–
AD14060/AD14060L
CLKIN
tSHBRI
tHHBRI
HBR
tHHBGO
tDHBGO
HBG
(OUT)
tHBRO
tDBRO
BRx
(OUT)
tDCPAO
CPA (OUT)
(O/D)
tTRCPA
tSHBGI
tHHBGI
HBG (IN)
tSBRI
tHBRI
BRx (IN)
CPA (IN) (O/D)
HBR
CS
tTRDYHG
tDRDYCS
REDY (O/D)
tARDYTR
REDY (A/D)
tHBGRCSV
HBG (OUT)
RD
WR
CS
tSRPBAI
tHRPBAI
RPBA
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
HBG WILL BE DELAYED BY n CLOCK CYCLES WHEN WAIT STATES OR BUS LOCK ARE IN EFFECT.
Figure 18. Multiprocessor Bus Request and Host Bus Request
–24–
REV. A
AD14060/AD14060L
Asynchronous Read/Write—Host to AD14060/AD14060L
Use these specifications for asynchronous host processor accesses
of an AD14060/AD14060L, after the host has asserted CS and
HBR (low). After HBG is returned by the AD14060/
AD14060L, the host can drive the RD and WR pins to access
the AD14060/AD14060L’s internal memory or IOP registers.
HBR and HBG are assumed low for this timing.
5V
Parameter
Min
Read Cycle
Timing Requirements:
tSADRDL
Address Setup/CS Low Before RD Low1
Address Hold/CS Hold Low After RD
tHADRDH
tWRWH
RD/WR High Width
RD High Delay After REDY (O/D) Disable
tDRDHRDY
RD High Delay After REDY (A/D) Disable
tDRDHRDY
0.5
0.5
6
0.5
0.5
3.3 V
Max
Min
Max
0.5
0.5
6
0.5
0.5
Switching Characteristics:
Data Valid Before REDY Disable from Low
tSDATRDY
tDRDYRDL
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
tRDYPRD
Data Disable After RD High
tHDARWH
45 + DT
1.5
Write Cycle
Timing Requirements:
tSCSWRL
CS Low Setup Before WR Low
CS Low Hold After WR High
tHCSWRH
Address Setup Before WR High
tSADWRH
tHADWRH
Address Hold After WR High
WR Low Width
tWWRL
RD/WR High Width
tWRWH
tDWRHRDY
WR High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WR High
tSDATWH
Data Hold After WR High
tHDATWH
0.5
0.5
5.5
2.5
7
6
0.5
5.5
1.5
Switching Characteristics:
REDY (O/D) or (A/D) Low Delay After WR/CS Low
tDRDYWRL
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
15
1 + 7DT/16
1.5
ns
ns
ns
ns
ns
1.5
11
9
11.5
45 + DT
1.5
9.5
0.5
0.5
5.5
2.5
7
6
0.5
5.5
1.5
11
9 + 7DT/16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.5
15
0 + 7DT/16
Units
8 + 7DT/16
ns
ns
ns
NOTE
1
Not required if RD and address are valid t HBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31–0 must be a non-MMS value 1/2 t CLK before RD
or WR goes low or by t HBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be
driven during asynchronous host accesses, see Table 8.2 of the ADSP-2106x SHARC User’s Manual.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19a. Synchronous REDY Timing
REV. A
–25–
AD14060/AD14060L
READ CYCLE
ADDRESS/CS
tHADRDH
tSADRDL
tWRWH
RD
tHDARWH
DATA (OUT)
tSDATRDY
tDRDYRDL
tDRDHRDY
tRDYPRD
REDY (O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
tSADWRH
tSCSWRL
tHADWRH
tHCSWRH
CS
tWWRL
tWRWH
WR
tHDATWH
tSDATWH
DATA (IN)
tDWRHRDY
tDRDYWRL
tRDYPWR
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19b. Asynchronous Read/Write—Host to ADSP-2106x
–26–
REV. A
AD14060/AD14060L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
5V
Parameter
Min
Timing Requirements:
SBTS Setup Before CLKIN
tSTSCK
tHTSCK
SBTS Hold Before CLKIN
12 + DT/2
3.3 V
Max
Min
–1.5 – DT/8
–1.5 – DT/8
–1.5 – DT/8
5.5 + DT/2
ns
ns
–1.25 – DT/8
–1.5 – DT/8
–1.5 – DT/8
1 – DT/4
2.5 – DT/4
3 – DT/4
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
Units
12 + DT/2
5.5 + DT/2
Switching Characteristics:
tMIENA
Address/Select Enable After CLKIN
tMIENS
Strobes Enable After CLKIN1
tMIENHG
HBG Enable After CLKIN
tMITRA
Address/Select Disable After CLKIN
tMITRS
Strobes Disable After CLKIN1
tMITRHG
HBG Disable After CLKIN
tDATEN
Data Enable After CLKIN2
tDATTR
Data Disable After CLKIN2
tACKEN
ACK Enable After CLKIN2
tACKTR
ACK Disable After CLKIN2
tADCEN
ADRCLK Enable After CLKIN
tADCTR
ADRCLK Disable After CLKIN
tMTRHBG
Memory Interface Disable Before HBG Low3
tMENHBG
Memory Interface Enable After HBG High3
Max
8 – DT/8
7 – DT/8
1 – DT/4
2.5 – DT/4
3 – DT/4
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
9 – DT/4
–1 + DT/8
18.5 + DT
8 – DT/8
7 – DT/8
9 – DT/4
–1 + DT/8
18.5 + DT
NOTES
1
Strobes = RD, WR, SW, PAGE, DMAG.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
CLKIN
tSTSCK
tHTSCK
SBTS
tMITRA, tMITRS, tMITRHG
tMIENA, tMIENS, tMIENHG
MEMORY
INTERFACE
tDATTR
tDATEN
DATA
tACKTR
tACKEN
ACK
tADCEN
tADCTR
ADRCLK
HBG
tMTRHBG
tMENHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 20. Three-State Timing
REV. A
–27–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD14060/AD14060L
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0,
ACK, and DMAG signals. For Paced Master mode, the data
transfer is controlled by ADDR31-0, RD, WR, MS3-0, and ACK
(not DMAG). For Paced Master mode, the “Memory Read–Bus
Master”, “Memory Write–Bus Master”, and “Synchronous
Read/Write–Bus Master” timing specifications for ADDR31-0,
RD, WR, MS3-0, SW, PAGE, DATA47-0, and ACK also apply.
5V
Parameter
Timing Requirements:
tSDRLC
DMARx Low Setup Before CLKIN 1
tSDRHC
DMARx High Setup Before CLKIN 1
DMARx Width Low (Nonsynchronous)
tWDR
Data Setup After DMAGx Low2
tSDATDGL
tHDATIDG
Data Hold After DMAGx High
Data Valid After DMAGx High2
tDATDRH
DMAGx Low Edge to Low Edge
tDMARLL
tDMARH
DMAGx Width High
Switching Characteristics:
tDDGL
DMAGx Low Delay After CLKIN
DMAGx High Width
tWDGH
DMAGx Low Width
tWDGL
tHDGC
DMAGx High Delay After CLKIN
Data Valid Before DMAGx High3
tVDATDGH
Data Disable After DMAGx High4
tDATRDGH
tDGWRL
WR Low Before DMAGx Low
DMAGx Low Before WR High
tDGWRH
WR High Before DMAGx High
tDGWRR
tDGRDL
RD Low Before DMAGx Low
RD Low Before DMAGx High
tDRDGH
RD High Before DMAGx High
tDGRDR
tDGWR
DMAGx High to WR, RD, DMAGx Low
Address/Select Valid to DMAGx High
tDADGH
tDDGHA
Address/Select Hold after DMAGx High
Min
3.3 V
Max
5
5
6
Min
Max
5
5
6
23 + 7DT/8
6
ns
ns
ns
ns
ns
ns
ns
ns
9 + DT/4
16 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
7 – DT/8
7.5 + 9DT/16
–0.5
8
–0.5
2.5
9.5 + 5DT/8 + W
0.5 + DT/16
3.5 + DT/16
–0.5
2
10.5 + 9DT/16 + W
–0.5
3.5
4.5 + 3DT/8 + HI
16 + DT
–1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.5 + 5DT/8
2.5
9.5 + 5DT/8
2.5
15.5 + 7DT/8
23 + 7DT/8
6
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
7.5 + 9DT/16
–0.5
–0.5
9.5 + 5DT/8 + W
0.5 + DT/16
–0.5
10.5 + 9DT/16 + W
–0.5
4.5 + 3DT/8 + HI
16 + DT
–1
16 + DT/4
7 – DT/8
8
2.5
3.5 + DT/16
2
3.5
Units
15.5 + 7DT/8
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
Only required for recognition in the current cycle.
tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven t DATDRH after DMARx is brought high.
3
tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t VDATDGH = 7.5 + 9DT/16 + (n × tCK)
where n equals the number of extra cycles that the access is prolonged.
4
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
1
2
–28–
REV. A
AD14060/AD14060L
CLKIN
tSDRLC
tDMARLL
tSDRHC
tWDR
tDMARH
DMARx
tHDGC
tDDGL
tWDGL
tWDGH
DMAGx
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
tVDATDGH
tDATRDGH
DATA (FROM
ADSP-2106x TO
EXTERNAL DRIVE)
tDATDRH
tHDATIDG
tSDATDGL
DATA (FROM
EXTERNAL DRIVE
TO ADSP-2106x)
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
WR
tDGWRL
tDGWRH
tDGWRR
(EXTERNAL DEVICE
TO EXTERNAL
MEMORY)
RD
tDGRDR
tDGRDL
(EXTERNAL
MEMORY TO
EXTERNAL DEVICE)
tDRDGH
tDADGH
ADDRESS
MSX, SW
* “MEMORY READ – BUS MASTER,” “MEMORY WRITE – BUS MASTER,” AND “SYNCHRONOUS READ/WRITE – BUS MASTER”
TIMING SPECIFICATIONS FOR ADDR31–0, RD, WR, SW, MS3-0 AND ACK ALSO APPLY HERE.
Figure 21. DMA Handshake Timing
REV. A
–29–
tDDGHA
AD14060/AD14060L
Link Ports: 1 × CLK Speed Operation
5V
Parameter
Min
Receive
Timing Requirements:
Data Setup Before LCLK Low
tSLDCL
tHLDCL
Data Hold After LCLK Low
LCLK Period (1 × Operation)
tLCLKIW
LCLK Width Low
tLCLKRWL
tLCLKRWH
LCLK Width High
3.5
3
tCK
6
5
Switching Characteristics:
tDLAHC
LACK High Delay After CLKIN High
LACK Low Delay After LCLK High 1
tDLALC
LACK Enable from CLKIN
tENDLK
tTDLK
LACK Disable from CLKIN
Transmit
Timing Requirements:
tSLACH
LACK Setup Before LCLK High
LACK Hold After LCLK High
tHLACH
Switching Characteristics:
LCLK Delay After CLKIN (1 × Operation)
tDLCLK
tDLDCH
Data Delay After LCLK High
Data Hold After LCLK High
tHLDCH
LCLK Width Low
tLCLKTWL
tLCLKTWH
LCLK Width High
LCLK Low Delay After LACK High
tDLACLK
LDAT, LCLK Enable After CLKIN
tENDLK
tTDLK
LDAT, LCLK Disable After CLKIN
Link Port Service Request Interrupts:
1 × and 2 × Speed Operations
Timing Requirements:
tSLCK
LACK/LCLK Setup Before CLKIN Low2
tHLCK
LACK/LCLK Hold After CLKIN Low 2
3.3 V
Max
Min
Max
3
3
tCK
6
5
18 + DT/2
–3
5 + DT/2
29.5 + DT/2
13.5
18 + DT/2
–3
5 + DT/2
21 + DT/2
18
–7
ns
ns
ns
ns
ns
29.5 + DT/2
13.5
21 + DT/2
20
–7
16.5
3.5
–3
(tCK/2) – 2
(tCK/2) – 2
(tCK/2) + 8.5
5 + DT/2
(tCK/2) + 2
(tCK/2) + 2
(3 × tCK/2) + 17.5
21 + DT/2
10
2.5
(tCK/2) + 1.25
(tCK/2) + 1
(3 × tCK/2) + 18
21 + DT/2
10
2.5
ns
ns
ns
ns
ns
ns
17.5
3
–3
(tCK/2) – 1
(tCK/2) – 1.25
(tCK/2) + 8
5 + DT/2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
LACK will go low with t DLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
2
Only required for interrupt recognition in the current cycle.
–30–
REV. A
AD14060/AD14060L
Link Ports: 2 × CLK Speed Operation
5V
Parameter
Min
3.3 V
Max
Min
Max
Units
Receive
Timing Requirements:
Data Setup Before LCLK Low
tSLDCL
tHLDCL
Data Hold After LCLK Low
LCLK Period (2 × Operation)
tLCLKIW
LCLK Width Low
tLCLKRWL
tLCLKRWH
LCLK Width High
2.5
2.25
tCK/2
4.5
4.25
Switching Characteristics:
tDLAHC
LACK High Delay After CLKIN High
LACK Low Delay After LCLK High 1
tDLALC
18 + DT/2
6
Transmit
Timing Requirements:
LACK Setup Before LCLK High
tSLACH
tHLACH
LACK Hold After LCLK High
19
–6.75
Switching Characteristics:
tDLCLK
LCLK Delay After CLKIN
Data Delay After LCLK High
tDLDCH
Data Hold After LCLK High
tHLDCH
tLCLKTWL
LCLK Width Low
LCLK Width High
tLCLKTWH
tDLACLK
LCLK Low Delay After LACK High
2.25
2.25
tCK/2
5
4
29.5 + DT/2
16.5
18 + DT/2
6
ns
ns
ns
ns
ns
30.5 + DT/2
18.5
19
–6.5
9
3
–2
(tCK/4) – 1
(tCK/4) – 1
(tCK/4) + 9
(tCK/4) + 1
(tCK/4) + 1
(3 × tCL/4) + 17
ns
ns
9
2.75
–2
(tCK/4) – 0.75
(tCK/4) – 1.5
(tCK/4) + 9
ns
ns
(tCK/4) + 1.5
(tCK/4) + 1
(3 × tCL/4) + 17
ns
ns
ns
ns
ns
ns
NOTE
1
LACK will go low with t DLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
REV. A
–31–
AD14060/AD14060L
TRANSMIT
CLKIN
tDLCLK
tLCLKTWH
tLCLKTWL
LAST NIBBLE
TRANSMITTED
FIRST NIBBLE
TRANSMITTED
LCLK 1x
OR
LCLK 2x
LCLK INACTIVE
(HIGH)
tDLDCH
tHLDCH
LDAT(3:0)
OUT
tDLACLK
tSLACH
tHLACH
LACK (IN)
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
RECEIVE
CLKIN
tLCLKIW
tLCLKRWH
tLCLKRWL
LCLK 1x
OR
LCLK 2x
tHLDCL
tSLDCL
LDAT(3:0)
IN
tDLALC
tDLAHC
LACK (OUT)
LACK GOES LOW ONLY AFFTER THE SECOND NIBBLE IS RECEIVED.
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
CLKIN
tENDLK
tTDLK
LCLK
LDAT(3:0)
LACK
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
LINK PORT INTERRUPT SETUP TIME
CLKIN
tSLCK
tHLCK
LCLK
LACK
Figure 22. Link Ports
–32–
REV. A
AD14060/AD14060L
Serial Ports
5V
3.3 V
Parameter
Min
External Clock
Timing Requirements:
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
tHFSE
TFS/RFS Hold After TCLK/RCLK1, 2
tSDRE
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
tHDRE
tSCLKW
TCLK/RCLK Width
tSCLK
TCLK/RCLK Period
4
4.5
2
4.5
9.5
tCK
4
4.5
2
4.5
9
tCK
ns
ns
ns
ns
ns
ns
Internal Clock
Timing Requirements:
tSFSI
TFS Setup Before TCLK1; RFS Setup Before RCLK1
tHFSI
TFS/RFS Hold After TCLK/RCLK1, 2
tSDRI
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
tHDRI
9
1
4
3
9
1
4
3
ns
ns
ns
ns
External or Internal Clock
Switching Characteristics:
tDFSE
RFS Delay After RCLK (Internally Generated RFS)3
tHFSE
RFS Hold After RCLK (Internally Generated RFS)3
3
External Clock
Switching Characteristics:
tDFSE
TFS Delay After TCLK (Internally Generated TFS)3
tHFSE
TFS Hold After TCLK (Internally Generated TFS)3
tDDTE
Transmit Data Delay After TCLK3
Transmit Data Hold After TCLK3
tHDTE
Internal Clock
Switching Characteristics:
tDFSI
TFS Delay After TCLK (Internally Generated TFS)3
tHFSI
TFS Hold After TCLK (Internally Generated TFS)3
Transmit Data Delay After TCLK3
tDDTI
tHDTI
Transmit Data Hold After TCLK3
tSCLKIW
TCLK/RCLK Width
Enable and Three-State
Switching Characteristics:
tDDTEN
Data Enable from External TCLK3
tDDTTE
Data Disable from External TCLK3
tDDTIN
Data Enable from Internal TCLK3
Data Disable from Internal TCLK3
tDDTTI
tDCLK
TCLK/RCLK Delay from CLKIN
tDPTR
SPORT Disable After CLKIN
External Late Frame Sync
Switching Characteristics:
tDDTLFSE Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 04
tDDTENFS Data Enable from late FS or MCE = 1, MFD = 04
Max
Min
14
Max
14
ns
ns
14
ns
ns
ns
ns
3
14
3
3
17
5
17
5
5
–1.5
5
ns
ns
8
ns
0
ns
(SCLK/2) – 2.5 (SCLK/2) + 2.5 ns
–1.5
8
0
(SCLK/2) – 2
(SCLK/2) + 2
3.5
4
3
23 + 3DT/8
18
3
23 + 3DT/8
18
ns
ns
ns
ns
ns
ns
13
13.8
ns
11.5
0
11.5
0
3.0
Units
3.5
ns
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
NOTES
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0.5 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0.5 ns minimum from drive edge.
3
Referenced to drive edge.
4
MCE = 1, TFS enable and TFS valid follow t DDTLFSE and tDDTENFS.
REV. A
–33–
AD14060/AD14060L
EXTERNAL RFS with MCE = 1, MFD = 0
DRIVE
DRIVE
SAMPLE
RCLK
tHFSE/I
(SEE NOTE 2)
tSFSE/I
RFS
tDDTE/I
tDDTENFS
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
DRIVE
SAMPLE
TCLK
tHFSE/I
(SEE NOTE 2)
tSFSE/I
TFS
tDDTE/I
tDDTENFS
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
Figure 23. External Late Frame Sync
–34–
REV. A
AD14060/AD14060L
DATA RECEIVE– INTERNAL CLOCK
DATA RECEIVE– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHFSE
tSFSI
tDFSE
tHFSE
tHFSI
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tHFSI
tDFSI
tSFSI
tDFSE
tHFSE
tHFSI
TFS
tSFSE
tHFSE
TFS
tHDTI
tDDTI
tHDTE
tDDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (EXT)
tDDTEN
tDDTTE
DT
DRIVE
EDGE
DRIVE
EDGE
TCLK (INT)
TCLK / RCLK
tDDTIN
tDDTTI
DT
CLKIN
CLKIN
tDPTR
TCLK, RCLK
TFS, RFS, DT
SPORT DISABLE DELAY
FROM INSTRUCTION
tSTFSCK
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
TFS (EXT)
tDCLK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR
MESH MULTIPROCESSING.
TCLK (INT)
RCLK (INT)
LOW TO HIGH ONLY
Figure 24. Serial Ports
REV. A
tHTFSCK
–35–
AD14060/AD14060L
JTAG Test Access Port and Emulation
5V
Parameter
Min
Timing Requirements:
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK Low1
tHSYS
System Inputs Hold After TCK Low1
tTRSTW
TRST Pulsewidth
tCK
5
6
8
18.5
4tCK
Switching Characteristics:
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low 2
3.3 V
Max
Min
Max
tCK
5
6
8
19
4tCK
13
20
Units
ns
ns
ns
ns
ns
ns
13
20
ns
ns
NOTES
1
System Inputs = DATA 47-0, ADDR 31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, RPBA, IRQ 2-0, FLAG2-0, DR0, DR1, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
2
System Outputs = DATA 47-0, ADDR 31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR 6-1, CPA, FLAG2-0, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 25. IEEE 11499.1 JTAG Test Access Port
–36–
REV. A
AD14060/AD14060L
OUTPUT DRIVE CURRENTS
Figure 26 shows typical I-V characteristics for the output drivers
of the ADSP-2106x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
120
100
HIGH LEVEL DRIVE
(P DEVICE)
80
SOURCE CURRENT – mA
60
40
The PEXT equation is calculated for each class of pins that can
drive:
Pin
Type
# of
Pins
%
Switching 3 C
Address
MS0
WR
Data
ADRCLK
15
1
1
32
1
50
0
–
50
–
× 55 pF
× 55 pF
× 55 pF
× 25 pF
× 15 pF
3f
3 VDD2 = PEXT
× 20 MHz
× 20 MHz
× 40 MHz
× 20 MHz
40 MHz
× 25 V
× 25 V
× 25 V
× 25 V
× 25 V
20
PEXT (5 V) = 0.476 W
PEXT (3.3 V) = 0.207 W
0
–20
–40
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
–60
–80
PTOTAL = PEXT + (IDDIN2 × 5.0 V )
LOW LEVEL DRIVE
(N DEVICE)
–100
–120
–140
–160
0
1
2
3
SOURCE VOLTAGE – V
4
5
Figure 26. ADSP-2106x Typical Drive Currents (VDD = 5 V)
POWER DISSIPATION
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Internal power dissipation is calculated in the following way:
PINT = IDDIN × VDD
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Also note that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ∆V is dependent on the capacitive load, CL, and
the load current, IL. This decay time can be approximated by
the following equation:
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
– the number of output pins that switch during each cycle (O)
– the maximum frequency at which they can switch (f)
– their load capacitance (C)
– their voltage swing (VDD)
and is calculated by:
PEXT = O × C × VDD2 × f
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2tCK). The write strobe
can switch every cycle at a frequency of 1/tCK. Select pins switch
at 1/(2tCK), but selects can switch on each cycle.
Example:
Estimate PEXT with the following assumptions:
–A system with one bank of external data memory RAM (32-bit)
–Four 128K × 8 RAM chips are used, each with a load of 10 pF
–External data memory writes occur every other cycle, a rate
–of 1/(4tCK), with 50% of the pins switching
–The instruction cycle rate is 40 MHz (tCK = 25 ns) and
–VDD = 5.0 V.
REV. A
= 0.206 W
= 0.00 W
= 0.055 W
= 0.200 W
= 0.015 W
t DECAY =
CL ∆V
IL
The output disable time, tDIS, is the difference between tMEASURED
and tDECAY as shown in Figure 27. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and
IL, and with ∆V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time, tENA, is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 27). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
∆V to be the difference between the ADSP-2106x’s output
voltage and the input threshold for the device requiring the hold
time. A typical ∆V will be 0.4 V. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
–37–
AD14060/AD14060L
(per data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tHDWD for the write cycle).
16.0
14.7
RISE AND FALL TIMES – ns
(0.5V – 4.5V, 10% – 90%)
14.0
REFERENCE
SIGNAL
tMEASURED
tENA
tDIS
VOH (MEASURED)
VOH (MEASURED) – ∆V
2.0V
VOL (MEASURED) + ∆V
1.0V
VOL (MEASURED)
VOH (MEASURED)
12.0
RISE TIME
10.0
8.0
4.0
3.7
VOL (MEASURED)
tDECAY
2.0
1.1
0
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
7.4
FALL TIME
6.0
0
20
40
60
80
100 120 140
LOAD CAPACITANCE – pF
160
180
200
Figure 30. Typical Output Rise Time (10%–90% VDD)
vs. Load Capacitance (VDD = 5 V)
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
Figure 27. Output Enable/Disable
3.5
TO
OUTPUT
PIN
RISE AND FALL TIMES – ns (0.8V–2.0V)
IOL
+1.5V
50pF
IOH
3.0
2.5
RISE TIME
2.0
1.5V
1.6
1.5
FALL TIME
1.0
0.6
0.5
0
Figure 28. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
INPUT OR
OUTPUT
2.9
0
20
40
60
80
100
120
140
160
180
200
LOAD CAPACITANCE – pF
Figure 31. Typical Output Rise Time (0.8 V –2.0 V)
vs. Load Capacitance (VDD = 5 V)
1.5V
Figure 29. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
5
4.5
OUTPUT DELAY OR HOLD – ns
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 28). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 30 and 31
show how output rise time varies with capacitance. Figure 32
graphically shows how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see the previous section Output Disable
Time under Test Conditions.) The graphs of Figures 30, 31 and
32 may not be linear outside the ranges shown.
4
3
2
1
NOMINAL
–0.7
–1
25
50
75
100
125
150
LOAD CAPACITANCE – pF
175
200
Figure 32. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature) (VDD = 5 V)
–38–
REV. A
AD14060/AD14060L
RISE AND FALL TIMES – ns (10% – 90%)
18
AD14060/AD14060L ASSEMBLY
RECOMMENDATIONS
16
SOCKET INFORMATION
14
Standard sockets and carriers are available for the AD14060/
AD14060L, if needed. Socket part number IC53-3084-262 and
carrier part number ICC-308-1 are available from Yamaichi
Electronics.
Y = 0.0796X + 1.17
12
10
RISE TIME
8
Trim and Form
6
The AD14060/AD14060L will be shipped as shown on the final
page of the data sheet with untrimmed and unformed leads and
with the nonconductive tie bar in place. This avoids disturbance of
lead spacing and coplanarity prior to assembly. Optimally, the
leads should be trimmed, formed and solder-dipped just prior to
placement on the board.
Y = 0.0467X + 0.55
4
FALL TIME
2
0
0
20
40
60
80
100
120
140
160
180
200
LOAD CAPACITANCE – pF
Figure 33. Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 3.3 V)
A trim/form tool specific to the AD14060/AD14060L has been
developed and is available for use by all parties at:
9
RISE AND FALL TIMES – ns (0.8V – 2.0V)
Trim/Form can be accomplished with a Universal Trim/Form,
Customer-Designed Trim/Form, or with the Analog Devices’
Developed Tooling described below.
8
Tintronics Industries
2122-A Metro Circle
Huntsville, AL 35801
205-650-0220
Contact Person: Tom Rice
7
Y = 0.0391X + 0.36
6
5
RISE TIME
4
The package outline and dimensions resulting from this tool are
shown below. (Alternatively, the package can also be trimmed/
formed for cavity-down placement.)
Y = 0.0305X + 0.24
3
FALL TIME
2
1
0
0
20
40
60
80
100
120
140
160
180
200
0.170
(4.318)
LOAD CAPACITANCE – pF
2.110 (53.59)
2.210 ± 0.010 (56.134 ± 0.254)
Figure 34. Typical Output Rise Time (0.8 V –2.0 V) vs.
Load Capacitance (VDD = 3.3 V)
5
4.5
Y = 0.0329X - 1.65
OUTPUT DELAY OR HOLD – ns
4
0.016 MIN
3
2
1
0° TO 8°
NOMINAL
–0.7
–1
0 TO 10 MILS
25
50
75
100
125
150
LOAD CAPACITANCE – pF
175
200
DETAIL "A"
Figure 35. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (VDD = 3.3 V)
REV. A
–39–
AD14060/AD14060L
PCB LAYOUT GUIDELINES
The drawing below assumes that the trim/form tooling described
above is used. These recommendations are provided for user
convenience and are recommendations only, based on standard practice. PCB pad footprint geometries and placement
are illustrated.
NOTE: These drawings are recommended PCB layout guidelines only, and they assume that the trim/form tooling described
above is used.
2.260 (57.404) 4 PLACES
2.060 (52.324) 4 PLACES
1.9000 (48.26) 4 PLACES
0.015
(0.381)
THIS IS A PC BOARD COMPONENT
FOOTPRINT, NOT THE PACKAGE
OUTLINE.
0.025
(0.635)
0.025 (0.635) MIN
0.025 (0.635) MIN
–40–
REV. A
AD14060/AD14060L
Thermal Characteristics
Thermal Conductivity
The AD14060/AD14060L is packaged in a 308-lead ceramic
quad flatpack (CQFP). The package is optimized for thermal
conduction through the core (base of the package) down to the
mounting surface. The AD14060/AD14060L is specified for a
case temperature (TCASE). Design of the mounting surface and
attachment material should be such that TCASE is not exceeded.
θJC = 0.36°C/W
Thermal Cross-Section
The data below, together with the detailed mechanical drawings
at the end of the data sheet, allows for constructing simple thermal models for further analysis within targeted systems. The top
layer of the package, where the die are mounted, is a metal VDD
layer. The approximate metal area coverage from the metal
planes and routing layers is estimated below.
KOVAR LID
0.015 MILS
Material
Thermal Conductivity
W/cm8C
Ceramic
Kovar
Tungsten
Thermoplastic
Silicon
0.18
0.14
1.78
0.03
1.45
Metal Coverage Per Layer
Layer
Percent Metal
(1 Mil Thick)
VDD
SIG2
SIG3
GND
SIG4
SIG5
BASE
88
16
14
91
15
13
95
KOVAR SEAL RING
HEIGHT = 50 MILS
SURFACE
SILICON DIE
19 MILS
CERAMIC LAYER 28 MILS
THERMOPLASTIC
THICKNESS 5 MILS
CERAMIC LAYER 6 MILS
CERAMIC LAYER 6 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
CERAMIC LAYER 10 MILS
VDD
SIG2
SIG3
GND
SIG4
SIG5
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
BASE
REV. A
–41–
AD14060/AD14060L
MECHANICAL CHARACTERISTICS
Lid Deflection Analysis
External Pressure Reduction
Delta Pressure
Deflection
12 psi
15 psi
10.0 mil
11.9 mil
0.670
4X
0.653
4X
0.302
2.050 SQ.
Mechanical Model
The data below, together with the detailed mechanical drawings
at the end of the data sheet, allows for construction of simple
mechanical models for further analysis within targeted systems.
0.616
0.633
Mechanical Properties
Material
Modulus of Elasticity
Ceramic
Kovar
Tungsten
Thermoplastic
Silicon
26 × 103 kg/mm2
14.1 × 103 kg/mm2
35 × 103 kg/mm2
279 kg/mm2
11 × 103 kg/mm2
0.260
0.250
0.345
1.890 ±0.005
1.810 ±0.005
1.780 ±0.018
0.040 ±0.002
0.012 REF
4X
308-LEAD CQFP PIN CONFIGURATION
308
232
231
1
AD14060/AD14060L
TOP VIEW
155
154
77
78
–42–
REV. A
AD14060/AD14060L
PIN CONFIGURATIONS
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
WR
RD
GND
CSA
CSB
CSC
CSD
GND
HBG
REDY
ADRCLK
VDD
RFS0
RCLK0
DR0
TFS0
TCLK0
DT0
GND
CPAA
CPAB
CPAC
CPAD
VDD
RFSA1
RCLKA1
DRA1
TFSA1
TCLKA1
DTA1
GND
RFSB1
RCLKB1
DRB1
TFSB1
TCLKB1
DTB1
VDD
RFSC1
RCLKC1
DRC1
TFSC1
TCLKC1
DTC1
REV. A
Pin Pin
No. Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
ADDR13
ADDR12
ADDR11
GND
ADDR10
ADDR9
ADDR8
VDD
ADDR7
ADDR6
ADDR5
GND
ADDR4
ADDR3
ADDR2
VDD
ADDR1
ADDR0
FLAGA0
GND
FLAGA2
FLAGB0
FLAGB2
FLAGC0
FLAGC2
FLAGD0
FLAGD2
VDD
FLAG1
EMU
TIMEXPA
TIMEXPB
TIMEXPC
TIMEXPD
GND
TDO
TRST
TDI
TMS
TCK
VDD
IRQA0
IRQA1
IRQA2
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
IRQB0
IRQB1
IRQB2
GND
IRQC0
IRQC1
IRQC2
IRQD0
IRQD1
IRQD2
VDD
EBOOTA
LBOOTA
EBOOTBCD
LBOOTBCD
GND
RESET
RPBA
GND
LD4ACK
LD4CLK
LD4DAT0
LD4DAT1
LD4DAT2
LD4DAT3
VDD
LD3ACK
LD3CLK
LD3DAT0
LD3DAT1
LD3DAT2
LD3DAT3
GND
LD1ACK
LD1CLK
LD1DAT0
LD1DAT1
LD1DAT2
LD1DAT3
VDD
LC4ACK
LC4CLK
LC4DAT0
LC4DAT1
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
LC4DAT2
LC4DAT3
GND
LC3ACK
LC3CLK
LC3DAT0
LC3DAT1
LC3DAT2
LC3DAT3
VDD
LC1ACK
LC1CLK
LC1DAT0
LC1DAT1
LC1DAT2
LC1DAT3
GND
LB4ACK
LB4CLK
LB4DAT0
LB4DAT1
LB4DAT2
LB4DAT3
VDD
LB3ACK
LB3CLK
LB3DAT0
LB3DAT1
LB3DAT2
LB3DAT3
GND
LB1ACK
LB1CLK
LB1DAT0
LB1DAT1
LB1DAT2
LB1DAT3
VDD
LA4ACK
LA4CLK
LA4DAT0
LA4DAT1
LA4DAT2
LA4DAT3
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
GND
LA3ACK
LA3CLK
LA3DAT0
LA3DAT1
LA3DAT2
LA3DAT3
VDD
LA1ACK
LA1CLK
LA1DAT0
LA1DAT1
LA1DAT2
LA1DAT3
GND
DATA0
DATA1
DATA2
DATA3
VDD
DATA4
DATA5
DATA6
DATA7
GND
DATA8
DATA9
DATA10
DATA11
VDD
DATA12
DATA13
DATA14
DATA15
GND
DATA16
DATA17
DATA18
DATA19
VDD
DATA20
DATA21
DATA22
DATA23
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
GND
DATA24
DATA25
DATA26
DATA27
VDD
DATA28
DATA29
DATA30
DATA31
GND
DATA32
DATA33
DATA34
DATA35
VDD
DATA36
DATA37
DATA38
DATA39
GND
DATA40
DATA41
CLKIN
GND
DATA42
DATA43
VDD
DATA44
DATA45
DATA46
DATA47
GND
BR1
BR2
BR3
BR4
BR5
BR6
PAGE
VDD
DMAG1
DMAG2
ACK
GND
RFSD1
RCLKD1
DRD1
TFSD1
TCLKD1
DTD1
VDD
HBR
DMAR1
DMAR2
SBTS
BMSA
BMSBCD
SW
GND
MS0
MS1
MS2
MS3
VDD
ADDR31
ADDR30
ADDR29
GND
ADDR28
ADDR27
ADDR26
VDD
ADDR25
ADDR24
ADDR23
ADDR22
ADDR21
ADDR20
VDD
ADDR19
ADDR18
ADDR17
GND
ADDR16
ADDR15
ADDR14
VDD
–43–
AD14060/AD14060L
Part Number
Case Temperature Range
SMD
Instruction Rate
Operating Voltage
AD14060BF-4
AD14060LBF-4
5962-9750601HXC
5962-9750701HXC*
–40°C to +100°C
–40°C to +100°C
–40°C to +100°C
–40°C to +100°C
N/A
N/A
QML-H
QML-H
40 MHz
40 MHz
40 MHz
40 MHz
5V
3.3 V
5V
3.3 V
*Part numbers marked with an * are shipping as x-grade (preproduction) material at the time of this printing. These parts are packaged in a 308-lead Ceramic Quad
Flatpack Package (CQFP). MIL-SMD parts, in the same package, are in development.
C3225–7–10/97
ORDERING GUIDE
PACKAGE DIMENSIONS
Dimensions shown in inches and (mm).
308-Lead Ceramic Quad Flatpack (CQFP)
(QS-308)
0.340 60.010
(8.636 60.254)
4x
3.050 (77.47) MAX
3.000 60.010 (76.2 60.254)
2.730 60.015 (69.34 60.381)
2.050 60.012 (52.07 60.305)
231
0.015 (0.381) x 45°
3 PLACES
155
232
154
2.300 60.030
(58.42 60.762)
0.008 60.002
(0.203 60.051)
TOP VIEW
0.025 (0.635) TYP
308
78
77
PRINTED IN U.S.A.
1
0.040 (1.016) x 45°
0.035
(0.889)
MAX
0.092 60.009
(2.337 60.229)
1.890 60.005
(48.006 60.127)
–44–
0.005 +0.0015 –0.001
(0.127 +0.0381 –0.025)
0.160
(4.064)
MAX
REV. A