Fairchild CGS3311M Cmos crystal clock generator Datasheet

Revised March 1999
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 •
CGS3316 • CGS3317 • CGS3318 • CGS3319
CMOS Crystal Clock Generators
General Description
Features
The CGS3311, CGS3312, CGS3313, CGS3314,
CGS3315, CGS3316, CGS3317, CGS3318 and CGS3319
devices are designed for Clock Generation and Support
(CGS) applications up to 110 MHz. The CGS331x series of
devices are crystal controlled CMOS oscillators requiring a
minimum of external components. The 331x devices provide selectable output divide ratio (and selectable crystal
drive level). The circuit is designed to operate over a wide
frequency range using fundamental model or overtone
crystals.
■ Fairchild’s CGS family of devices for high frequency
clock source applications
■ Crystal frequency operation range:
fundamental: 10 MHz to 100 MHz typical
3rd or 5th overtone: 10 MHz to 85 MHz
■ Programmable oscillator drive
■ Selectable fast output edge rates
■ Output symmetry circuit to adjust 50% duty cycle point
between CMOS and TTL levels
■ Output current drive of 48 mA for IOL/IOH
■ FACT CMOS output levels
■ Output has high speed short circuit protection
■ Basic oscillator type: Pierce
■ Hysteresis inputs to improve noise margin
Ordering Code:
Order Number
Package Number Package Description
CGS3311M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3312M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3313M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3314M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3315M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3316M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3317M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3318M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CGS3319M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010980.prf
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CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 CMOS Crystal
Clock Generators
September 1995
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
Connection Diagrams
(A) 3311
(E) 3315
(B)3312
(F) 3316
(C) 3313
(G) 3317
(D) 3314
(H) 3318
(I) 3319
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2
Division Selection
Rise and Fall Time Selection
DIVB DIVA OEL
OEH Divider Output
OSC_DR DIV TRF Rise/Fall Time (ns)
F
0/F
X
X
Divide-by 1
F
N
0/F
2
1
0/F
0
1
Divide-by 2
F
N
1
less than 2
0
0/F
0
1
Divide-by 4
F
Y
0/F
4
F
1
0
1
Divide-by 8
F
Y
1
2
1
1
0
1
Divide-by 16
0,1
X
0/F
4
0
1
0
1
Divide-by 32
0,1
X
1
2
X
X
1
X
Output Reset HIGH
at Re-enable
X
X
X
0
Drive Selection
Output Reset HIGH
at Re-enable
Note: Actual value of the floating OSC_DR and DIVB input is VCC/2
OSC_DR
Drive
0
Low
1
Medium
F
High
Note: Where “F” indicates floating the input.
Pin Descriptions
Note: Pin out varies for each device.
OSC_IN
Input to Oscillator Inverter. The output of the
crystal would be connected here.
OEL
Active LOW 3-STATE enable pin. This pin pulls
to a low value when left floating and 3-STATE
the output when forced HIGH. This pin has TTL
compatible input levels.
OSC_OUT Resistive Buffered Output of the Oscillator
Inverter
TRF
Rise and Fall time override pin. Available only
for die form.
OSC_DR
3 Level input pin that selects Oscillator Drive
Level
OUT
This pin is the main clock output on the device.
DIVA
Input used to select Binary Divide-by Option.
This pin has CMOS compatible input levels.
OSCLO_1
The Oscillator LOW pin is the ground for the
Oscillator.
OEH
Active HIGH 3-STATE enable pin. This pin pulls OSCLO_2
to a high value when left floating and 3-STATEs
the output when forced low. This pin has TTL
compatible input levels.
This pin is the same signal as OSCLO_1. It has
been provided as an alternate connection for
OSCLO_1 for hybrid assemblies.
VCC
The power pin for the chip.
GND
The ground pin for all sections of the circuitry
except the oscillator and oscillator related
circuitry.
Functional Table
Summary of Device Options
Each drive has one output with the choices of selecting frequency divide,
output enable, crystal drive and output rise and fall time. Crystal drive
options are:
L = LOW Drive
M = MEDIUM Drive
H = HIGH Drive
Output Rise/
Fall Time (ns)
Device
Divide
Enable
Drive
3311
1, 2, 4
OEH
L, M, H
2, 4
3312
1, 2, 4
OEH
H
2, 4
3313
8, 16, 32
OEH
H
4
3314
8, 16, 32
OEH
L, M, H
4
3315
1, 2, 4
OEL
H
1, 2
3316
4
OEH
H
4
3317
32
OEH
H
4
3318
1, 2, 4
OEH
H
1, 2
3319
1, 2, 4
OEL
L, M, H
2, 4
3
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CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
Truth Tables
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
Block Diagrams
Note: Pin numbers vary for each device
Oscillator Stage
Output Stage
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4
Recommended Operating
Conditions
Supply Voltage (VCC )
−0.5V to 7.0V
DC Input Voltage Diode Current (IIK)
±9 mA
DC Input Voltage (VI)
−0.5V to 7.0V
DC Output Diode Current (IOK)
±20 mA
DC Output Voltage (VO)
-0.5V to VCC + 0.5V
Supply Voltage (VCC)
DC Output Source
or Sink Current (IO)
Storage Temperature (TSTG)
0V to 5.5V
Output Voltage (VO)
0V to VCC V
Operating Temperature (TA)
−40° to +85°C
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the DC and AC
Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation.
±70 mA
−55°C to 150°C
Junction Temperature (TJ)
SOIC
4.5V to 5.5V
Input Voltage (VI)
140°C/W
DC Electrical Characteristics
TA = +25°C
VCC
TA = −40° C to +85°C
Guaranteed Limits
Symbol
Parameter
(V)
VIHTTL
Minimum HIGH Level
Input Voltage,
TTL Level Inputs (OEH, OEL)
4.5
2.0
2.0
5.5
2.0
2.0
Maximum LOW Level
Input Voltage, TTL Level
Inputs (OEH, OEL)
4.5
0.8
0.8
5.5
0.8
0.8
Minimum HIGH Level
Input Voltage. CMOS
Level Inputs (DIVA)
4.5
3.15
3.15
5.5
3.85
3.85
Maximum LOW Level
Input voltage. CMOS
Level Inputs (DIVA)
4.5
1.35
1.35
5.5
1.65
1.65
Minimum Logic 1 Input
for Three Level Input
(DIVB, OSC_DR)
4.5
4.05
4.05
5.5
4.95
4.95
Minimum Logic 1/2 Input
for Three Level Input
(DIVB, OSC_DR)
4.5
1.8
2.7
1.8
2.7
5.5
2.2
3.3
2.2
3.3
Maximum Logic 0 Input
Level Three Level Input
(DIVB, OSC_DR)
4.5
0.45
0.45
5.5
0.45
0.45
VILTTL
VIHCMOS
VILCMOS
VIN3L_H
VIN3L_1/2
VIN3L_L
VOH
VOL
Minimum HIGH Level
Output Voltage
Minimum LOW Level
Output Voltage
Typ
Min
Max
Min
4.5
4.49
4.40
4.40
5.5
5.49
5.40
5.40
4.5
3.86
3.76
5.5
4.86
4.76
Max
Units Conditions
V
V
V
V
V
V
V
V
IOUT = −50µA
IOH = −48 mA
VIN = VIH or VIH
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
4.5
0.44
0.44
5.5
0.44
0.44
V
IOUT = 50µA
IOL = +48mA
VIN = VIL or VIH
IIHRES
Input Current for Pins
DIVB, OSC_DR, and
DIVA (Input is Logic HIGH)
5.5
220
360
200
380
µA
VIN = 5.5V
IILRES
Input Current for Pins
DIVB, OSC_DR, and
DIVA (Input is Logic LOW)
5.5
−220
−360
−200
−380
µA
VIN = 0.0V
IIHENAB
Input Current for
Enable Pin OEL
5.5
90
160
85
175
µA
VIN = 5.5V
IILENAB
Input Current for
Enable Pin OEH
5.5
−90
−160
−85
−175
µA
VIN = 0.0V
IIHOSC
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
5.5
20
100
20
125
µA
VIN = 5.5V
IILOSC
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
5.5
−20
−100
−20
−125
µA
VIN = 0.0V
IOZH
Output Disabled Current
4.5
3.0
5.0
µA
VOUT = VCC
(Output HIGH)
5.5
3.0
5.0
5
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CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
Absolute Maximum Ratings(Note 1)
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
DC Electrical Characteristics
(Continued)
TA = +25°C
VCC
TA = −40° C to +85°C
Guaranteed Limits
Symbol
Parameter
(V)
Max
Units Conditions
IOZL
Output Disabled Current
4.5
−140
−150
µA
VOUT = 0.0V
(Output LOW)
5.5
−170
−180
IOLD
Minimum Dynamic
Output Current
5.5
75
75
mA
VOLD = 1.65v
IOHD
Minimum Dynamic
Output Current
5.5
−75
−75
mA
VOHD = 3.85V
ICCOSC_L
Additional ICC with OSC_IN
4.5
0.6
mA
OSC_IN = Float
Floating. LOW Drive Mode
5.5
mA
OSC_IN = Float
mA
OSC_IN = Float
ICCOSC_M
ICCOSC_H
Additional ICC with OSC_IN
4.5
Floating. LOW Drive Mode
5.5
Typ
Min
Max
Min
0.6
6.5
6.5
1.7
1.7
12.4
12.4
Additional ICC with OSC_IN
4.5
Floating. LOW Drive Mode
5.5
5.5
31.5
5.5
31.5
ICCT
Additional Maximum ICC
per Input
(OEH, OEL Pins)
5.5
1.5
1.5
mA
VIN = VCC − 2.1V
ICC3L
Additional Maximum ICC
per Input
(DIVB, OSC_DR Inputs)
5.5
1.5
1.5
mA
DIVB, OSC_DR
Inputs Equal to VCC/2
AC Electrical Characteristics
Over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
VCC
TA = −40°C to + 85°C
(V)
CL = 50 pF
Symbol
Parameter
(Note 2)
Min
fMAX
Frequency Maximum
5.0
100
tPZH
Output HIGH Enable Time
5.0
1.0
31.5
ns
tPZL
Output LOW Enable Time
5.0
1.0
28.0
ns
tPHZ
Output HIGH Disable Time
5.0
1.0
21.5
ns
tPLZ
Output LOW Disable Time
5.0
1.0
16.0
ns
tRISE
Rise/Fall Time
5.0
tFALL
30 pF (20% to 80%)
6
Max
Units
ns
4.0
Note 2: Voltage Range 5.0 is 5.0V ± 0.5V
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Type
ns
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M08A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 CMOS Crystal
Clock Generators
Physical Dimensions inches (millimeters) unless otherwise noted