Microchip MCP6143-I/P 600 na, non-unity gain rail-to-rail input/output op amp Datasheet

MCP6141/2/3/4
600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps
Features:
Description:
•
•
•
•
•
•
•
•
•
The MCP6141/2/3/4 family of non-unity gain stable
operational amplifiers (op amps) from Microchip Technology Inc. operate with a single supply voltage as low
as 1.4V, while drawing less than 1 μA (max.) of quiescent current per amplifier. These devices are also
designed to support rail-to-rail input and output operation. This combination of features supports
battery-powered and portable applications.
Low Quiescent Current: 600 nA/amplifier (typ.)
Gain Bandwidth Product: 100 kHz (typ.)
Stable for gains of 10 V/V or higher
Rail-to-Rail Input/Output
Wide Supply Voltage Range: 1.4V to 5.5V
Available in Single, Dual, and Quad
Chip Select (CS) with MCP6143
Available in 5-lead and 6-lead SOT-23 Packages
Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Applications:
•
•
•
•
The MCP6141/2/3/4 family operational amplifiers are
offered in single (MCP6141), single with Chip Select
(CS) (MCP6143), dual (MCP6142) and quad
(MCP6144) configurations. The MCP6141 device is
available in the 5-lead SOT-23 package, and the
MCP6143 device is available in the 6-lead SOT-23
package.
Toll Booth Tags
Wearable Products
Temperature Measurement
Battery Powered
Available Tools:
• SPICE Macro Models (at www.microchip.com)
• FilterLab™ Software (at www.microchip.com)
Related Devices:
• MCP6041/2/3/4: Unity Gain Stable Op Amps
Typical Application
Package Types
MCP6141
PDIP, SOIC, MSOP
MCP6143
PDIP, SOIC, MSOP
NC 1
8 NC
NC 1
8 CS
VIN– 2
7 VDD
VIN– 2
7 VDD
VIN+ 3
6 VOUT
VIN+ 3
6 VOUT
VSS 4
R1
5 NC
VSS 4
MCP6141
SOT-23-5
V1
R2
VOUT 1
V2
R3
The MCP6141/2/3/4 amplifiers have a gain bandwidth
product of 100 kHz (typ.) and are stable for gains of
10 V/V or higher. These specifications make these op
amps appropriate for battery powered applications
where a higher frequency response from the amplifier
is required.
VOUT
V3
MCP614X
VREF
Inverting, Summing Amplifier
VIN+ 3
VOUT 1
4 VIN–
VIN+ 3
VSS 2
MCP6142
PDIP, SOIC, MSOP
6 VDD
5 CS
4 VIN–
MCP6144
PDIP, SOIC, TSSOP
VOUTA 1
8 VDD
VOUTA 1
14 VOUTD
VINA– 2
7 VOUTB VINA– 2
6 VINB– VINA+ 3
13 VIND–
12 VIND+
VINA+ 3
VSS 4
© 2005 Microchip Technology Inc.
MCP6143
SOT-23-6
5 VDD
VSS 2
RF
5 NC
5 VINB+
VDD 4
11 VSS
VINB+ 5
10 VINC+
VINB– 6
9 VINC–
VOUTB 7
8 VOUTC
DS21668B-page 1
MCP6141/2/3/4
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
All Inputs and Outputs .................... VSS – 0.3V to VDD + 0.3V
Difference Input voltage ...................................... |VDD – VSS|
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.................................... –65°C to +150°C
Junction Temperature.................................................. +150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 200V
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2,
VOUT ≈ VDD/2, and RL = 1 MΩ to VDD/2.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset
Input Offset Voltage
Drift with Temperature
Power Supply Rejection
VOS
-3
—
+3
mV
ΔVOS/ΔTA
—
±1.5
—
μV/°C
VCM = VSS
PSRR
70
85
—
dB
IB
—
1
—
pA
IB
—
20
100
pA
TA = +85°
TA = +125°
VCM = VSS,
TA = -40°C to +125°C
VCM = VSS
Input Bias Current and Impedance
Input Bias Current
Industrial Temperature
IB
—
1200
5000
pA
Input Offset Current
IOS
—
1
—
pA
Common Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||6
—
Ω||pF
Common Mode Input Range
VCMR
VSS−0.3
—
VDD+0.3
V
Common Mode Rejection Ratio
CMRR
62
80
—
dB
VDD = 5V, VCM = -0.3V to 5.3V
CMRR
60
75
—
dB
VDD = 5V, VCM = 2.5V to 5.3V
CMRR
60
80
—
dB
VDD = 5V, VCM = -0.3V to 2.5V
AOL
95
115
—
dB
RL = 50 kΩ to VDD/2,
VOUT = 0.1V to VDD−0.1V
VOL, VOH
VSS + 10
—
VDD − 10
mV
RL = 50 kΩ to VDD/2,
0.5V output overdrive
VOVR
VSS + 100
—
VDD − 100
mV
RL = 50 kΩ to VDD/2,
AOL ≥ 95 dB
Extended Temperature
Common Mode
Open Loop Gain
DC Open Loop Gain (large signal)
Output
Maximum Output Voltage Swing
Linear Region Output Voltage Swing
Output Short Circuit Current
ISC
—
2
—
mA
VDD = 1.4V
ISC
—
20
—
mA
VDD = 5.5V
VDD
1.4
—
5.5
V
IQ
0.3
0.6
1.0
μA
Power Supply
Supply Voltage
Quiescent Current per amplifier
DS21668B-page 2
IO = 0
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 1 MΩ to VDD/2, and CL = 60 pF.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
100
—
kHz
Slew Rate
SR
—
24
—
V/ms
Phase Margin
PM
—
60
—
°
Input Voltage Noise
Eni
—
5.0
—
Input Voltage Noise Density
eni
—
170
—
nV/√Hz f = 1 kHz
Input Current Noise Density
ini
—
0.6
—
fA/√Hz f = 1 kHz
G = +10
Noise
μVP-P f = 0.1 Hz to 10 Hz
MCP6143 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 1 MΩ to VDD/2, and CL = 60 pF.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
VSS+0.3
V
CS Input Current, Low
ICSL
—
5
—
pA
CS Logic Threshold, High
VIH
VDD–0.3
—
VDD
V
CS Input Current, High
ICSH
—
5
—
pA
CS = VDD
ISS
—
-20
—
pA
CS = VDD
IOLEAK
—
20
—
pA
CS = VDD
CS Low to Amplifier Output Turn-on Time
tON
—
2
50
ms
G = +1V/V, CS = 0.3V to
VOUT = 0.9VDD/2
CS High to Amplifier Output High-Z
tOFF
—
10
—
μs
G = +1V/V, CS = VDD–0.3V to
VOUT = 0.1VDD/2
VHYST
—
0.6
—
V
VDD = 5.0V
CS Low Specifications
CS = VSS
CS High Specifications
CS Input High, GND Current
Amplifier Output Leakage, CS High
Dynamic Specifications
Hysteresis
CS
VIL
VIH
tOFF
tON
VOUT High-Z
ISS -20 pA (typ.)
High-Z
-0.6 μA (typ.)
ICS 5 pA (typ.)
-20 pA (typ.)
5 pA (typ.)
FIGURE 1-1:
Chip Select (CS) Timing
Diagram (MCP6143 only).
© 2005 Microchip Technology Inc.
DS21668B-page 3
MCP6141/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND.
Parameters
Sym.
Min.
Typ.
Max. Units
Conditions
TA
-40
—
+85
°C
Industrial Temperature parts
TA
-40
—
+125
°C
Extended Temperature parts
Operating Temperature Range
TA
-40
—
+125
°C
(Note 1)
Storage Temperature Range
TA
-65
—
+150
°C
°C/W
Temperature Ranges
Specified Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
Thermal Resistance, 6L-SOT-23
θJA
—
230
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note 1:
The MCP6141/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with
reduced performance. In any case, the internal Junction Temperature (TJ) should not exceed the Absolute
Maximum specification of +150°C.
DS21668B-page 4
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = 25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 MΩ to VDD/2,
VOUT ≈ VDD/2, and CL = 60 pF.
1200 Samples
VDD = 1.4V
12%
Percentage of Occurrences
10%
8%
6%
4%
2%
16%
1200 Samples
VDD = 5.5V
14%
12%
10%
8%
6%
4%
2%
0%
0%
-3
-2
-1
0
1
2
-3
3
-2
-1
Input Offset Voltage (mV)
FIGURE 2-1:
VDD = 1.4V.
FIGURE 2-4:
VDD = 5.5V.
Input Offset Voltage at
30%
235 Samples
VDD = 1.4V
TA = -40°C to +125°C
14%
Percentage of Occurrences
12%
10%
8%
6%
4%
2%
2
3
235 Samples
VDD = 5.5V
TA = -40°C to +125°C
25%
20%
15%
10%
5%
0%
0%
8
-10
10
-8
-2
0
2
4
6
8
10
Common Mode Input Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 1.4V.
Input Offset Voltage Drift at
VDD = 5.5V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
6.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
TA = +25°C
TA = -40°C
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
0.0
TA = +125°C
TA = +85°C
© 2005 Microchip Technology Inc.
-4
FIGURE 2-5:
VDD = 5.5V.
Input Offset Voltage (µV)
VDD = 1.4V
-0.4
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
Input Offset Voltage Drift at
-0.5
FIGURE 2-2:
VDD = 1.4V.
-6
Input Offset Voltage Drift (µV/°C)
Input Offset Voltage Drift (µV/°C)
5.5
6
5.0
4
4.5
2
4.0
0
3.5
-2
3.0
-4
2.5
-6
2.0
-8
1.5
-10
Input Offset Voltage (µV)
1
Input Offset Voltage at
0.5
Percentage of Occurrences
18%
16%
0
Input Offset Voltage (mV)
1.0
Percentage of Occurrences
14%
Common Mode Input Voltage (V)
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
DS21668B-page 5
MCP6141/2/3/4
Note: Unless otherwise indicated, TA = 25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 MΩ to VDD/2,
VOUT ≈ VDD/2, and CL = 60 pF.
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-1
0
Output Voltage (V)
200
150
100
50
1000
Common Mode Input Voltage (V)
Frequency (Hz)
FIGURE 2-8:
vs. Frequency.
Input Noise Voltage Density
90
100
PSRR, CMRR (dB)
CMRR, PSRR (dB)
FIGURE 2-11:
Input Noise Voltage Density
vs. Common Mode Input Voltage.
PSRR–
PSRR+
80
70
60
CMRR
50
40
30
5.5
0
5.0
100
f = 1 kHz
VDD = 5.0V
250
4.5
10
25
300
-0.5
1
20
FIGURE 2-10:
The MCP6141/2/3/4 family
shows no phase reversal.
100
0.1
10 (5 ms/div)
15
Time
4.0
1,000
5
0.0
Input Offset Voltage vs.
Input Noise Voltage Density
(nV/ Hz)
Input Noise Voltage Density
(nV/ Hz)
FIGURE 2-7:
Output Voltage.
VOUT
0
3.5
250
VIN
1
3.0
300
2
2.5
VDD = 5.5V
3
2.0
350
4
1.5
VDD = 1.4V
400
VDD = 5.0V
G = +11 V/V
5
1.0
450
0.5
RL = 50 kΩ
Input, Output Voltages (V)
Input Offset Voltage (µV)
500
95
PSRR (VCM = VSS)
90
85
80
CMRR (VDD = 5.0V,
VCM = -0.3V to +5.3V)
75
Referred to Input
70
20
1
1
FIGURE 2-9:
Frequency.
DS21668B-page 6
10
10
100
1k
100
1,000
Frequency (Hz)
CMRR, PSRR vs.
10k
10,000
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-12:
Temperature.
CMRR, PSRR vs. Ambient
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
10k
10000
10000
10k
1k
1000
Input Bias, Offset Currents
(pA)
Input Bias and Offset Currents
(pA)
Note: Unless otherwise indicated, TA = 25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 MΩ to VDD/2,
VOUT ≈ VDD/2, and CL = 60 pF.
VDD = 5.5V
VCM = VDD
100
100
VDD = 5.5V
1k
1000
IB
1010
11
| IOS |
10
11
55
65
75
85
95
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
105 115 125
Ambient Temperature (°C)
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias, Offset Currents
vs. Ambient Temperature.
0
100
-30
80
-60
Phase
60
130
-90
40
-120
Gain
20
-150
0
-180
-20
-210
FIGURE 2-16:
Input Bias, Offset Currents
vs. Common Mode Input Voltage.
DC Open-Loop Gain (dB)
120
Open-Loop Phase (°)
Open-Loop Gain (dB)
| IOS
|
TA = +85°C
0.1
0.1
0.1
0.1
45
-40
-240
10m
1 1.E+
10 1.E+
100 1.E+
1k 1.E+
10k 1.E+
100k
1.E- 100m
1.E- 1.E+
02
01
00 Frequency
01
02(Hz)03
04
05
FIGURE 2-14:
Frequency.
120
VDD = 5.5V
110
100
VDD = 1.4V
90
80
70
VOUT = 0.1V to VDD - 0.1V
60
100
1.E+02
Open-Loop Gain, Phase vs.
1k
10k
1.E+03
1.E+04
Load Resistance (Ω)
FIGURE 2-17:
Load Resistance.
100k
1.E+05
DC Open-Loop Gain vs.
140
130
120
110
100
RL = 50 kΩ
VOUT = 0.1V to VDD - 0.1V
90
80
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power Supply Voltage (V)
FIGURE 2-15:
DC Open-Loop Gain vs.
Power Supply Voltage.
© 2005 Microchip Technology Inc.
DC Open-Loop Gain (dB)
140
DC Open-Loop Gain (dB)
IB
TA = +125°C
100
130
RL = 50 kΩ
VDD = 5.5V
120
110
100
VDD = 1.4V
90
80
70
0.00
0.05
0.10
0.15
0.20
0.25
Output Voltage Headroom;
VDD – VOH or VOL – VSS (V)
FIGURE 2-18:
DC Open-Loop Gain vs.
Output Voltage Headroom.
DS21668B-page 7
MCP6141/2/3/4
90
80
80
70
60
60
50
50
GBWP
40
30
30
20
20
10
10
VDD = 1.4V
0
-50
-25
0
25
50
75 100
Ambient Temperature (°C)
0.8
Quiescent Current
(µA/Amplifier)
0.7
0.6
0.5
0.4
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.3
0.2
0.1
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-21:
Quiescent Current vs.
Power Supply Voltage.
DS21668B-page 8
5.5
80
70
70
60
60
PM
(G = +10)
50
50
40
40
30
30
20
10
20
10
VDD = 5.5V
0
0
125
FIGURE 2-20:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature at
VDD = 1.4V.
90
GBWP
-50
-25
Phase Margin (°)
90
70
40
4.5
5.0
FIGURE 2-22:
Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
Phase Margin (°)
Gain Bandwidth Product
(kHz)
PM
(G = +10)
80
4.0
Common Mode Input Voltage
FIGURE 2-19:
Channel-to-Channel
Separation vs. Frequency (MCP6142 and
MCP6144 only).
90
VDD = 5.0V
3.0
3.5
10k
1.E+04
Gain Bandwidth Product
(kHz)
Input Referred
80
1k
1.E+03
Frequency (Hz)
2.0
2.5
90
1.5
100
PM
(G = +10)
0.5
1.0
110
120
110
100
90
80
70
60
50
40
30
20
10
0
GBWP
0.0
120
120
110
100
90
80
70
60
50
40
30
20
10
0
-0.5
Gain Bandwidth Product
(kHz)
130
0
25
50
75
100
0
125
Ambient Temperature (°C)
FIGURE 2-23:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature at
VDD = 5.5V.
Output Short Circuit Current
(mA)
Channel-to-Channel
Separation (dB)
140
Phase Margin (°)
Note: Unless otherwise indicated, TA = 25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 MΩ to VDD/2,
VOUT ≈ VDD/2, and CL = 60 pF.
35
30
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
-35
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Ambient Temperature (°C)
FIGURE 2-24:
Output Short Circuit Current
vs. Power Supply Voltage.
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
Note: Unless otherwise indicated, TA = 25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 MΩ to VDD/2,
VOUT ≈ VDD/2, and CL = 60 pF.
Output Voltage Headroom,
VDD – VOH or VOL – VSS (mV)
Output Voltage Headroom,
VDD – VOH or VOL – VSS (mV)
1000
100
VDD – VOH
10
VOL – VSS
1
0.01
0.1
1
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.5V
RL = 50 kΩ
VDD – VOH
-50
10
-25
FIGURE 2-25:
Output Voltage Headroom
vs. Output Current Magnitude.
30
Maximum Output Voltage
Swing (V P-P)
Slew Rate (V/ms)
50
75
100
125
10
35
High-to-Low
VDD = 5.5V
15
Low-to-High
10
5
25
FIGURE 2-28:
Output Voltage Headroom
vs. Ambient Temperature.
40
20
0
Ambient Temperature (°C)
Output Current Magnitude (mA)
25
VOL – VSS
VDD = 1.4V
0
-50
-25
0
25
50
75
100
VDD = 5.5V
VDD = 1.4V
1
0.1
100
1.E+02
125
Ambient Temperature (°C)
FIGURE 2-26:
Temperature.
Slew Rate vs. Ambient
80
Output Voltage (20 mV/div)
10k
1.E+04
FIGURE 2-29:
Maximum Output Voltage
Swing vs. Frequency.
80
G = +11 V/V
RL = 50 kΩ
G = -10 V/V
RL = 50 kΩ
60
Voltage (20 mV/div)
60
1k
1.E+03
Frequency (Hz)
40
40
20
20
0
0
-20
-20
-40
-40
-60
-60
-80
-80
0.0
0.1
0.2
0.3 Time
0.4 (100
0.5 µs/div)
0.6 0.7
FIGURE 2-27:
Pulse Response.
0.8
0.9
1.0
Small Signal Non-inverting
© 2005 Microchip Technology Inc.
0.0
0.1
0.2
FIGURE 2-30:
Response.
0.3 Time
0.4 (100
0.5 µs/div)
0.6 0.7
0.8
0.9
1.0
Small Signal Inverting Pulse
DS21668B-page 9
MCP6141/2/3/4
Note: Unless otherwise indicated, TA = 25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 1 MΩ to VDD/2,
VOUT ≈ VDD/2, and CL = 60 pF.
5.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0
1 Time
1 (200
1 µs/div)
1
1
FIGURE 2-31:
Pulse Response.
27.5
25.0
22.5
20.0
17.5
15.0
12.5
10.0
7.5
5.0
2.5
0.0
2
2
Large Signal Non-inverting
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
VDD = 5.0V
G = +11 V/V
VIN = +3.0V
VOUT
On
High-Z
On
CS
0
1
2
3 Time
4 (15 ms/div)
6 7
8
9
10
FIGURE 2-32:
Chip Select (CS) to
Amplifier Output Response Time (MCP6143
only).
DS21668B-page 10
0
2
0
0
FIGURE 2-33:
Response.
Internal CS Switch Output (V)
0
Output Voltage (V)
0
CS Voltage (V)
VDD = 5.0V
G = -10 V/V
RL = 50 kΩ
4.5
Output Voltage (V)
Output Voltage (V)
5.0
VDD = 5.0V
G = +11 V/V
RL = 50 kΩ
4.5
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1 Time
1 (200
1 µs/div)
1
1
2
2
2
Large Signal Inverting Pulse
VOUT On
Hysteresis
CS
High-to-Low
CS
Low-to-High
VOUT High-Z
VDD = 5.0V
G = +11 V/V
VIN = 3.0V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CS Voltage (V)
FIGURE 2-34:
Internal Chip Select (CS)
Hysteresis (MCP6143 only).
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6143
MCP6141
(PDIP,
MCP6141
(PDIP,
MCP6143
MCP6142
MCP6144
SOIC,
(SOT-23-5)
SOIC,
(SOT-23-6)
MSOP)
MSOP)
Symbol
Description
6
1
1
6
1
1
VOUT, VOUTA Analog Output (op amp A)
2
4
2
2
4
2
VIN–, VINA–
Inverting Input (op amp A)
3
3
3
3
3
3
VIN+, VINA+
Non-inverting Input (op amp A)
7
5
8
7
6
4
VDD
—
—
5
—
—
5
VINB+
Non-inverting Input (op amp B)
—
—
6
—
—
6
VINB–
Inverting Input (op amp B)
—
—
7
—
—
7
VOUTB
Analog Output (op amp B)
—
—
—
—
—
8
VOUTC
Analog Output (op amp C)
—
—
—
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
—
—
10
VINC+
Non-inverting Input (op amp C)
4
2
4
4
2
11
VSS
—
—
—
—
—
12
VIND+
Positive Power Supply
Negative Power Supply
Non-inverting Input (op amp D)
—
—
—
—
—
13
VIND–
Inverting Input (op amp D)
—
—
—
—
—
14
VOUTD
Analog Output (op amp D)
—
—
—
8
5
—
CS
Chip Select
1, 5, 8
—
—
1, 5
—
—
NC
No Internal Connection
3.1
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents.
3.3
CS Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low-power mode of operation.
© 2005 Microchip Technology Inc.
3.4
Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.4V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 μF to
0.1 μF) within 2 mm of the VDD pin. These can share a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
DS21668B-page 11
MCP6141/2/3/4
4.0
APPLICATIONS INFORMATION
See Microchip’s related MCP6041/2/3/4 family of op
amps for applications needing unity gain stability.
The second specification that describes the output
swing capability of these amplifiers is the Linear Output
Voltage Range. This specification defines the maximum output swing that can be achieved while the
amplifier still operates in its linear region. To verify
linear operation in this range, the large signal DC
Open-Loop Gain (AOL) is measured at points inside the
supply rails. The measurement must meet the specified
AOL condition in the specification table.
4.1
4.3
The MCP6141/2/3/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process
These op amps are stable for gains of 10 V/V and
higher. They are suitable for a wide range of general
purpose, low-power applications.
Rail-to-Rail Inputs
The MCP6141/2/3/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-10 shows the input voltage exceeding the supply voltage without any phase reversal.
The input stage of the MCP6141/2/3/4 op amps uses
two differential CMOS input stages in parallel. One
operates at low Common mode input voltage (VCM),
while the other operates at high VCM. With this topology, the device operates with VCM tp to 0.3V above VDD
and 0.3V below VSS. The input offset voltage (VOS) is
measured at VCM = VSS – 0.3V and VDD + 0.3V to
ensure proper operation.
Input voltages that exceed the Absolute Maximum Voltage Range (VSS – 0.3V to VDD + 0.3V) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-1.
RIN
MCP614X
The MCP6141/2/3/4 op amp family has outstanding
quiescent current, which supports battery-powered
applications. There is minimal quiescent current glitching when Chip Select (CS) is raised or lowered. This
prevents excessive current draw, and reduced battery
life, when the part is turned off or on.
Heavy resistive loads at the output can cause excessive battery drain. Driving a DC voltage of 2.5V across
a 100 kΩ load resistor will cause the supply current to
increase by 25 μA, depleting the battery 43 times as
fast as IQ (0.6 μA, typ.) alone.
High frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current.
For instance, a 0.1 μF capacitor at the output presents
an AC impedance of 15.9 kΩ (1/2πfC) to a 100 Hz sinewave. It can be shown that the average power drawn
from the battery by a 5.0 Vp-p sinewave (1.77 Vrms),
under these conditions, is
EQUATION 4-1:
RF
VA
RIN
Output Loads and Battery Life
VOUT
PSupply = (VDD - VSS) (IQ + VL(p-p) f CL )
= (5V)(0.6 µA + 5.0Vp-p · 100Hz · 0.1µF)
= 3.0 µW + 50 µW
VB
( Maximum expected VIN ) – V DD
RIN ≥ -----------------------------------------------------------------------------2 mA
V SS – ( Minimum expected V IN )
R IN ≥ --------------------------------------------------------------------------2 mA
FIGURE 4-1:
Resistor (RIN).
4.2
Input Current-Limiting
Rail-to-Rail Output
There are two specifications that describe the output
swing capability of the MCP6141/2/3/4 family of op
amps. The first specification (Maximum Output Voltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load condition. Thus,
the output voltage swings to within 10 mV of either supply rail with a 50 kΩ load to VDD/2. Figure 2-10 shows
how the output voltage is limited when the input goes
beyond the linear region of operation.
DS21668B-page 12
This will drain the battery 18 times as fast as IQ alone.
4.4
4.4.1
Stability
NOISE GAIN
The MCP6141/2/3/4 op amp family is designed to give
high bandwidth and slew rate for circuits with high noise
gain (GN) or signal gain. Low gain applications should
be realized using the MCP6041/2/3/4 op amp family;
this simplifies design and implementation issues.
Noise gain is defined to be the gain from a voltage
source at the non-inverting input to the output when all
other voltage sources are zeroed (shorted out). Noise
gain is independent of signal gain and depends only on
components in the feedback loop. The amplifier circuits
in Figure 4-2 and Figure 4-3 have their noise gain
calculated as follows:
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
4.4.2
EQUATION 4-2:
RF
G N = 1 + ------- ≥ 10 V/V
RG
In order for the amplifiers to be stable, the noise gain
should meet the specified minimum noise gain. Note
that a noise gain of GN = +10 V/V corresponds to a
non-inverting signal gain of G = +10 V/V, or to an
inverting signal gain of G = -9 V/V.
RIN
VIN
MCP614X
RG
VOUT
RF
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +10), a small series
resistor at the output (RISO in Figure 4-5) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no
capacitive load.
RG
FIGURE 4-2:
Noise Gain for Non-inverting
Gain Configuration.
RF
VA
RISO
VOUT
MCP614X
RG
RF
VB
CL
VOUT
FIGURE 4-5:
Output Resistor, RISO
stabilizes large capacitive loads.
MCP614X
RIN
FIGURE 4-3:
Noise Gain for Inverting
Gain Configuration.
Figure 4-4 shows a unity gain buffer and Miller integrator that are unstable when used with the
MCP6141/2/3/4 family. Note that the capacitor makes
the integrator circuit reach unity gain at high
frequencies, which makes these op amps unstable.
Unity Gain Buffer
Figure 4-6 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -9 V/V gives GN = +10 V/V).
100k
100,000
Recommended RISO ( :)
VIN
10k
10,000
VOUT
MCP614X
VIN
GN = +10
GN = +20
GN t+50
1k
1,000
1p
1.E+00
100p
1n
10p
1.E+01
1.E+02
1.E+03
Normalized Load Capacitance; C L/GN (F)
Miller Integrator
R
C
VOUT
VIN
MCP614X
FIGURE 4-4:
Typical Unstable Circuits for
the MCP6141/2/3/4 Family.
© 2005 Microchip Technology Inc.
FIGURE 4-6:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and simulations with the MCP6141/2/3/4 SPICE macro model are
helpful.
DS21668B-page 13
MCP6141/2/3/4
4.5
MCP6143 Chip Select (CS)
4.8
PCB Surface Leakage
The MCP6143 is a single op amp with Chip Select
(CS). When CS is pulled high, the supply current drops
to 50 nA (typ.) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high impedance state. By pulling CS low, the amplifier
is enabled. If the CS pin is left floating, the amplifier
may not operate properly. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6141/2/3/4 family’s bias current at 25°C (1 pA,
typ.).
4.6
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-8.
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 μF to 0.1 μF) within 2 mm
for good high frequency performance. It can use a bulk
capacitor (i.e., 1 μF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor is not required
for most applications and can be shared with other
nearby analog parts.
4.7
Guard Ring
VIN– VIN+
Unused Op Amps
An unused op amp in a quad package (MCP6144)
should be configured as shown in Figure 4-7. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A and B are set near the minimum
noise gain. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage,
and minimizes the supply current draw of the unused
op amp. Circuit B may draw a little more supply current
for the unused op amp. Circuit C uses the minimum
number of components and operates as a comparator;
it may draw more current than either Circuit A or B.
¼ MCP6144 (A)
¼ MCP6144 (B)
VDD
R
VDD
VDD
R
R
R
15R
FIGURE 4-7:
DS21668B-page 14
10R
FIGURE 4-8:
for Inverting Gain.
1.
2.
Example Guard Ring Layout
Non-inverting Gain and Unity Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
Common mode input voltage.
Inverting Gain and Trans-impedance Gain (convert current to voltage, such as photo detectors)
amplifiers:
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
¼ MCP6144 (C)
VDD
Unused Op Amps.
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
4.9
4.9.2
Application Circuits
4.9.1
BATTERY CURRENT SENSING
The MCP6141/2/3/4 op amps’ Common Mode Input
Range, which goes 0.3V beyond both supply rails, supports their use in high side and low side battery current
sensing applications. The very low quiescent current
(0.6 μA, typ.) help prolong battery life, and the
rail-to-rail output supports detection low currents.
Figure 4-9 shows a high side battery current sensor
circuit. The 1 kΩ resistor is sized to minimize power
losses. The battery current (IDD) through the 1 kΩ
resistor causes its top terminal to be more negative
than the bottom terminal. This keeps the Common
mode input voltage of the op amp at VDD, which is
within its allowed range. When no current is flowing, the
output will be at its Maximum Output Voltage Swing
(VOH), which is virtually at VDD.
INVERTING SUMMING AMPLIFIER
The MCP6141/2/3/4 op amp is well suited for the
inverting summing amplifier shown in Figure 4-10
when the resistors at the input (R1, R2, and R3) make
the noise gain at least 10 V/V. The output voltage
(VOUT) is a weighted sum of the inputs (V1, V2, and V3),
and is shifted by the VREF input. The necessary
calculations follow in Equation 4-3.
.
R1
V1
R2
V2
R3
RF
VOUT
V3
MCP614X
VREF
.
VDD
VDD
FIGURE 4-10:
Summing Amplifier.
VOUT
MCP6141
IDD
1 kΩ
100 kΩ
1.4V to
5.5V
VSS
1 MΩ
VSS
FIGURE 4-9:
Sensor.
High Side Battery Current
EQUATION 4-3:
Noise Gain:
1- + ----1- + ----1-⎞ ≥ 10 V/V
GN = 1 + R F ⎛ ----⎝R
R
R ⎠
1
2
3
Signal Gains:
G1 = – R F ⁄ R 1
G2 = – R F ⁄ R 2
G3 = – R F ⁄ R 3
Output Signal:
VOUT = V1 G 1 + V2 G 2 + V 3 G 3 + V REF G N
© 2005 Microchip Technology Inc.
DS21668B-page 15
MCP6141/2/3/4
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6141/2/3/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6141/2/3/4
op amps is available on our web site at www.microchip.com. This model is intended to be an initial design
tool that works well in the op amp’s linear region of
operation at room temperature. See the model file for
information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
The FilterLab software is an innovative tool that
simplifies analog active filter (using op amps) design. It
is available free of charge from our web site at
www.microchip.com. The FilterLab software tool
provides full schematic diagrams of the filter circuit with
component values. It also outputs the filter circuit in
SPICE format, which can be used with the macro
model to simulate actual filter performance.
DS21668B-page 16
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
5-Lead SOT-23 (MCP6141)
Device
XXNN
MCP6141
E-Temp Code
ASNN
Note: Applies to 5-Lead SOT-23
Example:
6-Lead SOT-23 (MCP6143)
Device
XXNN
8-Lead MSOP
MCP6143
E-Temp Code
AWNN
Note: Applies to 6-Lead SOT-23
AW25
Example:
XXXXXX
6143I
YWWNNN
536256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
AS25
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2005 Microchip Technology Inc.
DS21668B-page 17
MCP6141/2/3/4
Package Marking Information (Continued)
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
YYWW
MCP6141
I/P256
0223
8-Lead SOIC (150 mil)
MCP6141
E/P e3 256
0536
Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6142
I/SN0223
256
OR
MCP6142E
SN e3 0536
256
Example:
14-Lead PDIP (300 mil) (MCP6144)
MCP6144-I/P
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
0434256
OR
DS21668B-page 18
OR
MCP6144
I/P e3
0536256
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6144)
Example:
MCP6144ISL
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
0434256
MCP6144
e3
I/SL^^
0536256
OR
Example:
14-Lead TSSOP (MCP6144)
XXXXXXXX
YYWW
6144ST
0534
NNN
256
OR
6144EST
0534
256
© 2005 Microchip Technology Inc.
DS21668B-page 19
MCP6141/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
E
E1
p
B
p1
n
D
1
α
c
A
φ
L
β
A1
INCHES*
Units
Dimension Limits
MIN
MILLIMETERS
NOM
MAX
Pitch
n
p
.038
Outside lead pitch (basic)
p1
.075
Number of Pins
Overall Height
A2
MIN
NOM
5
MAX
5
0.95
1.90
A
.035
.046
.057
0.90
1.18
1.45
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
L
f
.014
.018
.022
0.35
Foot Angle
Lead Thickness
c
.004
Lead Width
B
a
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
b
0
5
10
0.45
0
0.55
5
.006
.008
0.09
0.15
.017
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-091
DS21668B-page 20
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
E
E1
B
p1
n
D
1
α
c
φ
β
A
A1
L
INCHES*
Units
Dimension Limits
A2
MIN
MILLIMETERS
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
.038 BSC
Outside lead pitch
p1
.075 BSC
Overall Height
A
.035
.046
.057
0.90
1.18
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
L
φ
.014
.022
0.35
Foot Angle
Lead Thickness
c
.004
Lead Width
B
α
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
β
Number of Pins
6
0.95 BSC
1.90 BSC
.018
0
6
5
.006
.017
10
1.45
0.45
0
0.55
5
.008
0.09
0.15
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (formerly EIAJ) equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-120
© 2005 Microchip Technology Inc.
DS21668B-page 21
MCP6141/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
c
φ
L
F
A2
A
A1
β
Units
Dimension Limits
INCHES
MILLIMETERS*
NOM
MIN
MIN
MAX
NOM
MAX
Pitch
n
p
Overall Height
A
-
-
.043
-
-
1.10
Molded Package Thickness
A2
.030
.033
.037
0.75
0.85
0.95
Standoff
A1
.000
-
.006
0.00
-
0.15
Overall Width
E
.193 BSC
4.90 BSC
Molded Package Width
E1
.118 BSC
3.00 BSC
Overall Length
D
.118 BSC
Foot Length
L
0.60
0.80
Footprint (Reference)
Foot Angle
F
φ
Lead Thickness
c
.003
.006
.009
0.08
-
0.23
Lead Width
B
α
.009
.012
.016
0.22
-
0.40
Mold Draft Angle Top
Mold Draft Angle Bottom
β
Number of Pins
8
8
.026 BSC
.016
0.65 BSC
3.00 BSC
.024
.031
0.40
.037 REF
0°
0.95 REF
-
8°
0°
-
8°
5°
-
15°
5°
-
15°
5°
-
15°
5°
-
15°
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-187
Drawing No. C04-111
DS21668B-page 22
Revised 07-21-05
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
INCHES*
NOM
8
.100
.155
.130
MAX
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MAX
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
4.32
Molded Package Thickness
A2
.115
.145
3.68
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
8.26
Molded Package Width
E1
.240
.250
.260
6.60
Overall Length
D
.360
.373
.385
9.78
Tip to Seating Plane
L
.125
.130
.135
3.43
c
Lead Thickness
.008
.012
.015
0.38
Upper Lead Width
B1
.045
.058
.070
1.78
Lower Lead Width
B
.014
.018
.022
0.56
Overall Row Spacing
§
eB
.310
.370
.430
10.92
α
Mold Draft Angle Top
5
10
15
15
β
Mold Draft Angle Bottom
5
10
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2005 Microchip Technology Inc.
MIN
MIN
DS21668B-page 23
MCP6141/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
INCHES*
NOM
8
.100
.155
.130
MAX
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MAX
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
4.32
Molded Package Thickness
A2
.115
.145
3.68
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
8.26
Molded Package Width
E1
.240
.250
.260
6.60
Overall Length
D
.360
.373
.385
9.78
Tip to Seating Plane
L
.125
.130
.135
3.43
c
Lead Thickness
.008
.012
.015
0.38
Upper Lead Width
.045
.058
.070
1.78
B1
Lower Lead Width
B
.014
.018
.022
0.56
eB
Overall Row Spacing
§
.310
.370
.430
10.92
α
Mold Draft Angle Top
5
10
15
15
β
Mold Draft Angle Bottom
5
10
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21668B-page 24
MIN
MIN
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
14-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
Dimension Limits
n
p
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MAX
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
4.32
Molded Package Thickness
A2
.115
.145
3.68
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
8.26
Molded Package Width
.240
.250
.260
6.60
E1
Overall Length
D
.740
.750
.760
19.30
Tip to Seating Plane
L
.125
.130
.135
3.43
c
Lead Thickness
.008
.012
.015
0.38
Upper Lead Width
B1
.045
.058
.070
1.78
Lower Lead Width
B
.014
.018
.022
0.56
Overall Row Spacing
§
eB
.310
.370
.430
10.92
α
Mold Draft Angle Top
5
10
15
15
β
5
10
15
15
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
© 2005 Microchip Technology Inc.
MIN
MIN
DS21668B-page 25
MCP6141/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil Body (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
L
A1
β
Units
Dimension Limits
n
p
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.053
.069
1.75
Molded Package Thickness
A2
.052
.061
1.55
Standoff
§
A1
.004
.010
0.25
Overall Width
E
.228
.244
6.20
Molded Package Width
E1
.150
.157
3.99
Overall Length
D
.337
.347
8.81
Chamfer Distance
h
.010
.020
0.51
Foot Length
L
.016
.050
1.27
φ
Foot Angle
0
8
8
c
Lead Thickness
.008
.010
0.25
Lead Width
B
.014
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
DS21668B-page 26
MIN
MIN
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP)
E
E1
p
D
2
1
n
B
α
A
φ
c
β
L
Units
Dimension Limits
A1
A2
MILLIMETERS*
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
Overall Height
A
.039
.041
.043
1.00
1.05
1.10
Molded Package Thickness
A2
.033
.035
.037
0.85
0.90
0.95
Standoff
A1
.002
.004
.006
0.05
0.10
0.15
Overall Width
E
.246
.251
.256
6.25
6.38
6.50
Number of Pins
14
14
.026 BSC
0.65 BSC
Molded Package Width
E1
.169
.173
.177
4.30
4.40
4.50
Molded Package Length
D
.193
.197
.201
4.90
5.00
5.10
Foot Length
.020
.024
.028
0.50
0.60
0.70
Foot Angle
L
φ
Lead Thickness
c
.004
Lead Width
B
α
.007
Mold Draft Angle Top
Mold Draft Angle Bottom
β
4°
0°
8°
0°
.006
.008
0.09
.010
.012
0.19
4°
8°
0.15
0.20
0.25
0.30
12° REF
12° REF
12° REF
12° REF
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
© 2005 Microchip Technology Inc.
Revised: 08-17-05
DS21668B-page 27
MCP6141/2/3/4
NOTES:
DS21668B-page 28
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
APPENDIX A:
REVISION HISTORY
Revision B (November 2005)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
7.
8.
Added the following:
a) SOT-23-5 package for the MCP6141 single
op amps.
b) SOT-23-6 package for the MCP6143 single
op amps with Chip Select.
c) Extended Temperature (-40°C to +125°C)
op amps.
Updated specifications in Section 1.0 “Electrical Characteristics” for E-temp parts.
Corrected and updated plots in Section 2.0
“Typical Performance Curves”.
Added Section 3.0 “Pin Descriptions”.
Updated Section 4.0 “Applications Information” and added section on unused op amps.
Updated Section 5.0 “Design Tools” to
include FilterLab.
Added SOT-23-5 and SOT-23-6 packages and
corrected package marking information in
Section 6.0 “Packaging Information”.
Added Appendix A: “REVISION HISTORY”.
Revision A (September 2002)
• Original Release of this Document.
© 2005 Microchip Technology Inc.
DS21668B-page 29
MCP6141/2/3/4
NOTES:
DS21668B-page 30
© 2005 Microchip Technology Inc.
MCP6141/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
-X
Temperature
Range
MCP6141:
MCP6141T:
MCP6142:
MCP6142T:
MCP6143:
MCP6143T:
MCP6144:
MCP6144T:
/ XX
Package
Single Op Amp
Single Op Amp
(Tape and Reel for SOT-23, SOIC, MSOP)
Dual Op Amp
Dual Op Amp
(Tape and Reel for SOIC and MSOP)
Single Op Amp w/ CS
Single Op Amp w/ CS
(Tape and Reel for SOT-23, SOIC, MSOP)
Quad Op Amp
Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
Temperature
Range:
I
E
= -40°C to +85°C (Industrial)
= -40°C to +125°C (Extended)
Package:
CH
= Plastic Small Outline Transistor (SOT-23),
6-lead (Tape and Reel - MCP6143 only)
= Plastic Micro Small Outline (MSOP), 8-lead
= Plastic Small Outline Transistor (SOT-23),
5-lead (Tape and Reel - MCP6141 only)
= Plastic DIP (300 mil Body), 8-lead, 14-lead
= Plastic SOIC (150 mil Body), 14-lead
= Plastic SOIC (150 mil Body), 8-lead
= Plastic TSSOP (4.4 mm Body), 14-lead
MS
OT
P
SL
SN
ST
© 2005 Microchip Technology Inc.
Examples:
a)
MCP6141-I/P:
b)
MCP6141T-E/OT:
a)
MCP6142-I/SN:
b)
MCP6142T-E/MS:
a)
MCP6143-I/P:
b)
MCP6143T-E/CH:
a)
MCP6144-I/SL:
b)
MCP6144T-E/ST:
Industrial Temp.,
8LD PDIP package.
Tape and Reel,
Extended Temp.,
5LD SOT-23 package.
Industrial Temp.,
8LD SOIC package.
Tape and Reel,
Extended Temp.,
8LD MSOP package.
Industrial Temp.,
8LD PDIP package.
Tape and Reel,
Extended Temp.,
6LD SOT-23 package.
Industrial Temp.,
14LD PDIP package.
Tape and Reel,
Extended Temp.,
14LD TSSOP package.
DS21668B-page 31
MCP6141/2/3/4
NOTES:
DS21668B-page 32
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,
Smart Serial, SmartTel, Total Endurance and WiperLock are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21668B-page 33
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
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Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
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Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
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Tel: 43-7242-2244-399
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Tel: 45-4450-2828
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Fax: 60-4-646-5086
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
10/31/05
DS21668B-page 34
© 2005 Microchip Technology Inc.