ISO7421E-Q1 www.ti.com SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 Low-Power Dual Digital Isolators Check for Samples: ISO7421E-Q1 FEATURES DESCRIPTION • • The ISO7421E-Q1 provides double galvanic isolation of up to 2.5 KVrms for 1 minute per UL. This digital isolator has two isolation channels in a bi-directional configuration. Each isolation channel has a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. 1 • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified with the following results: – Device Temperature Grade 1: -40°C to +125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H3A – Device CDM ESD Classification Level C4 Propagation Delay Less Than 20 ns Low Power Consumption Wide Ambient Temperature: –40°C to 125°C Safety and Regulatory Approvals – 4 kV peak Maximum Isolation, 2.5 kVrms per UL 1577, IEC/VDE and CSA Approved, IEC 60950-1, IEC 61010-1 End Equipment Standards Approved. All Approvals Pending. 50 kV/µs Transient Immunity Typical Operates From 3.3 V or 5 V Supply and Logic Levels APPLICATIONS • Opto-Coupler Replacement in: – Servo Control Interface – Motor Control – Power Supply – Battery Packs The devices have TTL input thresholds and require two supply voltages, 3.3 V or 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply. Note: The ISO7421E-Q1 is specified for signaling rates up to 50 Mbps. Due to their fast response time, under most cases, these devices will also transmit data with much shorter pulse widths. Designers should add external filtering to remove spurious signals with input pulse duration < 20 ns if desired. ISO7421E-Q1 GND1 NC VCC1 OUTA INB NC GND1 NC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND2 NC VCC2 INA OUTB NC NC GND2 NC = No Internal Connection 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated ISO7421E-Q1 SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. PIN DESCRIPTIONS PIN NAME I/O ISO7421E-Q1 DESCRIPTION INA 13 I Input, channel A INB 5 – Input, channel B GND1 1, 7 – Ground connection for VCC1 GND2 9, 16 O Ground connection for VCC2 OUTA 4 O Output, channel A OUTB 12 – Output, channel B VCC1 14 – Power supply, VCC1 VCC2 14 - Power supply, VCC2 NC 2, 6, 8, 10, 11, 15 No Connect Pin DEVICE FUNCTION TABLE INPUT SIDE (VCC) (1) OUTPUT SIDE (VCC) (1) PU PU PD (1) INPUT (IN) (1) OUTPUT (OUT) (1) H H PU L L Open H X H PU = Powered Up (VCC ≥ 3.15V); PD = Powered Down (VCC ≤ 2.4V); X = Irrelevant; H = High Level; L = Low Level AVAILABLE OPTIONS PRODUCT RATED TA MARKED AS ORDERING NUMBER ISO7421E-Q1 –40°C to 125°C ISO7421EQ ISO7421EQDWRQ1 ABSOLUTE MAXIMUM RATINGS (1) VALUE MAX 6 VCC Supply voltage (2), VCC1, VCC2 –0.5 VI Voltage at IN, OUT –0.5 IO Output Current ESD Electrostatic discharge TJ Maximum junction temperature (1) (2) 2 Human Body Model AEC-Q100 Classification Level H3A Charged Device Model AEC-Q100 Classification Level C4 All pins UNIT MIN V 6 V ±15 mA 4 kV 1 kV 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 ISO7421E-Q1 www.ti.com SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 THERMAL INFORMATION ISO7421E-Q1 THERMAL METRIC (1) UNITS DW (16 Pins) θJA Junction-to-ambient thermal resistance 79.9 θJCtop Junction-to-case (top) thermal resistance 44.6 θJB Junction-to-board thermal resistance 51.2 ψJT Junction-to-top characterization parameter 18.0 ψJB Junction-to-board characterization parameter 42.2 θJCbot Junction-to-case (bottom) thermal resistance n/a PD Device power dissipation, Vcc1 = Vcc2 = 5.25 V, TJ = 150°C, CL = 15 pF, Input a 0.5 MHz 50% duty cycle square wave 42 °C/W mW spacer (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC1, VCC2 MIN TYP MAX UNIT Supply voltage - 3.3V Operation 3.15 3.3 3.45 V Supply voltage - 5V Operation 4.75 5 5.25 IOH High-level output current IOL Low-level output current VIH High-level output voltage 2 VCC VIL Low-level output voltage 0 0.8 V TA Ambient Temperature -40 125 °C TJ (1) Junction temperature –40 136 °C 1/tui Signaling rate 0 50 Mbps tui Input pulse duration 1 (1) –4 mA 4 mA V µs To maintain the recommended operating conditions for TJ, see the Package Thermal Characteristics table and the Icc Equations section of this data sheet Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 3 ISO7421E-Q1 SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP IOH = –4 mA; See Figure 1 VCC –0.8 4.6 IOH = –20 µA; See Figure 1 VCC –0.1 5 MAX V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 400 –10 VI = VCC or 0 V; See Figure 3 25 V mV 10 INx at 0 V or VCC UNIT µA µA 50 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 0.4 0.8 AC Input: CL = 15 pF 3.4 5 0.6 1 4.5 6 1 1.5 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 6.2 8 1.7 2.5 9 12 DC Input: VI = VCC or 0 V 2.3 3.6 AC Input: CL = 15 pF 2.3 3.6 2.9 4.5 2.9 4.5 4.3 6 50 Mbps ICC2 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA 4.3 6 6 9.1 6 9.1 TYP MAX 9 14 ns 0.3 SWITCHING CHARACTERISTICS VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 125°C PARAMETER tPLH, tPHL PWD (1) TEST CONDITIONS Propagation delay time See Figure 1 UNIT 3.7 ns tsk(pp) Part-to-part skew time 4.9 ns tsk(o) Channel-to-channel output skew time 3.6 ns tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) 4 Pulse width distortion |tPHL – tPLH| MIN See Figure 1 See Figure 2 1 ns 1 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 ISO7421E-Q1 www.ti.com SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP 5-V side VCC –0.8 4.6 3.3-V side VCC –0.4 3 IOH = –20 µA; See Figure 1 VCC –0.1 VCC IOH = –4 mA; See Figure 1 MAX UNIT V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 V 400 mV 10 INx at 0 V or VCC µA –10 VI = VCC or 0 V; See Figure 3 25 µA 40 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 0.4 0.8 AC Input: CL = 15 pF 2.6 3.7 0.6 1 3.3 4.3 1 1.5 4.4 5.6 1.7 2.5 6.2 7.5 DC Input: VI = VCC or 0 V 2.3 3.6 AC Input: CL = 15 pF 1.8 2.8 2.9 4.5 2.2 3.2 4.3 6 2.8 4.1 6 9.1 3.8 5.8 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA SWITCHING CHARACTERISTICS VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 125°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) See Figure 1 See Figure 1 See Figure 2 MIN TYP MAX UNIT 10 17 ns 0.5 5.6 ns 6.3 ns 4 ns 2 ns 2 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 5 ISO7421E-Q1 SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP 5-V side VCC –0.8 4.6 3.3-V side VCC –0.4 3 IOH = –20 µA; See Figure 1 VCC –0.1 VCC IOH = –4 mA; See Figure 1 MAX V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 400 –10 VI = VCC or 0 V; See Figure 3 25 V mV 10 INx at 0 V or VCC UNIT µA µA 40 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 0.2 AC Input: CL = 15 pF 3.4 5 0.4 0.6 10 Mbps ICC2 4.5 6 0.6 0.9 6.2 8 1 1.3 9 12 DC Input: VI = VCC or 0 V 1.8 2.8 AC Input: CL = 15 pF 2.3 3.6 2.2 3.2 2.9 4.5 2.8 4.1 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 0.4 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA 4.3 6 3.8 5.8 6 9.1 TYP MAX 10 17 ns 0.5 4 ns 8.5 ns 4 ns SWITCHING CHARACTERISTICS VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 125°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) 6 See Figure 1 See Figure 1 See Figure 2 MIN 2 UNIT ns 2 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 ISO7421E-Q1 www.ti.com SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP IOH = –4 mA; See Figure 1 VCC –0.4 3 IOH = –20 µA; See Figure 1 VCC –0.1 3.3 MAX UNIT V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 V 400 mV µA INx at 0 V or VCC –10 VI = VCC or 0 V; See Figure 3 25 µA 40 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 0.2 0.4 AC Input: CL = 15 pF 2.6 3.7 0.4 0.6 3.3 4.3 0.6 0.9 4.4 5.6 1 1.3 6.2 7.5 DC Input: VI = VCC or 0 V 1.8 2.8 AC Input: CL = 15 pF 1.8 2.8 2.2 3.2 2.2 3.2 2.8 4.1 2.8 4.1 3.8 5.8 3.8 5.8 TYP MAX 12 20 ns 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 125°C PARAMETER tPLH, tPHL PWD (1) TEST CONDITIONS Propagation delay time See Figure 1 1 UNIT 5 ns tsk(pp) Part-to-part skew time 6.8 ns tsk(o) Channel-to-channel output skew time 5.5 ns tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) Pulse width distortion |tPHL – tPLH| MIN See Figure 1 See Figure 2 2 ns 2 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 7 ISO7421E-Q1 SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W VCC1 VI 1.4V 1.4V OUT 0V t PHL tPLH VO CL VOH 90% NOTE B NOTE A Vcc/2 VO 10% tf tr Vcc/2 VOL A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3ns, tf ≤ 3ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI Vcc1 ISOLATION BARRIER Vcc1 0V IN or Vcc1 2.7 V VI OUT VO 0V tfs CL VO VOH 50% FAILSAFE HIGH VOL NOTE B A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms IN S1 C = 0.1 µF +1 % ISOLATION BARRIER V CC1 GND 1 V CC2 C = 0.1 µ F +1 % Pass-fail criteria – output must remain stable . OUT NOTE B V OH or V OL GND 2 V CM A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 ISO7421E-Q1 www.ti.com SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 DEVICE INFORMATION PACKAGE CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal to terminal distance through air 8.34 mm L(I02) Minimum external tracking (Creepage) Shortest terminal to terminal distance across the package surface 8.1 mm CTI Tracking resistance (Comparative Tracking DIN IEC 60112 / VDE 0303 Part 1 Index) ≥400 V Minimum internal gap (Internal Clearance) Distance through the insulation 0.014 mm RIO Isolation resistance, input to output (1) Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device CIO Barrier capacitance input to output (1) CI Input capacitance to ground (2) (1) (2) >1012 Ω VIO = 0.4 sin(2πft), f = 1 MHz 2 pF VI = VCC/2 + 0.4 sin(2πft), f = 1 MHz, VCC = 5 V 2 pF All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. empty para for space above the NOTE NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. IEC 60664-1 RATINGS TABLE PARAMETER Basic Isolation Group Installation Classification TEST CONDITIONS Material Group SPECIFICATION II Rated mains voltages <= 150 Vrms I - IV Rated mains voltages <= 300 Vrms I - IV Rated mains voltages <= 400 Vrms I - III Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 9 ISO7421E-Q1 SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 www.ti.com INSULATION CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIORM VPR TEST CONDITIONS SPECIFICATION UNIT 1414 Vpeak Maximum working insulation voltage Input to output test voltage VIOTM Transient overvoltage VISO Isolation voltage per UL RS Insulation resistance Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial discharge < 5 pC 2262 Method b1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC 2651 After Input/Output Safety Test Subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 1697 t = 60 sec (qualification) 4242 VTEST = VISO, t = 60 sec (qualification) 2500 t = 1 sec (100% production) 3000 VTEST = 500 V at TS = 150°C >109 Pollution degree Vpeak Vpeak Vrms Ω 2 REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice Recognized under 1577 Component Recognition Program File Number: pending File Number: pending File Number: E181974 IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER Is Safety input, output, or supply current Ts Maximum Case Temperature TEST CONDITIONS MIN TYP MAX θJA =212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C 112 θJA =212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C 171 150 UNIT mA °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 ISO7421E-Q1 www.ti.com SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 Safety Limiting Current - mA 500 VCC1 and VCC2 at 3.45 V 400 300 VCC1 and VCC2 at 5.25 V 200 100 0 0 50 100 150 200 250 Case Temperature - °C Figure 4. DW-16 Theta-JC Thermal Derating Curve per IEC 60747-5-2 GND1 0.1? F 2 mm max. from VCC1 NC VCC1 OUTA INB NC GND1 NC GND2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC 0.1? F 2 mm max. from VCC2 VCC2 INA OUTB NC NC GND2 ISO7421E-Q1 Figure 5. Typical ISO7421E-Q1 Application Circuit EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS Figure 6. I/O Schematic Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 11 ISO7421E-Q1 SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS INPUT VOLTAGE SWITCHING THRESHOLD vs FREE-AIR TEMPERATURE FAIL-SAFE VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE 2.62 VIT+, 5 V 1.5 Fail-Safe Voltage Threshold − V Input Voltage Switching Threshold − V 1.6 1.4 VIT+, 3.3 V 1.3 1.2 1.1 VIT−, 5 V 1.0 VIT−, 3.3 V 0.9 0.8 −55 −35 −15 5 25 45 65 85 105 TA − Free-Air Temperature − °C FS+ 2.60 2.59 2.58 2.57 2.56 2.55 FS− 2.54 2.53 2.52 −55 125 −35 5 25 45 65 85 105 G005 125 G006 Figure 7. Figure 8. HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 80 IOL − Low-Level Output Current − mA TA = 25°C −10 −20 −30 −40 VCC1, VCC2 at 3.3 V −50 −60 −70 VCC1, VCC2 at 5 V −80 −90 TA = 25°C 70 60 VCC1, VCC2 at 5 V 50 40 VCC1, VCC2 at 3.3 V 30 20 10 0 0 1 2 3 4 5 VOH − High-Level Output Voltage − V 6 0 G007 Figure 9. 12 −15 TA − Free-Air Temperature − °C 0 IOH − High-Level Output Current − mA 2.61 1 2 3 4 VOL − Low-Level Output Voltage − V 5 6 G008 Figure 10. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 ISO7421E-Q1 www.ti.com SLLSEA5B – MARCH 2012 – REVISED JUNE 2012 REVISION HISTORY Changes from Revision A (March 2012) to Revision B Page • Changed signaling rate info from 1 to 50 Mbps. ................................................................................................................... 1 • Changed Signaling rate max value from 1 to 50 Mbps, centered 0 in the min column. ....................................................... 3 • Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, changed 8.5 max value to 9.1. .......................................................................................................................................................................... 4 • Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, changed 8.5 max value to 9.1 and changed 5.5 max value to 5.8. ................................................................................................................... 5 • Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, changed 5.5 max value to 5.8 and changed 8.5 max value to 9.1. ................................................................................................................... 6 • Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, changed 5.5 max value to 5.8. .......................................................................................................................................................................... 7 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ISO7421E-Q1 13 PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2012 PACKAGING INFORMATION Orderable Device ISO7421EQDWRQ1 Status (1) Package Type Package Drawing ACTIVE SOIC DW Pins Package Qty 16 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ISO7421E-Q1 : • Catalog: ISO7421E NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ISO7421EQDWRQ1 Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7421EQDWRQ1 SOIC DW 16 2000 533.4 186.0 36.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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