Ultralow Power +3.3 V, RS-232 Notebook PC Serial Port Drivers/Receivers ADM560/ADM561 FUNCTIONAL BLOCK DIAGRAM FEATURES +3.3V INPUT CMOS INPUTS CMOS OUTPUTS 12 C1+ 14 C1– 15 C2+ 16 C2– +3.3V TO +6.6V VOLTAGE DOUBLER VCC 11 +6.6V TO –6.6V VOLTAGE INVERTER V– 17 V+ 13 C3 1µF 6.3V C4 1µF 10V 0.1µF T1IN 7 T1 2 T1OUT T2IN 6 T2 3 T2OUT T3IN 20 T3 1 T3OUT T4IN 21 T4 28 T4OUT R1OUT 8 R1 9 R1IN R2OUT 5 R2 4 R2IN R3OUT 26 R3 27 R3IN R4OUT 22 R4 23 R4IN R5OUT 19 R5 18 R5IN 25 SHDN (ADM560) SHDN (ADM561) EN (ADM560) EN (ADM561) 24 GND 10 ADM560/ ADM561 EIA/TIA-232 OUTPUTS EIA/TIA-232 INPUTS 05667-001 1µF + 10V APPLICATIONS Notebook computers Peripherals Modems Printers Battery-operated equipment + + 1µF 10V + RS-232 compatible Operates with 3 V or 5 V logic Ultralow power CMOS: 1.3 mA operation Low power shutdown: 0.2 μA Suitable for serial port mice 116 kbps data rate 1 μF charge pump capacitors Single +3 V to +3.6 V power supply Two receivers active in shutdown (ADM560) Figure 1. GENERAL DESCRIPTION The ADM560/ADM561 are four driver/five receiver interface devices designed to meet the EIA-232 standard and operate with a single +3.3 V power supply. The devices feature an on-board dc-to-dc converter, eliminating the need for dual ±5 V power supplies. This dc-to-dc converter contains a voltage doubler and voltage inverter, both of which internally generate ±6.6 V from the input +3.3 V power supply. device begins communication. The active receivers alert the processor, and then take the ADM560 out of shutdown mode. The ADM561 features active high shutdown and an active low receiver enable. In this device, all receivers are disabled in shutdown. The ADM560 and the ADM561 consume only 5 mW making them ideally suited for battery and other power-sensitive applications. A shutdown facility is also provided to reduce the power to 0.66 μW. The ADM560/ADM561 are fabricated using CMOS technology for minimal power consumption. They feature a high level of over-voltage protection and latch-up immunity. The receiver inputs can withstand up to ±25 V levels. The transmitter inputs can be driven from either 3 V or 5 V logic levels. This allows operation in mixed 3 V/5 V power supply systems. The ADM560 contains active low shutdown and an active high receiver enable signal. In shutdown mode, two receivers remain active, thereby allowing monitoring of peripheral devices. This feature allows the device to be shut down until a peripheral The ADM560/ADM561 are packaged in a 28-lead SOIC and a 28-lead SSOP package. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADM560/ADM561 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................5 Applications....................................................................................... 1 Typical Performance Characteristics ..............................................6 Functional Block Diagram .............................................................. 1 Theory of Operation .........................................................................8 General Description ......................................................................... 1 Circuit Description .......................................................................8 Revision History ............................................................................... 2 Enable and Shutdown ...................................................................8 Specifications..................................................................................... 3 Outline Dimensions ..........................................................................9 Absolute Maximum Ratings............................................................ 4 Ordering Guide .......................................................................... 10 ESD Caution.................................................................................. 4 REVISION HISTORY 9/06—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Specifications ................................................................ 3 10/05—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Specifications ................................................................ 3 Update to Outline Dimensions....................................................... 9 Changes to Ordering Guide .......................................................... 10 7/94—Revision 0: Initial Version Rev. B | Page 2 of 12 ADM560/ADM561 SPECIFICATIONS VCC = +3.3 V ± 10%, C1 to C4 = 1 μF, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter Output Voltage Swing Min ±5.0 ±4 VCC Power Supply Current Shutdown Supply Current Input Logic Threshold Low, VINL Input Logic Threshold High, VINH Logic Pull-Up Current EIA-232 Input Voltage Range EIA-232 Input Threshold Low EIA-232 Input Threshold High EIA-232 Input Hysteresis EIA-232 Input Resistance CMOS Output Voltage Low, VOL CMOS Output Voltage High, VOH CMOS Output Leakage Current Output Enable Time Output Disable Time Receiver Propagation Delay TPHL TPLH Transition Region Slew Rate Transmitter Output Resistance RS-232 Output Short-Circuit Current Typ ±5.5 ±4.5 3.5 3.5 0.2 Max 5 5 5 0.4 2.4 3 –25 0.4 3 0.8 1.1 0.3 5 20 +25 2.4 7 0.4 2.8 +0.05 100 50 ±5 0.1 0.5 4.5 1 2 300 ±10 Unit V V mA mA μA V V μA V V V V kΩ V V μA ns ns μs μs V/μs Ω mA Test Conditions/Comments VCC = 3.3 V, three transmitter outputs loaded with 3 kΩ to ground VCC = 3.0 V, all transmitter outputs, loaded with 3 kΩ to ground No load, TIN = VCC No load, TIN = GND SHDN = GND (ADM560), SHDN = VCC (ADM561), TIN = VCC TIN, EN, EN , SHDN, SHDN TIN, EN, EN, SHDN, SHDN TIN = GND IOUT = 1.6 mA IOUT = −40 mA EN = VCC, EN = GND, 0 V ≤ ROUT ≤ VCC RL = 3 kΩ, CL = 2500 pF measured from +3 V to −3 V or −3 V to +3 V VCC = V+ = V− = 0 V, VOUT = ±2 V Rev. B | Page 3 of 12 ADM560/ADM561 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VCC V+ V− Input Voltages TIN RIN Output Voltages TOUT ROUT Short-Circuit Duration TOUT Power Dissipation SSOP SOIC Operating Temperature Range Commercial (J Version) Storage Temperature Range Lead Temperature (Soldering, 10 sec) ESD Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.3 V to +6 V (VCC − 0.3 V) to +14 V +0.3 V to −14 V −0.3 V to (V+, +0.3 V) 25 V (V+, +0.3 V) to (V−, −0.3 V) −0.3 V to (VCC + 0.3 V) Continuous 900 mW 900 mW 0°C to +70°C −65°C to +150°C +300°C >2000 V ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 4 of 12 ADM560/ADM561 T3OUT 1 28 T4OUT T3OUT 1 28 T4OUT T1OUT 2 27 R3IN T1OUT 2 27 R3IN T2OUT 3 26 R3OUT T2OUT 3 26 R3OUT R2IN 4 25 SHDN R2IN 4 25 SHDN 24 EN 24 EN 23 R4IN T2IN 6 23 R4IN T1IN 7 22 R4OUT T1IN 7 22 R4OUT R1OUT 8 21 T4IN R1OUT 8 21 T4IN R1IN 9 20 T3IN R1IN 9 20 T3IN GND 10 19 R5OUT GND 10 19 R5OUT VCC 11 18 R5IN VCC 11 18 R5IN C1+ 12 17 V– C1+ 12 17 V– V+ 13 16 C2– V+ 13 16 C2– C1– 14 15 C2+ C1– 14 15 C2+ T2IN 6 ADM560 TOP VIEW (Not to Scale) R2OUT 5 05667-002 R2OUT 5 Figure 2.ADM560 Pin Configuration ADM561 TOP VIEW (Not to Scale) 05667-012 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. ADM561 Pin Configuration Table 3. Pin Function Descriptions Pin No. 2, 3, 1, 28 9, 4, 27, 23, 18 Mnemonic T1OUT to T4OUT R1IN to R5IN 8, 5, 26, 22, 19 7, 6, 20, 21 R1OUT to R5OUT T1IN to T4IN 10 11 12, 14 13 15, 16 17 24 25 GND VCC C1+, C1− V+ C2+, C2− V− EN/EN SHDN/SHDN Description Transmitter (Driver) Outputs. Typically ±6 V. Receiver Inputs. These inputs accept RS-232 signal levels. An internal 5 kΩ pull-down resistor to GND is connected on each of these inputs. Receiver Outputs. These are 3 V logic levels. Transmitter (Driver) Inputs. These inputs accept 3 V or 5 V logic levels. An internal 400 kΩ pull-up resistor to VCC is connected on each input. Ground Pin. Must be connected to 0 V. Power Supply Input 3.3 V ± 10%. External Capacitor 1 is connected between these pins. Internally Generated Positive Supply. +6.6 V nominal. External Capacitor 2 is connected between these pins. Internally Generated Negative Supply. −6.6 V nominal. Receiver Enable. EN, active high on ADM560. EN, active low on ADM561. Refer to Table 4. Shutdown Control. SHDN, active low on ADM560. SHDN, active high on ADM561. Refer to Table 4. Table 4. ADM560/ADM561 Enable and Shutdown Control Normal Operation Shutdown Mode ADM560 SHDN = 1 EN = 1; receivers active EN = 0; receivers inactive ADM561 SHDN = 0 EN = 0; receivers active EN = 1; receivers inactive SHDN = 0 EN = 1; Receiver R1 to Receiver R3 inactive EN = 1; Receiver R4 and Receiver R5 active EN = 0; Receiver R1 to Receiver R5 inactive SHDN = 1 EN = 0; receivers inactive EN = 1; receivers inactive Rev. B | Page 5 of 12 ADM560/ADM561 TYPICAL PERFORMANCE CHARACTERISTICS 6 0 5 –1 160kbps 80kbps 20kbps –2 VOL (V) 3 TA = 25°C VCC = 3.3V 4 TRANSMITTERS LOADED WITH RL = 5kΩ || CL C1 TO C4 = 1µF 2 –3 –4 160kbps 1 80kbps 0 0 500 1000 1500 2000 2500 20kbps –6 3000 0 500 LOAD CAPACITANCE (pF) 1000 1500 2000 2500 3000 LOAD CAPACITANCE (pF) Figure 4. Transmitter Output Voltage High vs. Load Capacitance Figure 7. Transmitter Output Voltage Low vs. Load Capacitance 45 6.25 TA = 25°C C1 TO C4 = 1µF VCC = 3.3V TRANSMITTERS UNLOADED 40 35 SLEW RATE (V/µs) 5.75 | TOUT | (V) TOUT HIGH 5.25 TOUT LOW 30 25 20 15 3 TRANSMITTERS LOADED 05667-006 10 4.75 0 1 2 3 | IOUT | (mA) 4 5 4 TRANSMITTERS LOADED 0 500 1000 1500 2000 LOAD CAPACITANCE (pF) 5 Figure 5. Transmitter Output Voltage vs. Load Current 10.5 –3 9.5 –4 8.5 –5 1 TRANSMITTER LOADED VOL (V) 7.5 TA = 25°C C1 TO C4 = 1µF TRANSMITTERS LOADED WITH 5kΩ || 2500pF 6.5 5.5 2500 3000 Figure 8. Transmitter Slew Rate vs. Load Capacitance TA = 25°C C1 TO C4 = 1µF TRANSMITTERS LOADED WITH 5kΩ || 2500pF 4 TRANSMITTERS LOADED –6 –7 –8 1 TRANSMITTER LOADED 4 TRANSMITTERS LOADED 3.5 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 Figure 6. Transmitter Output Voltage High vs. VCC –9 –10 2.5 05667-010 4.5 05667-007 VOH (V) 05667-008 05667-005 –5 05667-009 VOH (V) 4 TA = 25°C VCC = 3.3V 4 TRANSMITTERS LOADED WITH RL = 5kΩ || CL C1 TO C4 = 1µF 3.0 3.5 4.0 VCC (V) 4.5 5.0 Figure 9. Transmitter Output Voltage Low vs. VCC Rev. B | Page 6 of 12 5.5 ADM560/ADM561 TA = 25°C VCC = 3.3V C1 TO C4 = 1µF ALL TRANSMITTERS UNLOADED 5 0 V+ AND V– EQUALLY LOADED V+ LOADED V– LOADED NO LOAD ON V– NO LOAD ON V+ –5 05667-011 OUTPUT VOLTAGE V+, V– (V) 10 –10 0 5 10 13 15 20 25 CURRENT (mA) Figure 10. V+, V− vs. Load Current Rev. B | Page 7 of 12 ADM560/ADM561 THEORY OF OPERATION The drivers convert 3 V or 5 V logic input levels into EIA-232 output levels. With VCC = +3.3 V and driving an EIA-232 load, the output voltage swing is typically ±5.5 V. • 3 V logic to EIA-232 transmitters. • EIA-232 to 3 V logic receivers. + V+ = 2VCC C3 S2 + S4 VCC GND INTERNAL OSCILLATOR Figure 11. Charge Pump Voltage Double Operation V+ S1 S3 C2 + S2 GND C4 + S4 GND The internal circuitry consists of three main sections. These are as follows: A charge pump voltage converter. S3 C1 FROM VOLTAGE DOUBLER CIRCUIT DESCRIPTION • S1 VCC 05667-003 The ADM560/ADM561 contain an internal voltage doubler and a voltage inverter that generates ±6.6 V from the +3.3 V input. Four external 1 μF capacitors are required for the internal voltage converters. Transmitter (Driver) Section V– = – (V+) INTERNAL OSCILLATOR 05667-004 The ADM560/ADM561 are RS-232 transmission line drivers/ receivers, and operate from a single +3.3 V supply. This is achieved by integrating step-up voltage converters and level shifting transmitters and receivers onto the same chip. CMOS technology is used to keep the power dissipation at an absolute minimum. The ADM560/ADM561 are a modification, enhancement, and improvement to the ADM241L family and its derivatives thereof. These devices are essentially plug-in compatible and do not have materially different applications. Figure 12. Charge Pump Voltage Inverted Operation Charge Pump DC-to-DC Voltage Converter The charge pump voltage converter consists of an oscillator and a switching matrix. The converter generates a ±6.6 V supply from the input +3.3 V level. This is done in two stages using a switched capacitor technique (see Figure 11 and Figure 12). First, the +3.3 V input supply is doubled to +6.6 V using Capacitor C1 as the charge storage element. The +6.6 V level is then inverted to generate −6.6 V using Capacitor C2 as the storage element. Capacitor C3 and Capacitor C4 are used to reduce the output ripple. Their values are not critical and can be reduced if higher levels of ripple are acceptable. The C1 and C2 charge pump capacitors can also be reduced at the expense of the higher output impedance on the V+ and V− supplies. The V+ and V− supplies are also used to power external circuitry if the current requirements are small. Unused inputs can be left unconnected as an internal 400 kΩ pull-up resistor pulls them high forcing the outputs into a low state. The input pull-up resistors typically source 8 μA when grounded, so connect unused inputs to VCC or leave unconnected in order to minimize power consumption. Receiver Section The receivers are inverting level shifters; they accept EIA-232 input levels and translate them into 3 V logic output levels. The inputs have internal 5 kΩ pull-down resistors to ground and are also protected against overvoltages of up to ±25 V. The guaranteed switching thresholds are 0.4 V minimum and 2.4 V maximum. Unconnected inputs are pulled to 0 V by the internal 5 kΩ pulldown resistor. This results in a Logic 1 output level for unconnected inputs or for inputs connected to GND. The receivers have a Schmitt trigger input with a hysteresis level of 0.3 V. This ensures error-free reception for both noisy inputs and for inputs with slow transition times. ENABLE AND SHUTDOWN Table 4 shows the truth table for the enable and shutdown control signals. When disabled all receivers are placed in a high impedance state. In shutdown, all transmitters are disabled and all receivers on the ADM561 are disabled. On the ADM560, Receiver R4 and Receiver R5 remain enabled in shutdown. Rev. B | Page 8 of 12 ADM560/ADM561 OUTLINE DIMENSIONS 10.50 10.20 9.90 15 28 5.60 5.30 5.00 1 8.20 7.80 7.40 14 0.25 0.09 1.85 1.75 1.65 0.05 MIN COPLANARITY 0.10 0.65 BSC 0.38 0.22 8° 4° 0° SEATING PLANE 0.95 0.75 0.55 060106-A 2.00 MAX COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 13. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969) 15 28 7.60 (0.2992) 7.40 (0.2913) 14 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 14. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches) Rev. B | Page 9 of 12 45° 1.27 (0.0500) 0.40 (0.0157) 060706-A 1 ADM560/ADM561 ORDERING GUIDE Model ADM560JR ADM560JR-REEL ADM560JRZ 1 ADM560JRZ-REEL1 ADM560JRS ADM560JRS-REEL ADM560JRSZ1 ADM560JRSZ-REEL1 ADM561JR ADM561JR-REEL ADM561JRZ1 ADM561JRZ-REEL1 ADM561JRS ADM561JRS-REEL ADM561JRSZ1 ADM561JRSZ-REEL1 1 Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C Package Description 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] Z = Pb-free part. Rev. B | Page 10 of 12 Package Option RW-28 RW-28 RW-28 RW-28 RS-28 RS-28 RS-28 RS-28 RW-28 RW-28 RW-28 RW-28 RS-28 RS-28 RS-28 RS-28 ADM560/ADM561 NOTES Rev. B | Page 11 of 12 ADM560/ADM561 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05667-0-9/06(B) Rev. B | Page 12 of 12