19-2827; Rev 0; 4/03 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters Features ♦ 1.0ps(RMS) Jitter (max) at 670MHz The MAX9174 has a fail-safe LVDS input and LVDS outputs. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs. The MAX9174 features a fail-safe circuit that drives the outputs high when the input is open, undriven and shorted, or undriven and terminated. The MAX9175 has a bias circuit that forces the outputs high when the input is open. The power-down inputs are compatible with standard LVTTL/LVCMOS logic. The power-down inputs tolerate undershoot of -1V and overshoot of VCC + 1V. The MAX9174/MAX9175 are available in 10-pin µMAX and 10-lead thin QFN with exposed pad packages, and operate from a single +3.3V supply over the -40°C to +85°C temperature range. ♦ Anything Input (MAX9175) Accepts Differential CML/LVDS/LVPECL Applications Protection Switching Loopback Clock Distribution ♦ 80ps(P-P) Jitter (max) at 800Mbps Data Rate ♦ +3.3V Supply ♦ LVDS Fail-Safe Inputs (MAX9174) ♦ Power-Down Inputs Tolerate -1.0V and VCC + 1.0V ♦ Low-Power CMOS Design ♦ 10-Lead µMAX and Thin QFN Packages ♦ -40°C to +85°C Operating Temperature Range ♦ Conform to ANSI TIA/EIA-644 LVDS Standard ♦ IEC 61000-4-2 Level 4 ESD Rating Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9174EUB -40°C to +85°C 10 µMAX MAX9174ETB* -40°C to +85°C 10 Thin QFN-EP** MAX9175EUB -40°C to +85°C 10 µMAX MAX9175ETB* -40°C to +85°C 10 Thin QFN-EP** *Future product—contact factory for availability. Functional Diagram and Pin Configurations appear at end of data sheet. **EP = Exposed paddle. Typical Application Circuit CLOCK DISTRIBUTION ASIC MAX9174 MAX9176 CLK IN CLK1 ASIC MAX9174 MAX9176 CLK IN CLK2 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9174/MAX9175 General Description The MAX9174/MAX9175 are 670MHz, low-jitter, lowskew 1:2 splitters ideal for protection switching, loopback, and clock and signal distribution. The devices feature ultra-low 1.0ps(RMS) random jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing errors. MAX9174/MAX9175 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters ABSOLUTE MAXIMUM RATINGS VCC to GND ..………………………………………...-0.3V to +4.0V IN+, IN- to GND...........................................……...-0.3V to +4.0V OUT_+, OUT_- to GND..........................................-0.3V to +4.0V PD0, PD1 to GND .......................................-1.4V to (VCC + 1.4V) Single-Ended and Differential Output Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70°C) 10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW 10-Lead QFN (derate 24.4mW/°C above +70°C) ......1951mW Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (RD = 1.5kΩ, CS = 100pF) IN+, IN-, OUT_+, OUT_-...............................................…±2kV Other Pins (VCC, PD0, PD1) ...............................................2kV IEC 61000-4-2 Level 4 (RD = 330Ω, CS = 150pF) Contact Discharge IN+, IN-, OUT_+, OUT_- ...................±8kV Air-Gap Discharge IN+, IN-, OUT_+, OUT_- .................±15kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, PD_ = high, differential input voltage |VID| = 0.05V to 1.2V, MAX9174 input common-mode voltage VCM = |VID /2| to (2.4V - |VID /2|), MAX9175 input common-mode voltage VCM = |VID /2| to (VCC - | VID /2|), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25°C.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIFFERENTIAL INPUT (IN+, IN-) Differential Input High Threshold VTH Differential Input Low Threshold VTL Input Current Power-Off Input Current Fail-Safe Input Resistors (MAX9174) Input Resistors (MAX9175) IIN+, IINIIN+, IINRIN1 RIN2 RIN3 Input Capacitance CIN PD 0, PD 1) LVTTL/LVCMOS INPUTS (P Input High Voltage VIH Input Low Voltage VIL Input Current IIN +50 -50 Figure 1 MAX9174 VCC = 0V or open, Figure 1 MAX9175 VIN+ = 3.6V or 0V, VIN- = 3.6V or 0V, VCC = 0V or open, Figure 1 VCC = 3.6V, 0V or open, Figure 1 VCC = 3.6V, 0V or open, Figure 1 mV mV -20 +20 µA -20 +20 µA 60 108 200 394 212 450 kΩ 4.5 pF 2.0 VCC + 1 V -1.0 +0.8 IN+ or IN- to GND (Note 4) -1.0V ≤ PD_ ≤ 0V -1.5 0V ≤ PD_ ≤ VCC -20 kΩ V mA +20 µA +1.5 mA 393 475 mV 1.0 15 mV 1.29 1.375 V VCC ≤ PD_ ≤ VCC + 1.0V LVDS OUTPUTS (OUT_+, OUT_-) Differential Output Voltage Change in Differential Output Voltage Between Logic States Offset Voltage 2 VOD Figure 2 ∆VOD Figure 2 VOS Figure 3 250 1.125 _______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters (VCC = +3.0V to +3.6V, RL = 100Ω ±1%, PD_ = high, differential input voltage |VID| = 0.05V to 1.2V, MAX9174 input common-mode voltage VCM = |VID /2| to (2.4V - |VID /2|), MAX9175 input common-mode voltage VCM = |VID /2| to (VCC - | VID /2|), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25°C.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS Change in Offset Voltage Between Logic States ∆VOS Figure 3 Fail-Safe Differential Output Voltage (MAX9174) VOD Figure 2 Differential Output Resistance RDIFF VCC = 3.6V or 0V Power-Down Single-Ended Output Current IPD PD_ = low Power-Off Single-Ended Output Current IOFF PD0, PD1 = low, VCC = 0V or open Output Short-Circuit Current IOS VOUT_+ = open, VOUT_- = 3.6V or 0V MIN TYP MAX UNITS 1.0 15 mV 250 393 475 mV 86 119 160 Ω -1.0 ±0.03 +1.0 µA -1.0 ±0.03 +1.0 µA +15 mA 15 mA VOUT_- = open, VOUT_+ = 3.6V or 0V VOUT_+ = open, VOUT_- = 3.6V or 0V VOUT_- = open, VOUT_+ = 3.6V or 0V VID = +50mV or -50mV, VOUT_+ = 0V or VCC -15 VID = +50mV or -50mV, VOUT_- = 0V or VCC Differential Output Short-Circuit Current Magnitude Supply Current IOSD ICC Power-Down Supply Current Output Capacitance ICCPD CO VID = +50mV or -50mV, VOD = 0V (Note 4) PD0 = VCC, PD1 = 0V or PD0 = 0V, PD1 = VCC 17 26 PD0 = Vcc, PD1 = Vcc 25 35 PD1, PD0 = 0V 0.5 OUT_+ or OUT_- to GND (Note 4) mA 20 µA 5.2 pF _______________________________________________________________________________________ 3 MAX9174/MAX9175 DC ELECTRICAL CHARACTERISTICS (continued) MAX9174/MAX9175 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100Ω±1%, CL = 5pF, differential input voltage |VID| = 0.15V to 1.2V, MAX9174 input common-mode voltage, VCM = |VID/2| to (2.4V - |VID/2|), MAX9175 input common-mode voltage VCM = |VID/2| to (VCC - |VID/2|), PD_ = high, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25°C.) (Notes 5, 6, 7) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS High-to-Low Propagation Delay tPHL Figures 4, 5 1.33 2.38 3.23 ns Low-to-High Propagation Delay tPLH Figures 4, 5 1.33 2.39 3.23 ns Added Deterministic Jitter tDJ Figures 4, 5 (Note 8) 80 ps(P-P) Added Random Jitter tRJ Figures 4, 5 1.0 ps(RMS) tSKP Figures 4, 5 141 ps ps Pulse Skew tPLH - tPHL Output-to-Output Skew Part-to-Part Skew Rise Time Fall Time Power-Down Time Power-Up Time Maximum Data Rate Maximum Switching Frequency 10 tSKOO Figure 6 14 45 tSKPP1 Figures 4, 5 (Note 9) 0.4 1.3 tSKPP2 Figures 4, 5 (Note 10) 1.9 ns tR Figures 4, 5 110 257 365 ps tF Figures 4, 5 110 252 365 ps 10 13 ns 18 35 µs tPD tPU DRMAX fMAX Switching Supply Current ICCSW PRBS Supply Current ICCPR Figures 7, 8 PD0, PD1 = L → H, Figures 7, 8 PD0 = H, PD1 = L → H, Figures 7, 8 92 103 PD1 = H, PD0 L → H, Figures 7, 8 92 103 Figures 4, 5, VOD ≥ 250mV (Note 11) 800 Figures 4, 5, VOD ≥ 250mV (Note 11) 670 ns Mbps MHz fIN = 670MHz 55 65 fIN = 155MHz 35 44 DR = 800Mbps, 223 - 1 PRBS input 37 46 mA mA Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and ∆VOD. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25°C. Note 3: Tolerance on all external resistors (including figures) is ±1%. Note 4: Guaranteed by design. Note 5: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma. Note 6: CL includes scope probe and test jig capacitance. Note 7: Pulse-generator output for differential inputs IN+, IN- (unless otherwise noted): f = 670MHz, 50% duty cycle, RO = 50Ω, tR = 700ps, and tF = 700ps (0% to 100%). Pulse-generator output for single-ended inputs PD0, PD1: tR = tF = 1.5ns (0.2VCC to 0.8VCC), 50% duty cycle, VOH = VCC + 1.0V settling to VCC, VOL = -1.0V settling to zero, f = 10kHz. Note 8: Pulse-generator output for tDJ: |VOD| = 0.15V, VOS = 1.25V, data rate 800Mbps, 223 - 1 PRBS, RO = 50Ω, tR = 700ps, and tF = 700ps (0% to 100%). Note 9: tSKPP1 is the magnitude of the difference of any differential propagation delays between devices operating under identical conditions. Note 10: tSKPP2 is the magnitude of the difference of any differential propagation delays between devices operating over rated conditions. Note 11: Meets all AC specifications. 4 _______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters 34 33 380 280 370 360 350 340 330 -15 10 35 60 2.6 tPHL 2.5 2.4 2.3 2.2 tPLH MAX9174 toc05 16 10 35 60 14 12 10 8 6 45 40 35 25 20 -40 -15 10 35 60 85 0 100 200 300 400 500 600 700 800 TEMPERATURE (°C) FREQUENCY (MHz) SUPPLY CURRENT vs. DATA RATE SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT RISE/FALL TIME vs. SUPPLY VOLTAGE 40 30 25 20 38 37 36 35 34 33 100 200 300 400 500 600 700 800 DATA RATE (Mbps) fIN = 155MHz 290 280 tR 270 260 250 tF 240 230 32 220 31 210 200 30 15 300 RISE/FALL TIME (ps) 35 fIN = 155MHz 39 SUPPLY CURRENT (mA) 40 0 50 TEMPERATURE (°C) PRBS 223 - 1 85 30 4 85 60 55 MAX9174 toc08 45 -15 MAX9174 toc07 -40 SUPPLY CURRENT (mA) fIN = 155MHz 0 2.0 35 SUPPLY CURRENT vs. FREQUENCY 2 2.1 10 60 SUPPLY CURRENT (mA) 2.7 20 OUTPUT-TO-OUTPUT SKEW (ps) 2.8 MAX9174 toc04 OUTPUT-TO-OUTPUT SKEW vs. TEMPERATURE 18 -15 TEMPERATURE (°C) DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE fIN = 155MHz tF -40 100 200 300 400 500 600 700 800 FREQUENCY (MHz) 2.9 240 210 0 TEMPERATURE (°C) 3.0 DIFFERENTIAL PROPAGATION DELAY (ns) 85 250 220 300 -40 tR 260 230 320 310 32 270 MAX9174 toc03 MAX9174 toc02 390 fIN = 155MHz 290 MAX9174 toc06 35 300 MAX9174 toc09 36 400 RISE/FALL TIME (ps) SUPPLY CURRENT (mA) 37 410 DIFFERENTIAL OUTPUT VOLTAGE (mV) fIN = 155MHz MAX9174 toc01 38 OUTPUT RISE/FALL TIME vs. TEMPERATURE DIFFERENTIAL OUTPUT VOLTAGE vs. FREQUENCY SUPPLY CURRENT vs. TEMPERATURE 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 MAX9174/MAX9175 Typical Operating Characteristics ((MAX9174) VCC = +3.3V, |VID| = 0.15V, VCM = 1.25V, TA = +25°C, RL = 100Ω ±1%, CL = 5pf, PD_ = VCC, unless otherwise noted.) Typical Operating Characteristics (continued) ((MAX9174) VCC = +3.3V, |VID| = 0.15V, VCM = 1.25V, TA = +25°C, RL = 100Ω ±1%, CL = 5pf, PD_ = VCC, unless otherwise noted.) 2.6 tPHL 2.5 2.4 2.3 tPLH 2.2 2.1 8 7 6 5 4 3 2 1 2.0 0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.1 3.2 3.3 3.4 3.5 400 350 300 250 3.6 50 60 70 80 90 100 110 120 130 140 150 SUPPLY VOLTAGE (V) LOAD RESISTANCE (Ω) PROPAGATION DELAY vs. INPUT COMMON-MODE VOLTAGE 2.7 3.0 2.6 tPHL 2.4 tPLH fIN = 155MHz 2.9 PROPAGATION DELAY (ns) MAX9174 fIN = 155MHz PROPAGATION DELAY vs. INPUT COMMON-MODE VOLTAGE MAX9174 toc13a 2.8 PROPAGATION DELAY (ns) 450 200 3.0 SUPPLY VOLTAGE (V) 2.5 500 MAX9174 toc12 fIN = 155MHz 9 2.8 2.7 2.6 tPHL 2.5 2.4 2.3 2.2 2.3 MAX9174 toc13b 2.7 10 DIFFERENTIAL OUTPUT VOLTAGE (mV) 2.8 DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTANCE MAX9174 toc11 fIN = 155MHz 2.9 OUTPUT-TO-OUTPUT SKEW (ps) 3.0 OUTPUT-TO-OUTPUT SKEW vs. SUPPLY VOLTAGE MAX9174 toc10 DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE DIFFERENTIAL PROPAGATION DELAY (ns) tPLH 2.1 0.825 1.575 INPUT COMMON-MODE VOLTAGE (V) OUTPUT-TO-OUTPUT SKEW vs. INPUT COMMON-MODE VOLTAGE OUTPUT-TO-OUTPUT SKEW vs. INPUT COMMON-MODE VOLTAGE 7.6 7.4 7.2 7.0 6.8 6.6 6.4 5.5 MAX9175 fIN = 155MHz 5.0 4.5 4.0 3.5 3.0 2.5 6.2 6.0 0.075 6.0 OUTPUT-TO-OUTPUT SKEW (ps) MAX9174 fIN = 155MHz 7.8 MAX9174 toc14a INPUT COMMON-MODE VOLTAGE (V) 8.0 0.825 1.575 INPUT COMMON-MODE VOLTAGE (V) 6 2.0 0.075 0.525 0.975 1.425 1.875 2.325 2.775 3.225 2.325 MAX9174 toc14b 2.2 0.075 OUTPUT-TO-OUTPUT SKEW (ps) MAX9174/MAX9175 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters 2.325 2.0 0.075 0.525 0.975 1.425 1.875 2.325 2.775 3.225 INPUT COMMON-MODE VOLTAGE (V) _______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters PIN NAME FUNCTION µMAX QFN 1 1 IN+ Noninverting Differential Input 2 2 IN- Inverting Differential Input 3 3 GND Ground 4 4 PD0 LVTTL/LVCMOS Input. OUT0+, OUT0- are high impedance to ground when PD0 is low. Internal pulldown resistor to GND. 5 5 PD1 LVTTL/LVCMOS Input. OUT1+, OUT1- are high impedance to ground when PD1 is low. Internal pulldown resistor to GND. 6 6 OUT0- 7 7 OUT0+ 8 8 VCC Inverting LVDS Output 0 Noninverting LVDS Output 0 Power Supply 9 9 OUT1- Inverting LVDS Output 1 10 10 OUT1+ Noninverting LVDS Output 1 — EP Exposed Pad Exposed Pad. Solder to ground. Detailed Description The MAX9174/MAX9175 are 670MHz, low-jitter, lowskew 1:2 splitters ideal for protection switching, loopback, and clock and signal distribution. The devices feature ultra-low 80psP-P deterministic jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing error. The MAX9174 has a fail-safe LVDS input and LVDS outputs. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs. The MAX9174 features a fail-safe circuit that drives the outputs high when the input is open, undriven and shorted, or undriven and terminated. The MAX9175 has a bias circuit that forces the outputs high when the input is open. The power-down inputs are compatible with standard LVTTL/LVCMOS logic. The power-down inputs tolerate undershoot of -1V and overshoot of VCC + 1V. The MAX9174/MAX9175 are available in 10-pin µMAX and 10-lead thin QFN packages, and operate from a single +3.3V supply over the -40°C to +85°C temperature range. Current-Mode LVDS Outputs The LVDS outputs use a current-steering configuration. This approach results in less ground bounce and less output ringing, enhancing noise margin and system speed performance. A differential output voltage is produced by steering current through the parallel combination of the integrated differential output resistor and transmission line impedance/termination resistor. When driving a 100Ω termination resistor, a differential voltage of 250mV to 475mV is produced. For loads greater than 100Ω, the output voltage is larger, and for loads less than 100Ω, the output voltage is smaller. See the Differential Output Voltage vs. Load Resistance curve in Typical Operating Characteristics for more information. The outputs are short-circuit current limited for single-ended and differential shorts. MAX9174 Input Fail-Safe The fail-safe feature of the MAX9174 sets the outputs high when the differential input is: • Open • Undriven and shorted • Undriven and terminated Without a fail-safe circuit, when the input is undriven, noise at the input may switch the outputs and it may appear to the system that data is being sent. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when a driver output is in high impedance. A shorted input can occur because of a cable failure. _______________________________________________________________________________________ 7 MAX9174/MAX9175 Pin Description MAX9174/MAX9175 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters When the input is driven with a differential signal of |VID| = 50mV to 1.2V within a voltage range of 0 to 2.4V, the fail-safe circuit is not activated. If the input is open, undriven and shorted, or undriven and terminated, an internal resistor in the fail-safe circuit pulls the input above VCC - 0.3V, activating the fail-safe circuit and forcing the outputs high (Figure 1). Overshoot and Undershoot Voltage Protection The MAX9174/MAX9175 are designed to protect the power-down inputs (PD0 and PD1) against latchup due to transient overshoot and undershoot voltage. If the input voltage goes above VCC or below GND by up to 1V, an internal circuit limits input current to 1.5mA. Applications Information Power-Supply Bypassing Bypass the VCC pin with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC. Table 1. Input Function Table INPUT OUTPUTS (IN+) - (IN-) (OUT_+) - (OUT_-) ≥ +50mV H ≤ -50mV L -50mV < VID < +50mV MAX9175 Open MAX9174 Open, undriven short, or undriven parallel termination Cables and Connectors Interconnect for LVDS typically has a controlled differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Termination H Table 2. Power-Down Function Table PD1 PD0 H H OUT_+, OUT_Both outputs enabled Shutdown to minimum power, outputs high impedance to ground L or open L or open L or open High OUT0 enabled, OUT1 high impedance to ground High L or open OUT1 enabled, OUT0 high impedance to ground Differential Traces Input and output trace characteristics affect the performance of the MAX9174/MAX9175. Use controlledimpedance differential traces (100Ω typ). To reduce radiated noise and ensure that noise couples as common mode, route the differential input and output signals within a pair close together. Reduce skew by matching the electrical length of the two signal paths that make up the differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities. Indeterminate VCC VCC RIN2 RIN3 COMPARATOR IN+ IN+ RIN1 VCC - 0.3V TO OUTPUT RIN3 RIN1 IN- DIFFERENTIAL RCVR MAX9174 INTERNAL FAIL-SAFE CIRCUIT MAX9175 INPUT Figure 1. Input Structure termination resistor across the differential input and at the far end of the interconnect driven by the LVDS outputs. Place the input termination resistor as close to the receiver input as possible. Termination resistors should match the differential impedance of the transmission line. Use 1% surface-mount resistors. The MAX9174/MAX9175 require external input and output termination resistors. For LVDS, connect an input 8 IN- _______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175 OUT_+ 5kΩ OUT_+ 1.25V IN+ 1.20V 1.25V IN- VOD VTEST = 0 TO VCC RL 1.20V 1.25V IN+ 1.20V 1.25V IN- RL/2 VOS 1.20V OUT_ - RL/2 5kΩ OUT_ - Figure 2. VOD Test Circuit Figure 3. VOS Test Circuit 5kΩ OUT1+ RL OUT15kΩ CL CL VTEST = 0 TO VCC 5kΩ OUT0+ IN+ PULSE GENERATOR RL INOUT0- 50Ω 5kΩ 50Ω CL CL Figure 4. Transition Time, Propagation Delay, and Output-to-Output Skew Test Circuit The MAX9174/MAX9175 feature an integrated differential output resistor. This resistor reduces jitter by damping reflections produced by a mismatch between the transmission line and termination resistor at the far end of the interconnect. Board Layout Separate the differential and single-ended signals to reduce crosstalk. A four-layer printed circuit board with separate layers for power, ground, differential signals, and single-ended logic signals is recommended. Separate the differential signals from the logic signals with power and ground planes for best results. IEC 61000-4-2 Level 4 ESD Protection The IEC 61000-4-2 standard (Figure 9) specifies ESD tolerance for electronic systems. The IEC 61000-4-2 model specifies a 150pF capacitor that is discharged into the device through a 330Ω resistor. The MAX9174/ MAX9175 differential inputs and outputs are rated for IEC 61000-4-2 level 4 (±8kV Contact Discharge and ±15kV Air-Gap Discharge). The Human Body Model (HBM, Figure 10) specifies a 100pF capacitor that is discharged into the device through a 1.5kΩ resistor. IEC 61000-4-2 level 4 discharges higher peak current and more energy than the HBM due to the lower series resistance and larger capacitor. _______________________________________________________________________________________ 9 MAX9174/MAX9175 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters IN- IN+ tPHL tPLH OUT_- OUT_+ VOS = ((VOUT_+) + (VOUT_-))/2 80% 80% VOD+ 0V 0V (OUT_+) - (OUT_-) 20% 20% tR VOD- tF Figure 5. Transition Time and Propagation Delay Timing IN+ IN- OUT0+ OUT0- OUT1+ OUT1tSKOO tSKOO Figure 6. Output-to-Output Skew 10 ______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175 VCC + 1V VCC PD_ VCC/2 0 -1.0V tPD tPU VOH OUT_+ WHEN VID = +50mV 50% 50% OUT_- WHEN VID = -50mV 1.25V 1.25V OUT_+ WHEN VID = -50mV 50% 50% OUT_- WHEN VID = +50mV VOL tPD tPU Figure 7. Power-Up/Down Delay Waveform MAX9174 MAX9175 1.25V OUT1+ RL/2 IN+ 1.20V 1.25V OUT1- 1.25V RL/2 INOUT0+ 1.20V RL/2 OUT0- RL/2 1.25V PULSE GENERATOR 50Ω Figure 8. Power-Up/Down Delay Test Circuit ______________________________________________________________________________________ 11 MAX9174/MAX9175 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters RD 330Ω RC 50Ω TO 100Ω DISCHARGE RESISTANCE CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 150pF RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR DEVICE UNDER TEST STORAGE CAPACITOR Figure 9. IEC 61000-4-2 Contact Discharge ESD Test Model HIGHVOLTAGE DC SOURCE Cs 100pF RD 1.5kΩ DISCHARGE RESISTANCE DEVICE UNDER TEST STORAGE CAPACITOR Figure 10. Human Body ESD Test Model Functional Diagram Pin Configurations TOP VIEW 10 OUT1+ IN+ 1 IN- 2 GND 3 MAX9174 MAX9175 9 OUT1- 8 VCC IN+ 1 IN- 2 GND 3 PD0 4 7 OUT0+ PD0 4 PD1 5 6 OUT0- PD1 5 µMAX MAX9174 MAX9175 10 OUT1+ 9 OUT1- MAX9174 MAX9175 8 VCC 7 OUT0+ EXPOSED PAD 6 OUT0- OUT1+ LVDS DRIVER 0 IN+ OUT1DIFFERENTIAL RECEIVER INOUT0+ THIN QFN (LEADS UNDER PACKAGE) LVDS DRIVER 1 OUT0PD0 PD1 Chip Information TRANSISTOR COUNT: 693 PROCESS: CMOS 12 ______________________________________________________________________________________ 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters 10LUMAX.EPS e 4X S 10 10 INCHES H ÿ 0.50±0.1 0.6±0.1 1 1 0.6±0.1 BOTTOM VIEW TOP VIEW D2 MILLIMETERS MAX DIM MIN A 0.043 A1 0.002 0.006 A2 0.030 0.037 D1 0.116 0.120 D2 0.114 0.118 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S α 0∞ 6∞ MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0∞ 6∞ E2 GAGE PLANE A2 c A b A1 α E1 D1 FRONT VIEW L L1 SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 10L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0061 REV. I 1 1 ______________________________________________________________________________________ 13 MAX9174/MAX9175 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 6, 8, &10L, QFN THIN.EPS MAX9174/MAX9175 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters L A D D2 A2 PIN 1 ID 1 N 1 C0.35 b E PIN 1 INDEX AREA [(N/2)-1] x e REF. E2 DETAIL A e k A1 CL CL L L e e A DALLAS SEMICONDUCTOR PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY APPROVAL DOCUMENT CONTROL NO. 21-0137 REV. 1 D 2 COMMON DIMENSIONS SYMBOL A MIN. MAX. 0.70 0.80 D 2.90 3.10 E 2.90 3.10 A1 0.00 0.05 L k 0.20 0.40 0.25 MIN. A2 0.20 REF. PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b T633-1 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF T833-1 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF T1033-1 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF [(N/2)-1] x e DALLAS SEMICONDUCTOR PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm APPROVAL DOCUMENT CONTROL NO. 21-0137 REV. D 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.